TI1 LP3879MRX-1.2/NOPB Lp3879 micropower 800ma low noise ceramic stable voltage regulator for low voltage application Datasheet

LP3879
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SNVS396B – MAY 2006 – REVISED APRIL 2013
LP3879 Micropower 800mA Low Noise "Ceramic Stable" Voltage Regulator for Low
Voltage Applications
Check for Samples: LP3879
FEATURES
DESCRIPTION
•
•
The LP3879 is a 800 mA fixed-output voltage
regulator designed to provide high performance and
low noise in applications requiring output voltages
between 1.0V and 1.2V.
1
2
•
•
•
•
•
•
•
•
•
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Standard Output Voltage: 1.00V, 1.20V
Custom Voltages Available from 1.0V to 1.2V
(50 mV Increments)
Input Voltage: 2.5 to 6V
1% Initial Output Accuracy
Designed for Use with Low ESR Ceramic
Capacitors
Very Low Output Noise
Sense Option Improves Load Regulation
8-Lead SO PowerPad and WSON Surface
Mount Packages
<10 μA Quiescent Current in Shutdown
Low Ground Pin Current at all Loads
High Peak Current Capability
Over-Temperature/Over-Current Protection
-40°C to +125°C Junction Temperature Range
Using an optimized VIP (Vertically Integrated PNP)
process, the LP3879 delivers superior performance:
Ground Pin Current: Typically 5.5 mA @ 800 mA
load, and 200 µA @ 100 µA load.
Low Power Shutdown: The LP3879 draws less than
10 μA quiescent current when shutdown pin is pulled
low.
Precision Output: Ensured output voltage accuracy
is 1% at room temperature.
Low Noise: Broadband output noise is only 18 μV
(typical) with 10 nF bypass capacitor.
APPLICATIONS
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•
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ASIC Power Supplies In:
– Desktops, Notebooks and Graphic Cards
– Set Top Boxes, Printers and Copiers
DSP and FPGA Power Supplies
SMPS Post-Regulator
Medical Instrumentation
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated
LP3879
SNVS396B – MAY 2006 – REVISED APRIL 2013
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Basic Application Circuit
OUTPUT
6
*4.7 PF
(Ceramic or
Tantalum
recommended)
4
1
5
+
*0.01 PF
(See App
Hints)
+
-
2
N/C
7
N/C
*10 PF
(Ceramic
recommended)
8
**S/D
+
LP3879-X.X
1.23V
+
3
*Capacitance values shown are minimum required to assure stability. Larger output capacitor provides improved
dynamic response. Output capacitor must meet ESR requirements (see Application Information).
**The Shutdown pin must be actively terminated (see Application Information). Tie to INPUT (Pin 4) if not used.
Connection Diagram
GROUND 3
INPUT 4
GND
8 SHUTDOWN
7 N/C
BYPASS
1
N/C
2
GROUND
3
INPUT
4
8
SHUTDOWN
7
N/C
6
SENSE
5
OUTPUT
6 SENSE
5 OUTPUT
Figure 1. Top View
8-Lead SO PowerPad
See DDA0008B Package
GROUND
BYPASS 1
N/C 2
Figure 2. Top View
8-Lead WSON
See NGT0008A Package
PIN DESCRIPTIONS
Pin
Name
1
BYPASS
2
N/C
3
GROUND
4
INPUT
5
OUTPUT
6
SENSE
7
N/C
Function
The capacitor connected between BYPASS and GROUND lowers output noise voltage
level and is required for loop stability.
DO NOT CONNECT. This pin is used for post package test and must be left floating.
Device ground.
Input source voltage.
Regulated output voltage.
Remote Sense. Tie directly to output or remotely at point of load for best regulation.
No internal connection.
8
SHUTDOWN
Output is enabled above turn-on threshold voltage. Pull down to turn off regulator output.
SO PowerPad,
WSON
SUBSTRATE
GROUND
The exposed die attach pad should be connected to a thermal pad at ground potential. For
additional information on using Texas Instruments' Non Pull Back WSON package, please
refer to WSON application note SNOA401
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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Absolute Maximum Ratings (1) (2)
Storage Temperature Range
−65°C to +150°C
Operating Junction Temperature Range
-40°C to +125°C
Lead Temperature (Soldering, 5 seconds)
260°C
ESD Rating (3)
2 kV
Shutdown Pin
1kV
Power Dissipation (4)
Internally Limited
−0.3V to +16V
Input Supply Voltage (Survival)
Input Supply Voltage (Typical Operating)
2.5V to +6V
SENSE Pin
−0.3V to +6V
Output Voltage (Survival) (5)
−0.3V to +6V
IOUT (Survival)
Short Circuit Protected
Input-Output Voltage (Survival) (6)
(1)
(2)
(3)
(4)
(5)
(6)
−0.3V to +16V
Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Electrical specifications do not apply
when operating the device outside of its rated operating conditions.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
ESD testing was performed using Human Body Model, a 100 pF capacitor discharged through a 1.5 kΩ resistor.
The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction-to-ambient thermal
resistance, θJ−A, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated
using:
The value of θJ−A for the WSON and SO PowerPad packages are specifically dependent on PCB trace area,
trace material, and the number of layers and thermal vias. If a four layer board is used with maximum vias from the IC center to the heat
dissipating copper layers, values of θJ−A which can be obtained are approximately 60°C/W for the SO PowerPad and 40°C/W for the
WSON package. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go
into thermal shutdown.
If used in a dual-supply system where the regulator load is returned to a negative supply, the LP3879 output must be diode-clamped to
ground.
The output PNP structure contains a diode between the VIN and VOUT terminals that is normally reverse-biased. Forcing the output
above the input will turn on this diode and may induce a latch-up mode which can damage the part (see Application Hints).
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Electrical Characteristics
Limits in standard typeface are for TJ = 25°C, and limits in boldface type apply over the temperature range of -40°C to
125°C. Limits are ensured through design, testing, or correlation. The limits are used to calculate the Average Outgoing
Quality Level (AOQL). Unless otherwise specified: VIN = 3.0V, VOUT = 1V, IL = 1 mA, COUT = 10 µF, CIN = 4.7 µF, VS/D = 2V,
CBYPASS = 10 nF.
Symbol
Parameter
Conditions
VO
Output Voltage Tolerance
'VOUT
'VIN
Output Voltage Line
Regulation
VIN (min)
Minimum Input Voltage
Required To Maintain
Output Regulation
IGND
Ground Pin Current
1 mA ≤ IL ≤ 800 mA, 3.0V ≤ VIN ≤ 6V
Min (1)
Typical (2)
Max (1)
-1.0
1.00
1.0
-2.0
-3.0
1.00
2.0
3.0
Units
%Vnom
0.014
3.0V ≤ VIN ≤ 6V
0.007
0.032
IL = 800 mA, VOUT ≥ VOUT(NOM) - 1%
2.5
3.1
IL = 800 mA, VOUT ≥ VOUT(NOM) - 1%
0 ≤ TJ ≤ 125°C
2.5
2.8
IL = 750 mA, VOUT ≥ VOUT(NOM) - 1%
2.5
IL = 100 µA
200
IL = 200 mA
1.5
IL = 800 mA
5.5
%/V
V
3.0
250
275
µA
2
3.3
8.5
mA
15
IO(PK)
Peak Output Current
VOUT ≥ VOUT(NOM) − 5%
1200
IO(MAX)
Short Circuit Current
RL = 0 (Steady State)
1400
en
Output Noise Voltage
(RMS)
BW = 100 Hz to 100 kHz
CBYPASS = 10 nF
18
µV(RMS)
'VOUT
'VIN
Ripple Rejection
f = 1 kHz
60
dB
mA
SHUTDOWN INPUT
VS/D
VH = Output ON
S/D Input Voltage
IS/D
(1)
(2)
4
S/D Input Current
VL = Output OFF, IIN ≤ 10 µA
1.4
0.1
1.6
0.50
V
VOUT ≤ 10 mV, IIN ≤ 50 µA
0.6
VS/D = 0
0.02
−1
5
15
VS/D = 5V
µA
Limits are ensured through testing, statistical correlation, or design.
Typical numbers reperesent the most likely norm for 25°C operation.
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Typical Performance Characteristics
Unless otherwise specified: VIN = 3.3V, VOUT = 1V, IL = 1 mA, CIN = 4.7 µF, COUT = 10 µF, VS/D = 2V, CBYP = 10 nF, TJ = 25°C.
IGND vs Temperature
Minimum VIN Over Temperature
10.0
9.0
8.0
IGND (mA)
7.0
IL = 800 mA
6.0
5.0
4.0
3.0
IL = 240 mA
2.0
1.0
IL = 1 mA
0
-60 -40 -20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
Figure 3.
Figure 4.
IGND vs ILoad
VOUT vs Temperature
1.020
1.015
VOUT (V)
1.010
1.005
1.000
0.995
0.990
0.985
0.980
-50
-25
0
25
50
75
100
125
TEMPERATURE (oC)
Figure 5.
Figure 6.
VOUT vs Temperature
Ripple Rejection
1.202
100
90
VOUT = 1.2V
80
RIPPLE REJECTION (dB)
VOUT (V)
1.201
1.200
1.199
70
60
50
40
30
20
10
1.198
-40 -25
0
25
50
75
100
125
0
10
100
1k
10k
100k
1M
JUNCTION TEMPERATURE (ºC)
FREQUENCY (Hz)
Figure 7.
Figure 8.
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Typical Performance Characteristics (continued)
Unless otherwise specified: VIN = 3.3V, VOUT = 1V, IL = 1 mA, CIN = 4.7 µF, COUT = 10 µF, VS/D = 2V, CBYP = 10 nF, TJ = 25°C.
Ripple Rejection
Line Transient Response
100
90
IL= 800 mA
RIPPLE REJECTION (dB)
80
70
60
50
40
30
20
10
0
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
6
Figure 9.
Figure 10.
Line Transient Response
Line Transient Response
Figure 11.
Figure 12.
Line Transient Response
Line Transient Response
Figure 13.
Figure 14.
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Typical Performance Characteristics (continued)
Unless otherwise specified: VIN = 3.3V, VOUT = 1V, IL = 1 mA, CIN = 4.7 µF, COUT = 10 µF, VS/D = 2V, CBYP = 10 nF, TJ = 25°C.
Line Transient Response
Load Transient Response
Figure 15.
Figure 16.
Load Transient Response
Turn-On Characteristics
1.2
1
0o C
VOUT (V)
0.8
0.6
25oC
0.4
125oC
0.2
0
0
0.5
1
1.5
2
VS/D
Figure 17.
Figure 18.
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LP3879
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Block Diagram
SENSE
BYPASS
INPUT
OUTPUT
6
1
4
5
Error
Amp
2
N/C
8
SHUTDOWN
7
N/C
+
-
LP3879-X.X
1.23V
GROUND
+
3
APPLICATION INFORMATION
PACKAGE INFORMATION
The LP3879 is offered in the 8-lead SO PowerPad or WSON surface mount packages to allow for increased
power dissipation compared to the SO-8 and Mini SO-8.
EXTERNAL CAPACITORS
Like any low-dropout regulator, the LP3879 requires external capacitors for regulator stability. These capacitors
must be correctly selected for good performance.
INPUT CAPACITOR: A capacitor whose value is at least 4.7 µF (±20%) is required between the LP3879 input
and ground. A good quality X5R / X7R ceramic capacitor should be used.
Capacitor tolerance and temperature variation must be considered when selecting a capacitor (see Capacitor
Characteristics section) to assure the minimum requirement of input capacitance is met over all operating
conditions.
The input capacitor must be located not more than 0.5" from the input pin and returned to a clean analog ground.
Any good quality ceramic or tantalum capacitor may be used, assuming the minimum input capacitance
requirement is met.
OUTPUT CAPACITOR: The LP3879 requires a ceramic output capacitor whose size is at least 10 µF (±20%). A
good quality X5R / X7R ceramic capacitor should be used. Capacitance tolerance and temperature
characteristics must be considered when selecting an output capacitor.
The LP3879 is designed specifically to work with ceramic output capacitors, utilizing circuitry which allows the
regulator to be stable across the entire range of output current with an ultra low ESR output capacitor.
The output capacitor selected must meet the requirement for minimum amount of capacitance and also have an
ESR (equivalent series resistance) value which is within the stable range. A curve is provided which shows the
stable ESR range as a function of load current (see Figure 19).
8
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0.4
ESR (:)
0.3
0.2
STABLE REGION
0.1
0
0
200
400
600
800
LOAD CURRENT (mA)
Figure 19. Stable Region For Output Capacitor ESR
Important: The output capacitor must maintain its ESR within the stable region over the full operating
temperature range of the application to assure stability.
The output capacitor ESR forms a zero which is required to add phase lead near the loop gain crossover
frequency, typically in the range of 50kHz to 200 kHz. The ESR at lower frequencies is of no importance. Some
capacitor manufacturers list ESR at low frequencies only, and some give a formula for Dissipation Factor which
can be used to calculate a value for a term referred to as ESR. However, since the DF formula is usually at a
much lower frequency than the range listed above, it will give an unrealistically high value. If good quality X5R or
X7R ceramic capacitors are used, the actual ESR in the 50 kHz to 200 kHz range will not exceed 25 milli Ohms.
If these are used as output capacitors for the LP3879, the regulator stability requirements are satisfied.
It is important to remember that capacitor tolerance and variation with temperature must be taken into
consideration when selecting an output capacitor so that the minimum required amount of output capacitance is
provided over the full operating temperature range. (See Capacitor Characteristics section).
The output capacitor must be located not more than 0.5" from the output pin and returned to a clean analog
ground.
NOISE BYPASS CAPACITOR: The 10 nF capacitor on the Bypass pin significantly reduces noise on the
regulator output and is required for loop stability. However, the capacitor is connected directly to a highimpedance circuit in the bandgap reference.
Because this circuit has only a few microamperes flowing in it, any significant loading on this node will cause a
change in the regulated output voltage. For this reason, DC leakage current through the noise bypass capacitor
must never exceed 100 nA, and should be kept as low as possible for best output voltage accuracy.
The types of capacitors best suited for the noise bypass capacitor are ceramic and film. High-quality ceramic
capacitors with either NPO or COG dielectric typically have very low leakage. 10 nF polypropolene and
polycarbonate film capacitors are available in small surface-mount packages and typically have extremely low
leakage current.
CAPACITOR CHARACTERISTICS
CERAMIC: The LP3879 was designed to work with ceramic capacitors on the output to take advantage of the
benefits they offer: for capacitance values in the 10 µF range, ceramics are the least expensive and also have
the lowest ESR values (which makes them best for eliminating high-frequency noise). The ESR of a typical 10 µF
ceramic capacitor is in the range of 5 mΩ to 10 mΩ, which meets the ESR limits required for stability by the
LP3879.
One disadvantage of ceramic capacitors is that their capacitance can vary with temperature. Many large value
ceramic capacitors (≥ 2.2 µF) are manufactured with the Z5U or Y5V temperature characteristic, which results in
the capacitance dropping by more than 50% as the temperature goes from 25°C to 85°C.
Another significant problem with Z5U and Y5V dielectric devices is that the capacitance drops severely with
applied voltage. A typical Z5U or Y5V capacitor can lose 60% of its rated capacitance with half of the rated
voltage applied to it.
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For these reasons, X7R and X5R type ceramic capacitors must be used on the input and output of the
LP3879.
SHUTDOWN INPUT OPERATION
The LP3879 is shut off by pulling the Shutdown input low, and turned on by pulling it high. If this feature is not to
be used, the Shutdown input should be tied to VIN to keep the regulator output on at all times.
To assure proper operation, the signal source used to drive the Shutdown input must be able to swing above and
below the specified turn-on/turn-off voltage thresholds listed in the Electrical Characteristics section under
VON/OFF.
REVERSE INPUT-OUTPUT VOLTAGE
The PNP power transistor used as the pass element in the LP3879 has an inherent diode connected between
the regulator output and input.
During normal operation (where the input voltage is higher than the output) this diode is reverse-biased.
However, if the output is pulled above the input, this diode will turn ON and current will flow into the regulator
output.
In such cases, a parasitic SCR can latch which will allow a high current to flow into VIN (and out the ground pin),
which can damage the part.
In any application where the output may be pulled above the input, an external Schottky diode must be
connected from VIN to VOUT (cathode on VIN, anode on VOUT), to limit the reverse voltage across the LP3879 to
0.3V (see Absolute Maximum Ratings).
10
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REVISION HISTORY
Changes from Revision A (April 2013) to Revision B
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 10
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PACKAGE OPTION ADDENDUM
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1-Nov-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
LP3879MR-1.0/NOPB
Package Type Package Pins Package
Drawing
Qty
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DDA
8
95
Green (RoHS
& no Sb/Br)
SN | CU SN
Level-3-260C-168 HR
3879
MR1.0
SO PowerPAD
DDA
8
95
TBD
Call TI
Call TI
LP3879
MR1.2
LP3879MR-1.2/NOPB
ACTIVE SO PowerPAD
DDA
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
LP3879
MR1.2
LP3879MRX-1.0/NOPB
ACTIVE SO PowerPAD
DDA
8
2500
Green (RoHS
& no Sb/Br)
SN | CU SN
Level-3-260C-168 HR
3879
MR1.0
LP3879MRX-1.2/NOPB
ACTIVE SO PowerPAD
DDA
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
LP3879
MR1.2
LP3879MR-1.2
ACTIVE SO PowerPAD
Eco Plan
NRND
LP3879SD-1.0
NRND
WSON
NGT
8
1000
TBD
Call TI
Call TI
79SD1.0
LP3879SD-1.0/NOPB
ACTIVE
WSON
NGT
8
1000
Green (RoHS
& no Sb/Br)
SN
Level-1-260C-UNLIM
79SD1.0
LP3879SD-1.2/NOPB
ACTIVE
WSON
NGT
8
1000
Green (RoHS
& no Sb/Br)
SN
Level-1-260C-UNLIM
79SD1.2
LP3879SDX-1.0/NOPB
ACTIVE
WSON
NGT
8
4500
Green (RoHS
& no Sb/Br)
SN
Level-1-260C-UNLIM
79SD1.0
LP3879SDX-1.2/NOPB
ACTIVE
WSON
NGT
8
4500
Green (RoHS
& no Sb/Br)
SN
Level-1-260C-UNLIM
79SD1.2
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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1-Nov-2013
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
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11-Oct-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LP3879MRX-1.0/NOPB
SO
Power
PAD
DDA
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LP3879MRX-1.2/NOPB
SO
Power
PAD
DDA
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LP3879SD-1.0
WSON
NGT
8
1000
178.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
LP3879SD-1.0/NOPB
WSON
NGT
8
1000
178.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
LP3879SD-1.2/NOPB
WSON
NGT
8
1000
178.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
LP3879SDX-1.0/NOPB
WSON
NGT
8
4500
330.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
LP3879SDX-1.2/NOPB
WSON
NGT
8
4500
330.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Oct-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LP3879MRX-1.0/NOPB
SO PowerPAD
DDA
8
2500
367.0
367.0
35.0
LP3879MRX-1.2/NOPB
SO PowerPAD
DDA
8
2500
367.0
367.0
35.0
LP3879SD-1.0
WSON
NGT
8
1000
210.0
185.0
35.0
LP3879SD-1.0/NOPB
WSON
NGT
8
1000
210.0
185.0
35.0
LP3879SD-1.2/NOPB
WSON
NGT
8
1000
210.0
185.0
35.0
LP3879SDX-1.0/NOPB
WSON
NGT
8
4500
367.0
367.0
35.0
LP3879SDX-1.2/NOPB
WSON
NGT
8
4500
367.0
367.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
DDA0008B
MRA08B (Rev B)
www.ti.com
MECHANICAL DATA
NGT0008A
SDC08A (Rev A)
www.ti.com
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