Maxim MAX1200AEMH 5v single-supply, 1msps, 16-bit self-calibrating adc Datasheet

19-1413; Rev 0; 12/98
KIT
ATION
EVALU
LE
B
A
IL
A
AV
+5V Single-Supply, 1Msps, 16-Bit
Self-Calibrating ADC
The MAX1200 16-bit, monolithic, analog-to-digital converter (ADC) is capable of conversion rates up to
1Msps. This CMOS integrated circuit uses a fully differential, pipelined architecture with digital error correction
and a short self-calibration to ensure 16-bit linearity at
full sample rates. An on-chip track/hold (T/H) maintains
superb dynamic performance up to the Nyquist frequency. The MAX1200 operates from a single +5V supply.
The fully differential inputs allow an input swing of
±VREF. The reference is also differential with the positive reference (RFPF) typically connected to +4.096V
and the negative reference (RFNF) connected to analog ground. Additional sensing pins (RFPS, RFNS) are
provided to compensate for any resistive divider action
that may occur. A single-ended input is also possible
using two operational amplifiers.
Power dissipation is typically only 273mW at +5V, at a
sampling rate of 1Msps. The device employs a CMOScompatible, 16-bit parallel, two’s complement output
data format. For a higher sampling speed (up to
2.2Msps) but lower resolution (14-bit), select the
MAX1201, a pin-compatible version of the MAX1200.
The MAX1200 is available in an MQFP package and
operates over the commercial (0°C to +70°C) and
extended-industrial (-40°C to +85°C) temperature
ranges.
Features
♦ Monolithic 16-Bit, 1Msps A/D Converter
♦ Single +5V Supply
♦ ±VREF Differential Input Voltage Range
♦ 87dB SNR for fIN = 100kHz
♦ 91dB SFDR for fIN = 100kHz
♦ 273mW Low-Power Dissipation
♦ ±0.5LSB Differential Nonlinearity Error
♦ Three-State, Two’s Complement Output Data
♦ On-Demand Self-Calibration
♦ Pin-Compatible 14-Bit Versions Available
(1Msps MAX1205, 2.2Msps MAX1201)
Ordering Information
PART
TEMP. RANGE
PIN-PACKAGE
DNL
(LSB)
MAX1200ACMH
0°C to +70°C
44 MQFP
±0.5
MAX1200BCMH
0°C to +70°C
44 MQFP
—
MAX1200AEMH
-40°C to +85°C
44 MQFP
±0.5
MAX1200BEMH
-40°C to +85°C
44 MQFP
—
Pin Configuration
TEST0
34
35
RFPS
RFPF
CM
36
37
38
INP
RFNS
RFNF
39
40
41
INN
N.C.
N.C.
1
33
2
32
3
31
4
30
5
29
6
28
MAX1200
21
22
20
19
D3
DGND
D7
D11
D10
18
23
D6
D5
D4
24
11
17
25
10
16
26
9
15
27
8
14
7
12
Instrumentation
ST_CAL
AGND
AVDD
AGND
AGND
AVDD
DOR
D15
D14
D13
D12
D9
D8
DRVDD
Data Acquisition
13
Scanners
42
Communications
END_CAL
High-Resolution Imaging
43
Applications
44
TOP VIEW
OE
DAV
CLK
DVDD
DGND
DGND
DVDD
TEST1
D0
D1
D2
MQFP
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
MAX1200
General Description
MAX1200
+5V Single-Supply, 1Msps, 16-Bit
Self-Calibrating ADC
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND, DGND ..........................................................+7V
DVDD to DGND, AGND..........................................................+7V
DRVDD to DGND, AGND .......................................................+7V
INP, INN, RFPF, RFPS,
RFNF, RFNS, CLK, CM..........(AGND - 0.3V) to (AVDD + 0.3V)
Digital Inputs to DGND ............................-0.3V to (DVDD + 0.3V)
Digital Output (DAV) to DGND ..............-0.3V to (DRVDD + 0.3V)
Other Digital Outputs to DGND .............-0.3V to (DRVDD + 0.3V)
Continuous Power Dissipation (TA = +70°C)
44-Pin MQFP (derate 11.11mW/°C above +70°C).......889mW
Operating Temperature Ranges (TA)
MAX1200_CMH ..................................................0°C to +70°C
MAX1200_EMH................................................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD = +5V ±5%, DVDD = DRVDD = +3.3V, VRFPS = +4.096V, VRFNS = AGND, VCM = +2.048V, VIN = -0.5dBFS, fCLK = 2.048MHz;
digital output load ≤ 20pF; TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT
Input Voltage Range (Note 2)
VIN
Input Resistance (Note 3)
RI
Input Capacitance
CI
4.096
Single-ended
V
±4.096
Differential
Per side in track mode
55
kΩ
21
pF
EXTERNAL REFERENCE
Reference Voltage (Note 4)
VREF
Reference Input Resistance
RREF
4.096
700
4.5
V
Ω
1000
TRANSFER CHARACTERISTICS
Resolution
(No missing codes; Note 5)
RES
Integral Nonlinearity
INL
Differential Nonlinearity
DNL
After calibration, guaranteed for
MAX1200A only
16
MAX1200A
-1
Bits
±3.5
±0.5
LSB
+1
±0.6
MAX1200B
Offset Error
-0.2
±0.003
+0.2
Gain Error
-5
-3
5
Input-Referred Noise
LSB
%FSR
%FSR
75
µVRMS
4
fSAMPLE
Cycles
DYNAMIC SPECIFICATIONS (Note 6)
Maximum Sampling Rate
fSAMPLE
fSAMPLE = fCLK / 2
Conversion Time
(Pipeline Delay/Latency)
1.024
Msps
Acquisition Time
tACQ
125
ns
Overvoltage Recovery Time
tOVR
450
ns
Aperture Delay
tAD
3
ns
Aperture Jitter
tAJ
To full-scale step (0.006%)
5
psRMS
Full-Power Bandwidth
3.3
MHz
Small-Signal Bandwidth
78
MHz
2
_______________________________________________________________________________________
+5V Single-Supply, 1Msps, 16-Bit
Self-Calibrating ADC
(AVDD = +5V ±5%, DVDD = DRVDD = +3.3V, VRFPS = +4.096V, VRFNS = AGND, VCM = +2.048V, VIN = -0.5dBFS, fCLK = 2.048MHz;
digital output load ≤ 20pF; TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
VRFPS = 4.096V,
VRFNS = AGND
Signal-to-Noise Ratio
(Note 5)
SNR
VRFPS = 3.5V,
VRFNS = 1.5V
VRFPS = 4.096V,
VRFNS = AGND
Spurious-Free Dynamic Range
(Note 5)
SFDR
VRFPS = 3.5V,
VRFNS = 1.5V
VRFPS = 4.096V,
VRFNS = AGND
Total Harmonic Distortion
(Note 5)
THD
VRFPS = 3.5V,
VRFNS = 1.5V
VRFPS = 4.096V,
VRFNS = AGND
Signal-to-Noise Ratio plus
Distortion (Note 5)
SINAD
VRFPS = 3.5V,
VRFNS = 1.5V
fIN = 99.5kHz
MIN
TYP
83
87
fIN = 300.5kHz
84
fIN = 504.5kHz
83
fIN = 99.5kHz
78
81
fIN = 504.5kHz
80
84
91
fIN = 300.5kHz
89
fIN = 504.5kHz
88
fIN = 99.5kHz
85
91
fIN = 504.5kHz
90
fIN = 99.5kHz
-87
fIN = 300.5kHz
-86
fIN = 504.5kHz
-85
fIN = 99.5kHz
-90
fIN = 300.5kHz
-89
fIN = 504.5kHz
-88
80
fIN = 300.5kHz
-82
-84
dB
84
82
fIN = 504.5kHz
fIN = 99.5kHz
dB
92
fIN = 300.5kHz
fIN = 99.5kHz
UNITS
dB
83
fIN = 300.5kHz
fIN = 99.5kHz
MAX
81
77
dB
82
fIN = 300.5kHz
80.5
fIN = 504.5kHz
79.5
POWER REQUIREMENTS
Analog Supply Voltage
AVDD
Analog Supply Current
I(AVDD)
Digital Supply Voltage
DVDD
Digital Supply Current
I(DVDD)
Output Drive Supply Voltage
DRVDD
Output Drive Supply Current
I(DRVDD)
Power Dissipation
4.75
5
5.25
V
51
70
mA
5.25
V
1.2
mA
3
0.4
3
10pF loads on D0–D15 and DAV
PDSS
Warm-Up Time
DVDD
V
0.1
0.6
mA
273
377
mW
0.1
Power-Supply Rejection Ratio
PSRR
Offset
55
Gain
55
sec
dB
_______________________________________________________________________________________
3
MAX1200
ELECTRICAL CHARACTERISTICS (continued)
MAX1200
+5V Single-Supply, 1Msps, 16-Bit
Self-Calibrating ADC
TIMING CHARACTERISTICS (Figures 7, 8, 9)
(AVDD = +5V ±5%, DVDD = DRVDD = +3.3V, fCLK = 2.048MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at
TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
tCONV
Clock Period
tCLK
Clock HIGH Time
tCH
187
244
301
ns
Clock LOW Time
tCL
187
244
301
ns
Acquisition Time
tACQ
tCLK / 2
Output Delay
tOD
70
DAV Pulse Width
tDAV
1 / fCLK
CLK-to-DAV Rising Edge
4 / fSAMPLE
UNITS
Conversion Time
488
tS
Data Access Time
tAC
Bus Relinquish Time
tREL
Calibration Time
tCAL
ns
CL = 20pF
ST_CAL = DVDD
ns
ns
150
ns
ns
65
145
ns
16
75
ns
16
75
ns
fCLK
Cycles
17,400
DIGITAL INPUT AND OUTPUT CHARACTERISTICS
(AVDD = +5V ±5%, DVDD = DRVDD = +3.3V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
Input LOW Voltage
VIL
Input HIGH Voltage
VIH
CONDITIONS
MIN
TYP
V
V
4
CLK Input LOW Voltage
VCLK
CLK Input HIGH Voltage
VCLK
CLK Input Current
ICLK
CLK Input Capacitance
CCLK
pF
0.8
V
±10
µA
AVDD - 0.8
VIN = 0 or VDD
V
±1
9
Digital Input Current
IIN
Output Low Voltage
VOL
ISINK = 1.6mA
Output High Voltage
VOH
ISOURCE = 200µA
Three-State Output Capacitance
UNITS
0.8
DVDD - 0.8
Input Capacitance
Three-State Leakage Current
MAX
VIN = 0 or DVDD
DVDD
- 0.4
pF
±0.1
±10
µA
70
400
mV
DVDD
- 0.03
ILEAKAGE
±0.1
COUT
3.5
V
±10
µA
pF
Note 1: Reference inputs driven by operational amplifiers for Kelvin-sensed operation.
Note 2: For unipolar mode, the analog input voltage, VINP, must be within 0 and VREF, VINN = VCM / 2; where VREF = VRFPS - VRFNS.
For differential mode, the analog input voltages VINP and VINN must be within 0 and VREF; where VREF = VRFPS - VRFNS. The
common-mode voltage of the inputs INP and INN is VCM = (VRFPS + VRFNS) / 2.
Note 3: RI varies inversely with sample rate.
Note 4: Minimum and maximum parameters are not tested. Guaranteed by design.
Note 5: Calibration remains valid for temperature changes within ±20°C and power-supply variations ±5%. Guaranteed by design.
Note 6: All AC specifications are shown for the differential mode.
4
_______________________________________________________________________________________
+5V Single-Supply, 1Msps, 16-Bit
Self-Calibrating ADC
SINGLE-TONE SPURIOUS-FREE DYNAMIC RANGE
vs. INPUT AMPLITUDE (fIN = 99.5kHz)
DIFFERENTIAL NONLINEARITY vs.
TWO’S COMPLEMENT OUTPUT CODE
4
3
120
MAX1200toc02
1.0
MAX1200 toc01
5
0.75
(dBFS)
110
100
0.50
-1
0
-3
-4
-5
-32768
-16384
0
16384
50
-0.75
40
-1.0
-32,768
30
-16,384
0
16,384
-80
32,768
-70
-60
-50
-40
-30
-20
TWO’S COMPLEMENT OUTPUT CODE
INPUT AMPLITUDE (dBFS)
SIGNAL-TO-NOISE RATIO PLUS
DISTORTION vs. INPUT FREQUENCY
TOTAL HARMONIC DISTORTION
vs. INPUT FREQUENCY
SIGNAL-TO-NOISE RATIO
vs. INPUT FREQUENCY
AIN = -20dBFS
90
AIN = -0.5dBFS
85
-78
AIN = -6dBFS
76
-80
SNR (dB)
THD (dB)
80
AIN = -6dBFS
-82
-86
72
AIN = -20dBFS
70
70
AIN = -20dBFS
65
-90
10
100
1000
AIN = -6dBFS
80
AIN = -0.5dBFS
-88
68
1
10
100
1
1000
10
100
INPUT FREQUENCY (kHz)
INPUT FREQUENCY (kHz)
INPUT FREQUENCY (kHz)
SIGNAL-TO-NOISE RATIO PLUS DISTORTION
vs. SAMPLING RATE (fIN = 99.5kHz)
TYPICAL FFT, fIN = 99.5kHz,
8192 VALUE RECORD
TYPICAL FFT, fIN = 504.5MHz,
8192 VALUE RECORD
-30
82
81
80
-60
-75
-90
-105
1
SAMPLE RATE (Msps)
10
-30
-45
-60
-75
-90
-105
-120
-120
-135
-135
-150
-150
0.1
-15
AMPLITUDE (dBFS)
83
-45
1000
MAX1200 toc09
-15
AMPLITUDE (dBFS)
84
0
MAX1200 toc08
0
MAX1200 toc07
85
0
75
-84
74
-10
vsMAX1200 toc06
-76
MAX1200 toc05
-74
MAX1200 toc04
AIN = -0.5dBFS
82
SINAD (dB)
60
TWO’S COMPLEMENT OUTPUT CODE
84
1
70
-0.50
32768
86
78
80
(dBc)
-0.25
-2
SINAD (dB)
SFDR (dB)
0
90
0.25
DNL (LSB)
INL (LSB)
2
1
MAX1200toc03
INTEGRAL NONLINEARITY vs.
TWO’S COMPLEMENT OUTPUT CODE
0
200
400
FREQUENCY (kHz)
600
0
200
400
600
FREQUENCY (kHz)
_______________________________________________________________________________________
5
MAX1200
__________________________________________Typical Operating Characteristics
(AVDD = +5V ±5%, DVDD = DRVDD = +3.3V, VRFPS = +4.096V, VRFNS = AGND; VCM = +2.048V, differential input, fCLK = 2.048MHz,
calibrated, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics
(AVDD = +5V ±5%, DVDD = DRVDD = +3.3V, VRFPS = +3.5V, VRFNS = +1.5V; VCM = +2.5V, differential input, fCLK = 2.048MHz,
calibrated, TA = +25°C, unless otherwise noted.)
0.8
0.6
0.5
0.2
70
-0.5
0
-0.2
60
40
-0.4
-1.5
-0.6
20
-2.0
-0.8
10
-2.5
-32,768
-1.0
-32,768
-16,384
0
16,384
32,768
(dB)
50
-1.0
30
0
-16,384
0
16,384
32,768
-90 -80 -70 -60 -50 -40 -30 -20 -10
TWO’S COMPLEMENT OUTPUT CODE
TWO’S COMPLEMENT OUTPUT CODE
INPUT AMPLITUDE (dBFS)
SIGNAL-TO-NOISE RATIO PLUS DISTORTION
vs. INPUT FREQUENCY
TOTAL HARMONIC DISTORTION
vs. INPUT FREQUENCY
SIGNAL-TO-NOISE RATIO
vs. INPUT FREQUENCY
85
AIN = -6dBFS
THD (dB)
76
74
72
-83
SNR (dB)
78
-85
70
-87
68
-89
AIN = -0.5dBFS
80
-81
AIN = -6dBFS
0
MAX1200 toc16
AIN = -20dBFS
-79
MAX1200 TOC15
AIN = -0.5dBFS
80
-77
MAX1200 toc14
82
AIN = -6dBFS
75
70
65
66
-91
64
AIN = -20dBFS
62
1
10
AIN = -0.5dBFS
-93
100
AIN = -20dBFS
60
1
1000
10
100
1000
1
10
100
INPUT FREQUENCY (kHz)
INPUT FREQUENCY (kHz)
INPUT FREQUENCY (kHz)
SIGNAL-TO-NOISE RATIO PLUS DISTORTION
vs. SAMPLING RATE (fIN = 99.5kHz)
TYPICAL FFT, fIN = 99.5kHz,
8192 VALUE RECORD
TYPICAL FFT, fIN = 504.5MHz,
8192 VALUE RECORD
-30
82
81
80
79
78
-45
-60
-75
-90
-105
1
SAMPLE RATE (Msps)
10
-15
-30
-45
-60
-75
-90
-105
-120
-120
-135
-135
-150
0.1
0
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
83
-15
1000
MAX1200 toc19
0
MAX1200 toc17
84
MAX1200 toc18
SINAD (dB)
SFDR (dB)
80
0
(dBFS)
90
0.4
84
6
100
1.0
DNL (LSB)
INL (LSB)
1.5
110
MAX1200 toc12
2.0
SINGLE-TONE SPURIOUS-FREE DYNAMIC RANGE
vs. INPUT AMPLITUDE (fIN = 99.5kHz)
1.0
MAX1200 toc11
2.5
DIFFERENTIAL NONLINEARITY vs.
TWO’S COMPLEMENT OUTPUT CODE
MAX1200 toc13
INTEGRAL NONLINEARITY vs.
TWO’S COMPLEMENT OUTPUT CODE
SINAD (dB)
MAX1200
+5V Single-Supply, 1Msps, 16-Bit
Self-Calibrating ADC
-150
0
200
400
FREQUENCY (kHz)
600
0
200
400
FREQUENCY (kHz)
_______________________________________________________________________________________
600
+5V Single-Supply, 1Msps, 16-Bit
Self-Calibrating ADC
PIN
NAME
FUNCTION
Digital Input to Start Calibration.
ST_CAL = 0: Normal conversion mode.
ST_CAL = 1: Start self-calibration.
1
ST_CAL
2, 4, 5
AGND
Analog Ground
3, 6
AVDD
Analog Power Supply, +5V ±5%
7
DOR
Data Out-of-Range Bit
8
D15
Bit 15 (MSB)
9
D14
Bit 14
10
D13
Bit 13
11
D12
Bit 12
12
D11
Bit 11
13
D10
Bit 10
14
D9
Bit 9
15
D8
Bit 8
16
DRVDD
Digital Power Supply for the Output Drivers. +3V to +5.25V, DRVDD ≤ DVDD
17, 28, 29
DGND
Digital Ground
18
D7
Bit 7
19
D6
Bit 6
20
D5
Bit 5
21
D4
Bit 4
22
D3
Bit 3
23
D2
Bit 2
24
D1
Bit 1
25
D0
Bit 0 (LSB)
26
TEST1
Test Pin 1. Do not connect.
27, 30
DVDD
Digital Power Supply, +3V to +5.25V
31
CLK
Input Clock. Receives power from AVDD to reduce jitter.
32
DAV
Data Valid Clock. This clock can be used to transfer the data to a memory or any other data
acquisition system.
33
OE
Output Enable. OE = 0: D0–D15 and DOR are high impedance. OE = 1: All bits are active.
34
TEST0
35
CM
Test Pin 0. Do not connect.
Common-Mode Voltage. Analog Input. Drive midway between positive and negative reference
voltages.
36
RFPF
Positive Reference Voltage, Force Input
37
RFPS
Positive Reference Voltage, Sense Input
38
RFNF
Negative Reference Voltage, Force Input
39
RFNS
Negative Reference Voltage, Sense Input
40
INP
Positive Input Voltage
41, 42
N.C.
Not Connected. No internal connection.
43
INN
Negative Input Voltage
44
END_CAL
Digital Output for End of Calibration.
END_CAL = 0: Calibration in progress.
END_CAL = 1: Normal conversion mode.
_______________________________________________________________________________________
7
MAX1200
Pin Description
MAX1200
+5V Single-Supply, 1Msps, 16-Bit
Self-Calibrating ADC
Detailed Description
Converter Operation
The MAX1200 is a 16-bit, monolithic analog-to-digital
converter (ADC) capable of conversion rates up to
1Msps. It uses a multistage, fully differential, pipelined
architecture with digital error correction and self-calibration to provide typically 91dB spurious-free dynamic
range at a 1Msps sampling rate. It also provides excellent SNR and THD performance up to the Nyquist frequency. This makes the device suitable for applications
such as data acquisition, high-resolution imaging,
scanners, digital communication, and instrumentation.
Figure 1 shows the simplified, internal structure of the
ADC. A switched-capacitor, pipelined architecture is
used to digitize the signal at a high throughput rate.
The first four stages of the pipeline use a low-resolution
quantizer to approximate the input signal. The multiplying digital-to-analog converter (MDAC) stage is used to
subtract the quantized analog signal from the input.
The residue is then amplified with a fixed gain and
passed on to the next stage. The accuracy of the converter is improved by a digital calibration algorithm
which corrects for mismatches between the capacitors
in the switched-capacitor MDAC. Note that the pipeline
RFP_
RFN_
CLK
Requirements for Reference
and Analog Signal Inputs
Fully differential switched-capacitor circuits (SC) are used
for both the reference and analog inputs (Figure 2). This
allows either single-ended or differential signals to be
used in the reference and/or analog signal paths. The
signal voltage on these pins (INP, INN, RFP_, RFN_)
should never exceed the analog supply rail, AVDD, nor
fall below ground.
STAGE2
AVDD
STAGE3
AGND
STAGE4
8X
S/H
ADC
DVDD
• Common-mode noise immunity
• Virtual elimination of the even-order harmonics
• Less stringent requirements on the input signal processing amplifiers
CM
STAGE1
INP
INN
introduces latency of four sampling periods between
the input being sampled and the output appearing at
D15–D0.
While the device can handle both single-ended or differential inputs (see the Requirements for Reference
and Analog Signal Inputs section), the latter mode of
operation will guarantee best THD and SFDR performance. The differential input provides the following
advantages compared to a single-ended operation:
• Twice as much signal input span
ADC
MDAC
CLOCK
GENERATOR
DAV
CORRECTION AND
CALIBRATION LOGIC
END_CAL
ST_CAL
DGND
MAX1200
OE
OUTPUT DRIVERS
DRVDD
DOR
D15–D0
Figure 1. Internal Functional Diagram
8
_______________________________________________________________________________________
+5V Single-Supply, 1Msps, 16-Bit
Self-Calibrating ADC
MAX1200
CM
RFPF
RFPS
RFPF
INP
RFNF
INN
RFNF
RFPF
CM
Figure 2. Simplified MDAC Architecture
RFNS
Figure 3. Equivalent Input at the Reference Pins. The sense
pins should not draw any DC current.
Choice of Reference
It is important to choose a low-noise reference such as
the MAX6341, which can provide both excellent load
regulation and low temperature drift. The equivalent
input circuit for the reference pins is shown in Figure 3.
Note that the reference pins drive approximately 1kΩ of
resistance on-chip. They also drive a switched capacitor of 21pF. To meet the dynamic performance, the reference voltage is required to settle to 0.0015% within
one clock cycle. Carefully choose an appropriate driving circuit (Figure 4). The capacitors at the reference
pins (RFPF, RFNF) provide the dynamic charge
required during each clock cycle, while the op amps
ensure accuracy of the reference signals. These
capacitors must have low dielectric-absorption characteristics, such as polystyrene or teflon capacitors.
The reference pins can be connected to either singleended or differential voltages within the specified maximum levels. Typically the positive reference pin (RFPF)
would be driven to +4.096V, and the negative reference pin (RFNF) connected to analog ground for best
SNR performance. If THD performance is more important to the application than signal-to-noise ratio, choose
a lower level, differential voltage such as V RFPS =
+3.5V and VRFNS = +1.5V.
There are sense pins, RFPS and RFNS, which can be
used with external amplifiers to compensate for any
resistive drop on these lines, internal or external to the
chip. Ensure a correct reference voltage by using proper Kelvin connections at the sense pins.
Common-Mode Voltage
The switched-capacitor input circuit at the analog input
allows signals between AGND and the analog power
supply. Since the common-mode voltage has a strong
VRFP = +4.096V
5k
CHIP BOUNDARY
RFPF
MAX410
RFPS
5k
VRFN = 0
RFNF
MAX410
RFNS
CM
MAX410
Figure 4. Drive Circuit for Reference Pins and Common-Mode
Pin
influence on the performance of the ADC, the best
results are obtained by choosing V CM = (V RFPS +
VRFNS) / 2. This can be achieved by using a resistive
divider between the two reference potentials. Figure 4
shows a typical driving circuit for good dynamic performance.
_______________________________________________________________________________________
9
MAX1200
+5V Single-Supply, 1Msps, 16-Bit
Self-Calibrating ADC
Analog Signal Conditioning
For single-ended inputs, the negative analog input pin
(INN) is connected to the common-mode voltage pin
(CM) and the positive analog input pin (INP) is connected to the input.
To take full advantage of the ADC’s superior AC performance up to the Nyquist frequency, drive the chip with
differential signals. In communication systems the signals may inherently be available in differential mode;
however medical and/or other applications may only
provide single-ended inputs. In this case, convert the
single-ended signals into differential ones by using the
circuit recommended in Figure 5. Use low-noise, wideband amplifiers, such as the MAX4108, to maintain the
signal purity over the full-power bandwidth of the
MAX1200 input.
Lowpass or bandpass signals may be required to
improve the signal-to-noise and distortion of the incoming signal. For low-frequency signals (<100kHz), active
filters may be used. For higher frequencies, passive filters are more convenient.
Single-Ended to Differential
Conversion Using Transformers
An alternative single-ended to differential-ended conversion method is a balun transformer such as the
CTX03-13675 from Coiltronics. An important benefit of
these transformers is their ability to level-shift singleended signals referred to ground on the primary side to
optimum common-mode voltages on the secondary
side. At frequencies below 20kHz the transformer core
begins to saturate, causing odd-order harmonics.
Clock Source Requirements
Pipelined ADCs typically need a 50% duty cycle clock.
To avoid this constraint, the MAX1200 provides a
divide-by-two circuit to relax this requirement. The
clock generator should be chosen commensurate with
the frequency range, amplitude, and slew rate of the
signal source. If the slew rate of the input signal is
small, the jitter requirement on the clock is relaxed.
However, if the slew rate is high, the clock jitter needs
to be kept at a minimum. For a full-scale amplitude
input sine wave, the maximum possible signal-to-noise
ratio (SNR) due completely to clock jitter is given by:
SNRMAX =
V+
IN
INP
MAX4108
1
2 ⋅ π ⋅ fIN ⋅ σ JITTER
For example, if fIN is 500kHz and σJITTER is 10ps RMS,
then the SNR limit due to jitter is about 90dB. Generating
such a clock source requires a low-noise comparator and
a low-phase-noise signal generator. The clock circuit
shown in Figure 6 is a possible solution.
CM
VV+
0.1µF
V+
0.1µF
CLK_IN
INN
MAX4108
1k
5k
CLK
MAX961
V+
VCM
Figure 5. A simple circuit generates differential signals from a
single-ended input referred to analog ground. The commonmode voltage at INP and INN is the same as CM.
10
0.1µF
1k
Figure 6. Clock Generation Circuit Using Low-Noise Comparator
______________________________________________________________________________________
+5V Single-Supply, 1Msps, 16-Bit
Self-Calibrating ADC
The ST_CAL input may be asynchronous with the clock,
since it is retimed internally. With ST_CAL activated,
END_CAL goes low one or two clock cycles later and
remains low until the calibration is complete. During this
period, the reference voltages must be stable to less
than 0.01%; otherwise the calibration will be invalid.
During calibration, the analog inputs INP and INN are
not used; however, better performance is achieved if
these inputs are static. Once END_CAL goes high (indicating that the calibration procedure is complete), the
ADC is ready for conversion.
Once calibrated, the MAX1200 is insensitive to small
changes (±5%) in power-supply voltage or temperature. Following calibration, if the temperature changes
more than ±20°C, the device should be recalibrated to
maintain optimum performance.
N
N+1
AIN
N+5
N+2
tCH
N+4
N+3
tCL
CLK
SAMPLE
CLOCK
tS
DAV
D0–D15
tOD
N-3
N-2
N-1
N
N+1
MAX1200
Calibration Procedure
Since the MAX1200 is based on a pipelined architecture, low-resolution quantizers (“coarse ADCs”) are
used to approximate the input signal. MDACs of the
same resolution are then used to reconstruct the input
signal, which is subtracted from the input and the
residue amplified by the SC gain stage. This residue is
then passed on to the next stage.
The accuracy of the MAX1200 is limited by the precision of the MDAC, which is strongly dependent on the
matching of the capacitors used. The mismatch
between the capacitors is determined and stored in an
on-chip memory, which is later used during the conversion of the input signal.
During the calibration procedure, the clock must be
running continuously. ST_CAL (start of calibration) is
initiated by a positive pulse with a minimum width of
four clock cycles, but not longer than about 17,400
clock cycles (Figure 8).
CLK
ST_CAL
MIN 4 tCLK
END_CAL
~17,400 CLK CYCLES
Figure 8. Timing for Start and End of Calibration
OE
tAC
tREL
D0–D15
DOR
Z
Z
Z = HIGH IMPEDANCE (THREE-STATED)
Figure 9. Timing for Bus Access and Bus Relinquish—
Controlled by Output Enable (OE)
Two’s Complement Output
The MAX1200 outputs data in two’s complement format. Table 1 shows how to convert the various fullscale inputs into their two’s complement output codes.
Applications Information
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization
error only and results directly from the ADC’s resolution
(N bits):
SNR(MAX) = (6.02 · N + 1.76)dB
In reality, there are other noise sources besides quantization noise including thermal noise, reference noise,
clock jitter, etc. Therefore, SNR is computed by taking
the ratio of the RMS signal to the RMS noise which
includes all spectral components minus the fundamental, the first nine harmonics, and the DC offset.
Figure 7. Main Timing Diagram
______________________________________________________________________________________
11
MAX1200
+5V Single-Supply, 1Msps, 16-Bit
Self-Calibrating ADC
Table 1. Two’s Complement Output Codes
SCALE
OFFSET BINARY
ONE’S COMPLEMENT
TWO’S COMPLEMENT
+FSR - 1LSB
1111 .... 1111
0111 .... 1111
0111 .... 1111
+3/4FSR
1110 .... 0000
0110 .... 0000
0110 .... 0000
+1/2FSR
1100 .... 0000
0100 .... 0000
0100 .... 0000
+1/4FSR
1010 .... 0000
0010 .... 0000
0010 .... 0000
+0
1000 .... 0000
0000 .... 0000
0000 .... 0000
-0
—— .... ——
—— .... ——
1111 .... 1111
-1/4FSR
0110 .... 0000
1110 .... 0000
1101 .... 1111
-1/2FSR
0100 .... 0000
1100 .... 0000
1011 .... 1111
-3/4FSR
0010 .... 0000
1010 .... 0000
1001 .... 1111
-FSR +1LSB
0000 .... 0001
1000 .... 0001
1000 .... 0000
-FSR
0000 .... 0000
1000 .... 0000
—— .... ——
Signal-to-Noise
Plus Distortion (SINAD)
Spurious-Free
Dynamic Range (SFDR)
SINAD is the ratio of the fundamental input frequency’s
RMS amplitude to all other ADC output signals:
SFDR is the ratio of RMS amplitude of the fundamental
(maximum signal component) to the RMS value of the
next largest spurious component, excluding DC offset.
SINAD (dB) = 20log [SignalRMS / (Noise +
Distortion)RMS]
Effective Number of Bits (ENOB)
ENOB indicates the global accuracy of an ADC at a
specific input frequency and sampling rate. An ideal
ADC’s error consists of quantization noise only. With an
input range equal to the full-scale range of the ADC, the
effective number of bits can be calculated as follows:
ENOB = (SINAD - 1.76) / 6.02
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first nine harmonics of the input signal to the fundamental itself. This
is expressed as:
  2
2
2
2 
 V + V + V + ⋅⋅⋅ + V  
2
3
4
9
 

THD = 20log 

V1






where V1 is the fundamental amplitude, and V2 through
V9 are the amplitudes of the 2nd through 9th-order harmonics.
12
Grounding and Power-Supply Decoupling
Grounding and power-supply decoupling strongly influence the performance of the MAX1200. At 16-bit resolution, unwanted digital crosstalk may couple through
the input, reference, power supply, and ground connections; this adversely affects the SNR or SFDR. In
addition, electromagnetic interference (EMI) can either
couple into or be generated by the MAX1200.
Therefore, grounding and power-supply decoupling
guidelines should be closely followed.
First, a multilayer printed circuit board (PCB) with separate ground and power-supply planes is recommended. Run high-speed signal traces directly above the
ground plane. Since the MAX1200 has separate analog
and digital ground buses (AGND and DGND respectively), the PCB should also have separate analog and
digital ground sections connected at only one point
(star ground). Digital signals should run above the digital ground plane and analog signals should run above
the analog ground plane. Digital signals should be kept
far away from the sensitive analog inputs, reference
input senses, common-mode input, and clock input.
______________________________________________________________________________________
+5V Single-Supply, 1Msps, 16-Bit
Self-Calibrating ADC
The power-supply voltages should also be decoupled
with large tantalum or electrolytic capacitors at the
point they enter the PCB. Ferrite beads with additional
decoupling capacitors forming a pi network may
improve performance.
The analog power-supply input (AV DD ) for the
MAX1200 is typically +5V while the digital supplies can
vary from +3V to +5V. Usually, DVDD and DRVDD pins
are connected to the same power supply. Note that the
DVDD supply voltage must be greater than or equal to
the DRVDD voltage. For example, a digital +3.3V supply could be connected to DRVDD while a cleaner +5V
supply is connected to DV DD , resulting in slightly
improved performance. Alternatively, the +3.3V supply
could be connected to both DRV DD and DV DD .
However, the +3.3V supply must not be connected to
DVDD while the +5V supply is connected to DRVDD
(Table 2).
Table 2. Power-Supply Voltage
Combinations
AVDD
(V)
DVDD
(V)
DRVDD
(V)
ALLOWED/
NOT ALLOWED
+5
+5
+5
Allowed
+5
+5
+3.3
Allowed
+5
+3.3
+3.3
Allowed
+5
+3.3
+5
Not
Allowed
Chip Information
TRANSISTOR COUNT: 56,577
SUBSTRATE CONNECTED TO AGND
______________________________________________________________________________________
13
MAX1200
The MAX1200 has three power-supply inputs: analog
V DD (AV DD ), digital V DD (DV DD ), and drive V DD
(DRVDD). Each AVDD input should be decoupled with
parallel ceramic chip capacitors of values 0.1µF and
0.001µF, with these capacitors as close to the pin as
possible and with the shortest possible connection to
the ground plane. The DVDD pins should also have
separate 0.1µF capacitors again adjacent to their
respective pins, as should the DRVDD pin. Minimize the
digital load capacitance. However, if the total load
capacitance on each digital output exceeds 20pF, the
DRVDD decoupling capacitor should be increased or,
preferably, digital buffers should be added.
+5V Single-Supply, 1Msps, 16-Bit
Self-Calibrating ADC
MQFP44.EPS
MAX1200
Package Information
14
______________________________________________________________________________________
+5V Single-Supply, 1Msps, 16-Bit
Self-Calibrating ADC
______________________________________________________________________________________
MAX1200
NOTES
15
MAX1200
+5V Single-Supply, 1Msps, 16-Bit
Self Calibrating ADC
NOTES
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 1998 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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