ON NCV7703CD2R2G Triple half-bridge driver with spi control Datasheet

NCV7703C
Triple Half-Bridge Driver
with SPI Control
The NCV7703C is a fully protected Triple Half−Bridge Driver
designed specifically for automotive and industrial motion control
applications. The three half−bridge drivers have independent control.
This allows for high side, low side, and H−Bridge control. H−Bridge
control provides forward, reverse, brake, and high impedance states
(with EN = 0). The drivers are controlled via a standard Serial
Peripheral Interface (SPI).
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MARKING
DIAGRAM
Features
•
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14
Ultra Low Quiescent Current in Sleep Mode, 1 mA for VS and VCC
3 High−Side and 3 Low−Side Drivers Connected as Half−Bridges
Internal Free−Wheeling Diodes
Configurable as H−Bridge Drivers
500 mA (typ), 1.1 A (max) Drivers
RDS(on) = 0.8 W (typ), 1.7 W (max)
5 MHz SPI Control with Daisy Chain Capability
Compliance with 5 V and 3.3 V Systems
Overvoltage and Undervoltage Lockout
Fault Reporting
1.45 A Overcurrent Threshold Detection
3 A Current Limit
Shoot−Through Attempt Detection
Overtemperature Warning and Protection Levels
Internally Fused Leads in SOIC−14 for Better Thermal Performance
ESD Protection up to 6 kV
These are Pb−Free Devices
SOIC−14
D2 SUFFIX
CASE 751A
14
1
NCV7703CG
AWLYWW
1
NCV7703C = Specific Device Code
A
= Assembly Location
WL
= Wafer Lot
Y
= Year
WW
= Work Week
G
= Pb−Free Package
PIN CONNECTIONS
GND
OUT3
VS
CSB
SI
SCLK
GND
GND
OUT1
OUT2
VCC
EN
SO
GND
Typical Applications
• Automotive
• Industrial
• DC Motor Management
VS
ORDERING INFORMATION
VS
VS
M
OUT1
Device
Package
Shipping†
NCV7703CD2R2G
SOIC−14
(Pb−Free)
2500 /
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
M
OUT2
OUT3
Figure 1. Cascaded Application
© Semiconductor Components Industries, LLC, 2016
February, 2018 − Rev. 2
1
Publication Order Number:
NCV7703C/D
NCV7703C
VS
DRIVE 1
EN
ENABLE
VCC
Reference
& Bias
UVLO
OSC
VS
clk
clk
VS
Charge
Pump
Control
Logic
Fault
Detect
High−Side
Driver
Waveshaping
VS
OUT1
Low−Side
Driver
Channel Enable
Waveshaping
SI
SPI
SCLK
Fault
SO
16 Bit
Logic
and
Latch
CSB
VS
Undervoltage
Lockout
VS
Overvoltage
Lockout
Under−Load
Overcurrent
Thermal
Warning/Shutdown
VS
DRIVE 2
clk
Channel Enable
Fault
OUT2
VS
DRIVE 3
clk
Channel Enable
Fault
OUT3
GND
Figure 2. Block Diagram
PACKAGE PIN DESCRIPTION
Pin #
Symbol
Description
1
GND*
Ground. Connect all grounds together.
2
OUT3
Half Bridge Output 3.
3
VS
4
CSB
Power Supply input for the output drivers and internal supply voltage.
Chip Select Bar. Active low serial port operation.
5
SI
Serial Input
6
SCLK
Serial Clock
7
GND*
Ground. Connect all grounds together.
8
GND*
Ground. Connect all grounds together.
9
SO
Serial Output
10
EN
Enable. Logic high wakes the IC up from a sleep mode.
Power supply input for internal logic.
11
VCC
12
OUT2
Half Bridge Output 2.
13
OUT1
Half Bridge Output 1.
14
GND*
Ground. Connect all grounds together.
*Pins 1, 7, 8, and 14 are internally shorted together. It is recommended to also short these pins externally.
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2
NCV7703C
ENABLE
Wake Up
D1*
1N4001
NCV8518
RESET
+
WDI
VBAT
Vout
D2**
C1
22 mF
Delay
120k
GND
VCC
10 mF
VS
OUT1
EN
C2***
10 nF
microprocessor
M
OUT2
C3***
CSB
SI
10 nF
NCV7703C
M
SCLK
OUT3
SO
C4***
GND
GND
GND
GND
10 nF
GND
* D1 optional. For use where reverse battery protection is required.
** D2 optional. For use where load dump exceeds 40V.
*** C2−C4, Recommended for EMC performance.
Figure 3. Application Circuit
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3
−
NCV7703C
MAXIMUM RATINGS
Rating
Value
Unit
Power Supply Voltage (VS)
(DC)
(AC), t < 500 ms, Ivs > −2 A
−0.3 to 40
−1
V
Output Pin OUTx
(DC)
(AC), t < 500 ms, IOUTx > −2 A
−0.3 to 40
−1
V
Pin Voltage
(Logic Input pins, SI, SCLK, CSB, SO, EN, VCC)
−0.3 to 5.5
Output Current (OUTx)
(DC)
(AC) (50 ms pulse, 1 s period)
V
A
−1.8 to 1.8
−5.0 to 5.0
Electrostatic Discharge, Human Body Model,
VS, OUT1, OUT2, OUT3 (Note 3)
6
kV
Electrostatic Discharge, Human Body Model,
all other pins (Note 3)
2
kV
Electrostatic Discharge, Machine Model,
VS, OUT1, OUT2, OUT3 (Note 3)
300
V
Electrostatic Discharge, Machine Model,
all other pins (Note 3)
200
V
Operating Junction Temperature
−40 to 150
°C
Storage Temperature Range
−55 to 150
°C
MSL3
−
Moisture Sensitivity Level (MAX 260°C Processing)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Thermal Parameters
Test Conditions (Typical Value)
14 Pin Fused SOIC Package
Unit
min−pad board
(Note 1)
1″ pad board
(Note 2)
Junction−to−Lead (psi−JL8, YJL8) or Pins 1, 7, 8, 14
23
22
°C/W
Junction−to−Ambient (RqJA, qJA)
122
83
°C/W
1. 1−oz copper, 67 mm2 copper area, 0.062″ thick FR4.
2. 1−oz copper, 645 mm2 copper area, 0.062″ thick FR4.
3. This device series incorporates ESD protection and is characterized by the following methods:
ESD HBM according to AEC−Q100−002 (EIA/JESD22−A114)
ESD MM according to AEC−Q100−003 (EIA/JESD22−A115)
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4
NCV7703C
ELECTRICAL CHARACTERISTICS
(−40°C ≤ TJ ≤ 150°C, 5.5 V ≤ VS ≤ 40 V, 3.15 V ≤ VCC ≤ 5.25 V, EN = VCC, unless otherwise specified)
Characteristic
Conditions
Min
Typ
Max
Unit
VS = 13.2 V, OUTx = 0 V
EN = SI = SCLK = 0 V, CSB = VCC
0 V < VCC < 5.25 V
(TJ = −40°C to 85°C)
−
1.0
5.0
mA
VS = 13.2 V, OUTx = 0 V
EN = SI = SCLK = 0 V, CSB = VCC
0 V < VCC < 5.25 V, TJ = 25°C
−
−
2.0
mA
Supply Current (VS)
Active Mode
EN = VCC, 5.5 V < VS < 35 V
No Load
−
2.0
4.0
mA
Supply Current (VCC)
Sleep Mode (Note 6)
VCC = CSB, EN = SI = SCLK = 0 V
(TJ = −40°C to 85°C)
−
0.1
2.5
mA
Supply Current (VCC)
Active Mode
EN = VCC
−
1.5
3.0
mA
−
2.55
2.90
V
GENERAL
Supply Current (VS)
Sleep Mode (Note 5)
VCC Power−On−Reset Threshold
VS Undervoltage Detection
Threshold VS decreasing
Hysteresis
3.7
100
4.1
365
4.5
450
V
mV
VS Overvoltage Detection
Threshold VS increasing
Hysteresis
33.0
1.0
36.5
2.5
40.0
4.0
V
Thermal Warning (Note 4)
Threshold
Hysteresis
120
−
140
20
170
−
°C
Thermal Shutdown (Note 4)
Threshold
Hysteresis
155
−
175
30
195
−
°C
1.05
1.20
−
°C/°C
Ratio of Thermal Shutdown to Thermal
Warning temperature (Note 4)
OUTPUTS
Output RDS(on) (Source)
Iout = −500 mA
−
−
1.7
W
Output RDS(on) (Sink)
Iout = 500 mA
−
−
1.7
W
Source Leakage Current
Sum of I(OUTx) x = 1, 2, 3
OUTx = 0 V, VS = 40 V, EN = 0 V
CSB = VCC
0 V < VCC < 5.25 V
Sum(I(OUTx)
−5.0
−
−
mA
OUTx = 0 V, VS = 40 V, EN = 0 V
CSB = VCC
0 V < VCC < 5.25 V, TJ = 25°C
Sum(I(OUTx)
−1.0
−
−
OUTx = VS = 40 V, EN = 0 V
CSB = VCC
0 V < VCC < 5.25 V
−
−
300
OUTx = VS = 13.2 V, EN = 0 V
CSB = VCC
0 V < VCC < 5.25 V, TJ = 25°C
−
−
10
Sink Leakage Current
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Thermal characteristics are not subject to production test
5. For temperatures above 85°C, refer to Figure 6.
6. For temperatures above 85°C, refer to Figure 7.
7. Current limit is active with and without overcurrent detection.
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5
NCV7703C
ELECTRICAL CHARACTERISTICS
(−40°C ≤ TJ ≤ 150°C, 5.5 V ≤ VS ≤ 40 V, 3.15 V ≤ VCC ≤ 5.25 V, EN = VCC, unless otherwise specified)
Characteristic
Conditions
Min
Typ
Max
Unit
−17
2.0
−7.0
7.0
−2.0
17
mA
−
0.9
1.3
V
OUTPUTS
Under Load Detection Threshold
Source
Sink
Power Transistor Body Diode Forward Voltage If = 500 mA
OVERCURRENT
Overcurrent Shutdown Threshold (OUTHx)
VCC = 5 V, Vs = 13.2 V
−2.0
−1.45
−1.1
A
Overcurrent Shutdown Threshold (OUTLx)
VCC = 5 V, Vs = 13.2 V
1.1
1.45
2.0
A
−5.0
−3.0
−2.0
2.0
3.0
5.0
CURRENT LIMIT (Note 7)
Current Limit (OUTHx)
Current Limit (OUTLx)
VCC = 5 V, Vs = 13.2 V
A
VCC = 5 V, Vs = 13.2 V,
A
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Thermal characteristics are not subject to production test
5. For temperatures above 85°C, refer to Figure 6.
6. For temperatures above 85°C, refer to Figure 7.
7. Current limit is active with and without overcurrent detection.
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6
NCV7703C
ELECTRICAL CHARACTERISTICS
(−40°C ≤ TJ ≤ 150°C, 5.5 V ≤ VS ≤ 40 V, 3.15 V ≤ VCC ≤ 5.25 V, EN = VCC, unless otherwise specified)
Characteristic
Symbol
Conditions
Min
Typ
Max
Unit
Input Threshold
High
Low
2.0
−
−
−
−
0.8
Input Hysteresis (EN, SI, SCLK, CSB)
100
400
800
mV
LOGIC INPUTS (EN, SI, SCLK, CSB)
V
Pulldown Resistance (EN, SI, SCLK)
EN = SI = SCLK = VCC
50
125
250
kW
Pullup Resistance (CSB)
CSB = 0 V
50
125
250
kW
−
10
15
pF
VCC – 1.0
VCC – 0.7
−
V
−
0.2
0.4
V
−10
−
10
mA
−
10
15
pF
Input Capacitance (Note 8)
LOGIC OUTPUT (SO)
Output High
Iout = 1 mA
Output Low
Iout = −1.6 mA
Tri−state Leakage
CSB = VCC, 0 V v SO v VCC
Tri−state Input Capacitance (Note 8)
CSB = VCC
TIMING SPECIFICATIONS
200
350
600
ms
VCC = 5 V, Vs = 13.2 V,
Bit13 = 0
Bit13 = 1
80
10
200
25
400
50
ms
ms
Under Load Detection Delay Time
Overcurrent Shutdown Delay Time
High Side Turn On Time
ThsOn
VS = 13.2 V, Rload = 25 W
−
7.5
15
ms
High Side Turn Off Time
ThsOff
VS = 13.2 V, Rload = 25 W
−
3.0
6.0
ms
Low Side Turn On Time
TlsOn
VS = 13.2 V, Rload = 25 W
−
6.5
15
ms
Low Side Turn Off Time
TlsOff
VS = 13.2 V, Rload = 25 W
−
3.0
6.0
ms
High Side Rise Time
ThsTr
VS = 13.2 V, Rload = 25 W
−
5.0
10
ms
High Side Fall Time
ThsTf
VS = 13.2 V, Rload = 25 W
−
2.0
5.0
ms
Low Side Rise Time
TlsTr
VS = 13.2 V, Rload = 25 W
−
1.0
3.0
ms
Low Side Fall Time
TlsTf
VS = 13.2 V, Rload = 25 W
−
1.0
3.0
ms
NonOverlap Time
ThsOffLsOn
High Side Turn Off to Low Side Turn On
1.0
−
−
ms
NonOverlap Time
TlsOffHsOn
Low Side Turn Off to High Side Turn On
1.0
−
−
ms
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
8. Not production tested.
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7
NCV7703C
ELECTRICAL CHARACTERISTICS
(−40°C < TJ < 150°C, 5.5 V < VS < 3.15 V < VCC < 5.25 V, EN = VCC, unless otherwise specified)
Characteristic
Conditions
Symbol
Min
Typ
Max
Unit
−
−
−
5.0
MHz
SERIAL PERIPHERAL INTERFACE (VCC = 5 V)
SCLK Frequency
SCLK Clock Period
VCC = 5 V
VCC = 3.3 V
−
200
500
−
−
−
−
ns
Maximum Input Capacitance (Note 9)
SI, SCLK
−
−
−
12
pF
SCLK High Time
TCLKH
85
−
−
ns
SCLK Low Time
TCLKL
85
−
−
ns
TCLKSU1
TCLKSU2
85
85
−
−
−
−
ns
SI Setup Time
TISU
50
−
−
ns
SI Hold Time
TIHT
50
−
−
ns
TCSBSU1
TSSBSU2
100
100
−
−
−
−
ns
TCSBHT
5.0
−
−
ms
SO enable after CSB falling edge
TSOCSBF
−
−
50
ns
SO disable after CSB rising edge
TSOCSBR
−
−
50
ns
SCLK Setup Time
CSB Setup Time
CSB High Time (Note 10)
SO Rise Time (10% to 90%)
Cload = 40 pF
−
−
10
25
ns
SO Fall Time (90% to 10%)
Cload = 40 pF
−
−
10
25
ns
SO Valid Time (Note 9)
SCLK High to SO 50%
TSOV
−
50
100
ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
9. Not tested in production
10. This is the minimum time the user must wait between SPI commands.
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8
NCV7703C
CHARACTERISTIC TIMING DIAGRAMS
TlsTr
90%
TlsOff
50%
10%
LS Turn OFF
TlsOffHsOn
90%
50%
10%
HS Turn ON
ThsTr
50%
ThsOn
CSB
LS Turn On
TlsTf
90%
50%
TlsOn
10%
HS Turn Off
ThsOffLsOn
90%
50%
10%
ThsTf
50%
CSB
ThsOff
Figure 4. Detailed Driver Timing
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9
NCV7703C
TCLKSU2
TCSBHT
CSB
50%
SCLK
50%
TCSBSU1
50%
TCSBSU2
50%
TCLKSU1
50%
TCLKH
50%
50%
TCLKL
CSB
50%
50%
50%
50%
SO
TSOCSBF
TSOCSBR
SI
50%
50%
TIHT
50%
50%
SCLK
TSOV
SO
50%
TISU
50%
Figure 5. SPI Timing Diagram
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10
50%
NCV7703C
4.0
6.0
3.5
VS = 13.2 V
VCC SLEEP CURRENT (mA)
VS SLEEP CURRENT (mA)
7.0
5.0
4.0
3.0
2.0
1.0
0
20
40
60
80
3.0
2.5
2.0
1.5
1.0
0.5
VCC = 0 V to 5.25 V
0
−40 −20
VS = 5.25 V
0
−40 −20
100 120 140 160
TJ, TEMPERATURE (°C)
0
20
40
60
80
100 120 140 160
TJ, TEMPERATURE (°C)
Figure 6. VS Sleep Supply Current vs. Temperature
Figure 7. VCC Sleep Supply Current vs. Temperature
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11
NCV7703C
TYPICAL CHARACTERISTICS
140
120
1 oz Cu
qJA (°C/W)
100
80
2 oz Cu
60
40
20
0
0
100
200
300
400
500
600
COPPER HEAT SPREADING AREA
700
800
(mm2)
Figure 8. qJA vs. Copper Spreader Area,
14 Lead SON (fused leads)
1000
Cu Area = 100 mm2 1.0 oz
R(t) (°C/W)
100
200 mm2 1.0 oz
10
300 mm2 1.0 oz
400 mm2 1.0 oz
500 mm2 1.0 oz
1
0.1
0.01
0.000001 0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
TIME (sec)
Figure 9. Transient Thermal Response to a
Single Pulse 1 oz Copper (Log−Log)
140
Cu Area = 100 mm2 1.0 oz
R(t) (°C/W)
120
200 mm2 1.0 oz
100
300 mm2 1.0 oz
80
400 mm2 1.0 oz
500 mm2 1.0 oz
60
40
20
0
0.000001 0.00001
0.0001
0.001
0.01
0.1
1
TIME (sec)
Figure 10. Transient Thermal Response to a
Single Pulse 1 oz Copper (Semi−Log)
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12
10
100
1000
NCV7703C
SPI Communication
Frame Detection
Standard 16−bit communication has been implemented to
this IC to turn drivers on/off, and to report faults. (See
Figure 12). The LSB (Least Significant Bit) is clocked in
first.
Input word integrity (SI) is evaluated by the use of a frame
consistency check. The word frame length is compared to an
h x 16 bit acceptable word length before the data is latched
into the input register. This guarantees the proper word
length has been imported and allows for daisy chain
operation applications.
The frame length detector is enabled with the CSB falling
edge and the SCLK rising edge.
SCLK must be low during the CSB rising edge. The fault
register is cleared with a valid frame detection. Existing
faults are re−latched after the fault filter time.
Communication is Implemented as Follows:
1. CSB goes low to allow serial data transfer.
2. A 16 bit word is clocked (SCLK) into the SI
(Serial Input) pin.
3. CSB goes high to transfer the clocked in
information to the data registers.
NOTE: SO is tristate when CSB is high.
Frame detection starts
after the CSB falling edge
and the SCLK rising edge.
Frame detection mode ends with
CSB rising edge.
CSB
SCLK
SI
SRR
OUTL1 OUTH1 OUTL2 OUTH2 OUTL3 OUTH3
Internal Counter 1
2
3
4
5
6
X
X
7
8
9
X
X
X
X
OCD
10
11
12
13
ULDSD OVLO
14
15
16
Valid 16 bits shown
Figure 11. Frame Detection
CSB
SI
SRR
OUTL1 OUTH1 OUTL2 OUTH2 OUTL3 OUTH3
X
X
X
X
X
X
OUTL1 OUTH1 OUTL2 OUTH2 OUTL3 OUTH3
X
X
X
X
X
STA
OCD
ULDSD OVLO
SCLK
SO
TW
OCDR ULDR
PSF
Figure 12. SPI Communication Frame Format
clocked into the SI pin of the device. Daisy chain
communication between SPI compatible IC’s is possible by
connection of the Serial Output pin (SO) to the input of the
sequential IC (SI) (Reference the Daisy Chain Section).
Table 1 defines the programming bits and diagnostic bits.
Figure 12 displays the timing diagram associated with
Table 1. Fault information is sequentially clocked out the
SO pin of the NCV7703C as programming information is
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13
NCV7703C
Table 1. SPI BIT DESCRIPTION
Input Data
Output Data
Bit Number
Bit Description
Bit Status
Bit Number
Bit Description
Bit Status
15
Over Voltage Lock Out
Control (OVLO)
0 = Disable
15
Power Supply Fail Signal
(PSF for OVLO or UVLO)
0 = No Fault
Under Load Detection Shut
Down Control (ULDSD)
0 = Disable
Under Load Detection Reporting
Signal (ULDR)
0 = No Fault
Over Current Detection Shut
Down Control (OCD)
0 = 200 msec
Over Current Detection
Reporting Signal (OCDR)
0 = No Fault
Shoot−Through Attempt
(STA)
0 = No Attempt
14
13
12
1 = Enable
14
1 = Enable
13
1 = 25 msec
Not Used
12
11
Not Used
11
Not Used
10
Not Used
10
Not Used
9
Not Used
9
Not Used
8
Not Used
8
Not Used
7
Not Used
7
Not Used
6
OUTH3
6
OUTH3
0 = Off
1 = On
5
OUTL3
4
OUTH2
0 = Off
5
OUTL3
4
OUTH2
1 = On
OUTH1
1
OUTL1
3
0 = Off
OUTL2
0 = Off
0 = Off
0 = Off
0 = Off
2
OUTH1
1
OUTL1
0 = Off
1 = On
0 = Off
1 = On
Status Register Reset (SRR)
0 = Off
1 = On
1 = On
0
1 = Attempt
1 = On
1 = On
2
1 = Fault
1 = On
0 = Off
OUTL2
1 = Fault
1 = On
1 = On
3
1 = Fault
0 = Off
1 = On
0
0 = No Reset
Thermal Warning (TW)
1 = Reset
0 = Not in TW
1 = In TW
DETAILED OPERATING DESCRIPTION
General
Power Up/Down Control
The NCV7703C Triple Half Bridge Driver provides drive
capability for 3 Half−Bridge configurations. Each output
drive is characterized for a 500 mA load and has a typical
1.4 A surge capability. Strict adherence to integrated circuit
die temperature is necessary, with a maximum die
temperature of 150°C. This may limit the number of drivers
enabled at one time. Output drive control and fault reporting
are handled via the SPI (Serial Peripheral Interface) port.
An Enable function (EN) provides a low quiescent sleep
current mode when the device is not being utilized. A pull
down is provided on the EN, SI and SCLK inputs to ensure
they default to a low state in the event of a severed input
signal. A pull−up is provided on the CSB input disabling SPI
communication in the event of an open CSB input.
A feature incorporated in the IC is an under voltage
lockout circuit that prevents the output drivers from turning
on unintentionally. VCC and VS are monitored for
undervoltage conditions supporting a smooth turn−on
transition. All drivers are initialized in the off (high
impedance) condition, and will remain off during a VCC or
VS undervoltage condition. This allows power up
sequencing of VCC, and VS up to the user. Once VCC is out
of UVLO, SPI communication can begin regardless of the
voltage on VS. The VS supply input does not ever affect the
SPI logic. However, drivers will remain off if VS is in an
undervoltage condition. Hysteresis in the UVLO circuits
results in glitch free operation during power up/down.
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14
NCV7703C
Overvoltage Shutdown (Table 2)
to “1”, all outputs will turn off during this overvoltage
condition. Turn On/Off status is maintained in the logic
circuitry, so that when proper input voltage level is
reestablished, the programmed outputs will turn back on.
The PSF output bit is reset with SRR = 1.
Overvoltage lockout circuitry monitors the voltage on the
VS pin. The response to an overvoltage condition is selected
by SPI input bit 15. PSF output bit 15 is set when a VS
overvoltage condition exists. If input bit 15 (OVLO) is set
Table 2. INPUT BIT 15, OVERVOLTAGE LOCK OUT (OVLO) SHUT DOWN
OVLO Input
Bit 15
VS OVLO
Condition
Output Data Bit 15 Power
Supply Fail (PSF) Status
OUTx Status
0
0
0
Unchanged
0
1
1 (Need SRR to reset)
Unchanged
1
0
0
Unchanged
1
1
1 (Need SRR to reset)
All Outputs Shut Off (Remain off until VS is out of OVLO)
H−Bridge Driver Configuration
Detection shutdown protects the device during current limit
because the Overcurrent threshold is below the Current
Limit threshold. The Overcurrent Detection Shutdown
Control Timer is initiated at the Overcurrent Shutdown
Threshold which starts before the Current Limit is reached.
Note: High currents will cause a rise in die temperature.
Devices will not be allowed to turn on if the die temperature
exceeds the thermal shutdown temperature.
The NCV7703C has the flexibility of controlling each half
bridge driver independently. This allows for high side, low
side and H−bridge control. H−bridge control provides
forward, reverse, brake and high impedance states.
Overvoltage Clamping − Driving Inductive Loads
Each output is internally clamped to ground and VS by
internal freewheeling diodes. The diodes have ratings that
complement the FETs they protect. A flyback event from
driving an inductive load causes the voltage on the output to
rise up. Once the voltage rises higher than VS by a diode
voltage (body diode of the high−side driver), the energy in
the inductor will dissipate through the diode to VS. If a
reverse battery diode is used in the system, care must be
taken to insure the power supply capacitor is sufficient to
dampen any increase in voltage to VS caused by the current
flow through the body diode so that it is below 40 V.
Negative transients will momentarily occur when a
high−side driver driving an inductive load is turned off. This
will be clamped by an internal diode from the output pin
(OUT1 or OUT2) to the IC ground.
Shoot−Through Attempt
The NCV7703C provides detection for attempting to turn
on common drivers of the same channel (OUTL1&OUTH1,
OUTL2&OUTH2, OUTL3&OUTH3) simultaneously. An
attempt to turn on common drivers if allowed would result
in a high current event from VS to GND. Any attempt to
create this setup is recorded in bit 12 of the output data and
forces the common high−side and low−side driver to an off
state. The STA output bit is reset with SRR = 1. The STA bit
must be cleared before an affected driver can turn on.
Overcurrent Shutdown
Effected outputs will turn off when the Overcurrent
Shutdown Threshold has been breached for the Overcurrent
Shutdown Delay Time. The respective OCDR status bit will
be set to a “1” and the driver will latch off. The driver can
only be turned back on via the SPI port with a SPI command
that includes an SRR = 1.
Note: High currents will cause a rise in die temperature.
Devices will not be allowed to turn on if the die temperature
exceeds the thermal shutdown temperature.
Current Limit
OUTx current is limited per the Current Limit electrical
parameter for each driver. The magnitude of the current has
a minimum specification of 2 A at VCC = 5 V and Vs =
13.2 V. The output is protected for high power conditions
during Current Limit by thermal shutdown and the
Overcurrent Detection shutdown function. Overcurrent
Table 3. OVERCURRENT DETECTION SHUT DOWN
OCD Input
Bit 13
OUTx OCD
Condition
Output Data Bit 13 Over
Current Detect (OCDR) Status
OUTx Status
Current Limit
of all Drivers
0
0
0
0
Unchanged
3A
1
1 (Need SRR to reset)
OUTx Latches off after 200 ms
(Need SRR to reset)
3A
1
0
0
Unchanged
3A
1
1
1 (Need SRR to reset)
OUTx Latches Off After 25 ms
(Need SRR to reset)
3A
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15
NCV7703C
Overcurrent Detection Shut Down Control Timer
There are two protection mechanisms for output current,
overcurrent and current limit.
1. Current limit − Always active with a typical
threshold of 3 A (typ).
2. Overcurrent Detection − Selectable shutdown time
via Bit 13 with a 1.45 A (typ) threshold.
Figure 13 shows the typical performance of a part which
has exceeded the 1.45 A (typ) Overcurrent Detection
threshold and started the shutdown control timer. When Bit
13 = 1, the shutdown time is 25 msec (typ). When Bit 13 =
0, the shutdown time is 200 msec (typ).
Once an Overcurrent Shutdown Delay Time event has
been detected by the NCV7703C, the timer setting cannot be
interrupted by an attempted change via a SPI command of
Bit 13.
Table 4.
Input Bit 13
Overcurrent Shutdown Delay Time
0
200 msec (typ)
1
25 msec (typ)
(Current Limit) 3 A
(Current Limit) 1.45 A
OUTx Current
Bit13 = 1
25 msec (typ)
(Current Limit) 3 A
(Current Limit) 1.45 A
OUTx Current
Bit13 = 0
200 msec (typ)
Figure 13. Output Current Shutdown Control
UnderLoad Detection (Table 5)
under load occurs in another channel after the global timer
has been started, the delay for any subsequent under load
will be the remainder of the initially started timer. The timer
runs continuously with any persistent under load condition
and will impact multi−underload situations. The under load
detect bit is reset by setting input data bit 0, SRR = 1. Figures
14 and 15 highlight the timing conditions for an underload
state where the global timer is reset (discontinuous time) and
the conditions where the global timer is not reset
(continuous time).
The underload detection circuit monitors the current from
each output driver. A minimum load current (this is the
maximum open circuit detection threshold) is required when
the drivers are turned on. If the under−load detection
threshold has been detected continuously for more than the
under−load delay time, the ULDR bit (output bit #14) will
be set to a “1”. In addition, the offending driver will be
latched off if input Bit 14 (ULDSD) is set to 1 (true).
The NCV7703C uses a global under load timer. An under
load condition starts the global under load delay timer. If
Table 5. OUTPUT BIT 14, UNDER LOAD DETECTION SHUT DOWN
ULDSD Input
Bit 14
OUTx ULD
Condition
Output Data Bit 14, Under
Load Detect (ULDR) Status
OUTx Status
0
0
0
Unchanged
0
1
1 (Need SRR to reset)
Unchanged
1
0
0
Unchanged
1
1
1 (Need SRR to reset)
OUTx Latches Off (Need SRR to reset)
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16
NCV7703C
load[mA]
OUTx
OUTy
7[mA](typ)
Underload Detection Threshold
Bit 14 − Underload Detection Reporting Signal (ULDR) is set
Time
<350[us](typ)
>350[us](typ)
Global Timer
resets
here
If the 1st underload condition is <350 us,
the global timer resets and starts again
with the 2 nd underload condition.
Figure 14. Underload Discontinuous Time
load[mA]
OUTx
OUTy
7[mA](typ)
Underload Detection Threshold
Bit 14 − Underload Detection Reporting Signal (ULDR) is set
Time
350[us](typ)
After a total continuous period is more than 350[us] (typ)
(underload detection time), Bit 14 in the output register is set
Figure 15. Underload Continuous Time
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17
NCV7703C
Thermal Shutdown
software polling of this bit will allow for load control and
possible prevention of thermal shutdown conditions.
Thermal warning information can be retrieved
immediately without performing a complete SPI access
cycle. Figure 16 below displays how this is accomplished.
Bringing the CSB pin from high to low with SI = 0
immediately displays the information on Output Data Bit 0,
thermal warning. As the temperature of the NCV7703C
changes from a condition from below the thermal warning
threshold to above the thermal warning threshold, the state
of the SO pin changes and this level is available immediately
when the CSB goes low. A low on SO indicates there is no
thermal warning, while a high indicates the IC is above the
thermal warning threshold. This warning bit is reset by
setting SRR to “1”.
Three independent thermal shutdown circuits are featured
(one common sensor for each HS and LS transistor pair).
Each sensor has two temperature levels; Level 1, Thermal
Warning sets the “TW” status bit to a 1 and would have to
be reset with a command that includes the SRR after the IC
cools to a temperature below Level 1. The output will remain
on in this condition.
If the IC temperature reaches Level 2, Over Temperature
Shutdown, all drivers are latched off. It can be reset only
after the part cools below the shutdown temperature,
(including thermal hysteresis) with a turn−on command that
includes the SRR set bit.
The output data bit 0, Thermal Warning, will latch and
remain set, even after cooling, and is reset by sending a SPI
command to reset the status register (SRR, input 0 set to
“1”). Since thermal warning precedes a thermal shutdown,
CSB
CSB
SCLK*
SCLK*
Tristate Level
SO
SO
TWH
NTW
Tristate Level
Thermal Warning High
No Thermal Warning
*SCLK can be high or low in order to maintain the thermal information on SO. Toggling SCLK will cause other output bits to shift out.
TWH = Thermal Warning High
NTW = No Thermal Warning
Figure 16. Access to Temperature Warning Information
Applications Drawing
Daisy Chain
The NCV7703C is capable of being setup in a daisy chain
configuration with other similar devices which include
additional NCV7703C devices as well as the NCV7708
Double Hex Driver. Particular attention should be focused
on the fact that the first 16 bits which are clocked out of the
SO pin when the CSB pin transitions from a high to a low
will be the Diagnostic Output Data. These are the bits
representing the status of the IC and are detailed in the SPI
Bit Description Table. Additional programming bits should
be clocked in which follow the Diagnostic Output bits. Word
length must be h x 16 due to the use of frame detection.
www.onsemi.com
18
m icroprocessor
NCV7703C
CSB
SCLK
CSB
SCLK
CSB
SCLK
CSB
SCLK
NCV7703C
NCV7703C
NCV7708C
NCV7708C
SI
SI
SI
SI
SO
SO
SO
SO
Figure 17. Daisy Chain Operation
Parallel Control
A more efficient way to control multiple SPI compatible
devices is to connect them in a parallel fashion and allow
each device to be controlled in a multiplex mode. The
diagram below shows a typical connection between the
microprocessor or microcontroller and multiple SPI
compatible devices. In a daisy chain configuration, the
programming information for the last device in the serial
string must first pass through all the previous devices. The
parallel control setup eliminates that requirement, but at the
cost of additional control pins from the microprocessor for
each individual CSB pin for each controllable device. Serial
data is only recognized by the device that is activated
through its respective CSB pin.
VS
OUTx
NCV7703C
SI
SCLK
microprocessor
SO
CSB
chip1
CSB
chip2
CSB
chip3
SI
SCLK
CSB OUT1
SO
OUT2
OUT3
OUTx
NCV7703C
SI
SCLK
CSB OUT1
SO
OUT2
OUT3
GND
NCV7703C
Figure 18. Parallel Control
SI
SCLK
CSB OUT1
SO
OUT2
OUT3
Figure 19. High−Side / Low−Side Application Drawing
Any combination of H−bridge and high or low−side
drivers can be designed in. This allows for flexibility in
many systems.
Additional Application Setup
In addition to the cascaded H−Bridge application shown
in Figure 1, the NCV7703C can also be used as a high−side
driver or low−side driver (Figure 19).
www.onsemi.com
19
NCV7703C
PACKAGE DIMENSIONS
D
SOIC−14 NB
CASE 751A−03
ISSUE K
A
B
14
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
8
A3
E
H
L
1
0.25
M
DETAIL A
7
B
13X
M
b
0.25
M
C A
S
B
S
DETAIL A
h
A
X 45 _
M
A1
e
DIM
A
A1
A3
b
D
E
e
H
h
L
M
C
SEATING
PLANE
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.19
0.25
0.35
0.49
8.55
8.75
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
INCHES
MIN
MAX
0.054 0.068
0.004 0.010
0.008 0.010
0.014 0.019
0.337 0.344
0.150 0.157
0.050 BSC
0.228 0.244
0.010 0.019
0.016 0.049
0_
7_
SOLDERING FOOTPRINT*
6.50
14X
1.18
1
1.27
PITCH
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
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NCV7703C/D