LAPIS MSM56V16161N-6 2-bankã 524,288-wordã 16-bit synchronous dynamic ram Datasheet

FEDD56V16161N-01
Issue Date : April 27, 2016
MSM56V16161N
2-Bank×524,288-Word×16-Bit SYNCHRONOUS DYNAMIC RAM
DESCRIPTION
The MSM56V16161N is a 2-Bank  524,288-word  16-bit Synchronous dynamic RAM. The device
operates at 3.3V. The inputs and outputs are LVTTL compatible.
FEATURES
Product Name
MSM56V16161N
Organization
2Bank x 524,288Word x 16Bit
Address Size
2,048Row x 256Column
Power Supply VCC (Core)
3.3V0.3V
Power Supply VCCQ (I/O)
3.3V0.3V
Interface
LVTTL compatible
Operating Frequency
Max. 166MHz (Speed Rank 6)
Operating Temperature
0 to 70°C
Function
Standard SDRAM command interface
/CAS Latency
2, 3
Burst Length
1, 2, 4, 8, Full page
Burst Type
Sequential, Interleave
Write Mode
Burst, Single
Refresh
Package
Auto-Refresh, 4,096cycle/64ms (0°C  Ta  70°C), Self-Refresh
50-Pin Plastic TSOP(II) (Cu frame)
(P-TSOP(2)50-400-0.80-ZK)
PRODUCT FAMILY
Family
Max. Frequency
MSM56V16161N -6
Access Time (Max.)
tAC2
tAC3
166MHz
5.4ns
5.4ns
MSM56V16161N -7
143MHz
5.4ns
5.4ns
MSM56V16161N -75
133MHz
5.4ns
5.4ns
MSM56V16161N -10
100MHz
6ns
6ns
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FEDD56V16161N-01
MSM56V16161N
PIN CONFIGURATION (TOP VIEW)
50-Pin Plastic TSOP(II)
VCC
DQ0
DQ1
VSSQ
DQ2
DQ3
1
2
3
4
5
6
VCCQ 7
DQ4 8
DQ5 9
VSSQ 10
DQ6 11
DQ7 12
VCCQ 13
LDQM 14
/WE 15
/CAS 16
/RAS 17
/CS 18
A11 19
A10 20
A0 21
A1 22
A2 23
A3 24
VCC 25
50
49
48
47
VSS
DQ15
DQ14
VSSQ
46 DQ13
45 DQ12
44 VCCQ
43 DQ11
42 DQ10
41 VSSQ
40 DQ9
39 DQ8
38
9 VCCQ
37 NC
36 UDQM
35 CLK
34 CKE
33 NC
32 A9
31 A8
30 A7
29 A6
28 A5
27 A4
26 VSS
Pin Name
Function
Pin Name
Function
CLK
System Clock
UDQM, LDQM
Data Input / Output Mask
/CS
Chip Select
DQi
Data Input / Output
CKE
Clock Enable
VCC
Power Supply (3.3V)
A0 to A10
Address
VSS
Ground (0V)
A11
Bank Select Address
VCCQ
Data Output Power Supply (3.3V)
/RAS
Row Address Strobe
VSSQ
Data Output Ground (0V)
/CAS
Column Address Strobe
NC
No Connection
/WE
Write Enable
Note : The same power supply voltage must be provided to every VCC pin .
The same power supply voltage must be provided to every VCCQ pin.
The same GND voltage level must be provided to every VSS pin and VSSQ pin.
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FEDD56V16161N-01
MSM56V16161N
PIN DESCRIPTION
CLK
Clock (Input)
Fetches all inputs at the “H” edge.
Clock Enable (Input)
CKE
Masks system clock to deactivate the subsequent CLK operation.
If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is
deactivated. CKE should be asserted at least one cycle prior to a new command.
Chip Select (Input)
/CS
Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE
and UDQM, LDQM.
Row Address Strobe (Input)
/RAS
Functionality depends on the combination with other signals. For detail, see the function truth
table.
Column Address Strobe (Input)
/CAS
Functionality depends on the combination with other signals. For detail, see the function truth
table.
Write Enable (Input)
/WE
Functionality depends on the combination with other signals. For detail, see the function truth
table.
Bank Address (Input)
A11
Slects bank to be activated during row address latch time and selects bank for precharge and
read/write during column address latch time.
A0 to A10
Row & column multiplexed. (Input)
Row address
: RA0 – RA10
Column Address
: CA0 – CA7
DQ0 to DQ15
3-state Data Bus (Input/Output)
DQ Mask (Input)
UDQM, LDQM
Masks the read data of two clocks later when DQM are set “H” at the “H” edge of the clock
signal. Masks the write data of the same clock when DQM are set “H” at the “H” edge of the
clock signal. UDQM controls DQ7 to DQ15, LDQM controls DQ0 to DQ7.
Power Supply (Core), Ground (Core)
VCC, VSS
The same power supply voltage must be provided to every VCC pin.
The same GND voltage level must be provided to every VSS pin.
Power Supply (I/O), Ground (I/O)
VCCQ, VSSQ
The same power supply voltage must be provided to every VCCQ pin.
The same GND voltage level must be provided to every VSSQ pin.
NC
No Connection
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FEDD56V16161N-01
MSM56V16161N
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
VIN, VOUT
–0.5 to VCC+0.5
V
VCC
–0.5 to 4.6
V
VCCQ
–0.5 to 4.6
V
Power Dissipation (Ta=25°C)
PD
1000
mW
Short Circuit Output Current
IOS
50
mA
Storage Temperature
Tstg
–55 to 150
°C
Operating Temperature
Topr
0 to 70
°C
Voltage on Input/Output Pin Relative to VSS
VCC Supply Voltage
VCCQ Supply Voltage
Notes: 1. Permanent device damage may occur if Absolute Maximum Ratings are exceeded.
2. Functional operation should be restricted to recommended operating condition.
3. Exposure to higher than recommended voltage for extended periods of time could affect device
reliability.
4. The voltages are referenced to VSS.
Recommended Operating Conditions (1/2)
Ta= 0 to 70C
Parameter
Symbol
Min.
Typ.
Max.
Unit
Note
Power Supply Voltage (Core)
VCC
3.0
3.3
3.6
V
1
Power Supply Voltage (I/O)
VCCQ
3.0
3.3
3.6
V
1
Ground
VSS, VSSQ
0
0
0
V
Notes: 1. The voltages are referenced to VSS
2. The power supply voltages should input stable voltage. The power supply voltages should not input
oscillated voltage. If voltages
Recommended Operating Conditions (2/2)
Ta= 0 to 70C
Unit
Note
Parameter
Symbol
Min.
Max.
Input High Voltage
VIH
2.0
VCC + 0.3
V
1, 2
Input Low Voltage
VIL
0.3
0.8
V
1, 3
Notes: 1. The voltages are referenced to VSS.
2. The input voltage is VCC + 0.5V when the pulse width is less than 20ns (the pulse width is with respect
to the point at which VCC is applied).
3. The input voltage is  0.5V when the pulse width is less than 20ns (the pulse width respect to the point at
which VSS and VSSQ are applied).
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FEDD56V16161N-01
MSM56V16161N
Pin Capacitance
Ta = 25°C, VCC＝VCCQ＝3.3V, f＝1MHz
Parameter
Symbol
Min.
Max.
Unit
CCLK

4
pF
CIN

5
pF
COUT

6.5
pF
Input Capacitance (CLK)
Input Capacitance
(A0 to A11, /RAS, /CAS, /WE, /CS, CKE, UDQM, LDQM)
Input/Output Capacitance (DQ0 to DQ15)
DC Characteristics (Input/Output)
When Output Driver Strength=100%, 50%, 25%
Parameter
Ta= 0 to 70°C
VCC = VCCQ = 3.0V~3.6V
Max.
Unit
Symbol
Condition
Min.
Output High Voltage
VOH
IOH = 2mA
2.4

Output Low Voltage
V
VOL
IOL = 2mA

0.4
V
Input Leakage Current
ILI
0V VIN VCCQ
10
10
µA
Output Leakage Current
ILO

10
10
µA
Note : The voltages are referenced to VSS.
When Output Driver Strength=12.5%
Parameter
Ta= 0 to 70°C
VCC = VCCQ = 3.0V~3.6V
Max.
Unit
Symbol
Condition
Min.
Output High Voltage
VOH
IOH = 0.5mA
2.4

V
Output Low Voltage
VOL
IOL = 0.5mA

0.4
V
Input Leakage Current
ILI
0V VIN VCCQ
10
10
µA
Output Leakage Current
ILO

10
10
µA
Note : The voltages are referenced to VSS.
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FEDD56V16161N-01
MSM56V16161N
DC Characteristics (Power Supply Current)
Ta= 0 to 70°C
VCC = VCCQ = 3.0V~3.6V
MSM56V16161N
Condition
Parameter
Bank
Average Power
Supply Current
(Operating)
ICC1
One Bank
Active
Power Supply
Current
(Standby)
ICC2
Both
Banks
Precharge
Average Power
Supply Current
(Clock
Suspension)
Both
ICC3S Banks
Active
CKE
CKE VIH
Unit Note
-6
-7
-75
-10
Max.
Max.
Max.
Max.
tRC = Min.
No Burst
120
100
90
70
mA 1, 2
tCC = Min.
50
40
35
30
mA
3
3
3
3
3
mA
2
50
45
40
35
mA
3
160
140
130
100
mA
1, 2
160
140
130
100
mA
2
Symbol
Others
tCC = Min.
CKE
VIH
CKE
VIL tCC = Min.
CKE
VIH
Average Power
Supply Current
(Active
Standby)
ICC3
One Bank
Active
Power Supply
Current (Burst)
ICC4
Both
Banks
Active
CKE
VIH tCC = Min.
Power Supply
Current
(Auto-Refresh)
ICC5
One Bank
Active
CKE
VIH
Average Power
Supply Current
(Self-Refresh)
ICC6
Both
CKE
Banks
Precharge
VIL tCC = Min.
2
2
2
2
mA
Average Power
Supply Current
(Power Down)
ICC7
Both
CKE
Banks
Precharge
VIL tCC = Min.
2
2
2
2
mA
tCC = Min.
tCC = Min.
tRC = Min.
Notes: 1. Measured with outputs open.
2. The address and data can be changed once or left unchanged during one cycle.
3. The address and data can be changed once or left unchanged during two cycles.
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FEDD56V16161N-01
MSM56V16161N
AC Characteristics (1/2)
Ta= 0 to 70°C
VCC = VCCQ = 3.0V~3.6V
Note1,2
MSM56V16161N
Parameter
Symbol
-6
-7
Unit Note
-75
-10
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
CL=3
tCC3
6

7

7.5

10

ns
CL=2
tCC2
10

10

10

10

ns
Access
CL=3
Time from
CL=2
Clock
Clock High Pulse
Time
tAC3

5.4

5.4

5.4

6
ns
3,4
tAC2

5.4

5.4

5.4

6
ns
3,4
tCH
2

2

2.5

3

ns
4
Clock Low Pulse
Time
tCL
2

2

2.5

3

ns
4
Input Setup Time
tSI
2

2

2

2

ns
Input Hold Time
tHI
1

1

1

1

ns
Output Low
Impedance Time
from Clock
tOLZ
2

2

2

2

ns
Output High
Impedance Time
from Clock
tOHZ

5.4

5.4

5.4

6
ns
Output Hold from
Clock
tOH
2

2

2

2

ns
Random Read or
Write Cycle Time
tRC
60

60

65

70

ns
RAS Precharge
Time
tRP
18

20

20

20

ns
RAS Pulse Width
tRAS
42
10
42
10
45
10
50
10
/RAS to /CAS Delay
Time
tRCD
18

18

20

20

ns
Write Recovery
Time
tWR
2

2

2

2

Cycle
/RAS to /RAS Bank
Active Delay Time
tRRD
10

10

15

20

ns
Refresh Time
tREF

64

64

64

64
ms
Power-down Exit
setup Time
tPDE tSI+1CLK

tSI+1CLK

tSI+1CLK

tSI+1CLK

ns
Refresh cycle Time
tRCA

60

65

70

ns
Clock Cycle
Time
60
5
5
5
5
3
ns
6
5
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FEDD56V16161N-01
MSM56V16161N
AC Characteristics (2/2)
Ta= 0 to 70°C
VCC = VCCQ = 3.0V~3.6V
Note1,2
Parameter
Symbol
/CAS to /CAS Delay Time
(Min.)
MSM56V16161N
Unit
-6
-7
-75
-10
lCCD
1
1
1
1
Cycle
Clock Disable Time from
CKE
lCKE
1
1
1
1
Cycle
Data Output High
Impedance Time from
UDQM, LDQM
lDOZ
2
2
2
2
Cycle
Dada Input Mask Time
from UDQM, LDQM
lDOD
0
0
0
0
Cycle
Data Input Mask Time from
Write Command
lDWD
0
0
0
0
Cycle
Data Output High
Impedance Time from
Precharge Command
lROH
CL
CL
CL
CL
Cycle
Active Command Input
Time from Mode Register
Set Command Input (Min.)
lMRD
2
2
2
2
Cycle
Write Command Input Time
from Output
lOWD
2
2
2
2
Cycle
Note
Notes: 1. AC measurements assume that tT = 1ns,.
2. Test condition
Parameter
Test Condition
Input voltage for AC measurement
2.4
0.4
Transition Time for AC measurement
Reference level for timing of input signal (tT1ns)
Reference level for timing of input signal (tT>1ns)
Reference level for timing of output signal
Unit
V
tT＝1
ns
1.4
V
VIH Min.
VIL Max.
1.4
V
V
1.4V
3. Output load.
50
Z=50
Output
30pF (External Load)
4. If tT is longer than 1ns, then the reference level for timing of input signals is VIH and VIL.
5. It is necessary to operate auto-refresh 4096 cycles within tREF.
6. If tCC is longer than 20ns, the spec of tWR (min.) is 20ns (1 cycle).
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FEDD56V16161N-01
MSM56V16161N
POWER ON AND INITIALIZE
Power on Sequence
1. Apply power and attempt to maintain CKE=”H” and other pins are NOP condition at the input.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200 s.
3. Issue precharge commands for all banks of the devices.
4. Issue mode register set command to initialize the mode register.
5. Issue extended mode register set command to initialize the extended mode register.
6. Issue 2 or more auto-refresh commands.
Note 1: (4), (5) or (6): in no special order.
2. (5) can be omitted. When it is omitted, it becomes default settings.
3. Carry out an initialization sequence after each input terminal reaches a regulation voltage when
other input terminals were the undefined setup input (High-Z) at the CKE= "H" time. And, the
undefined setup input period of the CKE= "H" time can't hold data. It becomes more effective than
writing data after the initialization sequence.
Mode Register Set Command (MRS)
The mode register stores the data for controlling the various operating
modes. It programs the /CAS latency, burst type, burst length and write
mode. The default value of the mode register is not defined, therefore the
mode register must be written after power up to operate the SDRAM.
The mode register is written by mode register set command MRS. The
state of address pins A0 to A10 in the same cycle as MRS is the data
written in the mode register. Refer to the table for specific codes for
various /CAS latencies, burst type, burst length and write mode.
MRS
CLK
CKE
n-1
n
H
X
/CS
L
/RAS
X
L
/CAS
(Idle)
L
/WE
L
A11
X
0
A0 to A10
V
V
V: The value of mode register set
Extended Mode Register Set Command (EMRS)
EMRS
CLK
The extended mode register stores the data for controlling output driver
strength. The default value of the extended mode register is defined.
Therefore the mode register must be written after power up to operate the
SDRAM. The extended mode register is written by extended mode
register set command EMRS. The state of address pins A0 to A10 in the
same cycle as EMRS is the data written in the extended mode register.
Refer to the table for Extended Mode Register Set Address Keys.
CKE
n-1
n
H
X
/CS
L
/RAS
X
L
/CAS
(Idle)
L
/WE
L
A11
X
1
A0 to A10
V
V
V: The value of extended mode
register set
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FEDD56V16161N-01
MSM56V16161N
Mode Register Field Table To Program Mode
Write Burst Mode
/CAS Latency
Burst Type
Burst Length
A9
WM
A6
A5
A4
CL
A3
BT
A2
A1
A0
BT = 0
BT = 1
0
Burst
0
0
0
Reserved
0
Sequential
0
0
0
1
1
1
Single
0
0
1
Reserved
1
Interleave
0
0
1
2
2
0
1
0
2
0
1
0
4
4
0
1
1
3
0
1
1
8
8
1
0
0
Reserved
1
0
0
Reserved
Reserved
1
0
1
Reserved
1
0
1
Reserved
Reserved
1
1
0
Reserved
1
1
0
Reserved
Reserved
1
1
1
Reserved
1
1
1
Full Page
Reserved
Notes: 1. 1. Objects are all family products.
2. A11 should stay “0” during mode set cycle.
3. A7, A8 and A10 should stay “0” during mode set cycle.
4. Don’t set address keys of “Reserved”.
Extended Mode Register Set Address Keys
Output Driver Strength
A6
A5
DS
0
0
Full (Default)
0
1
1/2
1
0
1/8
1
1
1/4
Notes: 1. A11 should stay “1” during mode set cycle.
2. A0 to A4, A7 to A10 should stay “0” during mode set cycle.
3. If don’t set EMRS, DS is set to default (Full).
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FEDD56V16161N-01
MSM56V16161N
Output Driver Characteristics (1/2)
Ta＝0°C~+70°C, VCC,VCCQ＝3.0V~3.6V
Output Driver Strength=Full (Default)
min.
typ.
max.
typ.
max.
min.
Output Driver Strength=1/2
min.
typ.
max.
max.
typ.
min.
11/44
FEDD56V16161N-01
MSM56V16161N
Output Driver Characteristics (2/2)
Ta＝0°C~+70°C, VCC,VCCQ＝3.0V~3.6V
Output Driver Strength=1/4
min.
typ.
max.
max.
typ.
min.
Output Driver Strength=1/8
min.
typ.
max.
max.
typ.
min.
12/44
FEDD56V16161N-01
MSM56V16161N
Burst Mode
Burst operation is the operation to continuously increase a column address inputted during read or write command.
The upper bits select a column address block,
Access order in column address block
Burst Type
Start Address
(Lower bit)
BT=Sequential
BT=Interleave
0
0, 1
0, 1
1
1, 0
1, 0
A0
BL=2
A1
A0
0
0
0, 1, 2, 3
0, 1, 2, 3
0
1
1, 2, 3, 0
1, 0, 3, 2
1
0
2, 3, 0, 1
2, 3, 0, 1
1
1
3, 0, 1, 2
3, 2, 1, 0
A2
A1
A0
0
0
0
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
0
0
1
1, 2, 3, 4, 5, 6, 7, 0
1, 0, 3, 2, 5, 4, 7, 6
0
1
0
2, 3, 4, 5, 6, 7, 0, 1
2, 3, 0, 1, 6, 7, 4, 5
0
1
1
3, 4, 5, 6, 7, 0, 1, 2
3, 2, 1, 0, 7, 6, 5, 4
1
0
0
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
1
0
1
5, 6, 7, 0, 1, 2, 3, 4
5, 4, 7, 6, 1, 0, 3, 2
1
1
0
6, 7, 0, 1, 2, 3, 4, 5
6, 7, 4, 5, 2, 3, 0, 1
1
1
7, 0, 1, 2, 3, 4, 5, 6
7, 6, 5, 4, 3, 2, 1, 0
Burst Length
BL=4
BL=8
1
A0 to A7
BL=Full Page
(256)
0
0, 1… 255
Yn
Yn, Yn+1… 255, 0…
…Yn-1
Non Support
13/44
FEDD56V16161N-01
MSM56V16161N
READ / WRITE OPERATION
Bank
Bank Address
This SDRAM is organized as four independent banks of 524,288 words x
16 bits memory arrays. The A11 input is latched at the time of assertion
of /RAS and /CAS to select the bank to be used for operation. The bank
address A11 is latched at bank active, read, write, mode register set and
precharge operations.
Activate
A11
Bank
0
A
1
B
ACT
The bank activate command is used to select a random row in an idle bank.
By asserting low on /RAS and /CS with desired row and bank address, a
row access is initiated. The read or write operation can occur after a time
delay of tRCD(min) from the time of bank activation.
CLK
CKE
n-1
n
H
X
/CS
/RAS
L
L
X
(Idle)
H
A11
X
BA
A0 to A10
X
RA
/CAS
/WE
H
BA: Bank Address
RA: Row Address (Page)
Precharge
PRE
PALL
CLK
CLK
The precharge operation is
n-1
n
n-1
n
performed on an active bank by
CKE
H
X
CKE
H
X
precharge command (PRE) with
/CS
L
/CS
L
valid A11 of the bank to be
X
X
precharged.
The
precharge
/RAS
L
/RAS
L
(Page
(Page
command can be asserted anytime
/CAS
H
/CAS
H
Open)
Open)
after tRAS(min) is satisfied from
/WE
L
/WE
L
the bank active command in the
A11
X
BA
A11
X
X
desired bank. All bank can
precharged at the same time by
A10
X
0
A10
X
1
using precharge all command
A0 to A9
X
X
A0 to A9
X
X
(PALL). Asserting low on /CS,
BA: Bank Address
/RAS and /WE with high on A10
after all banks have satisfied tRAS(min) requirement, performs precharge on al banks. At the end of tRP after
performing precharge to all banks, all banks are in idle state.
14/44
FEDD56V16161N-01
MSM56V16161N
Write / Write with Auto-Precharge
The write command is used to
write data into the SDRAM on
consecutive clock cycles in
adjacent address depending on
burst length and burst sequence.
By asserting low on /CS, /CAS
and /WE with valid column
address, a write burst is initiated.
The data inputs are provided for
the initial address in the same
clock cycle as the burst write
command. The input buffer is
deselected at the end of the burst
length, even through the internal
writing can be completed yet. The
writing can be completed by
issuing a burst read and DQM for
blocking data inputs or burst write
in the same or another active bank.
The burst stop command is valid
at every burst length.
WRT
WRTA
CLK
CKE
n
H
X
CKE
L
/CS
/CS
X
/RAS
(Page
Open)
/CAS
CLK
n-1
/WE
A11
X
n-1
n
H
X
L
X
H
/RAS
L
/CAS
L
/WE
BA
A11
X
(Page
Open)
H
L
L
BA
A10
X
0
A10
X
1
A9, A8
X
X
A9, A8
X
X
A0 to A7
X
CA
A0 to A7
X
CA
DQ
X
D-in
DQ
X
D-in
BA: Bank Address
CA: Column Address
D-in: Data inputs
BA: Bank Address
CA: Column Address
D-in: Data inputs
Write Cycle
CLK
CL=2 or 3, BL=1 or WM=Single
Command
ACT
tRCD
DQ
tRAS
tRP
WRT
PRE
ACT
D0
Valid Single Data In
CL=2 or 3, BL=4, WM=Burst
Command
Page Open
DQ
WRT
D0
tWR
D1
D2
PRE
D3
tRAS
DQ
ACT
tRCD
ACT
Valid Burst Data In
CL=2 or 3, BL=4, WM=Burst
Command
tRP
Auto Precharge Start
WRTA
D0
tWR
D1
D2
tRP
ACT
D3
15/44
FEDD56V16161N-01
MSM56V16161N
Read / Read with Auto-Precharge
The read command is used to
access burst of data on
consecutive clock cycles from an
active row in an active bank. The
read command is issued by
asserting low on /CS and /CAS
with /WE being high on the
positive edge of the clock. The
bank must be active for at least
tRCD(min) before the read
command is issued. The first
output appears in /CAS latency
number of clock cycles after the
issue of read command. The burst
length, burst sequence and latency
from the read command are
determined by the mode register
that is already programmed.
RD
RDA
CLK
CKE
n-1
n
H
X
/CS
X
/RAS
(Page
Open)
/CAS
/WE
A11
X
CLK
CKE
n-1
n
H
X
L
/CS
H
/RAS
L
L
/CAS
H
/WE
BA
A11
X
X
(Page
Open)
H
L
H
BA
A10
X
0
A10
X
1
A9, A8
X
X
A9, A8
X
X
A0 to A7
X
CA
A0 to A7
X
CA
DQ
X
X
DQ
X
X
BA: Bank Address
CA: Column Address
BA: Bank Address
CA: Column Address
Read Cycle
CLK
CL=2, BL=4
Command
tRAS
ACT
tRCD
RD
DQ
/CAS Latency (CL) = 2
Q0
Q1
PRE
Q2
ACT
Q3
Valid Burst Data Out
CL=3, BL=4
Command
tRP
Page Open
RD
/CAS Latency (CL) = 3
DQ
Q0
CL=2, BL=4
PRE
Q1
ACT
tRP
Q2
Q3
Valid Burst Data Out
tRCD
Auto Precharge Start
Command
ACT
RDA
DQ
tRAS
Q0
Q1
ACT
tRP
Q2
Q3
CL=3, BL=4
Auto Precharge Start
Command
DQ
Page Open
RDA
ACT
tRP
Q0
Q1
Q2
Q3
16/44
FEDD56V16161N-01
MSM56V16161N
Write / Write interrupt
When a new write command is issued to same bank during write cycle or another active bank, current burst write is
terminated and new burst write start. When a new write command is issued to another bank during a write with
auto-precharge cycle, current burst is terminated and a new write command start. Then, current bank is precharged
after specified time. Don’t issue a new write command to same bank during write with auto-precharge cycle.
Write / Write interrupt cycle
CLK
CL=2 or 3, BL=4, WM=Burst
Command
DQ
tCCD
tCCD
WRTa
WRTb
Da0
Db0
WRTc
Db1
Dc0
Dc1
Dc2
Dc3
CL=2 or 3, BL=4, WM=Burst
Auto Precharge Start
Command
DQ
WRTa
Da0
tCCD
Da1
WRTAb
Db0
tWR
Db1
Db2
tRP
ACT
Db3
CL=2 or 3, BL=4, WM=Burst
Command
Bank Address
WRTA
tCCD
A
WRTA
ACT
B
A
tWR + 1clk
Bank A Internal State
Burst Write
Burst Interrupt,
Write Recovery
DQ
Row Active
DA0
DA1
Auto Precharge
Write
Recovery
Burst Write
DB0
DB1
ACT
B
tRP
tWR
Bank B Internal State
tRRD
DB2
Row Active
tRP
Row
Auto Precharge Active
DB3
17/44
FEDD56V16161N-01
MSM56V16161N
Read / Read interrupt
When a new read command is issued to same bank during read cycle or another active bank, current burst read is
terminated after the cycle same as /CAS latency and new burst read start. When a new read command is issued to
another bank during a read with auto-precharge cycle, current burst is terminated after the cycle same as /CAS
latency and a new read command start. Then, current bank is precharged after specified time. Don’t issue a new
read command to same bank during read with auto-precharge cycle.
Read / Read interrupt cycle
CLK
CL=2, BL=4
Command
tCCD
RDa
RDb
DQ
RDc
Qa0
CL=3, BL=4
Command
tCCD
Qb0
Qb1
Qc0
Qc1
tCCD
Qc2
High-Z
Auto Precharge Start
RDAb
RDa
Qc3
DQ
ACT
tRP
Qa0
Qa1
Qb0
Qb1
Qb2
Qb3
High-Z
CL=2, BL=4
Command
Bank Address
RDA
tCCD
A
RDA
ACT
B
A
tRRD
ACT
B
tRP + 1clk
Bank A Internal State
Burst Read
Burst
Interrupt
Auto Precharge
Row Active
tRP
Bank B Internal State
DQ
Row Active
Burst Read
QA0
QA1
Auto Precharge
QB0
QB1
QB2
Row
Active
QB3
18/44
FEDD56V16161N-01
MSM56V16161N
Write / Read interrupt
When a new read command is issued to same bank during write cycle or another active bank, current burst write is
terminated and new burst read start. When a new read command is issued to another bank during a write with
auto-precharge cycle, current burst is terminated and a new read command start. Then, current bank is precharged
after specified time. Don’t issue a new read command to same bank during write with auto-precharge cycle. DQ
must be hi-Z till 1 or more clock from first read data.
Write / Read interrupt cycle
CLK
CL=3, BL=4, WM=Burst
Command
tCCD
WRTa
DQ
RDb
Da0
High-Z
Qb0
Qb2
Qb1
Qb3
Invalid Data Input
CL=2, BL=4, WM=Burst
Command
tCCD
WRTa
DQ
Da0
Auto Precharge Start
RDAb
Da1
tRP
High-Z
Qb0
Qb1
Qb2
ACT
Qb3
Invalid Data Input
CL=2, BL=4, WM=Burst
Command
Bank Address
WRTA
tCCD
A
RDA
ACT
B
A
tWR + 1clk
Bank A Internal State
Burst Write
Burst Interrupt,
Write Recovery
tRRD
ACT
B
tRP
Auto Precharge
Row Active
tRP
Bank B Internal State
DQ
Row Active
DA0
DA1
Burst Read
High-Z
Auto Precharge
QB0
QB1
QB2
Row
Active
QB3
Invalid Data Input
19/44
FEDD56V16161N-01
MSM56V16161N
Read / Write interrupt
When a new write command is issued to same bank during read cycle or another active bank, current burst read is
terminated and new burst write start. When a new write command is issued to another bank during a read with
auto-precharge cycle, current burst is terminated and a new write command start. Then, current bank is precharged
after specified time. Don’t issue a new write command to same bank during read with auto-precharge cycle. DQ
must be Hi-Z till 1 or more clock from new write command. Therefore, DQM must be high till 3 clocks from new
write command.
Read / Write interrupt cycle
CLK
CL=3, BL=4, WM=Burst
Command
RDa
tOWD
WRTb
DQM
DQ
Qa0
Db0
High-Z
Db1
Db2
Db3
CL=2, BL=4, WM=Burst
Command
Bank Address
RDA
WRTA
ACT
A
B
A
tRP + 1clk
Bank A Internal State
Burst
Interrupt
Burst Read
Auto Precharge
Row Active
tWR
Bank B Internal State
Row Active
Write
Recovery
Burst Write
Auto
Precharge
tOWD
DQM
DQ
QA0
High-Z
DB0
DB1
DB2
DB3
20/44
FEDD56V16161N-01
MSM56V16161N
Burst Stop
When a burst stop command is issued during read cycle, current burst
read is terminated. The DQ is to Hi-Z after the cycle same as /CAS
latency and page keep open. When a burst stop command is issued during
write cycle, current burst write is terminated. The input data is ignored
after burst stop command. Don’t issue burst stop command during read
with auto-precharge cycle or write with auto-precharge cycle.
BST
CLK
n-1
n
H
X
/RAS
X
H
/CAS
(Burst)
H
A11
X
X
A0 to A10
X
X
CKE
/CS
L
/WE
L
Read / Burst Stop cycle
CLK
CL=2, BL=4~Full
Command
RD
BST
DQ
Q0
Q1
Q2
High-Z
CL=3, BL=4~Full
Command
RD
BST
DQ
Q0
Q1
Q2
High-Z
Write / Burst Stop cycle
CLK
CL=2 or 3, BL=4~Full, WM=Burst
Command
DQ
WRT
D0
BST
D1
D2
High-Z
Invalid Data Input
21/44
FEDD56V16161N-01
MSM56V16161N
Precharge Break
When a precharge command is issued to the same bank during read cycle or precharge all command is issued,
current burst read is terminated and DQ is to Hi-Z after the cycle same as /CAS latency. The objected bank is
precharged. When a precharge command is issued to the same bank during write cycle or precharge all command is
issued, current burst write is terminated and the objected bank is precharged. The input data after precharge
command is ignored.
Read / Precharge Break cycle
CLK
CL=2, BL=4~Full
Command
ACT
tRAS
tRCD
tRP
RD
PRE
DQ
Q0
CL=3 BL=4~Full
Command
ACT
Q1
ACT
tRAS
tRCD
High-Z
Q2
tRP
RD
PRE
DQ
Q0
ACT
Q1
High-Z
Q2
Write / Precharge Break cycle
CLK
CL=2, BL=4~Full
tRAS
ACT
Command
tRCD
tRP
WRT
あ
tWR
PRE
ACT
DQM
DQ
D0
D1
Invalid Data Input
CL=3, BL=4~Full
Command
ACT
tRAS
tRCD
tRP
WRT
あ
tWR
PRE
ACT
DQM
DQ
D0
D1
D2
22/44
FEDD56V16161N-01
MSM56V16161N
DQM Function
DQM masks input / output data at every byte. UDQM controls DQ8 to DQ15 and LDQM controls DQ0 to DQ7.
During read cycle, DQM mask output data after 2 clocks. During write cycle, DQM mask input data at same clock.
Read / DQM Function
CLK
CL=3, BL=8
Command
RD
UDQM
DQ8 to DQ15
QU0
QU1
QU4
High-Z High-Z
QU6
QU7
QL6
QL7
High-Z
LDQM
DQ0 to DQ7
QL0
QL3
QL4
High-Z High-Z
High-Z
Write / DQM Function
CLK
CL=2 or 3, BL=8
Command
WRT
UDQM
DQ8 to DQ15
DU0
DU1
DU4
DU6
DU7
DL4
DL6
DL7
LDQM
DQ0 to DQ7
DL0
DL3
Invalid Data Input
23/44
FEDD56V16161N-01
MSM56V16161N
Clock Suspend
The read / write operation can be stopped by CKE temporarily. When CKE is set low, the next clock is ignored.
When CKE is set low during read cycle, the burst read is stopped temporarily and the current output data is kept.
When CKE is set high, burst read is resumed. When CKE is set low during write cycle, the burst write is stopped
temporarily. When CKE is set high, burst write is resumed.
Read / Clock Suspend
CLK
CL=2, BL=8
CKE
Command
RD
Valid Data Output
DQ
Q0
Q1
Q2
Q3
Q4
Suspend
Q5
Suspend
Write / Clock Suspend
CLK
CL=2 or 3, BL=8
CKE
Command
DQ
WRT
D0
Invalid Data Input
D1
D2
Suspend
D4
D3
D5
D6
Suspend
C
L
=
2,
B
L
=
8
C
K
E
C
o
m
24/44
FEDD56V16161N-01
MSM56V16161N
REFRESH
The data of memory cells are maintained by refresh operation. The refresh operation is to activate all row addresses
within a refresh time. The method that row addresses are activated by activate and precharge command is called
RAS only refresh cycle. This method needs to input row address with activate command. But, auto-refresh and self
refresh don’t need to input address. Because, row addresses are generated in SDRAM automatically.
Auto Refresh
REF
All memory area is refreshed by 4,096 times refresh command REF. The
refresh command REF can be entered only when all the banks are in an
idle state. SDRAM is in idle state after refresh cycle time tRCA.
CLK
CKE
n-1
n
H
H
/CS
L
/RAS
X
L
/CAS
(Idle)
L
/WE
H
A11
X
X
A0 to A10
X
X
Auto-Refresh Cycle
CLK
Command
PALL
REF
REF
tRP
ACT
tRCA
tRCA
Intensive Refresh
4,096 times refresh command can be entered every refresh time t REF.
CLK
Read or Write
State
Auto Refresh
tREF=64ms
Read or Write
REF x 4,096
Auto Refresh
tREF=64ms
REF x 4,096
Dispersed Refresh
Refresh command can be entered every 15.6s (tREF 64ms / 4,096 cycles).
CLK
State
REF
R/W
15.6µs
REF
R/W
REF
R/W
REF
15.6µs
R/W
REF
15.6µs
4,096 times
tREF=64ms
25/44
FEDD56V16161N-01
MSM56V16161N
Self Refresh
SREF
When read or write is not operated in the long period, self refresh can
reduce power consumption for refresh operation. Refresh operation is
controlled automatically by refresh timer and row address counter
during self refresh mode. All signals except CKE are ignored and data
bus DQ is set Hi-Z during self refresh mode.
When CKE is set to high level, self refresh mode is finished. Then, CLK
must be operated before 1 clock or more. And, maintain NOP condition
within a period of tRCA(Min.) after CKE is set to be high level.
CLK
CKE
n-1
n
H
L
/CS
L
/RAS
X
L
/CAS
(Idle)
L
/WE
H
A11
X
X
A0 to A10
X
X
Self Refresh Cycle
CLK
Self Refresh
CKE
Command
REF
SREF
tRCA
REF
tRCA
Notes : 1. When intensive refresh is used, 4,096 times refresh must be issued before and after the self refresh.
26/44
FEDD56V16161N-01
MSM56V16161N
Power Down
SDRAM can be set to low power consumption condition with CKE function. CKE is reflected at 1 clock later
regardless /CAS latency. When CKE is set to low level, SDRAM go into power down mode. All signals except
CKE are ignored and DQ is set to High impedance in this state. When CKE is set to high level, SDRAM exit power
down mode. Then, Clock must be resumed before 1 or more clocks.
Power Down
CLK
CL=2, BL=4, Case 1
Active Power Down Mode
CKE
Command
DQ
Write Cycle
D1
D2
New Command
RD
Page Open Stand-by
High-Z
D3
Q0
Q1
CL=2, BL=4, Case 2
Power Down Mode
CKE
New Command
Auto Precharge Start
Command
REF
Precharge Stand-by / Idle
DQ
Q1
Q2
High-Z
Q3
Signal Condition in Power Down Mode
Signal
Input to SDRAM
Output from SDRAM
CLK
Don’t Care

CKE
“L” level

/CS,/RAS, /CAS, /WE
Don’t Care

A0 to A10, A11
Don’t Care

DQ0 to DQ15
Don’t Care
High-Z
UDQM,LDQM
Don’t Care

VCC,VCCQ,VSS,VSSQ
Power Supply

Notes : 1. “Don’t Care” means high or low level input.
27/44
FEDD56V16161N-01
MSM56V16161N
FUNCTION TRUTH TABLE
FUNCTION TRUTH TABLE (Table 1) (1/3)
Current
1
State *
Idle
Row
Active
Read
Write
/CS
/RAS
/CAS
/WE
ADDR
Command
Action
H
X
X
X
X
NOP
NOP
L
H
H
X
X
NOP/BST
NOP
L
H
L
H
BA, CA, A10
RD/RDA
ILLEGAL *2
L
H
L
L
BA, CA, A10
WRT/WRTA
ILLEGAL *2
L
L
H
H
BA, RA
ACT
Row Active
L
L
H
L
BA, A10
PRE/PALL
L
L
L
H
X
REF
Auto-Refresh or Self-Refresh *4
L
L
L
L
V, A11=0
MRS
Mode Register Set *4
L
L
L
L
V, A11=1
EMRS
NOP *3
Extended Mode Register Set *4
H
X
X
X
X
NOP
NOP
L
H
H
X
X
NOP/BST
NOP
L
H
L
H
BA, CA, A10
RD/RDA
Read / Read auto Precharge *5
L
H
L
L
BA, CA, A10
WRT/WRTA
Write / Write auto Precharge *5
L
L
H
H
BA, RA
ACT
ILLEGAL *6
L
L
H
L
BA, A10
PRE/PALL
Precharge
L
L
L
H
X
REF
ILLEGAL
L
L
L
L
X
MRS/EMRS
ILLEGAL
H
X
X
X
X
NOP
Continue Row Active after Burst ends
L
H
H
H
X
NOP
Continue Row Active after Burst ends
L
H
H
L
X
BST
Term Burst --> Row Active
L
H
L
H
BA, CA, A10
RD/RDA
Term Burst, start new Burst Read
L
H
L
L
BA, CA, A10
WRT/WRTA
Term Burst, start new Burst Write
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, A10
PRE/PALL
L
L
L
H
X
REF
ILLEGAL
ILLEGAL
ILLEGAL *6
Term Burst, execute Row Precharge
L
L
L
L
X
H
X
X
X
X
MRS/EMRS
NOP
L
H
H
H
X
NOP
Continue Row Active after Burst ends
Term Burst --> Row Active
Continue Row Active after Burst ends
L
H
H
L
X
BST
L
H
L
H
BA, CA, A10
RD/RDA
Term Burst, start new Burst Read
L
H
L
L
BA, CA, A10
WRT/WRTA
Term Burst, start new Burst Write
ILLEGAL *6
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, A10
PRE/PALL
L
L
L
H
X
REF
ILLEGAL
L
L
L
L
X
MRS/EMRS
ILLEGAL
Term Burst, execute Row Precharge
28/44
FEDD56V16161N-01
MSM56V16161N
FUNCTION TRUTH TABLE (Table 1) (2/3)
Current
*1
State
Read with
Auto
Precharg
e
Write with
Auto
Precharge
Precharge
Write
Recovery
*9
/CS
/RAS
/CAS
/WE
ADDR
Command
Action
H
X
X
X
X
NOP
Continue Burst to End and enter Row Precharge
L
H
H
H
X
NOP
Continue Burst to End and enter Row Precharge
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
BA, CA, A10
RD/RDA
ILLEGAL *7
L
H
L
L
BA, CA, A10
WRT/WRTA
ILLEGAL *7
L
L
H
H
BA, RA
ACT
ILLEGAL *6
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL *8
L
L
L
H
X
REF
ILLEGAL
ILLEGAL
L
L
L
L
X
MRS/EMRS
H
X
X
X
X
NOP
Continue Burst to End and enter Row Precharge
L
H
H
H
X
NOP
Continue Burst to End and enter Row Precharge
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
BA, CA, A10
RD/RDA
ILLEGAL *7
L
H
L
L
BA, CA, A10
WRT/WRTA
ILLEGAL *7
L
L
H
H
BA, RA
ACT
ILLEGAL *6
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL *8
L
L
L
H
X
REF
ILLEGAL
L
L
L
L
X
MRS/EMRS
ILLEGAL
H
X
X
X
X
NOP
Idle after tRP
L
H
H
H
X
NOP
Idle after tRP
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
BA, CA, A10
RD/RDA
ILLEGAL *2
L
H
L
L
BA, CA, A10
WRT/WRTA
ILLEGAL *2
L
L
H
H
BA, RA
ACT
ILLEGAL *6
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL *3
L
L
L
H
X
REF
ILLEGAL
L
L
L
L
X
MRS/EMRS
ILLEGAL
H
X
X
X
X
NOP
Row Active after tWR
L
H
H
H
X
NOP
Row Active after tWR
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
BA, CA, A10
RD/RDA
ILLEGAL *2
L
H
L
L
BA, CA, A10
WRT/WRTA
ILLEGAL *2
L
L
H
H
BA, RA
ACT
ILLEGAL *6
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL *8
L
L
L
H
X
REF
ILLEGAL
L
L
L
L
X
MRS/EMRS
ILLEGAL
29/44
FEDD56V16161N-01
MSM56V16161N
FUNCTION TRUTH TABLE (Table 1) (3/3)
Current
*1
State
Write
Recovery
in Auto
Precharge
*9
Auto
Refresh
Mode
Register
Access
/CS
/RAS
/CAS
/WE
ADDR
Command
Action
H
X
X
X
X
NOP
enter Row Precharge after tWR
L
H
H
H
X
NOP
enter Row Precharge after tWR
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
BA, CA, A10
RD/RDA
ILLEGAL *7
L
H
L
L
BA, CA, A10
WRT/WRTA
ILLEGAL *7
L
L
H
H
BA, RA
ACT
ILLEGAL *6
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL *8
L
L
L
H
X
REF
ILLEGAL
L
L
L
L
X
MRS/EMRS
ILLEGAL
H
X
X
X
X
NOP
Idle after tRCA
L
H
H
H
X
NOP
Idle after tRCA
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
BA, CA, A10
RD/RDA
ILLEGAL
L
H
L
L
BA, CA, A10
WRT/WRTA
ILLEGAL
L
L
H
H
BA, RA
ACT
ILLEGAL
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL
L
L
L
H
X
REF
ILLEGAL
ILLEGAL
L
L
L
L
X
MRS/EMRS
H
X
X
X
X
NOP
Idle after tMRD
L
H
H
H
X
NOP
Idle after tMRD
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
BA, CA, A10
RD/RDA
ILLEGAL
L
H
L
L
BA, CA, A10
WRT/WRTA
ILLEGAL
L
L
H
H
BA, RA
ACT
ILLEGAL
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL
L
L
L
H
X
REF
ILLEGAL
L
L
L
L
X
MRS/EMRS
ILLEGAL
ABBREVIATIONS
ADDR = Address
RA = Row Address
NOP = No OPeration command
BA = Bank Address
CA = Column Address
V = Value of Mode Register Set
Notes : 1. All inputs are enabled when CKE is set high for at least 1 cycle prior to the inputs.
2. RD/RDA or WRT/WRTA command to same bank is forbidden. But RD/RDA or WRT/WRTA
command to activated page in another bank is valid after tRCD(min.).
3. PRE command to another activated bank is valid. PALL command is valid to only activated bank.
4. Illegal if any bank is not idle.
5. RD/RDA or WRT/WRTA command to activated bank is valid after tRCD(min.) from ACT command.
6. Activate command to the same bank is forbidden. But activate command to another bank in idle state
is valid.
7. RD/RDA or WRT/WRTA command to same bank is forbidden. But RD/RDA or WRT/WRTA
command to activated page in another bank is valid.
8. PRE to same bank is forbidden. PRE to another bank must be issued after tRAS(min.). PALL
command is forbidden.
9. Write recovery states means a period from last data to the time that tWR(min.) passed.
30/44
FEDD56V16161N-01
MSM56V16161N
FUNCTION TRUTH TABLE for CKE (Table 2)
Current State
n-1
CKE
n-1
CKE
n
All Banks Idle
H
(ABI)
H
Self Refresh
Power Down
/CS
n
/RAS
n
/CAS
n
/WE
n
ADDR
n
H
X
X
X
X
X
Refer to Table 1
L
H
X
X
X
X
Enter Power Down
H
L
L
H
H
H
X
Enter Power Down
H
L
L
H
H
L
X
ILLEGAL
H
L
L
H
L
X
X
ILLEGAL
H
L
L
L
H
H
BA, RA
H
L
L
L
H
L
X
ILLEGAL
H
L
L
L
L
H
X
Enter Self Refresh
Action
Enter Active Power Down after Activate
H
L
L
L
L
L
BA, V
L
X
X
X
X
X
X
INVALID
*2
Enter Power Down after MRS
H
X
X
X
X
X
X
INVALID
L
H
H
X
X
X
X
Exit Self Refresh --> ABI
*3
L
H
L
H
H
H
X
Exit Self Refresh --> ABI
*3
L
H
L
H
H
L
X
ILLEGAL
L
H
L
H
L
X
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
L
L
X
X
X
X
X
NOP (Maintain Self Refresh)
H
X
X
X
X
X
X
INVALID
L
H
X
X
X
X
X
Exit Power Down --> ABI
L
L
X
X
X
X
X
NOP (Continue Power Down)
*4
Active Power
Down
H
X
X
X
X
X
X
INVALID
L
H
X
X
X
X
X
Exit Active Power Down --> Row Active
L
L
X
X
X
X
X
NOP (Continue Active Power Down)
Row Active
H
H
X
X
X
X
X
Refer to Table 1
H
L
H
X
X
X
X
Enter Active Power Down
H
L
L
H
H
H
X
Enter Active Power Down
H
L
L
H
H
L
X
ILLEGAL
H
L
L
H
L
X
X
Clock Suspension (Refer to Table 1)
H
L
L
L
H
X
X
Clock Suspension (Refer to Table 1)
H
L
L
L
L
X
X
ILLEGAL
L
X
X
X
X
X
X
INVALID
H
H
X
X
X
X
X
Refer to Table 1
H
L
X
X
X
X
X
Begin Clock Suspend Next Cycle
L
H
X
X
X
X
X
Enable Clock of Next Cycle
L
L
X
X
X
X
X
Continue Clock Suspension
Any State Other
than Listed
Above
ABBREVIATIONS
ADDR = Address
RA = Row Address
V = Value of Mode Register Set
*Notes : 1.
2.
3.
4.
BA = Bank Address
ABI = All Banks Idle
NOP = No OPeration command
Deep Power Down can be entered only when all the banks are in an idle state.
Self Refresh can be entered only when all the banks are in an idle state.
tRCA must be set after exit self refresh.
New command is enabled in the next clock.
31/44
*4
FEDD56V16161N-01
MSM56V16161N
SIMPLIFIED STATE DIAGRAM
MODE
REGISTER
SET
SELF
REFRESH
AUTO
REFRESH
EXTENDED
MODE
REGISTER
SET
Exit
Self
Refresh
MRS
Refresh
EMRS
IDLE
CKE
CKE
Active
POWER
DOWN
CKE
ACTIVE
POWER
DOWN
Burst
Stop
Read
CKE
ACTIVE
Burst
Stop
Read
Write
AP
WRITE
SUSPEND
CKE
Precharge
Write
Write
Read
AP
CKE
Read
WRITE
READ
Write
CKE
Read AP
CKE
Write AP
Write with Auto Precharge
WRITEA
SUSPEND
Read with Auto Precharge
CKE
CKE
WRITEA
READA
CKE
POWER
ON
Command / input signal
READ
SUSPEND
Precharge
Precharge
Precharge
READA
SUSPEND
CKE
PRECHARGE
Auto Sequence
32/44
FEDD56V16161N-01
MSM56V16161N
TIMING CHART
Synchronous Characteristics
Transition Time tT1ns
tCC2/3
tCH
Transition Time tT1ns
tT ≤ 1ns
tCL
CLK
tCC2/3
tCH
tT > 1ns
tCL
VIH
1.4V
VIL
tSI
tHI
tSI
Input *
Valid
Low
1.4V
DQ Output
tSI
tHI
tAC2/3
tAC2/3
tOLZ
tOH
Valid
Low
1.4V
High-Z
VIH
Valid
High
tOHZ
tOH
Valid
High
Valid
Low
VIL
tHI
tAC2/3
tAC2/3
tOLZ
High-Z
High-Z
Valid
High
tSI
VOH
VOL
tOH
Valid
Low
tHI
tOHZ2/3
tOH
Valid
High
High-Z
Note : The object of input are CKE, A0 to A11 /CS, /RAS, /CAS, /WE,UDQM to LDQM and DQ0 to DQ15
(input).
Power on Sequence
Max.
VCC, VCCQ 0V
200µs
Min.
CLK
Stable Clock Input
Command
(/CS, /RAS,
/CAS, /WE)
(NOP)
NOP
PALL
NOP
Don't Care
Address
UDQM,LDQM
DQ0 to DQ15
Initialize
Don't Care *1
High-Z
Notes : 1. It is advisable that UDQM and LDQM are set to high for set DQ to high impedance during power on
sequence.
33/44
FEDD56V16161N-01
MSM56V16161N
Initialization
CLK
CKE
High
Command
(/CS, /RAS,
/CAS,/WE)
tRP
200µs
PALL
Address
tMRD
tMRD
MRS
EMRS
V
V
tRCA
tRCA
REF
REF
ACT
Ra
A10
Ra
A11
Ba
UDQM,LDQM Don't Care *2
DQ0 to 15
Notes :
High-Z
1. V = Value of mode register, Rx = Row Address, Bx = Bank Address
= NOP command or High or Low
2. It is advisable that UDQM to LDQM are set to be high level for setting DQ to high impedance during
power on sequence.
Mode Register Set cycle
CLK
tSI
CKE
tRC
Command
(/CS, /RAS,
/CAS, /WE)
tRCA
REF
Address
tMRD
tRAS
MRS
ACT
V
Ra
A10
Ra
A11
Ba
tRP
PRE
tMRD
EMRS
SREF
V
Ba
UDQM,LDQM
DQ0 to 15
Notes :
High-Z
1. V = Value of mode register, Rx = Row Address, Bx = Bank Address
= NOP command or High or Low
34/44
FEDD56V16161N-01
MSM56V16161N
Burst Write Cycle (BL=4, WM=Burst)
CLK
tSI
tHI
Command
(/CS, /RAS,
ACT
/CAS, /WE) t
tHI
SI
Address
Ra
tSI
A10
WRT
PRE
tRAS
ACT
Rb
tWR
tRCD
PRE
tRAS
Cb
tRCD
Ra
tWR
Rb
tHI
Ba
A11
WRT
tRP
Ca
tHI
tSI
Ba
Ba
tSI
UDQM,
LDQM
(CL=2, 3)
tSI
Bb
Bb
Bb
tSI
tHI
tHI
tSI
Da0 Da1 Da2
DQ0 to 15
(CL=2, 3)
Notes :
tRC
tHI
tHI
Db0
1. Rx = Row Address, Cx = Column Address, Bx = Bank Address
= NOP command or High or Low level, CKE = High level
Burst Read Cycle (BL=4)
CLK
tRC
Command
(/CS, /RAS,
/CAS, /WE)
ACT
Address
Ra
RD
PRE
tRAS
ACT
tRP
Ra
A11
Ba
UDQM,
LDQM
(CL=2)
DQ0 to 15
(CL=2)
UDQM,
LDQM
(CL=3)
Ca
Rb
Notes :
Cb
tRCD
Rb
Ba
Ba
Bb
Bb
tAC2
Bb
tAC2
tOLZ
tOH
tOHZ
tOH
tOLZ
tOHZ
Qa0 Qa1 Qa2 Qa3
Qb0
tAC3
tOLZ
DQ0 to 15
(CL=3)
PRE
tRAS
tRCD
A10
RD
tAC3
tOH
tOHZ
Qa0 Qa1 Qa2 Qa3
tOH
tOLZ
tOHZ
Qb0
1. Rx = Row Address, Cx = Column Address, Bx = Bank Address
= NOP command or High or Low level, CKE = High level
35/44
FEDD56V16161N-01
MSM56V16161N
Bank Interleave  Write with Auto Precharge Cycle (CL=2, BL=4, WM=Burst)
CLK
Command
(/CS, /RAS,
/CAS, /WE)
ACT
ACT
WRTA
RAa
tRP
(Bank-A)
tRAS (Bank-A)
CAa
RBa
CBa
RAa
A11
A
ACT
WRTA
CAb
RBb
CBb
tRCD
RAb
tRP
(Bank-B)
tRAS (Bank-B)
RBa
A
WRTA
tWR
tRCD
A10
ACT
WRTA
tWR
tRCD
Address
tRC (Bank-B)
tRC (Bank-A)
RAb
B
B
tRCD
RBb
A
A
B
B
UDQM,
LDQM
tSI
DQ0 to 15
Notes :
tHI
tSI
tHI
tSI
DAa0 DAa1 DAa2 DAa3 DBa0 DBa1 DBa2 DBa3
tHI
tSI
tHI
DAb0 DAb1 DAb2 DAb3 DBb0
1. RXx = Row Address, CXx = Column Address, X = Bank, x = Address
= NOP command or High or Low level, CKE = High level
Bank Interleave  Read with Auto Precharge Cycle (CL=2, BL=4)
CLK
Command
(/CS, /RAS,
/CAS, /WE)
Address
tRC (Bank-B)
tRC (Bank-A)
ACT
RDA
tRCD
RAa
ACT
RDA
tRAS (Bank-A)
CAa
RBa
CBa
RAa
A11
A
UDQM,
LDQM
DQ0 to 15
Notes :
RAb
A
B
ACT
RDA
CAb
RBb
CBb
tRCD
tRP (Bank-B)
tRAS (Bank-B)
RBa
RDA
tRCD
tRP (Bank-A)
tRCD
A10
ACT
RAb
B
A
RBb
A
B
B
tAC2
tOLZ
tOH
tAC2
tOH
tOHZ
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3
QAb0 QAb1 QAb2
1. RXx = Row Address, CXx = Column Address, X = Bank, x = Address
= NOP command or High or Low level, CKE = High level
36/44
FEDD56V16161N-01
MSM56V16161N
Burst Read  Single Write Cycle (CL=2, BL=4,WM=Single)
CLK
Command
(/CS, /RAS,
/CAS, /WE)
Address
ACT
RD
ACT
WRT
WRT
RD
RAa
CAa
RBa
CBa
CBb
CAb
tRCD
A10
tRCD
RAa
A11
tCCD
tCCD
RBa
A
A
B
B
B
A
tOWD
UDQM,LDQM
tAC2
tAC2
tOLZ
tOH
DQ0 to 15
Notes :
tOHZ2 tSI
QAa0 QAa1 QAa2 QAa3
tHI
tSI
DBa
tHI
tOLZ
tOH
DBb
QAb0
1.RXx = Row Address, CXx = Column Address, X = Bank, x = Address
= NOP command or High or Low level, CKE = High level
Random Column  Read / Write Cycle (CL=3, BL=2, 4, 8, Full Page)
CLK
tRP (Bank-A)
tRCD (Bank-A)
Command (Bank-A=Active)
(/CS, /RAS,
RD RD RD RD PRE ACT
ACT WRT WRT WRT WRT RD RD RD RD
/CAS, /WE)
tCCD tCCD tCCD
tCCD tCCD tCCD tCCD tCCD tCCD tCCD
tRRD
Address
CAa CAb CAc CAd
RBa
RAb CBa CBb CAe CAf
CBc CBd CAg CAh
tRCD (Bank-B)
A10
A11
A
A
A
A
A
RBa
RAb
B
A
B
B
A
A
B
B
A
A
tOWD
UDQM,
LDQM
DQ0 to 15
Notes :
tAC3
tOLZ
tAC3
tOH
tOHZ
QAa0 QAb0 QAc0 QAd0
tSI
tHI
tOLZ
DBa0 DBb0 DAe0 DAf0
tOH
QBc0
1. RXx = Row Address, CXx = Column Address, X = Bank, x = Address
= NOP command or High or Low level, CKE = High level,
= Invalid Data Input
37/44
FEDD56V16161N-01
MSM56V16161N
Burst Stop  Read / Write Cycle (BL=Full Page, WM=Burst)
CLK
Command
(/CS, /RAS,
/CAS, /WE)
RD
Address
Ca
Cb
Ba
Ba
BST
WRT
BST PRE
A10
A11
tOWD
UDQM,
LDQM
(CL=2)
tWR
tAC2
tOLZ
tOH
DQ0 to 15
(CL=2)
Qa0 Qa1
UDQM,
LDQM
(CL=3)
tAC3
tOHZ
tSI
Qan-1 Qan
Dbn-1 Dbn
tOWD
tOHZ
Qa0
tHI
Db0 Db1
tOH
tOLZ
DQ0 to 15
(CL=3)
Notes :
Ba
tWR
tSI
Qan-2 Qan-1 Qan
tHI
Db0 Db1
1. Cx = Column Address, Bx = Bank Address
= NOP command or High or Low level, CKE = High level,
Dbn-1
= Invalid Data Input
Precharge Break  Read / Write Cycle (BL=Full Page, WM=Burst)
CLK
tRP
Command
(/CS, /RAS,
/CAS, /WE)
RD
Address
Ca
PRE
tRAS
ACT
UDQM,
LDQM
(CL=2)
Rb
DQ0 to 15
(CL=3)
Notes :
Cb
Rb
Ba
Ba
Ba
Ba
Ba
tOWD
tWR
tAC2
tOLZ
tOH
DQ0 to 15
(CL=2)
UDQM,
LDQM
(CL=3)
PRE
tRCD
A10
A11
WRT
Qa0 Qa1
tAC3
tOHZ
tSI
Qan-1 Qan
tOHZ
Qa0
Db0 Db1
Dbn-1 Dbn
tOWD
tOH
tOLZ
tHI
Qan-2 Qan-1 Qan
tSI
tWR
tHI
Db0 Db1
Dbn-1
1. RXx = Row Address, CXx = Column Address, X = Bank, x = Address
= NOP command or High or Low level, CKE = High level,
= Invalid Data Input
38/44
FEDD56V16161N-01
MSM56V16161N
Byte Read / Byte Write Cycle (CL=2, BL=8, WM=Burst)
CLK
Command
(/CS, /RAS,
/CAS, /WE)
RD
WRT
Address
Ca
Cb
Ba
Ba
A10
A11
UDQM
DQ8 to 15
Qa0 Qa1
tSI
tHI
tOHZ
Qa0
Qa2
Qa4 Qa5
tOLZ
Db0 Db1
tSI
tHI
Db4 Db5
Qa4 Qa5
Db0
Db4 Db5
LDQM
DQ0 to 7
Notes :
1. Cx = Column Address, Bx = Bank Address
= NOP command or High or Low level, CKE = High level,
Db2
= Invalid Data Input
Clock Suspend  Read / Write Cycle (CL=3, BL=4, WM=Burst)
CLK
tSI
tHI
tSI
tHI
CKE
Command
(/CS, /RAS,
/CAS, /WE)
RD
WRT
Address
Ca
Cb
Ba
Ba
A10
A11
UDQM,
LDQM
DQ0 to 15
Notes :
tAC3
tOLZ
tOWD
tOH
Qa0
Qa1
tOHZ
Qa2
Qa3
1. Cx = Column Address, Bx = Bank Address
= NOP command or High or Low level, CKE = High level,
tSI
Db0 Db1
tHI
Db2 Db3
= Invalid Data Input
39/44
FEDD56V16161N-01
MSM56V16161N
Auto Refresh Cycle
CLK
CKE
Command
(/CS, /RAS,
/CAS, /WE)
High
tRP
PALL
tRCA
REF
tRCA
tRCA
REF
REF
ACT
Address
Ra
A10
Ra
A11
Ba
UDQM,
LDQM
DQ0 to 15
Notes :
High-Z
1. Rx = Row Address, Bx = Bank Address
= NOP command or High or Low level, CKE = High level,
= Invalid Data Input
Self Refresh Cycle
CLK
tSI
1clk
CKE
tSI
Self Refresh
Command
(/CS, /RAS,
/CAS, /WE)
tRP
PALL
NOP
tRCA
SREF
Don't Care
NOP
ACT
Address
Ra
A10
Ra
A11
Ba
UDQM,
LDQM
DQ0 to 15
Notes :
High-Z
1. Rx = Row Address, Bx = Bank Address
= High or Low level
40/44
FEDD56V16161N-01
MSM56V16161N
Power Down Cycle
CLK
tSI
1clk
tSI
1clk
tSI
CKE
tSI
Active Power Down
Command
(/CS, /RAS,
/CAS,/WE)
Power Down
1clk
ACT NOP
Don't Care
NOP PRE
1clk
NOP
Don't Care
NOP ACT
Address
Ra
Rb
A10
Ra
Rb
A11
Ba
Ba
Bb
UDQM,
LDQM
DQ0 to 15
Notes :
High-Z
1. Rx = Row Address, Bx = Bank Address
= High or Low level
41/44
FEDD56V16161N-01
MSM56V16161N
PACKAGE DIMENSIONS
(Unit: mm)
NOTES:
1.
LEAD WITH DOES NOT INCLUDE TRIM OFFSET.
2.
PACKAGE WIDTH AND LENGTH DO NOT INCLUDE MOLD PROTRUSION, DIEPAD
SUPPORT PROTRUSION AND CAVITY OFFSET BETWEEN TOP AND BOTTOM CAVITY.
3.
THE SEATING PLANE IS THE SURFACE WHICH THE PACKAGE IS MOUNTED ON
AND GETS IN CONTACT WITH.
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package name,
pin number, package code and desired mounting conditions (reflow method, temperature and times).
42/44
FEDD56V16161N-01
MSM56V16161N
REVISION HISTORY
Document No.
FEDD56V16161N-01
Date
April 27, 2016
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Final edition 1
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FEDD56V16161N-01
MSM56V16161N
Notes
1) The information contained herein is subject to change without notice.
2) Although LAPIS Semiconductor is continuously working to improve product reliability and quality,
semiconductors can break down and malfunction due to various factors. Therefore, in order to prevent
personal injury or fire arising from failure, please take safety measures such as complying with the derating
characteristics, implementing redundant and fire prevention designs, and utilizing backups and fail-safe
procedures. LAPIS Semiconductor shall have no responsibility for any damages arising out of the use of our
Products beyond the rating specified by LAPIS Semiconductor.
3) Examples of application circuits, circuit constants and any other information contained herein are provided
only to illustrate the standard usage and operations of the Products. The peripheral conditions must be taken
into account when designing circuits for mass production.
4) The technical information specified herein is intended only to show the typical functions of the Products and
examples of application circuits for the Products. No license, expressly or implied, is granted hereby under
any intellectual property rights or other rights of LAPIS Semiconductor or any third party with respect to the
information contained in this document; therefore LAPIS Semiconductor shall have no responsibility
whatsoever for any dispute, concerning such rights owned by third parties, arising out of the use of such
technical information.
5) The Products are intended for use in general electronic equipment (i.e. AV/OA devices, communication,
consumer systems, gaming/entertainment sets) as well as the applications indicated in this document.
6) The Products specified in this document are not designed to be radiation tolerant.
7) For use of our Products in applications requiring a high degree of reliability (as exemplified below), please
contact and consult with a LAPIS Semiconductor representative: transportation equipment (i.e. cars, ships,
trains), primary communication equipment, traffic lights, fire/crime prevention, safety equipment, medical
systems, servers, solar cells, and power transmission systems.
8) Do not use our Products in applications requiring extremely high reliability, such as aerospace equipment,
nuclear power control systems, and submarine repeaters.
9) LAPIS Semiconductor shall have no responsibility for any damages or injury arising from non-compliance
with the recommended usage conditions and specifications contained herein.
10) LAPIS Semiconductor has used reasonable care to ensure the accuracy of the information contained in this
document. However, LAPIS Semiconductor does not warrant that such information is error-free and LAPIS
Semiconductor shall have no responsibility for any damages arising from any inaccuracy or misprint of such
information.
11) Please use the Products in accordance with any applicable environmental laws and regulations, such as the
RoHS Directive. For more details, including RoHS compatibility, please contact a ROHM sales office.
LAPIS Semiconductor shall have no responsibility for any damages or losses resulting non-compliance with
any applicable laws or regulations.
12) When providing our Products and technologies contained in this document to other countries, you must abide
by the procedures and provisions stipulated in all applicable export laws and regulations, including without
limitation the US Export Administration Regulations and the Foreign Exchange and Foreign Trade Act.
13) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS
Semiconductor.
Copyright 2016 LAPIS Semiconductor Co., Ltd.
2-4-8 Shinyokohama, Kouhoku-ku,
Yokohama 222-8575, Japan
http://www.lapis-semi.com/en/
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