GS1675 SD/HD SDI Reclocker The GS1675 is a multi-rate serial digital reclocker designed to automatically recover the embedded clock from a digital video signal and retime the incoming video data. It will recover the embedded clock signal and retime the data from a SMPTE 292M or SMPTE 259M-C compliant digital video signal. The GS1675 can operate in either Auto or Manual rate selection mode. In Auto mode, the device will automatically detect and lock onto incoming SMPTE SDI data signals at SD and HD data rates. For single-rate data systems, the GS1675 can be configured to operate in Manual mode. In both modes, the device requires only one external crystal to set the VCO frequency when not locked, and provides adjustment-free operation. In systems which require passing non-SMPTE data rates, the GS1675 can be configured to either automatically or manually enter a bypass mode in order to pass the signal without reclocking. The GS1675 accepts industry-standard differential input levels including LVPECL and CML. The differential data and clock outputs feature selectable output swing via the host interface, ensuring compatibility with most industry-standard, terminated differential receivers. The GS1675 features dual differential outputs. The second output can be configured to emit either the recovered clock signal or the re-timed video data. • Key Features • • • • • • • • SMPTE 292M and SMPTE 259M-C compliant Supports DVB-ASI at 270Mb/s Single-supply operation at 3.3V or 2.5V 180mW typical power consumption (213mW with RCO enabled) at 2.5V 2:1 input multiplexer patented technology Choice of dual reclocked data outputs or one reclocked data output and one clock output Uses standard 27MHz crystal Differential inputs and outputs supports DC-coupling to industry-standard differential logic on-chip 100Ω differential data input/output termination selectable 400mVppd or 800mVppd output swing on each output 4-wire SPI host interface for device configuration and monitoring Standard logic control and status signal levels Auto and Manual modes for rate selection Standards indication in Auto mode Lock Detect Output Mute, Bypass and Autobypass functions SD/HD indication output to control GS1678 or GS1679 cable drivers Operating temperature range: -40°C to +85°C 32 pin 5mm x 5mm QFN package Pb-free and RoHS compliant Forward pin-compatible with the Gennum's 3G GS2965 reclocker • • • • • • • • • • • Typical Application Circuit 3 VCC2 JP5 2 VCO_SEL 1 R23 R24 422R 267R VCC2 VDD_DIG (Pin14) VCC_VCO (Pin9) C31 C30 C33 10u C32 1u 10n C34 VCC_DDO1 (Pin19) VCC_DDO0 (Pin23) C20 C23 C27 10n C13 C15 C16 10n DNP DNP 10n DNP DNP VCC_CP (Pin32) C7 10n 220n GND VEE_DDO1 (Pin20) VEE_DDO0 (Pin24) Data Input 1 7 HIFb 4 CSb SCK SDO SDI 27 28 29 30 8 1 2 C3 47n C4 220n DDO0 DDO0 DDI1 DDO1/RCO DDI1 DDO1/RCO GS1675 CS SCK SDO SDI XTAL- 22 21 Data Output 0 18 17 Data Output 1 ABM7-27.000MHZ-D2Y-T 26 Y1 R6 C1 25 XTAL+ NC LF+ CP_CAP SD/HD LOS LOCKED 18p GND 1M 16 13 12 C2 SD/HD LOS LOCKED 18p GND 10 15 20 24 31 GND DDI0 DDI0 HIF VEE_CP (Pin31) GND TAB 6 VEE_VCO VSS_DIG VEE_DDO1 VEE_DDO0 VEE_CP 3 5 Data Input 0 SPI VSS_DIG (Pin15) VDD_1P8 VCC_VCO VDD_DIG VCC_DDO1 VCC_DDO0 VCC_CP U2 11 9 14 19 23 32 VEE_VCO (Pin10) GND GND GS1675 SD/HD SDI Reclocker Data Sheet 54174 - 1 June 2011 www.gennum.com 1 of 37 Contents Key Features........................................................................................................................................................1 Typical Application Circuit.............................................................................................................................1 1. Pin Out...............................................................................................................................................................4 1.1 Pin Assignment ..................................................................................................................................4 1.2 Pin Descriptions ................................................................................................................................5 1.3 Default Start-up Settings ................................................................................................................7 2. Electrical Characteristics ............................................................................................................................8 2.1 Absolute Maximum Ratings ..........................................................................................................8 2.2 DC Electrical Characteristics ........................................................................................................8 2.3 AC Electrical Characteristics ........................................................................................................9 3. Functional Description ............................................................................................................................. 11 3.1 Serial Data Input ............................................................................................................................ 11 3.2 Modes of Operation ...................................................................................................................... 11 3.3 2:1 Input Mux .................................................................................................................................. 11 3.4 Crystal Buffer .................................................................................................................................. 12 3.5 LOS (Loss Of Signal) Detection .................................................................................................. 12 3.6 Serial Digital Reclocker ............................................................................................................... 13 3.7 Lock Detection ................................................................................................................................ 13 3.7.1 Lock Detect and Asynchronous Lock ......................................................................... 14 3.8 Serial Data Output ......................................................................................................................... 14 3.8.1 Output Signal Interface Levels...................................................................................... 14 3.8.2 Adjustable Output Swing................................................................................................ 14 3.9 Automatic and Manual Data Rate Selection ......................................................................... 14 3.10 SD/HD Indication ........................................................................................................................ 15 3.11 Bypass Mode ................................................................................................................................. 15 3.12 DVB-ASI ......................................................................................................................................... 16 3.13 Output Mute and Data/Clock Output Selection ............................................................... 16 3.14 Host Interface ............................................................................................................................... 17 3.14.1 Introduction ...................................................................................................................... 17 3.14.2 Legacy Mode & Startup ................................................................................................. 17 3.14.3 Host Interface Mode & Startup ................................................................................... 17 3.14.4 Clock & Data Timing....................................................................................................... 18 3.14.5 Single Device Operation............................................................................................... 18 3.14.6 Write Operation - Single Device ................................................................................ 19 3.14.7 Read Operation - Single Device ................................................................................. 20 3.14.8 Daisy Chain Operation.................................................................................................. 22 3.14.9 Read & Write Operation - Daisy Chained Devices .............................................. 23 3.14.10 Writing to all Devices .................................................................................................. 23 3.14.11 Writing to a Single Device in the Chain ................................................................ 24 3.14.12 Reading from all Devices ........................................................................................... 24 3.14.13 Reading from a Single Device in the Chain.......................................................... 25 3.14.14 Host Register Map......................................................................................................... 26 GS1675 SD/HD SDI Reclocker Data Sheet 54174 - 1 June 2011 2 of 37 3.15 Device Power Up ......................................................................................................................... 29 3.16 Standby ........................................................................................................................................... 29 4. Typical Application Circuit ..................................................................................................................... 30 5. Input/Output Circuits ............................................................................................................................... 31 6. Package and Ordering Information...................................................................................................... 34 6.1 Package Dimensions ..................................................................................................................... 34 6.2 Recommended PCB Footprint ................................................................................................... 34 6.3 Packaging Data ............................................................................................................................... 35 6.4 Marking Diagram ........................................................................................................................... 35 6.5 Solder Reflow Profile .................................................................................................................... 36 6.6 Ordering Information ................................................................................................................... 36 Revision History .............................................................................................................................................. 37 GS1675 SD/HD SDI Reclocker Data Sheet 54174 - 1 June 2011 3 of 37 1. Pin Out VCC_CP VEE_CP SDI SDO SCK CS XTAL- XTAL+ 1.1 Pin Assignment 32 31 30 29 28 27 26 25 LF+ 1 24 VEE_DDO0 CP_CAP 2 23 VCC_DDO0 DDI0 3 22 DDO0 HIF 4 21 DDO0 DDI0 5 20 VEE_DDO1 DDI1 6 19 VCC_DDO1 DDI1 7 18 DDO1/RCO RSVD 8 17 DDO1/RCO 13 14 15 16 VDD_DIG VSS_DIG SD/HD 12 LOCKED 11 VDD_1P8 10 VEE_VCO Ground Pad (bottom of package) VCC_VCO 9 LOS GS1675 32-pin QFN (top view) Figure 1-1: GS1675 Pin Out GS1675 SD/HD SDI Reclocker Data Sheet 54174 - 1 June 2011 4 of 37 1.2 Pin Descriptions Table 1-1: GS1675 Pin Descriptions Pin Number Name Type Description 1 LF+ Passive Loop Filter Capacitor connection (CLF = 47nF). Connect as shown in the Typical Application Circuit on page 30. 2 CP_CAP Power External capacitor for internal LDO regulator supplying the charge pump circuit. 3, 5 DDI0, DDI0 Input Serial Digital Differential Input 0. 4 HIF Logic Input 6, 7 DDI1, DDI1 Input 8 RSVD Reserved 9 VCC_VCO Power Most positive power supply connection for the internal VCO section. Connect to a 3.3V supply with a 422Ω resistor, or a 2.5V supply with a 267Ω resistor. 10 VEE_VCO Power Most negative power supply connection for the internal VCO section. Connect to GND. 11 VDD_1P8 Power External capacitor for internal 1.8V digital supply. 12 LOCKED Output Lock Detect status signal. HIGH when the PLL is locked. 13 LOS Output Loss Of Signal status. HIGH when the input signal is invalid. 14 VDD_DIG Power Most positive power supply connection for the digital core. Connect to 3.3V or 2.5V. 15 VSS_DIG Power Most negative power supply for the digital core. Connect to GND. 16 SD/HD Output This signal will be LOW for all rates other than 270Mb/s. This signal is HIGH for 270Mb/s. 17, 18 DDO1/RCO, DDO1/RCO Output Differential serial clock or data outputs. 19 VCC_DDO1 Power Most positive power supply connection for the DDO1/DDO1 output driver. Connect to 3.3V or 2.5V. 20 VEE_DDO1 Power Most negative power supply connection for the DDO1/DDO1 output driver. Connect to GND. 21, 22 DDO0, DDO0 Output Differential Serial Digital Outputs. 23 VCC_DDO0 Power Most positive power supply connection for the DDO0/DDO0 output driver. Connect to 3.3V or 2.5V. 24 VEE_DDO0 Power Most negative power supply connection for the DDO0/DDO0 output driver. Host interface selection pin. Active-low input. See Section 3.14.1. Serial Digital Differential Input 1. Reserved pin. Do not connect to this pin. Connect to GND. 25 XTAL+ GS1675 SD/HD SDI Reclocker Data Sheet 54174 - 1 June 2011 Output Reference crystal output. 5 of 37 Table 1-1: GS1675 Pin Descriptions (Continued) Pin Number Name Type 26 XTAL- Input 27 CS Input/Logic Input Description Reference crystal input. In host mode (HIF set LOW): Chip select input for SPI serial host interface. Active-low input. In non-host mode (HIF set HIGH): Set LOW. Gennum recommends using a weak pull-down resistor (~50kΩ). 28 SCK Input/Logic Input In host mode (HIF set LOW): Burst-mode clock input for SPI serial host interface. In non-host mode (HIF set HIGH): Set LOW. Gennum recommends using a weak pull-down resistor (~50kΩ). 29 SDO Input/Logic Input In host mode (HIF set LOW): Serial digital data output for SPI serial host interface. Active-high output. In non-host mode (HIF set HIGH): Set LOW. Gennum recommends using a weak pull-down resistor (~50kΩ). 30 SDI Input/Logic Input In host mode (HIF set LOW): Serial digital data input for SPI serial host interface. Active-high input. In non-host mode (HIF set HIGH): Set LOW. Gennum recommends using a weak pull-down resistor (~50kΩ). 31 VEE_CP Power Most negative power supply connection for the internal charge pump. Connect to GND. 32 VCC_CP Power Most positive power supply connection for the internal charge pump. Connect to 3.3V or 2.5V − Center Pad GS1675 SD/HD SDI Reclocker Data Sheet 54174 - 1 June 2011 − Ground pad on bottom of package. Connect to GND. 6 of 37 1.3 Default Start-up Settings The GS1675 has some functions that are not accessible via direct pin control, and are only accessible through the host interface registers. These functions have an internal pull-up or pull-down resistor that sets the default logic level or start-up state, if it is not already set by a pin. If the user wishes to override these logic levels, the associated bit should be programmed within the PIN_OR_1 register (pin override register) at address 0x0C. The logic values within the PIN_OR_1 register become active when the user sets the Pin Override Enable bit to HIGH within that same register. Table 1-2 shows: 1. The default logic state set by the internal pull up or pull down resistors. 2. The default values within the Pin Override register upon reset. Table 1-2: GS1675 Default Start-up Settings Default State set by Internal Resistors Default State within the Pin Override Register 0:0 0:0 Bypasses the reclocker stage when set HIGH. 0 0 When set HIGH, this bit automatically bypasses the reclocker stage when the PLL is not locked to a supported rate. 0 0 When set HIGH, the standard is automatically detected from the input data rate. 1 0 None 0:0 Floating Ground Mutes the DDO0/DDO0 and DDO1/DDO1 (if data is selected) outputs when LOW. 1 0 Disables the DDO1/RCO and DDO1/RCO outputs when LOW. 0 0 HIGH = DATA LOW = CLOCK 0 0 Name DDI_SEL[0:1] BYPASS AUTOBYPASS AUTO/MAN SS0, SS1 KBB DATA_MUTE DDO1_DISABLE DATA/CLOCK Description Selects one of two serial digital input signals for processing. DDI0 is selected by default. When AUTO/MAN is set HIGH, SS[1:0] are outputs displaying the data rate to which the PLL has locked. Therefore, they will not have default values. Controls the loop bandwidth of the PLL. GS1675 SD/HD SDI Reclocker Data Sheet 54174 - 1 June 2011 7 of 37 2. Electrical Characteristics 2.1 Absolute Maximum Ratings Parameter Value Supply Voltage -0.5 to +3.6VDC Input ESD Voltage 4kV Storage Temperature Range -50ºC < TA < 125ºC Operating Temperature Range -40ºC to 85ºC Input Voltage Range -0.3 to (VCC + 0.3) VDC Solder Reflow Temperature 260ºC 2.2 DC Electrical Characteristics Table 2-1: DC Electrical Characteristics Parameter Supply Voltage Power (DDO1/RCO disabled, minimum output swing) Symbol VDD P Power (DDO1/RCO enabled, minimum output swing) Power in Power-down mode Conditions Min Typ Max Units 3.3V 3.135 3.3 3.465 V 2.5V 2.375 2.5 2.625 V VDD = 3.3V − 250 − mW VDD = 2.5V − 180 − mW VDD = 3.3V − 300 − mW VDD = 2.5V − 210 − mW VDD = 3.3V − 40 − mW 30 − mW VDD = 2.5V Serial Input Termination − Differential 80 100 120 Ω Serial Output Termination − Differential 80 100 120 Ω Serial Input Common Mode Voltage − − 1.6 − VDD V Serial Output Common Mode Voltage − − − VCC(ΔVOD /2) − V VIL (2.5V operation) − VOUT≤VOL, max -0.3 − 0.7 V VOUT≤VOL, max -0.3 − 0.8 V VIL (3.3V operation) GS1675 SD/HD SDI Reclocker Data Sheet 54174 - 1 June 2011 8 of 37 Table 2-1: DC Electrical Characteristics (Continued) Parameter Symbol Conditions − VIH (2.5V operation) VIH (3.3V operation) Min Typ Max Units VOUT≥VOH, min 1.7 − VDD +0.3 V VOUT≥VOH, min 2 − VDD +0.3 V IIN − VIN = 0V or VIN = VDD − − +/-10 μA VOL (2.5V operation) − VDD = min, IOL = 100μA − − 0.4 V VDD = min, IOL = 100μA − − 0.4 V VDD = min, IOH = -100μA 2.1 − − V VDD = min, IOH = -100μA VDD -0.4 − − V 2.5V operation − 350 − mV 3.3V operation − 350 − mV VOL (3.3V operation) − VOH (2.5V operation) VOH (3.3V operation) − Hysteresis Voltage (SPI inputs) NOTE: guaranteed by simulation. 2.3 AC Electrical Characteristics Table 2-2: AC Electrical Characteristics Parameter Serial Input Data Rate (for reclocking) Symbol DRSDO Serial Input Data Rate (bypass) Conditions Min Typ Max Units Notes − 0.27 − 1.485 Gb/s − − DC − 1.485 Gb/s − − − − 10 MHz − 2000 mVp-pd − SPI Operating Speed − Input Voltage Swing ΔVSDI Set ATTEN_EN = 1 for ΔVSDI>1Vpp 100 Output Voltage Swing ΔVOD default 300 400 500 mVp-pd − see DRIVER_1 register (0x01) addresses 8 & 9 in 3.14.14 Host Register Map. 600 800 1000 mVp-pd − LOW Recommended setting for 0 to 10 inches of FR4 − MED Recommended setting for 10 to 20 inches of FR4 − HIGH Recommended setting for >20 inches of FR4 − Input Trace Equalization GS1675 SD/HD SDI Reclocker Data Sheet 54174 - 1 June 2011 − 9 of 37 Table 2-2: AC Electrical Characteristics (Continued) Parameter Output De-Emphasis Input Jitter Tolerance Loop Bandwidth Symbol − − BWLOOP Conditions Min Typ Max Units Notes OFF - 0 − 0 − dB − ON - 0 − 0 − dB − ON - 1 − 0.7 − dB − ON - 2 − 1.3 − dB − ON - 3 − 2 − dB − ON - 4 − 2.6 − dB − ON - 5 − 3.3 − dB − ON - 6 − 4 − dB − ON - 7 − 4.7 − dB − 0.8 − − UI − KBB = VCC − 170 − kHz − KBB = FLOAT − 340 − kHz − KBB = GND − 680 − kHz − KBB = VCC − 0.875 − MHz − KBB = FLOAT − 1.75 − MHz − KBB = GND − 3.5 − MHz − square-wave modulated jitter (270Mb/s) BWLOOP (1485Mb/s) PLL Lock Time (asynchronous) talock − − 0.5 1 ms − PLL Lock Time (synchronous) tslock CLF = 47nF, SD/HD = 0 − 0.5 4 μs − CLF = 47nF, SD/HD = 1 − 5 10 μs − KBB = FLOAT − 0.01 − UI − − 0.03 − UI − 20% to 80% (400mV swing) − 65 − ps − 20% to 80% (800mV swing) − 80 − ps − Serial Data Output Jitter Intrinsic (DDO0) tOJ(270MB/s) PRN 2^23-1 test pattern tOJ(1485MB/s) KBB = FLOAT PRN 2^23-1 test pattern Output Rise/Fall Time tr/f Output Rise/Fall Time Mismatch − − − − 15 ps − Eye Cross Shift − percentage of signal amplitude − − 5 % − Power Supply Noise Rejection − 50 - 100Hz − 100 − mVp-p − 100Hz - 10MHz − 40 − mVp-p − 10MHz - 1.485GHz − 10 − mVp-p − GS1675 SD/HD SDI Reclocker Data Sheet 54174 - 1 June 2011 10 of 37 3. Functional Description The GS1675 is a multi-standard reclocker for serial digital SDTV signals operating at 270Mb/s, and HDTV signals operating at 1.485Gb/s, 1.485/1.001Gb/s. 3.1 Serial Data Input The GS1675 features two differential input buffers. The serial data input signal is connected to the DDI0/DDI0 and DDI1/DDI1 input pins of the device. Input signals can be single-ended or differential, DC or AC-coupled. The input circuit is self-biasing, to allow for simple AC or DC-coupling of input signals to the device. The serial digital data inputs are also compatible when DC-coupled with LVPECL or CML differential outputs from crosspoint switches which operate from 3.3V or 2.5V supplies. This includes but is not limited to the GS1674 Equalizer. 3.2 Modes of Operation The GS1675 has two modes of operation: Legacy Mode (HIF = HIGH) and SPI Mode (HIF = LOW). In Legacy Mode, chip functions are controlled via pins only, and offers limited control of input equalization. In SPI mode, access is gained to extended digital controls like: Bypass, Autobypass, Auto/Manual selection, Control status inputs or outputs, changes to KBB settings, as well as access to additional features such as LOS adjustment, polarity invert, auto-mute, etc. 3.3 2:1 Input Mux The GS1675 incorporates a 2:1 input mux, which allows the connection of two independent streams of video/data. There are two differential inputs (DDI[1:0] / DDI[1:0]). The active channel can be selected via the DDI_SEL[1:0] registers as shown in Table 3-1. Table 3-1: Input Selection Table DDI_SEL[1:0] Selected Input 00 DDI0* 01 NOT VALID 10 NOT VALID 11 DDI1 * Power-up default GS1675 SD/HD SDI Reclocker Data Sheet 54174 - 1 June 2011 11 of 37 Active circuitry associated with the input buffers and trace EQ can only be turned on for the selected input. Inputs which are not selected have their input buffers and trace EQs turned OFF to save power. Unused inputs can be either left floating, or tied to VCC. 3.4 Crystal Buffer The GS1675 features a crystal buffer supporting a Gennum recommended external 27MHz crystal. The GS1675 requires an external 27MHz reference clock for correct operation. This reference clock is generated by connecting a crystal to the XTAL- and XTAL+ pins of the device. Alternately, a 27MHz external clock source can be connected to the XTAL- pin of the device, while the XTAL+ pin should be left floating. 3.5 LOS (Loss Of Signal) Detection The LOS (Loss Of Signal) status pin is an active-high output that indicates when the serial digital input signal selected at the 2:1 input mux is invalid. In order for this output to be asserted, transitions must not be present for a period of tLA = 5 - 10μs. After this output has been asserted, LOS will de-assert within tLD = 0 - 5μs after the appearance of a transition at the DDIx input. See Figure 3-1. This signal is HIGH (signal lost), when the number of data edges within a window is below a defined threshold. The output is automatically muted when LOS is detected. This signal is LOW (signal valid), when the number of data edges within a window is above a defined threshold. See Table 3-2. Table 3-2: LOS Operation LOS Signal HIGH Invalid LOW Valid The LOS function is operational for all operating modes of the device. t LA t LD DATA LOS Figure 3-1: LOS Signal Timing GS1675 SD/HD SDI Reclocker Data Sheet 54174 - 1 June 2011 12 of 37 The LOS mode can be selected using the host interface, in register TOP_1. The LOS detector has two major modes. In legacy mode, a simple edge-based detector is used to monitor the received signal at the output of the data slicer. Since the incoming signal has undergone considerable gain by this point, the legacy detector can be more susceptible to false de-assertion of LOS for unused channels which experience significant cross-talk from adjacent active channels. The new LOS detector uses a measure of both signal amplitude and duration to minimize false detection of the impulse like signals that are characteristic of cross-talk. In this mode, the signal is tapped off at the output of the equalizer stage, prior to the high gain buffers. The threshold setting within the detector can be adjusted to increase or decrease its sensitivity. Higher sensitivity allows lower amplitude signals to be detected but also increases the susceptibility to false de-assertion of LOS due to noise or cross-talk. Therefore the lowest sensitivity acceptable for a given application should always be used. See TOP_1 register, bits 8:7, in the host register map. NOTE: It is also possible to have both legacy mode & threshold mode enabled together. In this case, the reclocker must detect transitions within a set window, and the signal amplitude must be greater than the setting for the LOS threshold. 3.6 Serial Digital Reclocker The output of the Equalizer is fed to the reclocker. The function of the reclocker is to re-time the input signal and to generate system clocks. The reclocker operates at two data rates; 1.485Gb/s and 270Mb/s, and provides a minimum input jitter tolerance of 0.8UI to square-wave-modulated jitter. When there is no serial input signal, the internal clock maintains a frequency close to the expected incoming data rate by locking to the external reference crystal. 3.7 Lock Detection The lock detect block indicates, via the active-high LOCKED signal, when the device has achieved lock to the incoming data stream. The lock logic within the GS1675 includes a system that monitors the frequency and the phase of the incoming data, as well as a monitor to detect harmonic lock. Table 3-3: Lock Operation LOCKED Status HIGH Locked LOW Not locked The LOCKED output signal is also available via the host interface. GS1675 SD/HD SDI Reclocker Data Sheet 54174 - 1 June 2011 13 of 37 3.7.1 Lock Detect and Asynchronous Lock The reference crystal is used to assist the PLL in achieving a short lock time. The lock detection algorithm is a continuous process, which begins at device power up or after a system reset, and continues until the device is powered down. The asynchronous lock time is defined as the time it takes the device to lock when a video signal is first applied to the serial digital inputs, or when the digital video signal rate changes. The synchronous lock time is defined as the time it takes the device to lock to a signal which has been momentarily interrupted. 3.8 Serial Data Output The GS1675 features two current-mode differential output drivers, each capable of driving a maximum of 800mVpp differential, into an external 100Ω differential load. Each of the GS1675's output buffers include two on-chip, 50Ω termination resistors. 3.8.1 Output Signal Interface Levels The serial digital outputs of the GS1675 are compatible when DC-coupled with all Gennum serial digital interface products that feature a differential LVPECL or CML receiver designed for SDI applications and operate from 3.3V or 2.5V supplies. This includes but is not limited to the GS1678 and the GS1679. The serial digital data inputs are also compatible when DC-coupled with LVPECL or CML differential outputs from crosspoint switches which operate from 3.3V or 2.5V supplies. This includes but is not limited to the GS1674 equalizer. 3.8.2 Adjustable Output Swing It is possible, via the host interface, to force the output swing to 400mVpp or 800mVpp differential, when the outputs are terminated with 50Ω loads. The default output swing upon power-up is 400mVpp differential. 3.9 Automatic and Manual Data Rate Selection The GS1675 can be configured to manually lock to a specific data rate or automatically search for and lock to the incoming data rate. The default configuration is AUTO mode. This can be changed via the host interface. In AUTO mode, the SS[1:0] registers become read only, and the bit pattern indicates the data rate at which the PLL is currently locked to (or previously locked to). The search algorithm cycles through the data rates and starts over if that data rate is not found (see Figure 3-2). A “search algorithm” cycles through the supported data rates until lock is achieved, as shown in Figure 3-2 below. GS1675 SD/HD SDI Reclocker Data Sheet 54174 - 1 June 2011 14 of 37 Power up 270Mb/s 1485Mb/s *Note: the search algorithm does not necessarily begin with 270Mb/s. Figure 3-2: GS1675 Automatic Mode Search Algorithm In MANUAL mode, the SS[1:0] registers become read or write accessible, and the data rate can be programmed. In this mode, the search algorithm is disabled and the GS1675's PLL will only lock to the data rate selected in accordance with Table 3-4. Table 3-4: Data Rate Indication/Selection Bit Pattern SS[1:0] Data Rate (Mb/s) 0 Reserved for 3G migration 1 270 2 1485 or 1485/1.001 3 Reserved for 3G migration 3.10 SD/HD Indication The SD/HD signal indicates the output data rate of the device and can be connected to the SD/HD input pin of the GS1678 and GS1679. When this signal is HIGH, the data rate is 270Mb/s. This signal is LOW for all other data rates. This signal is also LOW when the device is operating in bypass mode (Auto-bypass and User-bypass). The SD/HD signal is LOW when the device is not locked. 3.11 Bypass Mode In bypass mode, the GS1675 passes the data at the inputs, directly to the output. There are two register bits that control the bypass function: BYPASS and AUTOBYPASS. GS1675 SD/HD SDI Reclocker Data Sheet 54174 - 1 June 2011 15 of 37 The BYPASS bit is an active-high signal which forces the GS1675 into bypass mode for as long as the bit is asserted HIGH. The AUTOBYPASS bit is an active-high signal that places the GS1675 into bypass mode only when the PLL has not locked to a data rate. Table 3-5: Bypass Modes Bypass Autobypass Device Operation HIGH X Bypass Mode LOW HIGH Bypass Mode if the PLL has not locked to a data rate LOW LOW Power-up default. Normal Operation, part always tries to lock to the incoming data stream. Note that if BYPASS is HIGH, this will override the AUTOBYPASS functionality. When the GS1675's PLL is not locked and BYPASS = LOW and AUTOBYPASS = LOW, the serial digital output DDO/DDO will produce invalid data. The AUTOBYPASS function will bypass unsupported signal rates without producing bit errors. 3.12 DVB-ASI The GS1675 also reclocks DVB-ASI signals at 270Mb/s. In auto mode, the device will automatically lock to the incoming 270Mb/s signal. In manual mode, the SS[1:0] bits must be set to 01 (270Mb/s) to ensure proper operation. 3.13 Output Mute and Data/Clock Output Selection The DATA_MUTE register is provided to allow muting of the primary serial digital data output. Setting DATA_MUTE = LOW will force the serial digital outputs DDO/DDO to mute (statically latch HIGH) under all conditions and operating modes. DATA_MUTE will also mute the secondary digital data output when DATA/CLOCK is set HIGH. The DDO1_DISABLE register is provided to allow the second data/clock output to be powered down. When DDO1_DISABLE is set LOW, the serial digital clock outputs DDO1/RCO and DDO1/RCO are muted and the driver is powered-down. The DATA/CLOCK register is provided to allow the second output to emit a copy of the reclocked serial data or the recovered clock. By default, this output will be set as DATA. GS1675 SD/HD SDI Reclocker Data Sheet 54174 - 1 June 2011 16 of 37 Table 3-6: Configuration of GS1675 Output Drivers and Mute/Disable Pins DATA_MUTE DDO1_DISABLE DATA/CLOCK DDO0 DDO1/RCO 1 1 0 DATA CLOCK 1 1 1 DATA DATA 0 1 0 MUTE CLOCK 0 1 1 MUTE MUTE 1 0 X DATA Power down 0 0 X MUTE Power down 3.14 Host Interface 3.14.1 Introduction The GS1675 offers a Serial Peripheral Interface (SPI) to access advanced features and programmability. The polarity of the HIF pin tells the GS1675 whether or not the host interface is active (HIF = 0) or in legacy mode (HIF = 1). Using the host interface, it is possible to override the control pin settings, and such settings will persist until the device has been powered-down and/or reset. The host interface is capable of reading hard-wired pin configuration, pin override settings and the values of all status monitoring pins. There is an optional 3-state feature available in the Control Status Registers (CSR) that puts the SPI SDO to high-impedance when it’s not being used (Register: TOP_1, bit: 2). 3.14.2 Legacy Mode & Startup In legacy mode, basic configuration of the device is available at the pin level. In this mode, register settings are automatically set to default so that the GS1675 is live at power-up. 3.14.3 Host Interface Mode & Startup In host interface mode, the user gains access to Control and Status Registers (CSRs) that manage advanced features. In this mode, equalizer and de-emphasis settings are set through the CSR. The SPI control is functional at startup without need for a reset signal. However, to clear the registers to their default state, a reset command is recommended via the SPI. This is done by setting the R bit (reset) LOW in the command word. This will guarantee the CSR will not start up in a random state. The maximum operating speed of the SPI is 10MHz. GS1675 SD/HD SDI Reclocker Data Sheet 54174 - 1 June 2011 17 of 37 3.14.4 Clock & Data Timing The SPI signals are Serial Data Input (SDI), Serial Data Output (SDO), active-low Chip Select (CS), and Serial Clock Input (SCK). The host interface operates in SPI Mode 0, i.e. the SDI input will latch data in on the rising edge of SCK. The SDO data output will transition on falling edges of SCK. Data is transmitted or received on the SPI port MSB first LSB last. SCK CS Cycle # SDI 1 2 3 4 5 6 7 8 z 1 2 3 4 5 6 7 8 z SDO z 1 2 3 4 5 6 7 8 z Figure 3-3: Data Clock Alignment 3.14.5 Single Device Operation For applications with a single device or applications with multiple devices where daisy chaining is not desired, the chain position bits C[6:0] should always be set to 0. As a by-product of the daisy chaining feature, Read and Write operations experience a 32 SCK cycle latency from SDI to SDO. For more details on daisy-chaining, refer to Section 3.14.8 on page 22. rw Read/ Write 0 0 R A[4:0] C N[6:0] = `0000000’ Reset Address Chain Position Figure 3-4: 16-bit Command Format GS1675 SD/HD SDI Reclocker Data Sheet 54174 - 1 June 2011 18 of 37 3.14.6 Write Operation - Single Device A Write operation consists of a 16-bit command word and a 16-bit data word, followed by 32 cycles with the slave SDI held HIGH. When writing to a single non-daisy chained device, the following format should be used: 16 bit command rw R/W 0 R A[4:0] C[6:0] = 0 Reset Address Chain Position 0 CS MOSI Command Command [15:0] Data [15:0] [15:0] MISO Data High 32 cycles Command’ [15:0] Data [15:0] Figure 3-5: Single Device Write 1. At power-up, the device should be reset by setting the R bit LOW. A simple way to accomplish a reset is to hold the slave SDI line LOW for an entire 64 cycle communication. 2. For a Write operation, the r/w bit should be set to 0. 3. The 2nd and 3rd bits are reserved, and should be set to 0. 4. The R bit should always be set HIGH for a normal Write operation. 5. Refer to the Register Map for information on Address and Data bits. 6. The slave SDI line should be held HIGH for 32 cycles before de-asserting CS. GS1675 SD/HD SDI Reclocker Data Sheet 54174 - 1 June 2011 19 of 37 3.14.7 Read Operation - Single Device For Reading from a device the following format should be used: 16 bit command rw R/W 0 R A[4:0] C[6:0] = 0 Reset Address Chain Position 0 CS MOSI Command [15:0] Data High 16 cycles MISO Data High 16 cycles Data High 16 cycles Command’ [15:0] Data [15:0] Figure 3-6: Single Device Read 1. For a Read operation, the r/w bit should be set to 1. 2. The 2nd and 3rd bits are reserved and should be set to 0. 3. The R bit should always be set HIGH for a normal Read Operation. 4. Data Out at the slave SDO will appear after holding the slave SDI line HIGH for 32 cycles. 5. The 16-bit data is now available on the slave SDO line. Detailed timing diagrams for Write and Read can be seen in Figure 3-7 and Figure 3-8. GS1675 SD/HD SDI Reclocker Data Sheet 54174 - 1 June 2011 20 of 37 R/W 0 0 t3 R t1 A4 A3 t2 A2 A1 A0 t8 C6 C5 C4 R/W 0 t3 0 R t1 A4 A3 t2 A2 A1 A0 t8 C6 C5 C4 C3 C3 C2 C2 C1 C0 C1 C0 D15 D14 D13 D12 D11 t6 t7 t8 Output hold time (15pF load) CS_n HIGH after last HOST_CLK rising edge Input data hold time GS1675 SD/HD SDI Reclocker Data Sheet 54174 - 1 June 2011 t3 Input data setup time D3 t2 D4 HOST_CLK duty cycle D5 t1 D6 HOST_CLK period D7 t0 D8 CS_n LOW before HOST_CLK rising edge D9 Symbol D10 Parameter Table 3-7: SPI Interface Specifications Figure 3-8: SPI Read Timing 32 cycles delated SDO SDI CS SCK t0 Figure 3-7: SPI Write Timing 32 cycles delayed SDO SDI CS SCK t0 D2 D0 R/W 0 0 t6 R/W R 50% levels Conditions D1 0 A4 0 A3 R A0 A3 C3 C2 D15 D14 C1 1.5 1.5 40 1.5 60 − − − − 50 − − − − C0 D9 D8 D7 ns ns ns ns % ns ns Units D15 D14 D13 D12 D13 D12 D11 D10 − C4 C0 − C5 C1 100 C6 C2 − A0 C3 − A1 C4 1.5 A2 C5 Max C6 Typ Min A4 A1 75% of HOST_CLK period A2 D11 D6 D10 D5 D9 D4 D8 D3 D7 D2 D6 D1 D5 D0 t7 D4 D3 D2 D1 21 of 37 D0 3.14.8 Daisy Chain Operation For applications with multiple GS1675 devices, it is possible to daisy-chain up to 127 parts in serial. In this configuration, the first device SDI should be connected to the SPI Master SDO. The serial data output of each device is then connected to the serial data input of the following device, and so on. The last device's SDO connects to the Master's SDI. Connecting devices in serial reduces the number of I/O ports required by the master by removing the need for additional chip select lines. SPI Master SCK SDO SDI CS SCK SDI SDO CS SPI Slave Chain Position 0 SCK SDI SDO CS SPI Slave Chain Position 1 SCK SDI SDO CS SPI Slave Chain Position 2 Figure 3-9: Daisy Chained SPI Bus The position of each GS1675 device in the serial chain is referred to as its Chain Position, with 0 corresponding to the first device. The Chain Position in the SPI command word is decoded by each slave to know which device the master is talking to. Each GS1675 slave is designed to output a replica of what it receives at its input after a delay of 32 cycles. The Chain Position part of the command is decremented by one in the duplicated command word at the output. Each device in the chain will only execute the issued command if it verifies that the current chain position is set to 0. A[4:0] C[6:0]=N Chain Position A[4:0] C[6:0]=N-1 Chain Position -1 32 cycles A[4:0] 32 cycles SDI SDO GS1675 SDI SDO C[6:0]=N-2 Chain Position -2 GS1675 Figure 3-10: Chain Position Decoding GS1675 SD/HD SDI Reclocker Data Sheet 54174 - 1 June 2011 22 of 37 3.14.9 Read & Write Operation - Daisy Chained Devices In a serial daisy chain configuration, Read and/or Write operations can be performed to multiple devices in the chain via consecutive operations. Figure 3-11 below shows a simple 3 device configuration. MISO MOSI µC SDI SDO GS1675 SDI SDO GS1675 SDI SDO GS1675 Figure 3-11: Three Devices in Daisy Chain Configuration 3.14.10 Writing to all Devices When writing to all devices in the chain, a Write Command and corresponding Data is required for each device. When the devices are being configured in the same way, all of them will have the same command and data with the exception of the Chain Position bits. This example assumes a 3-device daisy chain. A command is issued to the last device in the chain first, although it is possible to talk to the devices in any order. CS MOSI Command2 [15:0] Data [15:0] Command1 [15:0] Data [15:0] Command0 [15:0] Data [15:0] Data High 32 cycles Chain Position = 2 Chain Position = 1 Chain Position = 0 MISO Command0' [15:0] Data [15:0] Figure 3-12: Daisy Chain Write 1. The first command issued in time is the command for the last device in the chain (chain position = 2). When the first device receives this command it will recognize that the Chain Position is 2 and will not execute the command. It will duplicate the command and data word at its output and decrement the Chain Position by one. 2. Consecutive commands are issued for each device in the chain as shown. GS1675 SD/HD SDI Reclocker Data Sheet 54174 - 1 June 2011 23 of 37 3.14.11 Writing to a Single Device in the Chain The following example shows how to write to a single device in a chain: CS MOSI CommandN [15:0] DataN [15:0] Data High 32xN cycles Data High 32 cycles Chain Position = N MISO CommandN’ [15:0] DataN [15:0] Chain Position = N (N = 0 for first device in chain) Figure 3-13: Daisy Chain Write to a Single Device 1. The command is issued to Chain Position N. 2. 32xN cycles are required to shift the command through N devices. The device at chain position N executes the command. 3. 32 additional cycles are needed to complete the communication. 3.14.12 Reading from all Devices To read from all devices in the chain, a Read command is issued for each device consecutively. After each command, the data is held HIGH for 16 cycles. Once a device recognizes that it is being talked to, it will output data from the register requested. A clock needs to be applied to cycle the output data through all devices in the chain. CS SDI Command 2 Data HIGH for 16 cycles (Chain Position = 2) Command 1 Data HIGH for 16 cycles Command 0 Data HIGH for 16 cycles (Chain Position = 0) (Chain Position = 1) SDO CS SDI Data held HIGH for 32x3 cycles SDO Command2’ Data2 Command1’ Data1 Command0’ Data0 Figure 3-14: Daisy Chain Read GS1675 SD/HD SDI Reclocker Data Sheet 54174 - 1 June 2011 24 of 37 1. Read command is issued to the last device in the chain, followed by Read commands to the lower chain positions. 2. Clock is applied to cycle the output data through the chain. 3. Command2’ refers to the altered or decremented Command2. 3.14.13 Reading from a Single Device in the Chain The following example shows how to read from a single device in a chain: CS MOSI CommandN [15:0] Data High 16 cycles Data High 32xN cycles Data High 32x(K-N-1) cycles Data High 16 cycles Data High 16 cycles CommandN’ [15:0] DataN [15:0] Chain Position = N MISO Chain Position = N (N = 0 for first device in chain) Chain Length = K (K ≥ 1) Figure 3-15: Daisy Chain Read from a Single Device 1. Read command and 16 cycles of data held HIGH are issued to chain position N. 2. 32xN cycles are applied with data HIGH to cycle the command through N devices in the chain (NOTE: N is 0 for first device in chain). Device N executes the command. 3. With K representing the total number of devices in the chain, 32x(K-N-1) cycles are applied to bring the return data through the rest of the chain. 4. 16 additional cycles are applied until the data from device N is available on the Master SDI. GS1675 SD/HD SDI Reclocker Data Sheet 54174 - 1 June 2011 25 of 37 3.14.14 Host Register Map Table 3-8: Host Register Map Register Name Register Address Bit Position Access Function Default Value Valid Range Comments EQ_1 0x00 15:10 RW Reserved. 9 RW Input Attenuation Enable (ATTEN_EN) 0x0 0 or 1 Enable for input signals above 1Vpp differential 8 RW Equalizer Offset Correction Enable 0x1 0 or 1 Recommend always on 7 RW Equalizer Gain Setting for DDI1 0x0 0 or 1 See supplementary table below 6-5 RW Unused 0x0 0 or 1 − 4 RW Equalizer Gain Setting for DDI0 0x00 0 or 1 See supplementary table below 3 RW Equalizer Enable for DDI1 0x00 0 or 1 See supplementary table below 2-1 RW Unused 0x00 0 or 1 − 0 RW Equalizer Enable for DDI0 0x00 0 or 1 See supplementary table below Equalizer Decode Logic EQ_EN EQ_GAI N EQ Setting Recommended Trace Lengths 0 0 LOW 0 to 10 inches of FR4 0 1 LOW 0 to 10 inches of FR4 1 0 MED 10 to 20 inches of FR4 1 1 HIGH 20 or more inches of FR4 GS1675 SD/HD SDI Reclocker Data Sheet 54174 - 1 June 2011 26 of 37 Table 3-8: Host Register Map Register Name Register Address Bit Position Access DRIVER_1 0x01 15:10 RW 9 TOP_1 0x02 GS1675 SD/HD SDI Reclocker Data Sheet 54174 - 1 June 2011 Function Default Value Valid Range Comments Unused 0x0 0 or 1 − RW Amplitude Control for DDO1 0x1 0 or 1 0 = 800mV swing 1 = 400mV swing 8 RW Amplitude Control for DDO0 0x1 0 or 1 0 = 800mV swing 1 = 400mV swing 7:5 RW De-Emphasis Boost Amplitude Control for DDO1 0x2 0x0 to 0x7 0x0 = Lowest Setting 0x7 = Highest Setting 4:2 RW De-Emphasis Boost Amplitude Control for DDO0 0x2 0x0 to 0x7 0x0 = Lowest Setting 0x7 = Highest Setting 1 RW De-Emphasis Enable for DDO1 0x0 0 or 1 − 0 RW De-Emphasis Enable for DDO0 0x0 0 or 1 − 15:9 RW Reserved. 8:7 RW LOS Threshold Adjust 0x0 0x0 to 0x3 0x0 = least sensitive 0x3 = most sensitive 6:5 RW LOS Detection Method Select 0x0 0x0 to 0x2 0x0 = legacy edge detectionmethod 0x1 = new signal strength detection method 0x2 = dual detection method: both must detect signal present for LOS to be LOW 4 RW LOS Mute Enable 0x0 0 or 1 When enabled the output will automatically mute if LOS is HIGH 3 RW Power Down 0x0 0 or 1 Chip powers down when asserted 2 RW Tri-State Enable for SPI Output 0x0 0 or 1 When enabled the SPI SDO will be high Z when CS is not selected 1 RW Crystal Buffer Disable 0x0 0 or 1 0 = Enabled 1 = Disabled 0 RW Data Polarity Invert 0x0 0 or 1 0 = Not Inverted 1 = Inverted 27 of 37 Table 3-8: Host Register Map Register Name Register Address 0X03 to 0X0B PIN_OR_1 STATUS_1 Bit Position Function Default Value Valid Range Comments Reserved. 0x0C 0X0D 0X0E to 0X11 Access 15:13 RW Unused 0x0 0 or 1 − 12 RW DATA/CLOCK 0x0 0 or 1 − 11 RW DDO1_DISABLE 0x0 0 or 1 − 10 RW DATA_MUTE 0x0 0 or 1 − 9:8 RW KBB 0x0 0x0, 0x2 or 0x3 Equivalent settings: 0x0 = KBB to ground 0x2 = KBB floating 0x3 = KBB to VCC 7 RW SS1 0x0 0 or 1 − 6 RW SS0 0x0 0 or 1 − 5 RW AUTO/MAN 0x0 0 or 1 − 4 RW AUTOBYPASS 0x0 0 or 1 − 3 RW BYPASS 0x0 0 or 1 − 2 RW DDI_SEL1 0x0 0 or 1 -See Table 3-1 for valid values 1 RW DDI_SEL0 0x0 0 or 1 0 RW Pin Override Enable 0x0 0 or 1 When enabled, input values will be taken from this register instead of package pins 15:4 RO Reserved. − − − 3 RO SD/HD − − − 2 RO LOCKED − − − 1 RO SS1 − − − 0 RO SS0 − − − Reserved. GS1675 SD/HD SDI Reclocker Data Sheet 54174 - 1 June 2011 28 of 37 3.15 Device Power Up In host mode (HIF pin tied LOW), control & status registers (CSRs) may start up in a random state. There is a bit in the command word R which will reset the CSR when set LOW. In non-host mode (HIF pin tied HIGH), the HIF pin is used to trigger an internal reset signal to place all registers in a deterministic, default state upon power-up. In either host mode or non-host mode, other internal state machines (example: offset correction and PLL) automatically recover from any state at start-up with no reset required. It takes ~10μs for the device to lock after start-up. 3.16 Standby The purpose of Standby mode is to allow operating power to be reduced when the device's functionality is not required, and to have a rapid and simple transition to full operation when the device is required. In order to achieve this, the device can be powered-down by writing a ‘1’ to the ‘Power Down’ bit located in register address 0x02. GS1675 SD/HD SDI Reclocker Data Sheet 54174 - 1 June 2011 29 of 37 4. Typical Application Circuit 3 VCC2 JP5 2 VCO_SEL 1 R23 R24 422R VCC2 267R VDD_DIG (Pin14) VCC_VCO (Pin9) C31 C30 C33 10u C32 1u 10n C34 VCC_DDO1 (Pin19) VCC_DDO0 (Pin23) C20 C23 C27 10n C13 C15 C16 10n DNP DNP 10n DNP DNP VCC_CP (Pin32) C7 10n 220n GND GND VEE_DDO0 (Pin24) 7 HIFb 4 CSb SCK SDO SDI 27 28 29 30 8 1 2 C3 47n C4 220n DDI0 DDO0 DDI1 DDO1/RCO DDI1 DDO1/RCO GS1675 CS SCK SDO SDI XTAL- 22 21 Data Output 0 18 17 Data Output 1 ABM7-27.000MHZ-D2Y-T 26 Y1 R6 C1 25 XTAL+ NC LF+ CP_CAP SD/HD LOS LOCKED 18p GND 1M 16 13 12 C2 SD/HD LOS LOCKED 18p GND 10 15 20 24 31 GND GND DDO0 HIF VEE_CP (Pin31) TAB 6 Data Input 1 DDI0 VEE_VCO VSS_DIG VEE_DDO1 VEE_DDO0 VEE_CP 3 5 Data Input 0 SPI VEE_DDO1 (Pin20) VDD_1P8 VCC_VCO VDD_DIG VCC_DDO1 VCC_DDO0 VCC_CP U2 VSS_DIG (Pin15) 11 9 14 19 23 32 VEE_VCO (Pin10) GND Figure 4-1: GS1675 Typical Application Circuit GS1675 SD/HD SDI Reclocker Data Sheet 54174 - 1 June 2011 30 of 37 5. Input/Output Circuits VCC 5.55kΩ 12.96kΩ 25Ω VCC 25Ω DDI VCC 25Ω 25Ω DDI Figure 5-1: High-speed Inputs (DDI0, DDI0, DDI1, DDI1) VCC 2.5µA VCC 1.4kΩ VREF IN Figure 5-2: Low-speed Input with weak internal pull-up (HIF) VCC VCC 972Ω OUT Figure 5-3: Low-speed Outputs (LOCKED, LOS, SD/HD) GS1675 SD/HD SDI Reclocker Data Sheet 54174 - 1 June 2011 31 of 37 VCC VCC VCC 50Ω 50Ω DDO DDO Figure 5-4: High-speed Outputs (DDO1/RCO, DDO1/RCO, DDO0, DDO0) VCC VCC EN VCC VCC XTAL+ 246Ω XTALEN Figure 5-5: High-speed Crystal Oscillator I/O (XTAL-, XTAL+) VCC IN VCC 1kΩ 2.5µA Figure 5-6: SPI Inputs (CS, SCK, SDI) GS1675 SD/HD SDI Reclocker Data Sheet 54174 - 1 June 2011 32 of 37 VCC VCC 1.4kΩ VREF 2.5µA VCC Tgate SDO SPI SDO tri-state Logic Figure 5-7: SPI Output (SDO) GS1675 SD/HD SDI Reclocker Data Sheet 54174 - 1 June 2011 33 of 37 6. Package and Ordering Information 6.1 Package Dimensions Detail A 3.300±0.050 Exp. DAP 5.000±0.050 Pin 1 dot by marking 0.180 Typ. 0. 0 15 p. Ty 0.500 Bsc Pin #1 Identification Chamfer 0.400 x 45° 3.300±0.050 Exp. DAP 5.000±0.050 0.000-0.100 0.240±0.050 Detail A 0.375±0.050 3.500 Ref. Top View Bottom View 0.750 ±0.050 0.000-0.050 0.203 Ref. Side View 6.2 Recommended PCB Footprint 0.5 0.85 0.25 3.45 4.1 4.95 5.8 3.45 0.25 4.1 5.8 GS1675 SD/HD SDI Reclocker Data Sheet 54174 - 1 June 2011 NOTE: All dimensions are in millimeters. 34 of 37 6.3 Packaging Data Parameter Value Package Type 5mm x 5mm 32-pin QFN Moisture Sensitivity Level 3 Junction to Case Thermal Resistance, θj-c 19.9°C/W Junction to Air Thermal Resistance, θj-a (at zero airflow) 34.9°C/W Junction to Board Thermal Resistance, θj-b 12.5°C/W Psi, ψ 0.5°C/W Pb-free and RoHS Compliant Yes 6.4 Marking Diagram Pin 1 Indicator HD-SDI GS1675 XXXXE3 YYWW GS1675 SD/HD SDI Reclocker Data Sheet 54174 - 1 June 2011 GS1675 - Package Mark XXXX - Last 4 digits (excluding decimal) of SAP Batch Assembly (FIN) as listed on Packing Slip E3 - Pb-free & Green Indicator YYWW - Date Code 35 of 37 6.5 Solder Reflow Profile Temperature 60-150 sec. 20-40 sec. 260°C 250°C 3°C/sec max 217°C 6°C/sec max 200°C 150°C 25°C Time 60-180 sec. max 8 min. max Figure 6-1: Maximum Pb-free Solder Reflow Profile 6.6 Ordering Information Part Number Package Temperature Range GS1675 GS1675-INE3 Pb-free 32-pin QFN -40°C to 85°C GS1675 GS1675-INTE3 Pb-free 32-pin QFN (250pc. tape and reel) -40°C to 85°C GS1675 GS1675-INTE3Z Pb-free 32-pin QFN (2.5k tape and reel) -40°C to 85°C GS1675 SD/HD SDI Reclocker Data Sheet 54174 - 1 June 2011 36 of 37 Revision History Version ECR PCN Date Changes and/or Modifications 1 156399 – June 2011 Added Host Register Map. 0 154128 – May 2010 Converted to Data Sheet. A 153741 – April 2010 New document. DOCUMENT IDENTIFICATION CAUTION DATA SHEET ELECTROSTATIC SENSITIVE DEVICES The product is in production. Gennum reserves the right to make changes to the product at any time without notice to improve reliability, function or design, in order to provide the best product possible. DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION GENNUM CORPORATE HEADQUARTERS Phone: +1 (905) 632-2996 Fax: +1 (905) 632-2055 4281 Harvester Road, Burlington, Ontario L7L 5M4 Canada E-mail: [email protected] www.gennum.com OTTAWA SNOWBUSH IP - A DIVISION OF GENNUM GERMANY 415 Legget Drive, Suite 200 Kanata, Ontario K2K 2B2 Canada 439 University Ave. Suite 1700 Toronto, Ontario M5G 1Y8 Canada Hainbuchenstraße 2 80935 Muenchen (Munich), Germany Phone: +1 (613) 270-0458 Phone: +1 (416) 925-5643 Fax: +49-89-35804653 Fax: +1 (613) 270-0429 Fax: +1 (416) 925-0581 E-mail: [email protected] CALGARY E-mail: [email protected] 3553 - 31st St. N.W., Suite 320 Calgary, Alberta T2L 2K7 Canada Web Site: http://www.snowbush.com Phone: +1 (403) 284-2672 UNITED KINGDOM South Building, Walden Court Parsonage Lane, Bishop’s Stortford Hertfordshire, CM23 5DB United Kingdom MEXICO 288-A Paseo de Maravillas Jesus Ma., Aguascalientes Mexico 20900 NORTH AMERICA WESTERN REGION 691 South Milpitas Blvd., Suite #200 Milpitas, CA 95035 United States Phone: +1 (408) 934-1301 Fax: +1 (408) 934-1029 Phone: +1 (416) 848-0328 E-mail: [email protected] JAPAN KK NORTH AMERICA EASTERN REGION Fax: +44 1279 714171 Shinjuku Green Tower Building 27F 6-14-1, Nishi Shinjuku Shinjuku-ku, Tokyo, 160-0023 Japan INDIA Phone: +81 (03) 3349-5501 #208(A), Nirmala Plaza, Airport Road, Forest Park Square Bhubaneswar 751009 India Fax: +81 (03) 3349-5505 Phone: +91 (674) 653-4815 TAIWAN Fax: +91 (674) 259-5733 6F-4, No.51, Sec.2, Keelung Rd. Sinyi District, Taipei City 11502 Taiwan R.O.C. Phone: +44 1279 714170 Phone: +49-89-35831696 E-mail: [email protected] 4281 Harvester Road Burlington, Ontario L7L 5M4 Canada Phone: +1 (905) 632-2996 Fax: +1 (905) 632-2055 E-mail: [email protected] Web Site: http://www.gennum.co.jp Phone: (886) 2-8732-8879 Fax: (886) 2-8732-8870 E-mail: [email protected] Gennum Corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. The sale of the circuit or device described herein does not imply any patent license, and Gennum makes no representation that the circuit or device is free from patent infringement. All other trademarks mentioned are the properties of their respective owners. GENNUM and the Gennum logo are registered trademarks of Gennum Corporation. © Copyright 2010 Gennum Corporation. All rights reserved. www.gennum.com GS1675 SD/HD SDI Reclocker Data Sheet 54174 - 1 June 2011 37 of 37 37