Sample & Buy Product Folder Support & Community Tools & Software Technical Documents DRV8701 SLVSCX5B – MARCH 2015 – REVISED JULY 2015 DRV8701 Brushed DC Motor Full-Bridge Gate Driver 1 Features 2 Applications • • • • • • • 1 • • • • • • • • • • Single H-Bridge Gate Driver – Drives Four External N-Channel MOSFETs – Supports 100% PWM Duty Cycle 5.9-V to 45-V Operating Supply Voltage Range Two Control Interface Options – PH/EN (DRV8701E) – PWM (DRV8701P) Adjustable Gate Drive (5 Levels) – 6-mA to 150-mA Source Current – 12.5-mA to 300-mA Sink Current Supports 1.8-V, 3.3-V, and 5-V Logic Inputs Current Shunt Amplifier (20 V/V) Integrated PWM Current Regulation – Limits Motor Inrush Current Low-Power Sleep Mode (9 μA) Two LDO Voltage Regulators to Power External Components – AVDD: 4.8 V, up to 30-mA Output Load – DVDD: 3.3 V, up to 30-mA Output Load Small Package and Footprint – 24-Pin VQFN (PowerPAD™) – 4.0 × 4.0 × 0.9 mm Protection Features: – VM Undervoltage Lockout (UVLO) – Charge Pump Undervoltage (CPUV) – Overcurrent Protection (OCP) – Pre-Driver Fault (PDF) – Thermal Shutdown (TSD) – Fault Condition Output (nFAULT) Industrial Brushed-DC Motors Robotics Home Automation Industrial Pumps and Valves Power Tools Handheld Vacuum Cleaners 3 Description The DRV8701 is a single H-bridge gate driver that uses four external N-channel MOSFETs targeted to drive a 12-V to 24-V bidirectional brushed DC motor. A PH/EN (DRV8701E) or PWM (DRV8701P) interface allows simple interfacing to controller circuits. An internal sense amplifier allows for adjustable current control. The gate driver includes circuitry to regulate the winding current using fixed off-time PWM current chopping. DRV8701 drives both high- and low-side FETs with 9.5-V VGS gate drive. The gate drive current for all external FETs is configurable with a single external resistor on the IDRIVE pin. A low-power sleep mode is provided which shuts down internal circuitry to achieve very-low quiescent current draw. This sleep mode can be set by taking the nSLEEP pin low. Internal protection functions are provided: undervoltage lockout, charge pump faults, overcurrent shutdown, short-circuit protection, predriver faults, and overtemperature. Fault conditions are indicated on the nFAULT pin. Device Information(1) PART NUMBER PACKAGE DRV8701 BODY SIZE (NOM) VQFN (24) 4.00 × 4.00 x 0.90 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. SPACE Gate-Drive Current tDRIVE Simplified System Block Diagram ISTRONG IHOLD IHOLD IDRIVE,SNK IDRIVE,SRC High-side gate drive current 5.9V to 45 V IHOLD DRV8701 PH/EN or PWM nSLEEP VREF tDRIVE sense Protection LDO M 3.3 & 4.8 V 30 mA Low-side gate drive current IHOLD IHOLD IDRIVE,SRC nFAULT Shunt Amp FETs ISTRONG sense output Gate drive IDRIVE,SNK Controller H-Bridge Gate Driver High-side VGS IHOLD Low-side VGS 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DRV8701 SLVSCX5B – MARCH 2015 – REVISED JULY 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 5 6.1 6.2 6.3 6.4 6.5 6.6 5 5 5 6 7 9 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 12 7.1 Overview ................................................................. 12 7.2 Functional Block Diagram ....................................... 13 7.3 Feature Description................................................. 14 7.4 Device Functional Modes........................................ 26 8 Application and Implementation ........................ 28 8.1 Application Information............................................ 28 8.2 Typical Applications ............................................... 28 9 Power Supply Recommendations...................... 32 9.1 Bulk Capacitance Sizing ......................................... 32 10 Layout................................................................... 33 10.1 Layout Guidelines ................................................. 33 10.2 Layout Example .................................................... 33 11 Device and Documentation Support ................. 34 11.1 11.2 11.3 11.4 11.5 Documentation Support ........................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 34 34 34 34 34 12 Mechanical, Packaging, and Orderable Information ........................................................... 34 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (May 2015) to Revision B • Updated test conditions for IDRIVE,SNK and corrected TYP values ........................................................................................... 8 Changes from Original (March 2015) to Revision A • 2 Page Page Updated device status to production data ............................................................................................................................. 1 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: DRV8701 DRV8701 www.ti.com SLVSCX5B – MARCH 2015 – REVISED JULY 2015 5 Pin Configuration and Functions 15 19 20 21 22 GND (PPAD) 3 4 16 15 5 14 6 13 7 12 11 9 DVDD nFAULT SNSOUT SO IDRIVE AVDD 10 13 8 14 6 7 5 17 SH1 GH1 GND IN1 IN2 nSLEEP 12 16 2 AVDD 4 18 11 GND (PPAD) 3 1 9 17 VM VCP CPH CPL GND VREF 10 2 SH1 GH1 GND PH EN nSLEEP 8 18 DVDD nFAULT SNSOUT SO IDRIVE 1 23 24 19 20 21 22 23 24 VM VCP CPH CPL GND VREF GH2 SH2 GL2 SP SN GL1 RGE Package 24-Pin VQFN DRV8701P Top View GH2 SH2 GL2 SP SN GL1 RGE Package 24-Pin VQFN DRV8701E Top View DRV8701E (PH/EN) PIN NAME NO. TYPE DESCRIPTION EN 14 Input Bridge enable input Logic low places the bridge in brake mode; see Table 1 PH 15 Input Bridge phase input Controls the direction of the H-bridge; see Table 1 DRV8701P (PWM) PIN NAME NO. TYPE IN1 15 Input IN2 14 Input DESCRIPTION Bridge PWM input Logic controls the state of H-bridge; see Table 2 Common Pins PIN NAME VM NO. 1 TYPE DESCRIPTION Power Power supply Connect to motor supply voltage; bypass to GND with a 0.1-µF ceramic plus a 10-µF minimum capacitor rated for VM; additional capacitance may be required based on drive current Power Device ground Must be connected to ground Power Charge pump output Connect a 16-V, 1-µF ceramic capacitor to VM Power Charge pump switching nodes Connect a 0.1-µF X7R capacitor rated for VM between CPH and CPL 5 GND 16 PPAD VCP 2 CPH 3 CPL 4 DVDD 8 Power Logic regulator 3.3-V logic supply regulator; bypass to GND with a 6.3-V, 1-µF ceramic capacitor AVDD 7 Power Analog regulator 4.8-V analog supply regulator; bypass to GND with a 6.3-V, 1-µF ceramic capacitor nSLEEP 13 Input Device sleep mode Pull logic low to put device into a low-power sleep mode with FETs High-Z; internal pulldown IDRIVE 12 Input Gate drive current setting pin Resistor value or voltage forced on this pin sets the gate drive current; see applications section for more details Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: DRV8701 3 DRV8701 SLVSCX5B – MARCH 2015 – REVISED JULY 2015 www.ti.com Common Pins (continued) PIN NAME NO. TYPE DESCRIPTION VREF 6 Input Analog reference input Controls the current regulation; apply a voltage between 0.3 V and AVDD nFAULT 9 Open Drain Fault indication pin Pulled logic low with fault condition; open-drain output requires an external pullup SNSOUT 10 Open Drain Sense comparator output Pulled logic low when the drive current hits the current chopping threshold; open-drain output requires an external pullup SO 11 Output Shunt amplifier output Voltage on this pin is equal to the SP voltage times AV plus an offset; place no more than 1 nF of capacitance on this pin SN 20 Input Shunt amplifier negative input Connect to SP through current sense resistor and to GND SP 21 Input Shunt amplifier positive input Connect to low-side FET source and to SN through current sense resistor GH1 17 GH2 24 Output High-side gate Connect to high-side FET gate GL1 19 GL2 22 Output Low-side gate Connect to low-side FET gate SH1 18 SH2 23 Phase node Connect to high-side FET source and low-side FET drain Input External Passive Components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF ceramic capacitor rated for VM CVM2 VM GND ≥10-µF capacitor rated for VM CVCP VCP VM 16-V, 1-µF ceramic capacitor CSW CPH CPL 0.1-µF X7R capacitor rated for VM CDVDD DVDD GND 6.3-V, 1-µF ceramic capacitor CAVDD AVDD GND 6.3-V, 1-µF ceramic capacitor RIDRIVE IDRIVE GND See Typical Applications for resistor sizing RnFAULT VCC (1) nFAULT ≥10-kΩ pullup SNSOUT ≥10-kΩ pullup SN/GND Optional low-side sense resistor RSNSOUT VCC RSENSE SP (1) (1) VCC is not a pin on the DRV8701, but a VCC supply voltage pullup is required for open-drain outputs nFAULT and SNSOUT. The system controller supply can be used for this pullup voltage, or these pins can be pulled up to either AVDD or DVDD. External FETs 4 Component Gate Drain Source QHS1 GH1 VM SH1 QLS1 GL1 SH1 SP or GND QHS2 GH2 VM SH2 QLS2 GL2 SH2 SP or GND Recommended Supports up to 200-nC FETs at 40-kHz PWM; see Detailed Design Procedure for more details Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: DRV8701 DRV8701 www.ti.com SLVSCX5B – MARCH 2015 – REVISED JULY 2015 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range referenced with respect to GND (unless otherwise noted) Power supply voltage (VM) Power supply voltage ramp rate (VM) (1) MIN MAX UNIT –0.3 47 V 0 2 V/µs Charge pump voltage (VCP, CPH) –0.3 VM + 12 V Charge pump negative switching pin (CPL) –0.3 VM V Internal logic regulator voltage (DVDD) –0.3 3.8 V Internal analog regulator voltage (AVDD) –0.3 5.75 V Control pin voltage (PH, EN, IN1, IN2, nSLEEP, nFAULT, VREF, IDRIVE, SNSOUT) –0.3 5.75 V High-side gate pin voltage (GH1, GH2) –0.3 VM + 12 V Continuous phase node pin voltage (SH1, SH2) –1.2 VM + 1.2 V Pulsed 10 µs phase node pin voltage (SH1, SH2) –2.0 VM + 2 V Low-side gate pin voltage (GL1, GL2) –0.3 12 V Continuous shunt amplifier input pin voltage (SP, SN) –0.5 1 V –1 1 V –0.3 5.75 V Pulsed 10-µs shunt amplifier input pin voltage (SP, SN) Shunt amplifier output pin voltage (SO) Open-drain output current (nFAULT, SNSOUT) 0 10 mA Gate pin source current (GH1, GL1, GH2, GL2) 0 250 mA Gate pin sink current (GH1, GL1, GH2, GL2) 0 500 mA Shunt amplifier output pin current (SO) 0 5 mA Operating junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM) ESD stress voltage (1) ±2000 Charged device model (CDM) ESD stress voltage (2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX 5.9 45 UNIT V 0 5.5 V 0.3 (1) AVDD V VM Power supply voltage range VCC Logic level input voltage VREF Reference RMS voltage range (VREF) ƒPWM Applied PWM signal (PH/EN or IN1/IN2) 100 kHz IAVDD AVDD external load current 30 (2) mA IDVDD DVDD external load current 30 (2) mA ISO Shunt amplifier output current loading (SO) 5 mA TA Operating ambient temperature 125 °C (1) (2) –40 Operational at VREF = 0 to 0.3 V, but accuracy is degraded Power dissipation and thermal limits must be observed Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: DRV8701 5 DRV8701 SLVSCX5B – MARCH 2015 – REVISED JULY 2015 www.ti.com 6.4 Thermal Information DRV8701 THERMAL METRIC (1) RGE (VQFN) UNIT 24 PINS RθJA Junction-to-ambient thermal resistance 34.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 37.1 °C/W RθJB Junction-to-board thermal resistance 12.2 °C/W ψJT Junction-to-top characterization parameter 0.6 °C/W ψJB Junction-to-board characterization parameter 12.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 3.7 °C/W (1) 6 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: DRV8701 DRV8701 www.ti.com SLVSCX5B – MARCH 2015 – REVISED JULY 2015 6.5 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 45 V 6 9.5 mA 9 15 14 25 POWER SUPPLIES (VM, AVDD, DVDD) VM VM operating voltage IVM VM operating supply current VM = 24 V; nSLEEP high 5.9 IVMQ VM sleep mode supply current nSLEEP = 0 VM = 24 V tSLEEP Sleep time nSLEEP low to sleep mode tWAKE Wake-up time nSLEEP high to output change tON Turn-on time VM > UVLO to output transition DVDD Internal logic regulator voltage External load 0 to 30 mA 3.0 3.3 3.5 V AVDD Internal logic regulator voltage External load 0 to 30 mA 4.4 4.8 5.2 V VM = 12 V; IVCP = 0 to 12 mA 20.5 21.5 22.5 VM = 8 V; IVCP = 0 to 10 mA 13.5 14.4 15 VM = 5.9 V; IVCP = 0 to 8 mA 9.4 9.9 10.4 VM > 12 V 12 8 V < VM < 12 V 10 5.9 V < VM < 8 V 8 TA = 25°C TA = 125°C (1) μA 100 μs 1 ms 1 ms CHARGE PUMP (VCP, CPH, CPL) VCP VCP operating voltage IVCP Charge pump current capacity (1) fVCP Charge pump switching frequency VM > UVLO 200 V mA 400 700 kHz 0.8 V CONTROL INPUTS (PH, EN, IN1, IN2, nSLEEP) VIL Input logic low voltage VIH Input logic high voltage 1.5 V VHYS Input logic hysteresis 100 mV IIL Input logic low current VIN = 0 V IIH Input logic high current VIN = 5 V RPD Pulldown resistance tPD Propagation delay –5 64 PH/EN, IN1/IN2 to GHx/GLx 115 5 μA 78 μA 173 kΩ 500 ns CONTROL OUTPUTS (nFAULT, SNSOUT) VOL Output logic low voltage IO = 2 mA IOZ Output high impedance leakage VIN = 5 V –2 0.1 V 2 μA FET GATE DRIVERS (GH1, GH2, SH1, SH2, GL1, GL2) VGHS VM > 12 V; VGHS with respect to SHx High-side VGS gate drive (gate-toVM = 8 V; VGHS with respect to SHx source) VM = 5.9 V; VGHS with respect to SHx VGLS Low-side VGS gate drive (gate-tosource) tDEAD Output dead time tDRIVE Gate drive time 8.5 9.5 5.5 6.4 7 3.5 4.0 4.5 VM > 12 V 8.5 9.3 10.5 VM = 5.9 V 3.9 4.3 4.9 Observed tDEAD depends on IDRIVE setting RIDRIVE < 1 kΩ to GND RIDRIVE = 33 kΩ ±5% to GND IDRIVE,SRC (1) Peak source current RIDRIVE = 200 kΩ ±5% to GND, or RIDRIVE < 1 kΩ to AVDD 10.5 V V 380 ns 2.5 μs 6 12.5 25 RIDRIVE > 500 kΩ ±5% to GND 100 RIDRIVE = 68 kΩ ±5% to AVDD 150 mA Specified by design and characterization data Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: DRV8701 7 DRV8701 SLVSCX5B – MARCH 2015 – REVISED JULY 2015 www.ti.com Electrical Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN RIDRIVE < 1 kΩ to GND IDRIVE,SNK Peak sink current IHOLD FET holding current ISTRONG FET hold-off strong pulldown ROFF FET gate hold-off resistor TYP MAX UNIT 12.5 RIDRIVE = 33 kΩ ±5% to GND 25 RIDRIVE = 200 kΩ ±5% to GND, or RIDRIVE < 1 kΩ to AVDD 50 RIDRIVE > 500 ±5% kΩ to GND 200 RIDRIVE = 68 kΩ ±5% to AVDD 300 Source current after tDRIVE mA 6 Sink current after tDRIVE mA 25 GHx 490 GLx 690 Pulldown GHx to SHx 200 Pulldown GLx to GND 150 mA kΩ CURRENT SHUNT AMPLIFIER AND PWM CURRENT CONTROL (SP, SN, SO, VREF) VVREF VREF input voltage For current internal chopping AV Amplifier gain VOFF SO offset VSP = VSN = GND ISP 18 20 22 10 < VSP < 50 mV; VSN = GND 16 20 24 50 250 SP input current VSP = 100 mV; VSN = GND tSET Settling time to ±1% VSP = VSN = GND to VSP = 100 mV, VSN = GND CSO (3) Allowable SO pin capacitance PWM current regulation off-time tBLANK PWM blanking time AVDD 50 < VSP < 200 mV; VSN = GND (3) tOFF 0.3 (2) V V/V mV μA -40 1.5 µs 1 nF 25 µs 2 µs PROTECTION CIRCUITS VM falling; UVLO report 5.4 5.8 VM rising; UVLO recovery 5.6 5.9 VUVLO VM undervoltage lockout VUVLO,HYS VM undervoltage hysteresis Rising to falling threshold tUVLO VM UVLO falling deglitch time VM falling; UVLO report VCPUV Charge pump undervoltage CPUV report VDS OCP Overcurrent protection trip level, VDS of each external FET High-side FETs: VM – SHx Low-side FETs: SHx – SP VSP OCP Overcurrent protection trip level, measured by sense amplifier VSP voltage with respect to GND tOCP Overcurrent deglitch time tRETRY (3) Thermal shutdown temperature Die temperature, TJ THYS (3) Thermal shutdown hysteresis Die temperature, TJ (2) (3) 8 CLAMP Gate drive clamping voltage Positive clamping voltage Negative clamping voltage mV 10 μs VM + 2.8 V 0.8 1 V 0.8 1 V 4.5 µs 3 ms Overcurrent retry time TTSD VGS 100 V 150 °C 20 10.5 –1 °C 13 –0.7 –0.5 V Operational at VREF = 0 to 0.3 V, but accuracy is degraded Specified by design and characterization data Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: DRV8701 DRV8701 www.ti.com SLVSCX5B – MARCH 2015 – REVISED JULY 2015 6.6 Typical Characteristics 6.5 6.4 S u p p ly C u rre n t (m A ) 6.3 Supply Current (mA) T A = 125°C T A = 85°C T A = 25°C T A ±& 6.2 6.1 6 5.9 5.8 5.7 5.6 5.5 5 10 15 20 25 30 Supply Voltage VM (V) 35 40 45 6.15 6.1 6.05 6 5.95 5.9 5.85 5.8 5.75 5.7 5.65 5.6 5.55 5.5 -50 VM = 24 V VM = 12 V -25 Figure 1. Supply Current over VM 100 125 D002 Figure 2. Supply Current over Temperature 20 16 T A = 125°C T A = 85°C T A = 25°C T A ±& 18 VM = 24 V VM = 12 V 15 14 13 Sleep Current (µA) 16 S le e p C u rre n t (µ A ) 0 25 50 75 Ambient Temperature (°C) D001 14 12 10 8 12 11 10 9 8 7 6 6 4 5 4 -50 2 5 10 15 20 25 30 Supply Voltage VM (V) 35 40 45 -25 0 25 50 75 Ambient Temperature (°C) D003 Figure 3. Sleep Current over VM 125 D004 Figure 4. Sleep Current over Temperature 12 4.6 VM = 12 V VM = 10 V 11 VM = 8 V VM = 5.9 V T A = 125°C T A = 85°C T A = 25°C T A ±& 4.5 4.4 10 4.3 9 4.2 V C P -V M (V ) V C P -V M (V ) 100 8 7 6 4.1 4 3.9 3.8 3.7 5 3.6 4 3.5 3 3.4 0 1 2 3 4 5 6 7 8 9 10 Load Current (mA) 11 12 13 14 15 0 1 D005 Figure 5. VCP over Load (TA = 25°C) 2 3 4 5 6 7 8 9 10 Load Current (mA) 11 12 13 14 Product Folder Links: DRV8701 D006 Figure 6. VCP over Load (VM = 5.9 V) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated 15 9 DRV8701 SLVSCX5B – MARCH 2015 – REVISED JULY 2015 www.ti.com Typical Characteristics (continued) 4.875 3.295 3.29 4.85 3.285 4.825 3.28 3.275 4.8 AVDD (V) D V D D (V ) 3.27 3.265 3.26 3.255 4.775 4.75 4.725 3.25 3.245 T A = 125°C T A = 85°C 3.24 4.7 T A = 25°C T A ±& 3.235 4.65 3.23 4.625 3.225 0 3 6 9 12 15 18 Load Current (mA) 21 24 27 0 30 12 15 18 21 Load Current (mA) 24 27 30 D008 19.9 19.7 19.5 19.3 19.1 18.9 SP = 225 mV SP = 100 mV SP = 50 mV SP = 10 mV 18.7 VM = 24 V VM = 12 V -25 0 25 50 75 Ambient Temperature (°C) 100 18.5 18.3 -50 125 -25 0 D009 25 50 75 Ambient Temperature (°C) 100 125 D010 Figure 10. Amplifier Gain over Temperature 20 20 19.96 19.92 19.88 19.84 19.8 19.76 19.72 19.68 19.64 19.6 19.56 19.52 19.48 19.44 19.4 19.36 T A = 125°C T A = 85°C T A = 25°C T A ±& 19.8 19.6 19.4 A v (V /V ) A v (V /V ) 9 Figure 8. AVDD Regulator over Load (VM = 12 V) Figure 9. SO Offset over Temperature 19.2 19 18.8 18.6 18.4 MAX MIN 18.2 5 10 15 20 25 30 Supply Voltage VM (V) 35 40 45 18 10 D011 Figure 11. Amplifier Gain over VM (SP = 50 mV) 10 6 20.1 A v (V /V ) 55 52.5 50 47.5 45 42.5 40 37.5 35 32.5 30 27.5 25 22.5 20 17.5 15 -50 3 D007 Figure 7. DVDD Regulator over Load (VM = 12 V) S O O ffs e t (m V ) TA = -40°C TA = +25°C TA = +85°C TA = +125°C 4.675 30 50 70 90 110 130 SP (mV) 150 170 190 210 225 D012 Figure 12. Amplifier Gain over VM and Temperature Range Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: DRV8701 DRV8701 www.ti.com SLVSCX5B – MARCH 2015 – REVISED JULY 2015 Typical Characteristics (continued) 6.2 180 6 140 H ig h -S id e ID R IV E P (m A ) H ig h -S id e ID R IV E P (m A ) 160 120 100 80 150/300 mA 100/200 mA 25/50 mA 60 12.5/25 mA 6/12.5 mA 40 5.8 5.6 5.4 5.2 5 20 0 -50 T A ±& T A = 25°C 4.8 -25 0 25 50 75 Ambient Temperature (°C) 100 5 125 15 15.5 32 H ig h -S id e ID R IV E P (m A ) 33 15 14.5 14 13.5 13 T A ±& T A = 25°C 20 25 30 Supply Voltage VM (V) 35 40 45 D014 Figure 14. 6-/12.5-mA High-Side IDRIVEP over VM 16 12.5 10 D013 Figure 13. High-Side IDRIVEP over Temperature (VM = 12 V) H ig h -S id e ID R IV E P (m A ) T A = 85°C T A = 125°C T A = 85°C T A = 125°C 31 30 29 28 27 26 T A ±& T A = 25°C 25 12 T A = 85°C T A = 125°C 24 5 10 15 20 25 30 Supply Voltage VM (V) 35 40 45 5 10 15 D015 Figure 15. 12.5-/25-mA High-Side IDRIVEP over VM 20 25 30 Supply Voltage VM (V) 35 40 45 D016 Figure 16. 25-/50-mA High-Side IDRIVEP over VM 130 185 180 125 H ig h -S id e ID R IV E P (m A ) H ig h -S id e ID R IV E P (m A ) 175 120 115 110 105 100 T A ±& T A = 25°C T A = 85°C T A = 125°C 95 170 165 160 155 150 145 T A ±& T A = 25°C T A = 85°C T A = 125°C 140 135 90 130 5 10 15 20 25 30 Supply Voltage VM (V) 35 40 45 5 D017 Figure 17. 100-/200-mA High-Side IDRIVEP over VM 10 15 20 25 30 Supply Voltage VM (V) 35 40 45 D018 Figure 18. 150-/300-mA High-Side IDRIVEP over VM Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: DRV8701 11 DRV8701 SLVSCX5B – MARCH 2015 – REVISED JULY 2015 www.ti.com 7 Detailed Description 7.1 Overview The DRV8701 is an H-bridge gate driver (also called a pre-driver or controller). The device integrates FET gate drivers in order to control four external NMOS FETs. The device can be powered with a supply voltage between 5.9 and 45 V. A simple PH/EN (DRV8701E) or PWM (DRV8701P) interface allows interfacing to the controller circuit. A low-power sleep mode is included, which can be enabled using the nSLEEP pin. The gate drive strength can be adjusted to optimize a system for a given FET without adding external resistors in series with the FET gates. The IDRIVE pin allows for selection of the peak current driven into the external FET gate. Both the high-side and low-side FETs are driven with a VGS of 9.5 V nominally when VM > 12 V. At lower VM voltages, the VGS is reduced. The high-side gate drive voltage is generated using a doubler-architecture charge pump that regulates to VM + 9.5 V. This device greatly reduces the component count of discrete motor driver systems by integrating the necessary FET drive circuitry into a single device. In addition, the DRV8701 adds protection features above traditional discrete implementations: UVLO, OCP, pre-driver faults, and thermal shutdown. A start-up (inrush) or running current limitation is built in using a fixed time-off current chopping scheme. The chopping current level is set by choosing the sense resistor value and by setting a voltage on the VREF pin. A shunt amplifier output is provided for accurate current measurements by the system controller. The SO pin outputs a voltage that is 20 times the voltage seen across the sense resistor. 12 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: DRV8701 DRV8701 www.ti.com SLVSCX5B – MARCH 2015 – REVISED JULY 2015 7.2 Functional Block Diagram VM VM 0.1 µF 10 µF minimum VM VM 1 µF 30 mA Gate Driver Charge Pump VGLS SH1 GL1 LS CPL DVDD VM Logic AVDD BDC 3.3-V LDO 1 µF 30 mA GH1 HS VCP CPH 0.1 µF VCP Power VCP 4.8-V LDO GH2 HS 1 µF VGLS LDO Gate Driver VGLS SH2 GL2 LS PH/IN1 EN/IN2 nSLEEP Control Inputs Current Regulation SP IDRIVE + RIDRIVE RSENSE AV SN SNSOUT Outputs SO VREF nFAULT PPAD GND GND Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: DRV8701 13 DRV8701 SLVSCX5B – MARCH 2015 – REVISED JULY 2015 www.ti.com 7.3 Feature Description 7.3.1 Bridge Control The DRV8701E is controlled using a PH/EN interface. The following logic table (Table 1) gives the full H-bridge state when driving a single brushed DC motor. Note that Table 1 does not take into account the current control built into the DRV8701E. Positive current is defined in the direction of xOUT1 → xOUT2. Table 1. DRV8701E (PH/EN) Control Interface nSLEEP EN PH SH1 SH2 AVDD/DVDD 0 X X High-Z High-Z Disabled Sleep mode; H-bridge disabled High-Z Description 1 0 X L L Enabled Brake, low-side slow decay 1 1 0 L H Enabled Reverse drive (current SH2 → SH1) 1 1 1 H L Enabled Forward drive (current SH1 → SH2) The DRV8701P is controlled using a PWM interface (IN1/IN2). The following logic table (Table 2) gives the full Hbridge state when driving a single brushed DC motor. Note that Table 2 does not take into account the current control built into the DRV8701P. Positive current is defined in the direction of xOUT1 → xOUT2. Table 2. DRV8701P (PWM) Control Interface nSLEEP IN1 IN2 SH1 SH2 AVDD/DVDD 0 X X High-Z High-Z Disabled Sleep mode; H-bridge disabled High-Z 1 0 0 High-Z High-Z Enabled Coast; H-bridge disabled High-Z 1 0 1 L H Enabled Reverse (current SH2 → SH1) 1 1 0 H L Enabled Forward (current SH1 → SH2) 1 1 1 L L Enabled Brake; low-side slow decay VM VM 1 Forward drive 1 SH1 Description SH2 2 2 Slow decay (brake) 1 Reverse drive 1 SH1 3 High-Z (coast) SH2 2 2 Slow decay (brake) 3 High-Z (coast) 3 3 Figure 19. H-Bridge Operational States 14 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: DRV8701 DRV8701 www.ti.com SLVSCX5B – MARCH 2015 – REVISED JULY 2015 7.3.2 Half-Bridge Operation The DRV8701 can be used to drive only a single half-bridge instead of a full H-bridge. To operate in this mode, leave GH1 and GL1 disconnected. Also, connect a 1/10 W, 330-Ω 5% resistor from SH1 to GND. GH1 PH/IN1 EN/IN2 SH1 Gate Drive Control Inputs 330 GL1 nSLEEP VM GH2 Logic SH2 Gate Drive GL2 nFAULT BDC SP + Outputs SNSOUT RSENSE AV SN - SO VREF Figure 20. Half-H Bridge Operation Mode For the DRV8701E, this mode is controlled by tying the PH pin low. Table 3 gives the control scheme. EN = 1 enables the high-side FET, and EN = 0 enables the low-side FET. EN = 1 and PH = 1 is an invalid state. Table 3. DRV8701E (PH/EN) Control Interface for Half-H Bridge Mode nSLEEP EN PH SH2 AVDD/DVDD 0 X X High-Z Disabled Sleep mode; disabled High-Z Description 1 0 X L Enabled Brake, low-side slow decay 1 1 0 H Enabled Drive (Current SH2 → GND) 1 1 1 Invalid state For the DRV8701P, Table 4 gives the control scheme. IN1 = 1 and IN2 = 0 is an invalid state. Table 4. DRV8701P (PWM) Control Interface for Half-H Bridge Mode nSLEEP IN1 IN2 SH2 AVDD/DVDD 0 X X High-Z Disabled Sleep mode; disabled High-Z Description 1 0 0 High-Z Enabled Coast; disabled High-Z 1 0 1 H Enabled Drive (current SH2 → GND) 1 1 0 1 1 1 L Enabled Brake; low-side slow decay Invalid state Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: DRV8701 15 DRV8701 SLVSCX5B – MARCH 2015 – REVISED JULY 2015 www.ti.com 7.3.3 Current Regulation The maximum current through the motor winding is regulated by a fixed off-time PWM current regulation, or current chopping. When an H-bridge is enabled in forward or reverse drive, current rises through the winding at a rate dependent on the DC voltage and inductance of the winding. After the current hits the current chopping threshold, the bridge enters a brake (low-side slow decay) mode until tOFF has expired. Note that immediately after the current is enabled, the voltage on the SP pin is ignored for a period of time (tBLANK) before enabling the current sense circuitry. The PWM chopping current is set by a comparator which compares the voltage across a current sense resistor connected to the SP pin, multiplied by a factor of AV, with a reference voltage from the VREF pin. The factor AV is the shunt amplifier gain, which is 20 V/V in the DRV8701. The chopping current is calculated as follows: 9REF ± 9OFF ICHOP A V u RSENSE (1) Example: If a 50 mΩ sense resistor is used and VREF = 3.3 V, the full-scale chopping current will be 3.25 A. AV is 20 V/V and VOFF is assumed to be 50 mV in this example. For DC motors, current regulation is generally used to limit the start-up and stall current of the motor. If the current regulation feature is not needed, it can be disabled by tying VREF directly to AVDD and tying SP and SN to GND. Drive Current (A) ICHOP Drive Brake / Slow Decay Drive Brake / Slow Decay WWBLANK tOFF WWBLANK tOFF SNSOUT SO (V) VREF Figure 21. Sense Amplifier and Current Chopping Operation During brake mode (slow decay), current is recirculated through the low-side FETs. Because current is not flowing through the sense resistor, SO does not represent the motor current. 16 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: DRV8701 DRV8701 www.ti.com SLVSCX5B – MARCH 2015 – REVISED JULY 2015 7.3.4 Amplifier Output SO The SO pin on the DRV8701 outputs an analog voltage equal to the voltage seen across the SP and SN pins multiplied by AV. The factor AV is the shunt amplifier gain, which is 20 V/V in the DRV8701. SO is only valid during forward or reverse drive. The H-bridge current is approximately equal to: 62 ± 9OFF I A V u RSENSE (2) When SP and SN are 0 V, SO outputs the amplifier offset voltage VOFF. No capacitor is required on the SO pin. I R Logic + - + VCC SP - SN RSENSE AV/(AV-1) x R SNSOUT AV x R SO VREF Figure 22. Sense Amplifier Diagram If the voltage across SP and SN exceeds 1 V, then the DRV8701 flags an overcurrent condition. The SO pin can source up to 5 mA of current. If the pin is shorted to GND, or if a higher-current load is driven by this pin, the output acts as a constant-current source. The output voltage is not representative of the H-bridge current in this state. This shunt amplifier feature can be disabled by tying the SP and SN pins to GND. When the amplifier is disabled, current regulation is also disabled. SO (V) AVDD Slope = Av VOFF SP - SN (V) Figure 23. Sense Amplifier Output 7.3.4.1 SNSOUT The SNSOUT pin of the DRV8701 indicates when the device is in current chopping mode. When the driver is in a slow decay mode caused by internal PWM current chopping (ICHOP threshold hit), the open-drain SNSOUT output is pulled low. If the current regulation is disabled, then the SNSOUT pin will be high-Z. Note that if the H-bridge is put into a slow decay mode using the inputs (PH/EN or IN1/IN2), then SNSOUT is not pulled low. During forward or reverse drive mode, SNSOUT is high until the DRV8701 is internally forced into current chopping. If the drive current rises above ICHOP, the driver enters a brake mode (low-side slow decay). The SNSOUT pin will be pulled low during this current chopping brake mode. After the driver is re-enabled, the SNSOUT pin is released high-Z and the drive mode is restarted. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: DRV8701 17 DRV8701 SLVSCX5B – MARCH 2015 – REVISED JULY 2015 www.ti.com 7.3.5 PWM Motor Gate Drivers The DRV8701 contains gate drivers for a single H-bridge with external NMOS FETs. Figure 24 shows a block diagram of the gate driver circuitry. VM VGHS PH or IN1 GH1 EN or IN2 ROFF SH1 Pre-Drive nSLEEP VGLS GL1 ROFF Logic VM VGHS BDC GH2 ROFF SH2 Pre-Drive VGLS GL2 ROFF SP RSENSE SN Figure 24. PWM Motor Gate Drivers Gate drivers inside the DRV8701 directly drive N-channel MOSFETs, which drive the motor current. The highside gate drive is supplied by the charge pump, while the low-side gate drive voltage is generated by an internal regulator. The peak drive current of the gate drivers is adjustable through the IDRIVE pin. Peak source currents may be set to 6, 12.5, 25, 100, or 150 mA. The peak sink current is approximately 2× the peak source current. Adjusting the peak current changes the output slew rate, which also depends on the FET input capacitance and gate charge. The peak drive current is selected by setting the value of the RIDRIVE resistor on the IDRIVE pin or by forcing a voltage onto the IDRIVE pin (see Table 6 for details). Fast switching times can cause extra voltage noise on VM and GND. This can be especially due to a relatively slow reverse-recovery time of the low-side body diode, where it conducts reverse-bias momentarily, being similar to shoot-through. Slow switching times can cause excessive power dissipation since the external FETs take a longer time to turn on and turn off. 18 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: DRV8701 DRV8701 www.ti.com SLVSCX5B – MARCH 2015 – REVISED JULY 2015 When changing the state of the output, the peak current (IDRIVE) is applied for a short drive period (tDRIVE) to charge the gate capacitance. After this time, a weaker current source (IHOLD) is used to keep the gate at the desired state. When selecting the gate drive strength for a given external FET, the selected current must be high enough to fully charge and discharge the gate during tDRIVE, or excessive power will be dissipated in the FET. During high-side turn-on, the low-side gate is pulled low with a strong pull-down (ISTRONG). This prevents the lowside FET QGS from charging and keeps the FET off, even when there is fast switching at the outputs. The pre-driver circuits include enforcement of a dead time in analog circuitry, which prevents the high-side and low-side FETs from conducting at the same time. When switching FETs on, this handshaking prevents the highor low-side FET from turning on until the opposite FET has been turned off. tDRIVE ISTRONG IHOLD IDRIVE,SNK IHOLD IDRIVE,SRC High-side gate drive current IHOLD High-side VGS tDRIVE IHOLD IHOLD IDRIVE,SRC IHOLD ISTRONG IDRIVE,SNK Low-side gate drive current Low-side VGS Figure 25. Gate Driver Output to Control External FETs QGD Miller charge When a FET gate is turned on, three different capacitances must be charged. • QGS – Gate-to-source charge • QGD – Gate-to-drain charge (miller charge) • Remaining QG The FET output is slewing primarily during the QGD charge. 10 25 8 20 6 15 4 10 2 5 Pre-Drive GHx G CGD CGS SHx S 10 QGS 30 40 20 Remaining QG QGD QG gate charge (nC) VDS (drain-to-source) (V) D VGHS VGS (gate-to-source) (V) VM 50 Figure 26. Example FET Gate Charging Profile Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: DRV8701 19 DRV8701 SLVSCX5B – MARCH 2015 – REVISED JULY 2015 www.ti.com 7.3.6 IDRIVE Pin The rise and fall times of the H-bridge output (SHx pins) can be adjusted by setting the IDRIVE resistor value or forcing a voltage onto the IDRIVE pin. The FET gate voltage ramps faster if a higher IDRIVE setting is chosen. The FET gate ramp directly affects the H-bridge output rise and fall time. Tying IDRIVE to GND selects the lowest drive setting of 6-mA source and 12.5-mA sink. If this pin is left unconnected, then the 100-mA source and 200-mA sink setting are selected. If IDRIVE is shorted to AVDD, then the VDS OCP monitor on the high-side FETs is disabled. In this setting, the gate driver is configured as 25-mA source and 50-mA sink. + 4.3V AVDD + 3.7V IDRIVE - 190k Digital Core + 2.5V 310k + 1.3V + 0.1V - Figure 27. IDRIVE Pin Internal Circuitry Table 5. IDRIVE Pin Configuration Settings IDRIVE Resistance IDRIVE Voltage <1 kΩ to GND GND 33 kΩ ±5% to GND 0.7 V ±5% 200 kΩ ±5% to GND Source Current (IDRIVE,SRC) Sink Current (IDRIVE,SNK) HS OCP Monitor 6 mA 12.5 mA ON 12.5 mA 25 mA ON 2 V ±5% 25 mA 50 mA ON >500 kΩ to GND, High-Z 3 V ±5% 100 mA 200 mA ON 68 kΩ ±5% to AVDD 4 V ±5% 150 mA 300 mA ON <1 kΩ to AVDD AVDD 25 mA 50 mA OFF Table 6. IDRIVE Pin Resistor Settings <1 kΩ to GND 33 kΩ ±5% to GND 200 kΩ ±5% to GND >500 kΩ to GND, High-Z 68 kΩ ±5% to AVDD <1 kΩ to AVDD AVDD AVDD IDRIVE IDRIVE RIDRIVE IDRIVE IDRIVE RIDRIVE ««« 20 IDRIVE ««« IDRIVE IDRIVE 6 / 12.5 mA 12.5 / 25 mA (33 kΩ) 25 / 50 mA (200 kΩ) ««« IDRIVE 100 / 200 mA Submit Documentation Feedback IDRIVE IDRIVE 150 / 300 mA 25 / 50 mA HS OCP monitor off Copyright © 2015, Texas Instruments Incorporated Product Folder Links: DRV8701 DRV8701 www.ti.com SLVSCX5B – MARCH 2015 – REVISED JULY 2015 7.3.7 Dead Time Dead time (tDEAD) is measured as the time when SHx is High-Z between turning off one of the H-bridge FETs and turning on the other. For example, the output is High-Z between turning off the high-side FET and turning on the low-side FET. The DRV8701 inserts a digital dead time of approximately 150 ns. The total dead time also includes the FET gate turn-on time. The total dead time is dependent on the IDRIVE resistor setting because a portion of the FET gate ramp (GHx and GLx pins) includes the observable dead time. 7.3.8 Propagation Delay The propagation delay time (tDELAY) is measured as the time between an input edge to an output change. This time is composed of two parts: an input deglitch time and output slewing delay. The input deglitcher prevents noise on the input pins from affecting the output state. The gate drive slew rate also contributes to the delay time. For the output to change state during normal operation, first, one FET must be turned off. The FET gate is ramped down according to the IDRIVE setting, and the observed propagation delay ends when the FET gate has fallen below the threshold voltage. 7.3.9 Overcurrent VDS Monitor The gate driver circuit monitors the VDS voltage of each external FET when it is driving current. When the voltage monitored is greater than the OCP threshold voltage (VDS OCP), after the OCP deglitch time (tOCP) has expired, an OCP condition will be detected. VM VM + High-side VDS OCP Monitor GH1 SH1 + Low-side VDS OCP Monitor - VM + BDC High-side VDS OCP Monitor + Low-side VDS OCP Monitor - GL1 GH2 SH2 GL2 SP RSENSE SN Figure 28. Overcurrent VDS Monitors When IDRIVE is shorted to AVDD, the VDS OCP monitor on the high-side FETs is disabled. In cases where the VM supplied to the DRV8701 can be different from the external H-bridge supply, this setting must be used in order to prevent false overcurrent detection. In this mode, the IDRIVE current is set to 25-mA source and 50-mA sink. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: DRV8701 21 DRV8701 SLVSCX5B – MARCH 2015 – REVISED JULY 2015 www.ti.com 7.3.10 Charge Pump A charge pump is integrated to supply a high-side NMOS gate drive voltage of VHGS. The charge pump requires a capacitor between the VM and VCP pins. Additionally a low-ESR ceramic capacitor is required between pins CPH and CPL. When VM is below 12 V, this charge pump behaves as a doubler and generates VCP = 2 × VM – 1.5 V if unloaded. Above VM = 12 V, the charge pump regulates VCP such that VCP = VM + 9.5 V. VM 1 µF VCP CPH VM 0.1 µF CPL Charge Pump Figure 29. Charge Pump Diagram 7.3.11 LDO Voltage Regulators Two LDO regulators are integrated into the DRV8701. They can be used to provide the supply voltage for a lowpower microcontroller or other low-current devices. For proper operation, bypass the AVDD and DVDD pins to GND using ceramic capacitors. The AVDD output voltage is nominally 4.8 V, and the DVDD output is nominally 3.3 V. When the AVDD or DVDD current load exceeds 30 mA, the LDO behaves like a constant current source. The output voltage drops significantly with currents greater than this limit. Note that AVDD and DVDD are disabled when the device is in sleep mode (nSLEEP = 0). In addition, when an overtemperature (TSD) or undervoltage (UVLO) fault is encountered, the AVDD regulator is shut off. VM + 4.8 V AVDD - 1 µF 30 mA max VM + 3.3 V DVDD - 1 µF 30 mA max Figure 30. AVDD and DVDD LDOs The power dissipated in the DRV8701 due to these LDOs may be approximated by: Power = (VM – AVDD) × IAVDD + (VM – DVDD) × IDVDD (3) For example at VM = 24 V, drawing 10 mA out of both AVDD and DVDD results in a power dissipation of: Power = (24 V – 4.8 V) × 10 mA + (24 V – 3.3 V) × 10 mA = 192 mW + 207 mW = 399 mW 22 Submit Documentation Feedback (4) Copyright © 2015, Texas Instruments Incorporated Product Folder Links: DRV8701 DRV8701 www.ti.com SLVSCX5B – MARCH 2015 – REVISED JULY 2015 7.3.12 Gate Drive Clamp A clamping structure limits the gate drive output voltage to VGS CLAMP to protect the power FETs from damage. The positive voltage clamp is realized using a series of diodes. The negative voltage clamp uses the body diodes of the internal gate driver FET. VGHS VM IREVERSE GHx VGS > VCLAMP ICLAMP SHx Pre-Drive VGLS VGS negative GLx RSENSE GND Figure 31. Gate Drive Clamp Diagram Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: DRV8701 23 DRV8701 SLVSCX5B – MARCH 2015 – REVISED JULY 2015 www.ti.com 7.3.13 Protection Circuits The DRV8701 is fully protected against VM undervoltage, charge pump undervoltage, overcurrent, gate driver shorts, and overtemperature events. 7.3.13.1 VM Undervoltage Lockout (UVLO) If at any time the voltage on the VM pin falls below the UVLO threshold voltage, all FETs in the H-bridge are disabled, the charge pump is disabled, AVDD is disabled, and the nFAULT pin is driven low. Operation resumes when VM rises above the UVLO threshold. The nFAULT pin is released after operation has resumed. 7.3.13.2 VCP Undervoltage Lockout (CPUV) If at any time the voltage on the VCP pin falls below the charge pump undervoltage threshold voltage (VCPUV), all FETs in the H-bridge are disabled and the nFAULT pin is driven low. Operation resumes when VCP rises above the CPUV threshold. The nFAULT pin is released after operation has resumed. 7.3.13.3 Overcurrent Protection (OCP) Overcurrent is sensed by monitoring the VDS voltage drop across the external FETs (see Figure 28). If the voltage across a driven FET exceeds the overcurrent trip threshold (VDS OCP) for longer than the OCP deglitch time (tOCP), an OCP event is recognized. As a result, all FETs in the H-bridge are disabled and the nFAULT pin is driven low; the driver is re-enabled after the OCP retry period (tRETRY) has passed. nFAULT releases high-Z again at after the retry time. If the fault condition is still present, the cycle repeats. If the fault is no longer present, normal operation resumes and nFAULT remains released high-Z. This VDS overcurrent monitor on the high-side FETs can be disabled by using a specific IDRIVE setting. This allows the system to have a higher DRV8701 VM supply than the H-bridge supply. In addition to this FET VDS monitor, an overcurrent condition is also detected if the voltage at SP exceeds VSP OCP. 7.3.13.4 Pre-Driver Fault (PDF) The GHx and GLx pins are monitored such that if the voltage on the external FET gate does not increase above 1 V (when sourcing current) or decrease below 1 V (when sinking current) after tDRIVE, a pre-driver fault is detected. The device encounters this fault if GHx or GLx are shorted to GND, SHx, or VM. Additionally, the device encounters the pre-driver fault if the IDRIVE setting selected is not sufficient to turn on the external FET. As a result, all FETs in the H-bridge are disabled and the nFAULT pin is driven low. The driver is re-enabled after the retry period (tRETRY) has passed. The nFAULT pin is released after operation has resumed. 7.3.13.5 Thermal Shutdown (TSD) If the die temperature exceeds TTSD, all FETs in the H-bridge are disabled, the charge pump is shut down, AVDD is disabled, and the nFAULT pin is driven low. After the die temperature has fallen below TTSD – THYS, operation automatically resumes. The nFAULT pin is released after operation has resumed. Table 7. Fault Response Condition H-Bridge Charge Pump AVDD DVDD Recovery VM undervoltage (UVLO) Fault VM ≤ VUVLO Disabled Disabled Disabled Operating VM ≥ VUVLO VCP undervoltage (CPUV) VCP < VCPUV Disabled Operating Operating Operating VCP > VCPUV External FET overload (OCP) VDS ≥ 1.0 V or VSP – VSN > 1.0 V Disabled Operating Operating Operating tRETRY Pre-driver fault (PDF) Gate voltage unchanged after tDRIVE Disabled Operating Operating Operating tRETRY TJ ≥ 150°C Disabled Disabled Disabled Operating TJ ≤ 130°C Thermal shutdown (TSD) 24 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: DRV8701 DRV8701 www.ti.com SLVSCX5B – MARCH 2015 – REVISED JULY 2015 7.3.14 Reverse Supply Protection The following circuit may be implemented to protect the system from reverse supply conditions. This circuit requires the following additional components: • NMOS FET • npn BJT • Diode • 10-kΩ resistor • 43-kΩ resistor VM 43 k 10 k 0.1 µF 1 µF Bulk 10 µF min 0.1 µF CP1 CP2 VCP VM + GH1 SH1 GL1 BDC GH2 SH2 GL2 SP RSENSE SN Figure 32. Reverse Supply Protection External Circuitry Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: DRV8701 25 DRV8701 SLVSCX5B – MARCH 2015 – REVISED JULY 2015 www.ti.com 7.4 Device Functional Modes The DRV8701 is active unless the nSLEEP pin is brought low. In sleep mode, the charge pump is disabled, the H-bridge FETs are High-Z, and the AVDD and DVDD regulators are disabled. Note that tSLEEP must elapse after a falling edge on the nSLEEP pin before the device is in sleep mode. The DRV8701 is brought out of sleep mode if nSLEEP is brought high. Note that tWAKE must elapse before the outputs change state after wake-up. While nSLEEP is brought low, all external H-bridge FETs are disabled. The high-side gate pins GHx are pulled to the output node SHx by an internal resistor, and the low-side gate pins GLx are pulled to GND. When VM is not applied, and during the power-on time (tON), the outputs are disabled using weak pulldown resistors between the GHx and SHx pins and between GLx and GND. Table 8. Functional Modes Charge Pump GHx GLx AVDD and DVDD Unpowered Condition VM < VUVLO Disabled Weak pulldown to SHx Weak pulldown to GND Disabled Sleep mode VUVLO < VM nSLEEP low Disabled Strong pulldown to GND Strong pulldown to GND Disabled Operating VUVLO < VM nSLEEP high Enabled Depends on inputs Depends on inputs Operating 26 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: DRV8701 DRV8701 www.ti.com SLVSCX5B – MARCH 2015 – REVISED JULY 2015 7.4.1 Operating DRV8701 and H-Bridge on Separate Supplies The DRV8701 can operate with a different supply voltage (VM) than the system H-bridge supply (VBAT). Case 1 describes normal operation when VM and VBAT are roughly the same. Special considerations must be taken into account for Cases 2, 3, and 4. • Case 1: VM ≈ VBAT. Recommended operation • Case 2: VM > VBAT. IDRIVE must be shorted to AVDD to disable the high-side OCP. The IDRIVE current is fixed at 25-mA source and 50-mA sink. This case can allow the driver to better enhance the external FETs for VBAT < 11.5 V, or operate down to a lower supply voltage below 5.9 V. • Case 3: VM > VBAT (higher than Case 2). IDRIVE must be shorted to AVDD to disable the high-side OCP. This case can also allow the driver to better enhance the external FETs, or operate down to a lower supply voltage below 5.9 V. The IDRIVE current is fixed at 25-mA source and 50-mA sink. Excess gate drive current may be driven through the DRV8701 gate clamps causing additional power dissipation in the DRV8701. • Case 4: VM < VBAT. The high-side FETs may not be in saturation. There may be a significant voltage drop across the high-side FET when driving current. This causes high power dissipation in the external FET. When operating in Case 4, the external FET threshold voltage must be greater than 2 V. Otherwise the DRV8701 will report a pre-driver fault whenever the FET is out of saturation. Table 9. VM Operational Range based on VBAT VBAT Range Case 3 1 V ≤ VBAT < 5.9 V 5.9 V ≤ VBAT < 6.4 V VM ≥ 0.5 × VBAT + 5.75 V VM ≤ 45 V 6.4 V ≤ VBAT < 11.5 V 11.5 V ≤ VBAT < 14 V 14 V ≤ VBAT ≤ 45 V VM > VBAT VM ≤ 45 V Case 2 Case 1 Case 4 VM ≥ 5.9 V VM < 0.5 × VBAT + 5.75 V N/A N/A VM = VBAT VM ≥ 5.9 V VM < VBAT VM > 0.6 × VBAT + 2.5 V VM ≤ VBAT VM ≥ 5.9 V VM ≤ 0.6 × VBAT + 2.5 V VM > VBAT – 4 V VM ≤ VBAT VM ≥ 5.9 V VM ≤ VBAT – 4 V VM > VBAT VM < 0.5 × VBAT + 5.75 V N/A Figure 33. VM Operating Range Based on Motor Supply Voltage When nSLEEP is low, VM may be reduced down to 0 V with up to 45 V present at VBAT. However, nSLEEP should not be brought high until VM is supplied with a voltage aligning with one of the cases outlined above. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: DRV8701 27 DRV8701 SLVSCX5B – MARCH 2015 – REVISED JULY 2015 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The DRV8701 is used in brushed-DC, solenoid, or relay control. 8.2 Typical Applications 8.2.1 Brushed-DC Motor Control The following design procedure can be used to configure the DRV8701. 0.1 µF R1 VM 1 µF R2 VM + 0.1 µF 1 2 3 4 5 6 VM VCP CPH CPL GND VREF 7 24 AVDD GH2 DVDD SH2 8 1 µF 1 µF 10 k 10 k Bulk 23 9 22 nFAULT GL2 GND (PPAD) 10 SNSOUT 21 SP 11 50 m 20 SO BDC SN 12 19 SH1 GH1 EN PH GND 33 k GL1 nSLEEP IDRIVE 18 17 16 15 14 13 VM Figure 34. Typical Application Schematic 8.2.1.1 Design Requirements Table 10 gives design input parameters for system design. Table 10. Design Parameters Design Parameter Reference Nominal supply voltage Supply voltage range FET total gate charge (1) FET gate-to-drain charge (1) Target FET gate rise time Motor current chopping level (1) 28 Example Value VM 18 V VMMIN, VMMAX 12 to 24 V QG 14 nC (typically) QGD 2.3 nC (typically) RT 100 to 300 ns ICHOP 3A FET part number is CSD88537ND. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: DRV8701 DRV8701 www.ti.com SLVSCX5B – MARCH 2015 – REVISED JULY 2015 8.2.1.2 Detailed Design Procedure 8.2.1.2.1 External FET Selection The DRV8701 FET support is based on the charge pump capacity and output PWM frequency. For a quick calculation of FET driving capacity, use the following equations when drive and brake (slow decay) are the primary modes of operation: I QG VCP ¦PWM where • • fPWM is the maximum desired PWM frequency to be applied to the DRV8701 inputs or the current chopping frequency, whichever is larger. IVCP is the charge pump capacity, which depends on VM. (5) The internal current chopping frequency is at most: 1 ¦PWM | N+] tOFF tBLANK (6) Example: If a system at VM = 7 V (IVCP = 8 mA) uses a maximum PWM frequency of 40 kHz, then the DRV8701 will support QG < 200 nC FETs. If the application will require a forced fast decay (or alternating between drive and reverse drive), the maximum FET driving capacity is given by: IVCP QG u ¦PWM (7) 8.2.1.2.2 IDRIVE Configuration Select IDRIVE based on the gate charge of the FETs. Configure this pin so that the FET gates are charged completely during tDRIVE. If the designer chooses an IDRIVE that is too low for a given FET, then the FET may not turn on completely. TI suggests to adjust these values in-system with the required external FETs and motor to determine the best possible setting for any application. For FETs with a known gate-to-drain charge (QGD) and desired rise time (RT), select IDRIVE based on: Q IDRIVE ! GD RT (8) Example: If the gate-to-drain charge is 2.3 nC, and the desired rise time is around 100 to 300 ns, IDRIVE1 = 2.3 nC / 100 ns = 23 mA IDRIVE2 = 2.3 nC / 300 ns = 7.7 mA Select IDRIVE between 7.7 and 23 mA Select IDRIVE as 12.5-mA source (25-mA sink) Requires a 33-kΩ resistor from the IDRIVE pin to GND 8.2.1.2.3 Current Chopping Configuration The chopping current is set based on the sense resistor value and the analog voltage at VREF. Calculate the current using Equation 9. The amplifier gain AV is 20 V/V and VOFF is typically 50 mV. Example: If the desired chopping current is 3 A, Set RSENSE = 50 mΩ IC H O P 9 5 ( ) ± 9O F F A V u R SENSE (9) VREF would have to be 3.05 V. Create a resistor divider from AVDD (4.8 V) to set VREF ≈ 3 V Set R2 = 3.3 kΩ; set R1 = 2 kΩ. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: DRV8701 29 DRV8701 SLVSCX5B – MARCH 2015 – REVISED JULY 2015 www.ti.com 8.2.1.3 Application Curves Figure 35. SH1 Rise Time (12.5-mA Source, 25-mA Sink) Figure 36. SH1 Fall Time (12.5-mA Source, 25-mA Sink) Figure 37. Current Regulating at 3 A on Motor Startup Figure 38. Current Profile on Motor Startup With Regulation Figure 39. Current Profile on Motor Startup Without Regulation 30 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: DRV8701 DRV8701 www.ti.com SLVSCX5B – MARCH 2015 – REVISED JULY 2015 8.2.2 Alternate Application In this example, the DRV8701 is powered from a supply that is boosted above VBAT. This allows the system to work at lower VBAT voltages, but requires the user to disable OCP monitoring. VBAT Boost + 0.1 µF 10 µF 0.1 µF 1 µF R1 R2 0.01 µF 1 2 3 4 5 6 C1 VM VCP CPH CPL GND VREF 7 + 24 AVDD GH2 DVDD SH2 8 1 µF 1 µF 10 k 10 k 23 9 22 nFAULT GL2 GND (PPAD) 10 SNSOUT 21 SP 11 AVDD BDC SN 12 19 GL1 SH1 GH1 GND PH EN nSLEEP IDRIVE 68 k 50 m 20 SO 18 17 16 15 14 13 VBAT Figure 40. DRV8701 on Boosted Supply 8.2.2.1 Design Requirements Table 11 gives design input parameters for system design. Table 11. Design Parameters Design Parameter Reference Example Value VBAT 12 V nominal Minimum operation: 4.0 V DRV8701 supply voltage VM VM = 7 V when VBAT < 7 V VM = VBAT when VBAT ≥ 7 V FET total gate charge QG 42 nC FET gate-to-drain charge QGD 11 nC Motor current chopping level ICHOP 3A Battery voltage 8.2.3 Detailed Design Procedure 8.2.3.1 IDRIVE Configuration Because the VM supply to the DRV8701 is different from the external H-bridge supply VBAT, the designer must disable the overcurrent monitor to prevent false overcurrent detection. The designer must place a 68-kΩ resistor between the IDRIVE pin and AVDD. IDRIVE is fixed at 25-mA source and 50-mA sink in this mode. So, the rise time is 11 nC / 25 mA = 440 ns. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: DRV8701 31 DRV8701 SLVSCX5B – MARCH 2015 – REVISED JULY 2015 8.2.3.2 www.ti.com VM Boost Voltage To determine an effective voltage to boost VM, first determine the minimum VBAT at which the system must operate. Select VM such that the gate driver clamps do not turn on during normal operation. VM < V B A T + 1 1 .5 V (10) 2 Example: If VBAT minimum is 4.0 V, VM < 7.75 V So VM = 7 V is selected to allow for adequate margin. 9 Power Supply Recommendations The DRV8701 is designed to operate from an input voltage supply (VM) range between 5.9 and 45 V. A 0.1-µF ceramic capacitor rated for VM must be placed as close to the DRV8701 as possible. In addition, the designer must include a bulk capacitor with a valued of at least 10 µF on VM. Bypassing the external H-bridge FETs requires additional bulk capacitance. 9.1 Bulk Capacitance Sizing Having appropriate local bulk capacitance is an important factor in motor drive system design. It is generally beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: • The highest current required by the motor system • The power supply’s capacitance and ability to source current • The amount of parasitic inductance between the power supply and motor system • The acceptable voltage ripple • The type of motor used (brushed DC, brushless DC, stepper) • The motor braking method The inductance between the power supply and motor drive system will limit the rate current can change from the power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The datasheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Power Supply Parasitic Wire Inductance Motor Drive System VM + ± + Motor Driver GND Local Bulk Capacitor IC Bypass Capacitor Figure 41. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. 32 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: DRV8701 DRV8701 www.ti.com SLVSCX5B – MARCH 2015 – REVISED JULY 2015 10 Layout 10.1 Layout Guidelines Bypass the VM pin to GND using a low-ESR ceramic bypass capacitor with a recommended value of 0.1 µF rated for VM. Place this capacitor as close to the VM pin as possible with a thick trace or ground plane connection to the device GND pin. Bypass the VM pin to ground using a bulk capacitor rated for VM. This component may be an electrolytic. This capacitance must be at least 10 µF. The bulk capacitor should be placed to minimize the distance of the highcurrent path through the external FETs. The connecting metal trace widths should be as wide as possible, and numerous vias should be used when connecting PCB layers. These practices minimize inductance and allow the bulk capacitor to deliver high current. Place a low-ESR ceramic capacitor in between the CPL and CPH pins. The value for this component is 0.1 µF rated for VM. Place this component as close to the pins as possible. Place a low-ESR ceramic capacitor in between the VM and VCP pins. The value for this component is 1 µF rated for 16 V. Place this component as close to the pins as possible. Bypass AVDD and DVDD to ground with ceramic capacitors rated at 6.3 V. Place these bypassing capacitors as close to the pins as possible. If desired, align the external NMOS FETs as shown in Figure 42 to facilitate layout. Route the SH2 and SH1 nets to the motor. Use separate traces to connect the SP and SN pins to the RSENSE terminals. 10.2 Layout Example + GND 10 µF minimum 2 24 8 23 9 22 GND (PPAD) 10 G S D S D S 21 11 20 12 19 GH2 SH2 GL2 SP SN GL1 S D S D S D G D SH2 0.1 µF D D 1 VM VCP 4 3 CPH CPL 7 RSENSE 18 17 16 15 14 13 RIDRIVE 5 AVDD DVDD nFAULT SNSOUT SO IDRIVE 6 1 µF GND VREF 1 µF 1 µF GND 0.1 µF VM GND S D S D D D VM SH1 SH1 GH1 GND PH EN nSLEEP S G GND D G D S D S D S Figure 42. Layout Recommendation Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: DRV8701 33 DRV8701 SLVSCX5B – MARCH 2015 – REVISED JULY 2015 www.ti.com 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation • PowerPAD™ Thermally Enhanced Package, SLMA002 • PowerPAD™ Made Easy, SLMA004 • Current Recirculation and Decay Modes, SLVA321 11.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.3 Trademarks PowerPAD, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 34 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: DRV8701 PACKAGE OPTION ADDENDUM www.ti.com 30-Jun-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) DRV8701ERGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 8701E DRV8701ERGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 8701E DRV8701PRGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 8701P DRV8701PRGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 8701P (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 30-Jun-2015 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 30-Jun-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing DRV8701ERGER VQFN RGE 24 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 DRV8701ERGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 DRV8701PRGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 DRV8701PRGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 30-Jun-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRV8701ERGER VQFN RGE 24 3000 367.0 367.0 35.0 DRV8701ERGET VQFN RGE 24 250 210.0 185.0 35.0 DRV8701PRGER VQFN RGE 24 3000 367.0 367.0 35.0 DRV8701PRGET VQFN RGE 24 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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