MPS MP62180DH 3.3v/5v, single-channel 2a current-limited power distribution switch Datasheet

MP62180/MP62181
3.3V/5V, Single-Channel 2A
Current-Limited Power Distribution Switch
The Future of Analog IC Technology
DESCRIPTION
FEATURES
The MP62180/MP62181 Power Distribution
Switch features internal current limiting to
prevent damage to host devices due to faulty
load conditions. The MP62180/MP62181
operates from a 3.3V or 5V nominal input
voltage and includes an 85mΩ Power MOSFET
to handle up to 2A continuous load with a 2.8A
typical current limit. The MP62180/MP62181
has built-in protection for both over current and
increased thermal stress. For over-current
protection (OCP), the device will limit the
current by going into a constant current mode.
•
•
•
•
•
•
•
•
•
•
•
When continuous output overload condition
exceeds power dissipation of the package, the
thermal protection will shut the part off. The
device will recover once the device temperature
reduces to approx 120°C.
APPLICATIONS
2A Continuous Current
2.8A accurate Current Limit
2.7V to 5.5V Supply Range
90uA Quiescent Current
75mΩ MOSFET
Thermal-Shutdown Protection
Under-Voltage Lockout
8ms FLAG Deglitch Time
No FLAG Glitch During Power Up
Reverse Current Blocking
Active High & Active Low Options
•
•
•
•
•
•
•
The MP62180/MP62181 is available in QFN8E,
MSOP8E and SOIC8 packages.
Smartphone and PDA
Portable GPS Device
Notebook PC
Set-top-box
Telecom and Network Systems
PC Card Hot Swap
USB Power Distribution
“MPS” and “The Future of Analog IC Technology” are Registered Trademarks of
Monolithic Power Systems, Inc.
TYPICAL APPLICATION
3.5V/5V Input
1 GND
2, 3 IN
4
MP62180
EN*
OUT
6, 7, 8
To VBUS
USB Ports
FLAG 5
SINGLE-CHANNEL
* EN is active high for MP62181
MP62180_MP62181 Rev. 0.9
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1
MP62180/MP62181 –CURRENT-LIMITED POWER DISTRIBUTION SWITCH
ORDERING INFORMATION
Part Number Enable Switch
Maximum
Typical ShortContinuous Circuit Current
Load Current
@ TA=25C
MP62180DS
SOIC8
QFN8E
(2mm x 3mm)
MSOP8E
SOIC8
QFN8E
(2mm x 3mm)
MSOP8E
Active
Low
MP62180DD
MP62180DH
MP62181DS
Single
2A
2.8A
Active
High
MP62181DD
Top
Marking
Package
MP62181DH
Free Air
Temperature (TA)
62180DS
62180DD
62180DH
62181DS
–40°C to +85°C
62181DD
62181DH
* For Tape & Reel, add suffix –Z (e.g. MP62180DH–Z).
For RoHS Compliant Packaging, add suffix –LF (e.g. MP62180DH–L)
PACKAGE REFERENCE
TOP VIEW
TOP VIEW
TOP VIEW
GND
1
8
OUT
GND
1
8
OUT
IN
2
7
OUT
IN
2
7
OUT
GND
1
8
OUT
IN
3
6
OUT
IN
3
6
OUT
IN
2
7
OUT
EN*
4
5
FLAG
EN*
4
5
FLAG
IN
3
6
OUT
EN*
4
5
FLAG
EXPOSED PAD
ON BACKSIDE
CONNECT TO GND
MSOP8E
EXPOSED PAD
ON BACKSIDE
CONNECT TO GND
QFN8E (2mm x 3mm)
SOIC8
MP62180
*: EN is active high for MP62181
ABSOLUTE MAXIMUM RATINGS (1)
Thermal Resistance
(3)
IN .................................................-0.3V to +6.0V
EN, FLAG, OUT to GND ..............-0.3V to +6.0V
(2)
Continuous Power Dissipation (TA = +25°C)
MSOP8E .................................................... 2.3W
QFN8E (2mm x 3mm)................................ 2.3W
SOIC8 ........................................................ 1.4W
Junction Temperature ...............................150°C
Lead Temperature ....................................260°C
Storage Temperature............... –65°C to +150°C
Operating Temperature.............. –40°C to +85°C
MSOP8E................................. 55 ...... 12... °C/W
QFN8E (2mm x 3mm) ............ 55 ...... 12... °C/W
SOIC8..................................... 90 ...... 42... °C/W
θJA
θJC
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ(MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD(MAX)=(TJ(MAX)TA)/θJA. Exceeding the maximum allowable power dissipation
will cause excessive die temperature, and the regulator will go
into thermal shutdown. Internal thermal shutdown circuitry
protects the device from permanent damage.
3) Measured on JESD51-7, 4-layer PCB.
MP62180_MP62181 Rev. 0.9
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MP62180/MP62181 –CURRENT-LIMITED POWER DISTRIBUTION SWITCH
ELECTRICAL CHARACTERISTICS (4)
VIN=5V, TA=+25°C, unless otherwise noted.
Parameter
IN Voltage Range
Supply Current
Shutdown Current
Off Switch Leakage
Condition
Min
Under-voltage Lockout
Under-voltage Hysteresis
FET On Resistance
EN Input Logic High Voltage
EN Input Logic Low Voltage
FLAG Output Logic Low Voltage
FLAG Output High Leakage
Current
Thermal Shutdown
Thermal Shutdown Hysteresis
Device Active, IOUT=0
Device Disable, VOUT=float, VIN=5.5V
Device Disable, VIN=5.5V
Current Ramp (slew rate≤100A/s) on
Output
Rising Edge
IOUT=100mA (-40°C≤ TA
≤85°C)
V
µA
µA
µA
2.8
3.5
A
3.1
4
A
2.65
1.95
MSOP8E
QFN8E
(2mm x 3mm)
SOIC8
250
75
120
V
mV
mΩ
75
120
mΩ
85
130
0.8
0.4
mΩ
V
V
V
1
µA
0.5
0.5
3
°C
°C
ms
ms
ms
ms
ms
ISINK=5mA
VIN=VFLAG=5.5V
Turn Off Time, Toff (8)
CL=100µF, RL=5Ω
FLAG Deglitch Time
EN Input Leakage
Reverse Leakage Current
5.5
120
2
Turn On Time, Ton (7)
VOUT Falling Time, Tf (6)
Units
90
1
1
2.1
VIN=5.5V, CL=1uF, RL=5Ω
VIN=2.7V, CL=1uF, RL=5Ω
VIN=5.5V, CL=1uF, RL=5Ω
VIN=2.7V, CL=1uF, RL=5Ω
CL=100µF, RL=5Ω
VOUT Rising Time, Tr (5)
Max
2.7
Current Limit
Trip Current
Typ
140
20
0.9
1.7
4
-1
OUT=5.5V, IN=GND
8
0.2
10
ms
15
ms
µA
µA
NOTE:
4) Production test at +25°C. Specifications over the temperature range are guaranteed by design and characterization.
5) Measured from 10% to 90%.
6) Measured from 90% to 10%.
7) Measured from (50%) EN signal to (90%) output signal.
8) Measured from (50%) EN signal to (10%) output signal.
MP62180_MP62181 Rev. 0.9
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MP62180/MP62181 –CURRENT-LIMITED POWER DISTRIBUTION SWITCH
PIN FUNCTIONS
Pin #
SOIC8
Pin #
MSOP8E
Pin #
QFN8E
Name
Description
1
2, 3
1
2, 3
1
2, 3
GND
IN
Ground.
Input Voltage. Accepts 2.7V to 5.5V input.
4
4
4
———
5
5
5
FLAG
IN-to-OUT Over-current, active-low output flag. Open-Drain.
6, 7, 8
6, 7, 8
6, 7, 8
OUT
IN-to-OUT Power-Distribution Output (for all 3 output pins)
EN
Active Low: (MP62180), Active High: (MP62181)
TYPICAL PERFORMANCE CHARACTERISTICS
TA = +25ºC, unless otherwise noted.
OUTX
RL
tf
tr
CL
VO(OUTX)
90%
10%
90%
10%
TEST CIRCUIT
50%
50%
50%
VI(ENX)
50%
VI(ENX)
toff
ton
VO(OUTX)
90%
ton
VO(OUTX)
10%
toff
90%
10%
VOLTAGE WAVEFORMS
Figure 1—Test Circuit and Voltage Waveforms
MP62180_MP62181 Rev. 0.9
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MP62180/MP62181 –CURRENT-LIMITED POWER DISTRIBUTION SWITCH
TYPICAL PERFORMANCE CHARACTERISTICS
VIN =5V, VEN=0V for MP62180 or 5V for MP62181, CL=2.2µF, TA = +25ºC, unless otherwise noted.
Supply Current, Output Enabled
vs. Input Voltage
100
0.25
3.5
TURN OFF DELAY (ms)
3
2.5
2
1.5
1
2.5
3 3.5
4 4.5
5 5.5
95
0.2
90
85
0.15
80
0.1
75
70
0.05
65
0
2.5
6
3 3.5
INPUT VOLTAGE (V)
5 5.5
60
2.5
6
Static Drain-Source On-State
Resistance vs. Input Voltage
170
160
150
140
130
120
110
100
90
80
70
2.5
15 30 45 60 75 90
Current Limit
vs. Input Voltage
3.2
TRIP CURRENT (A)
CURRENT LIMIT (A)
3.1
2.7
3
3.5
4
4.5
5
5.5
6
300
Vin=2.7V
250
200
Vin=3.3V
150
Vin=5.5V
Vin=5V
100
Vin=4.5V
50
0
0
2.5
2.5
3
3.5 4 4.5 5 5.5
INPUT VOLTAGE (V)
6
0.4
0.8
1.2
1.6
2
OUTPUT CURRENT (A)
Current Limit Response Time
vs. Peak Current
3.4
30
3.2
25
20
3
15
2.8
10
2.6
2.6
6
350
Threshold Trip Current vs.
Input Voltage
2.8
5 5.5
Input to Output Voltage vs.
Load Current
INPUT VOLTAGE (V)
2.9
4 4.5
IO=2A
IO=0.1A
3
3 3.5
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Static Drain-Source On-State
Resistance Variation vs.
Ambient Temperature
30
25
20
15
10
5
0
-5
-10
-15
-20
-25
-30
-45 -30 -15 0
4 4.5
INPUT TO OUTPUT VOLTAGE (mV)
TURN ON DELAY (ms)
4
2.4
2.5
5
0
3
3.5 4 4.5 5 5.5
INPUT VOLTAGE (V)
6
2
5
8
11
14
PEAK CURRENT (A)
MP62180_MP62181 Rev. 0.9
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5
MP62180/MP62181 –CURRENT-LIMITED POWER DISTRIBUTION SWITCH
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN =5V, VEN=0V for MP62180 or 5V for MP62181, CL=2.2µF, TA = +25ºC, unless otherwise noted.
VOUT
2V/div
VOUT
2V/div
VOUT
2V/div
EN
5V/div
EN
5V/div
EN
5V/div
4s/div
Short Circuit Current,
Device Enabled into Short
VOUT
2V/div
IOUT
1A/div
EN
5V/div
EN
5V/div
Threshold Trip Current with
Ramped Load
on Enabled Device
VOUT
2V/div
IOUT
1A/div
1ms/div
Ramped Load
on Enabled Device
470uF
220uF
Flag
5V/div
100uF
IOUT
1A/div
EN
5V/div
IOUT
1A/div
Flag
5V/div
IOUT
2A/div
2ms/div
MP62180_MP62181 Rev. 0.9
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2ms/div
6
MP62180/MP62181 –CURRENT-LIMITED POWER DISTRIBUTION SWITCH
FUNCTION BLOCK DIAGRAM
+
UVLO
Vref
--
IN
Current
Sense
OUT
Charge
Pump
-Logic
AMP
+
FLAG
EN*
Deglitch
Thermal
Sense
GND
*: EN is active high for MP62181; EN is active low for MP62180
Figure2—Function Block Diagram
DETAILED DESCRIPTION
Over Current
When the load exceeds trip current (minimum
threshold current triggering constant-current
mode) or a short is present, MP62180/MP62181
switches into to a constant-current mode (current
limit value). MP62180/MP62181 will be shutdown
only if the overcurrent condition stays long
enough to trigger thermal protection.
Trigger overcurrent protection for different
overload conditions occurring in applications:
1) The output has been shorted or overloaded
before the device is enabled or input applied.
MP62180/MP62181 detects the short or
overload and immediately switches into a
constant-current mode.
2) A short or an overload occurs after the device
is enabled. After the current-limit circuit has
been tripped (reached the trip current
threshold), the device switches into constantcurrent mode. However, high current may
flow for a short period of time before the
current-limit circuit can react.
3) Output current has been gradually increased
beyond the recommended operating current.
The load current rises until the trip current
threshold is reached or until the thermal limit
of
the
device
is
exceeded.
The
MP62180/MP62181 is capable of delivering
current up to the trip current threshold without
damaging the device. Once the trip threshold
has been reached, the device switches into
its constant-current mode.
Flag Response
The FLAG pin is an open drain configuration.
This FAULT will report a fail mode after an 8ms
deglitch timeout. This is used to ensure that no
false fault signals are reported. This internal
deglitch circuit eliminates the need for extend
components. The FLAG pin is not deglitched
during an over temp. or a voltage lockout.
MP62180_MP62181 Rev. 0.9
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MP62180/MP62181 –CURRENT-LIMITED POWER DISTRIBUTION SWITCH
Thermal Protection
The purpose of thermal protection is to prevent
damage in the IC by allowing exceptive current to
flow and heating the junction. The die
temperature is internally monitored until the
thermal limit is reached. Once this temperature is
reached, the switch will turn off and allow the
chip to cool. The switch has a built-in hysteresis.
Under-voltage Lockout (UVLO)
This circuit is used to monitor the input voltage to
ensure that the MP62180/MP62181 is operating
correctly.
This UVLO circuit also ensures that is no
operation until the input voltage reaches the
minimum spec.
Enable
The logic pin disables the switch to reduce
overall supply current .Once the EN pin reaches
logic enable threshold, the MP62180/MP62181 is
enabled.
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MP62180/MP62181 –CURRENT-LIMITED POWER DISTRIBUTION SWITCH
APPLICATION INFORMATION
Power-Supply Considerations
Over 10µF capacitor between IN and GND is
recommended. This precaution reduces powersupply transients that may cause ringing on the
input and improves the immunity of the device to
short-circuit transients.
In order to achieve smaller output load transient
ripple, placing a high-value electrolytic capacitor
on the output pin(s) is recommended when the
load is heavy.
MP62180_MP62181 Rev. 0.9
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MP62180/MP62181 –CURRENT-LIMITED POWER DISTRIBUTION SWITCH
PACKAGE INFORMATION
MSOP8E (EXPOSED PAD)
0.087(2.20)
0.099(2.50)
0.114(2.90)
0.122(3.10)
5
8
0.114(2.90)
0.122(3.10)
PIN 1 ID
(NOTE 5)
0.187(4.75)
0.199(5.05)
0.062(1.58)
0.074(1.88)
Exposed Pad
0.010(0.25)
0.014(0.35)
4
1
0.0256(0.65)BSC
BOTTOM VIEW
TOP VIEW
GAUGE PLANE
0.010(0.25)
0.030(0.75)
0.037(0.95)
0.043(1.10)MAX
SEATING PLANE
0.002(0.05)
0.006(0.15)
FRONT VIEW
NOTE:
0.181(4.60)
0.040(1.00)
0.016(0.40)
0.004(0.10)
0.008(0.20)
SIDE VIEW
0.100(2.54)
0.075(1.90)
0o-6o
0.016(0.40)
0.026(0.65)
1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN BRACKET IS
IN MILLIMETERS.
2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH,
PROTRUSION OR GATE BURR.
3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR
PROTRUSION.
4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING)
SHALL BE 0.004" INCHES MAX.
5) PIN 1 IDENTIFICATION HAS HALF OR FULL CIRCLE OPTION.
6) DRAWING MEETS JEDEC MO-187, VARIATION AA-T.
7) DRAWING IS NOT TO SCALE.
0.0256(0.65)BSC
RECOMMENDED LAND PATTERN
MP62180_MP62181 Rev. 0.9
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MP62180/MP62181 –CURRENT-LIMITED POWER DISTRIBUTION SWITCH
QFN8E (2mm x 3mm)
2.90
3.10
PIN 1 ID
MARKING
0.30
0.50
0.18
0.30
1.90
2.10
PIN 1 ID
INDEX AREA
1.65
1.85
8
PIN 1 ID
SEE DETAIL A
1
1.50
1.70
0.50
BSC
4
5
TOP VIEW
BOTTOM VIEW
PIN 1 ID OPTION A
0.30x45” TYP.
0.80
1.00
PIN 1 ID OPTION B
R0.20 TYP.
0.20 REF
0.00
0.05
SIDE VIEW
DETAIL A
2.90
0.70
NOTE:
1.70
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH.
3) LEAD COPLANARITY SHALL BE 0.10 MILLIMETER MAX.
4) DRAWING CONFORMS TO JEDEC MO-229, VARIATION VCED-2.
5) DRAWING IS NOT TO SCALE.
0.25
1.60
0.50
RECOMMENDED LAND PATTERN
MP62180_MP62181 Rev. 0.9
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MP62180/MP62181 –CURRENT-LIMITED POWER DISTRIBUTION SWITCH
SOIC8
0.189(4.80)
0.197(5.00)
8
0.050(1.27)
0.024(0.61)
5
0.063(1.60)
0.150(3.80)
0.157(4.00)
PIN 1 ID
1
0.228(5.80)
0.244(6.20)
0.213(5.40)
4
TOP VIEW
RECOMMENDED LAND PATTERN
0.053(1.35)
0.069(1.75)
SEATING PLANE
0.004(0.10)
0.010(0.25)
0.013(0.33)
0.020(0.51)
0.0075(0.19)
0.0098(0.25)
SEE DETAIL "A"
0.050(1.27)
BSC
SIDE VIEW
FRONT VIEW
0.010(0.25)
x 45o
0.020(0.50)
GAUGE PLANE
0.010(0.25) BSC
0o-8o
0.016(0.41)
0.050(1.27)
DETAIL "A"
NOTE:
1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN
BRACKET IS IN MILLIMETERS.
2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS.
3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH
OR PROTRUSIONS.
4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING)
SHALL BE 0.004" INCHES MAX.
5) DRAWING CONFORMS TO JEDEC MS-012, VARIATION AA.
6) DRAWING IS NOT TO SCALE.
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
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