LM4906, LM4906LDBD, LM4906MMBD www.ti.com SNAS191E – APRIL 2003 – REVISED MAY 2013 LM4906 1W, Bypass-Capacitor-less Audio Amplifier with Internal Selectable Gain Check for Samples: LM4906, LM4906LDBD, LM4906MMBD FEATURES DESCRIPTION • • The LM4906 is an audio power amplifier primarily designed for demanding applications in mobile phones and other portable communication device applications. It is capable of delivering 1W of continuous average power to an 8Ω BTL load with less than 1% distortion (THD+N) from a +5V power supply. 1 2 • • • • • • Selectable Gain of 6dB (2V/V) or 12dB (4V/V) No Output or PSRR Bypass Capacitors Required Improved “Click and Pop” Suppression Circuitry Very Fast Turn on Time: 5ms (Typ) Minimum External Components 2.6 - 5.5V Operation BTL Output Can Drive Capacitive Loads Ultra Low Current Shutdown Mode (SD Low) APPLICATIONS • • • Portable Computers Desktop Computers Multimedia Monitors KEY SPECIFICATIONS • • • • Improved PSRR at 217Hz for +3V: 71 dB Power Output at +5V, THD+N = 1%, 8Ω: 1.0 W (Typ) Power Output at +3V, THD+N = 1%, 8Ω: 390 mW (Typ) Total Shutdown Power Supply Current: 0.1µA (Typ) The LM4906 is the first Texas Instruments Boomer Power Amplifier that does not require an external PSRR bypass capacitor. The LM4906 also has an internal selectable gain of either 6dB or 12dB. In addition, no output coupling capacitors or bootstrap capacitors are required which makes the LM4906 ideally suited for cell phone and other low voltage portable applications. The LM4906 contains advanced pop and click circuitry that eliminates noise, which would otherwise occur during turn-on and turn-off transitions. Boomer audio power amplifiers were designed specifically to provide high quality output power with a minimal amount of external components. The LM4906 features a low -power consumption shutdown mode (the part is enabled by pulling the SD pin high). Additionally, the LM4906 features an internal thermal shutdown protection mechanism. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2013, Texas Instruments Incorporated LM4906, LM4906LDBD, LM4906MMBD SNAS191E – APRIL 2003 – REVISED MAY 2013 www.ti.com Typical Application Figure 1. Typical Audio Amplifier Application Circuit Connection Diagram Figure 2. VSSOP Package (Top View) See Package Number DGK Figure 3. WSON Package (Top View) See Package Number NGZ LM4906GR Pin Designation Pin (Bump) Number 2 Pin Function A1 Shutdown A2 No Connect A3 VO2 A4 No Connect B1 GND B2 No Connect B3 GND B4 GND C1 Gain Select C2 IN C3 No Connect Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LM4906 LM4906LDBD LM4906MMBD LM4906, LM4906LDBD, LM4906MMBD www.ti.com SNAS191E – APRIL 2003 – REVISED MAY 2013 LM4906GR Pin Designation (continued) C4 VDD D1 No Connect D2 No Connect D3 VO1 D4 VDD Absolute Maximum Ratings (1) (2) Supply Voltage (3) 6.0V −65°C to +150°C Storage Temperature −0.3V to VDD +0.3V Input Voltage Power Dissipation (4) (5) ESD Susceptibility Internally Limited (6) 2000V ESD Susceptibility (7) 200V Junction Temperature 150°C Thermal Resistance (1) (2) (3) (4) (5) (6) (7) θJC (VSSOP) 56°C/W θJA (VSSOP) 190°C/W θJC (WSON) 12°C/W θJA (WSON) 63°C/W Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not ensured for parameters where no limit is given; however, the typical value is a good indication of device performance. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. If the product is in Shutdown mode and VDD exceeds 6V (to a max of 8V VDD), then most of the excess current will flow through the ESD protection circuits. If the source impedance limits the current to a max of 10mA, then the device will be protected. If the device is enabled when VDD is greater than 5.5V and less than 6.5V, no damage will occur, although operation life will be reduced. Operation above 6.5V with no current limit will result in permanent damage. The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature TA. The maximum allowable power dissipation is PDMAX = (TJMAX–TA)/θJA or the number given in Absolute Maximum Ratings, whichever is lower. For the LM4906, see Figure 10 for additional information. Maximum power dissipation in the device (PDMAX) occurs at an output power level significantly below full output power. PDMAX can be calculated using Equation 1 shown in the Application Information section. It may also be obtained from the power dissipation graphs. Human body model, 100pF discharged through a 1.5kΩ resistor. Machine Model, 220pF–240pF discharged through all pins. Operating Ratings TMIN ≤ TA ≤ TMAX Temperature Range −40°C ≤ TA ≤ 85°C 2.6V ≤ VDD ≤ 5.5V Supply Voltage Copyright © 2003–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4906 LM4906LDBD LM4906MMBD 3 LM4906, LM4906LDBD, LM4906MMBD SNAS191E – APRIL 2003 – REVISED MAY 2013 www.ti.com Electrical Characteristics VDD = 5V (1) (2) The following specifications apply for the circuit shown in Figure 1, unless otherwise specified. Limits apply for TA = 25°C. Symbol Parameter Conditions IDD Quiescent Power Supply Current ISD Shutdown Current VOS Output Offset Voltage LM4906 Typical (3) Limit (4) (5) Units (Limits) VIN = 0V, Io = 0A, No Load 3.5 7 mA (max) VIN = 0V, Io = 0A, 8Ω Load 4 8 mA (max) 0.1 2 µA (max) VSD = GND 7 35 mV (max) THD+N = 1% (max); f = 1 kHz RL = 8Ω 1.0 0.9 W (min) 5 ms 0.2 % 67 (f = 217Hz) 70 (f = 1kHz) dB Po Output Power TWU Wake-up time THD+N Total Harmonic Distortion+Noise Po = 0.4 Wrms; f = 1kHz PSRR Power Supply Rejection Ratio Vripple = 200mV sine p-p Input terminated with 10Ω Gain at 6dB VSDIH Shutdown Voltage Input High SD Pin High = Part On 1.5 V (min) VSDIL Shutdown Voltage Input Low SD Pin Low = Part Off 1.3 V (max) (1) (2) (3) (4) (5) 4 All voltages are measured with respect to the ground pin, unless otherwise specified. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not ensured for parameters where no limit is given; however, the typical value is a good indication of device performance. Typicals are measured at 25°C and represent the parametric norm. Datasheet min/max specification limits are specified by design, test, or statistical analysis. Limits are specified to AOQL (Average Outgoing Quality Level). Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LM4906 LM4906LDBD LM4906MMBD LM4906, LM4906LDBD, LM4906MMBD www.ti.com SNAS191E – APRIL 2003 – REVISED MAY 2013 Electrical Characteristics VDD = 3V (1) (2) The following specifications apply for the circuit shown in Figure 1, unless otherwise specified. Limits apply for TA = 25°C. Symbol Parameter LM4906 Conditions IDD Quiescent Power Supply Current ISD Shutdown Current VOS Output Offset Voltage Typical (3) Limit (4) (5) Units (Limits) VIN = 0V, Io = 0A, No Load 2.6 6 mA (max) VIN = 0V, Io = 0A, 8Ω Load 3 7 mA (max) 0.1 2 µA (max) 7 35 mV (max) VSD = GND THD+N = 1% (max); f = 1 kHz RL = 8Ω 390 mW Po Output Power TWU Wake-up time 4 ms THD+N Total Harmonic Distortion+Noise Po = 0.15 Wrms; f = 1kHz 0.1 % PSRR Power Supply Rejection Ratio Vripple = 200mV sine p-p Input terminated with 10Ω Gain at 6dB 71 (f = 217Hz) 73 (f = 1kHz) dB VSDIH Shutdown Voltage Input High SD Pin High = Part On 1.1 V (min) VSDIL Shutdown Voltage Input Low SD Pin Low = Part Off 0.9 V (max) (1) (2) (3) (4) (5) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not ensured for parameters where no limit is given; however, the typical value is a good indication of device performance. All voltages are measured with respect to the ground pin, unless otherwise specified. Typicals are measured at 25°C and represent the parametric norm. Limits are specified to AOQL (Average Outgoing Quality Level). Datasheet min/max specification limits are specified by design, test, or statistical analysis. External Components Description Components Functional Description 1. C2 Input coupling capacitor which blocks the DC voltage at the amplifiers input terminals. Also creates a highpass filter with Ri at fc = 1 / (2πRiCi). Refer to the section, AUDIO POWER AMPLIFIER DESIGN, for an explanation of how to determine the value of Ci. 2. C1 Supply bypass capacitor which provides power supply filtering. Refer to the Power Supply Bypassing section for information concerning proper placement and selection of the supply bypass capacitor. Copyright © 2003–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4906 LM4906LDBD LM4906MMBD 5 LM4906, LM4906LDBD, LM4906MMBD SNAS191E – APRIL 2003 – REVISED MAY 2013 www.ti.com Typical Performance Characteristics 6 THD+N vs Frequency VDD = 5V, RL = 8Ω, f = 1kHz, PWR = 500mW THD+N vs Frequency VDD = 3V, RL = 8Ω, f = 1kHz, PWR = 250mW Figure 4. Figure 5. THD+N vs Power Out VDD = 5V, RL = 8Ω, f = 1kHz THD+N vs Power Out VDD = 3V, RL = 8Ω, f = 1kHz Figure 6. Figure 7. Power Supply Rejection Ratio vs Frequency VDD = 5V, RL = 8Ω Power Supply Rejection Ratio vs Frequency VDD = 3V, RL = 8Ω Figure 8. Figure 9. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LM4906 LM4906LDBD LM4906MMBD LM4906, LM4906LDBD, LM4906MMBD www.ti.com SNAS191E – APRIL 2003 – REVISED MAY 2013 Typical Performance Characteristics (continued) Noise Floor VDD = 5V, RL = 8Ω 80kHz Bandwith, Input to GND Power Derating Curve Figure 10. Figure 11. Power Dissipation vs Output Power, VDD = 3V, RL = 8Ω Power Dissipation vs Output Power, VDD = 5V, RL = 8Ω 0.7 0.25 POWER DISSIPATION (mW) POWER DISSIPATION (mW) 0.6 0.20 0.15 0.10 0.5 0.4 0.3 0.2 0.05 0.1 0.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 OUTPUT POWER (W) OUTPUT POWER (W) Figure 12. Figure 13. Shutdown Hysteresis Voltage VDD = 5V, SD Mode = VDD (High) Shutdown Hysteresis Voltage VDD = 5V, SD Mode = VDD (Low) 4.5 4.5 4.0 4.0 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 0.00 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 3.5 3.0 2.5 2.0 1.5 1.0 3.0 2.5 2.0 1.5 1.0 0.5 0.5 0.0 0.0 3.5 1.0 2.0 3.0 SHUTDOWN VOLTAGE (V) 4.0 0.0 0.0 1.0 Figure 14. Copyright © 2003–2013, Texas Instruments Incorporated 2.0 3.0 4.0 SHUTDOWN VOLTAGE (V) Figure 15. Submit Documentation Feedback Product Folder Links: LM4906 LM4906LDBD LM4906MMBD 7 LM4906, LM4906LDBD, LM4906MMBD SNAS191E – APRIL 2003 – REVISED MAY 2013 www.ti.com Typical Performance Characteristics (continued) Shutdown Hysteresis Voltage VDD = 3V, SD Mode = VDD (High) 3.5 Shutdown Hysteresis Voltage VDD = 3V, SD Mode = GND (Low) SUPPLY CURRENT (mA) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0.0 1.0 2.0 3.0 4.0 SHUTDOWN VOLTAGE (V) Figure 16. Figure 17. Output Power vs Supply Voltage, RL = 8Ω Output Power vs Supply Voltage, RL = 32Ω 600.0 2000 500.0 1600 OUTPUT POWER (mW) OUTPUT POWER (mW) 1800 1400 THD+N = 10% 1200 1000 800 600 400 400.0 THD+N = 10% 300.0 200.0 THD+N = 1% 100.0 THD+N = 1% 200 0.0 1.5 0 2 3 4 5 6 2.5 3.5 4.5 5.5 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) Figure 18. Figure 19. Output Power vs Supply Voltage, RL = 16Ω Frequency Response vs Input Capacitor Size 1200 7 0.39PF 6 800 OUTPUT LEVEL (dB) OUTPUT POWER (mW) 1000 THD+N = 10% 600 400 THD+N = 1% 200 5 4 3 1PF 2 1 0 1.5 3.0 4.5 SUPPLY VOLTAGE (V) 6.0 0 20 200 2k 20k FREQUENCY (Hz) Figure 20. 8 Submit Documentation Feedback Figure 21. Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LM4906 LM4906LDBD LM4906MMBD LM4906, LM4906LDBD, LM4906MMBD www.ti.com SNAS191E – APRIL 2003 – REVISED MAY 2013 Typical Performance Characteristics (continued) PSRR Distribution VDD = 5V, f = 1kHz, RL = 8Ω -80 -70 PSRR Distribution VDD = 5V, f = 217Hz, RL = 8Ω -60 -68 -75 (dBr) Figure 22. Figure 23. PSRR Distribution VDD = 3V, f = 1kHz, RL = 8Ω PSRR Distribution VDD = 3V, f = 217Hz, RL = 8Ω -85 -74 -62 -72 -80 (dBr) -63 (dBr) Figure 24. Copyright © 2003–2013, Texas Instruments Incorporated -61 (dBr) Figure 25. Submit Documentation Feedback Product Folder Links: LM4906 LM4906LDBD LM4906MMBD 9 LM4906, LM4906LDBD, LM4906MMBD SNAS191E – APRIL 2003 – REVISED MAY 2013 www.ti.com APPLICATION INFORMATION BRIDGE CONFIGURATION EXPLANATION As shown in Figure 26, the LM4906 has two internal operational amplifiers. The first amplifier's gain is either 6dB or 12dB depending on the gain select input (Low = 6dB, High = 12dB). The second amplifier's gain is fixed by the two internal 20kΩ resistors. Figure 26 shows that the output of amplifier one serves as the input to amplifier two which results in both amplifiers producing signals identical in magnitude, but out of phase by 180°. Consequently, the differential gain for the IC is AVD = 2 * (20k / 20k) or 2 * (40k / 20k) (1) By driving the load differentially through outputs Vo1 and Vo2, an amplifier configuration commonly referred to as “bridged mode” is established. Bridged mode operation is different from the classical single-ended amplifier configuration where one side of the load is connected to ground. A bridge amplifier design has a few distinct advantages over the single-ended configuration, as it provides differential drive to the load, thus doubling output swing for a specified supply voltage. Four times the output power is possible as compared to a single-ended amplifier under the same conditions. This increase in attainable output power assumes that the amplifier is not current limited or clipped. In order to choose an amplifier's closedloop gain without causing excessive clipping, please refer to the Audio Power Amplifier Design section. A bridge configuration, such as the one used in LM4906, also creates a second advantage over single-ended amplifiers. Since the differential outputs, Vo1 and Vo2, are biased at half-supply, no net DC voltage exists across the load. This eliminates the need for an output coupling capacitor which is required in a single supply, singleended amplifier configuration. Without an output coupling capacitor, the half-supply bias across the load would result in both increased internal IC power dissipation and also possible loudspeaker damage. POWER DISSIPATION Power dissipation is a major concern when designing a successful amplifier, whether the amplifier is bridged or single-ended. A direct consequence of the increased power delivered to the load by a bridge amplifier is an increase in internal power dissipation. Since the LM4906 has two operational amplifiers in one package, the maximum internal power dissipation is 4 times that of a single-ended amplifier. The maximum power dissipation for a given application can be derived from the power dissipation graphs or from Equation 2. PDMAX = 4 * (VDD)2 / (2π2RL) (2) It is critical that the maximum junction temperature TJMAX of 150°C is not exceeded. TJMAX can be determined from the power derating curves by using PDMAX and the PC board foil area. By adding copper foil, the thermal resistance of the application can be reduced from the free air value of θJA, resulting in higher PDMAX values without thermal shutdown protection circuitry being activated. Additional copper foil can be added to any of the leads connected to the LM4906. It is especially effective when connected to VDD, GND, and the output pins. Refer to the Application Information on the LM4906 reference design board for an example of good heat sinking. If TJMAX still exceeds 150°C, then additional changes must be made. These changes can include reduced supply voltage, higher load impedance, or reduced ambient temperature. Internal power dissipation is a function of output power. Refer to the Typical Performance Characteristics curves for power dissipation information for different output powers and output loading. POWER SUPPLY BYPASSING As with any amplifier, proper supply bypassing is critical for low noise performance and high power supply rejection. The capacitor location on the power supply pin should be as close to the device as possible. Typical applications employ a 5V regulator with 10µF tantalum or electrolytic capacitor and a ceramic bypass capacitor which aid in supply stability. This does not eliminate the need for bypassing the supply nodes of the LM4906. 10 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LM4906 LM4906LDBD LM4906MMBD LM4906, LM4906LDBD, LM4906MMBD www.ti.com SNAS191E – APRIL 2003 – REVISED MAY 2013 TURNING ON THE LM4906 The power supply must first be applied before the application of an input signal to the device and the ramp time to VDD must be less than 4ms, otherwise the wake-up time of the device will be affected. After applying VDD, the LM4906 will turn-on after an initial minimum threshold input signal of 7mVRMS, resulting in a generated output differential signal. An input signal of less than 7mVRMS will result in a negligible output voltage. Once the device is turned on, the input signal can go below the 7mVRMS without shutting the device off. If, however, SHUTDOWN or VDD is cycled, the minimum threshold requirement for the input signal must first be met again, with VDD ramping first. SHUTDOWN FUNCTION In order to reduce power consumption while not in use, the LM4906 contains shutdown circuitry that is used to turn off the amplifier's bias circuitry. The device is placed into shutdown mode by toggling the Shutdown pin Low/ground. The trigger point for shutdown low is shown as a typical value in the Supply Current vs Shutdown Voltage graphs in the Typical Performance Characteristics section. It is best to switch between ground and supply for maximum performance. While the device may be disabled with shutdown voltages in between ground and supply, the idle current may be greater than the typical value of 0.1µA. In either case, the shutdown pin should be tied to a definite voltage to avoid unwanted state changes. In many applications, a microcontroller or microprocessor output is used to control the shutdown circuitry, which provides a quick, smooth transition to shutdown. Another solution is to use a single-throw switch in conjunction with an external pull-up resistor (or pull-down, depending on shutdown high or low application). This scheme ensures that the shutdown pin will not float, thus preventing unwanted state changes. SELECTION OF INPUT CAPACITOR SIZE Large input capacitors are both expensive and space hungry for portable designs. Clearly, a certain sized capacitor is needed to couple in low frequencies without severe attenuation. But in many cases the speakers used in portable systems, whether internal or external, have little ability to reproduce signals below 100Hz to 150Hz. Thus, using a large input capacitor may not increase actual system performance. In addition to system cost and size, click and pop performance is effected by the size of the input coupling capacitor, Ci. A larger input coupling capacitor requires more charge to reach its quiescent DC voltage (nominally 1/2 VDD). This charge comes from the output via the feedback and is apt to create pops upon device enable. Thus, by minimizing the capacitor size based on necessary low frequency response, turn-on pops can be minimized. AUDIO POWER AMPLIFIER DESIGN A 1W/8Ω Audio Amplifier Power Output 1 Wrms Load Impedance Given: 8Ω Input Level 1 Vrms Input Impedance 20 kΩ Bandwidth 100 Hz–20 kHz ± 0.25 dB A designer must first determine the minimum supply rail to obtain the specified output power. By extrapolating from the Output Power vs Supply Voltage graphs in the Typical Performance Characteristics section, the supply rail can be easily found. Extra supply voltage creates headroom that allows the LM4906 to reproduce peaks in excess of 1W without producing audible distortion. At this time, the designer must make sure that the power supply choice along with the output impedance does not violate the conditions explained in the Power Dissipation section. The gain of the LM4906 is internally set at either 6dB or 12dB. Copyright © 2003–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4906 LM4906LDBD LM4906MMBD 11 LM4906, LM4906LDBD, LM4906MMBD SNAS191E – APRIL 2003 – REVISED MAY 2013 www.ti.com The final design step is to address the bandwidth requirements which must be stated as a pair of −3dB frequency points. Five times away from a −3dB point is 0.17dB down from passband response which is better than the required ±0.25dB specified. fL = 100Hz / 5 = 20Hz fH = 20kHz * 5 = 100kHz As stated in the External Components Description section, Rin (20k) in conjunction with C2 create a highpass filter. C2 ≥ 1 / (2π*20kΩ*20Hz) = 0.397µF; use 0.39µF Figure 26. REFERENCE DESIGN BOARD SCHEMATIC 12 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LM4906 LM4906LDBD LM4906MMBD LM4906, LM4906LDBD, LM4906MMBD www.ti.com SNAS191E – APRIL 2003 – REVISED MAY 2013 LM4906 VSSOP DEMO BOARD ARTWORK Figure 27. Top Layer Figure 28. Bottom Layer Copyright © 2003–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4906 LM4906LDBD LM4906MMBD 13 LM4906, LM4906LDBD, LM4906MMBD SNAS191E – APRIL 2003 – REVISED MAY 2013 www.ti.com LM4906 LD DEMO BOARD ARTWORK Figure 29. Top Layer Figure 30. Bottom Layer 14 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LM4906 LM4906LDBD LM4906MMBD LM4906, LM4906LDBD, LM4906MMBD www.ti.com SNAS191E – APRIL 2003 – REVISED MAY 2013 Table 1. Mono LM4906 Reference Design Boards Bill of Material Part Description Quantity Reference Designator LM4906 Audio Amplifier 1 U1 Tantalum Capcitor, 1µF 1 C1 Ceramic Capacitor, 0.39µF 1 C2 Jumper Header Vertical Mount 2X1 0.100“ spacing 5 J1, J2, Input, Output, VDD PCB LAYOUT GUIDELINES This section provides practical guidelines for mixed signal PCB layout that involves various digital/analog power and ground traces. Designers should note that these are only "rule-of-thumb" recommendations and the actual results will depend heavily on the final layout. GENERAL MIXED SIGNAL LAYOUT RECOMMENDATION Power and Ground Circuits For 2 layer mixed signal design, it is important to isolate the digital power and ground trace paths from the analog power and ground trace paths. Star trace routing techniques (bringing individual traces back to a central point rather than daisy chaining traces together in a serial manner) can have a major impact on low level signal performance. Star trace routing refers to using individual traces to feed power and ground to each circuit or even device. This technique will require a greater amount of design time but will not increase the final price of the board. The only extra parts required will be some jumpers. Single-Point Power / Ground Connections The analog power traces should be connected to the digital traces through a single point (link). A "Pi-filter" can be helpful in minimizing High Frequency noise coupling between the analog and digital sections. It is further recommended to put digital and analog power traces over the corresponding digital and analog ground traces to minimize noise coupling. Placement of Digital and Analog Components All digital components and high-speed digital signal traces should be located as far away as possible from analog components and circuit traces. Avoiding Typical Design / Layout Problems Avoid ground loops or running digital and analog traces parallel to each other (side-by-side) on the same PCB layer. When traces must cross over each other do it at 90 degrees. Running digital and analog traces at 90 degrees to each other from the top to the bottom side as much as possible will minimize capacitive noise coupling and cross talk. Copyright © 2003–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM4906 LM4906LDBD LM4906MMBD 15 LM4906, LM4906LDBD, LM4906MMBD SNAS191E – APRIL 2003 – REVISED MAY 2013 www.ti.com REVISION HISTORY Changes from Revision D (May 2013) to Revision E • 16 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 15 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LM4906 LM4906LDBD LM4906MMBD PACKAGE OPTION ADDENDUM www.ti.com 2-May-2013 PACKAGING INFORMATION Orderable Device Status (1) LM4906MM/NOPB ACTIVE Package Type Package Pins Package Drawing Qty VSSOP DGK 8 1000 Eco Plan Lead/Ball Finish (2) Green (RoHS & no Sb/Br) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) CU SN Level-1-260C-UNLIM (4) -40 to 85 GA8 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 8-May-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device LM4906MM/NOPB Package Package Pins Type Drawing VSSOP DGK 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 178.0 12.4 Pack Materials-Page 1 5.3 B0 (mm) K0 (mm) P1 (mm) 3.4 1.4 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 8-May-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM4906MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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