Not Recommended For New Designs LF411JAN www.ti.com SNOSAQ4A – OCTOBER 2005 – REVISED MARCH 2013 LF411JAN Low Offset, Low Drift JFET Input Operational Amplifier Check for Samples: LF411JAN FEATURES DESCRIPTION • • • • • • • • • This device is a low cost, high speed, JFET input operational amplifier with very low input offset voltage and ensured input offset voltage drift. It requires low supply current yet maintains a large gain bandwidth product and fast slew rate. In addition, well matched high voltage JFET input devices provide very low input bias and offset currents. The LF411 is pin compatible with the standard LM741 allowing designers to immediately upgrade the overall performance of existing designs. 1 23 • • Internally Trimmed Offset Voltage: 0.5 mV(Typ) Input Offset Voltage Drift: 30 μV/°C Low Input Bias Current: 50 pA Low Input Noise Current: 0.01 pA/√Hz Wide Gain Bandwidth: 3 MHz Typ. High Slew Rate: 7V/μs (Min.) Low Supply Current: 1.8 mA High Input Impedance: 1012Ω Low Total Harmonic Distortion: AV = 10, RL = 10KΩ, VO = 20VP-P, BW = 20Hz - 20kHz <0.02% Low 1/f Noise Corner: 50 Hz Fast Settling Time to 0.01%: 1.5 μs Connection Diagram This amplifier may be used in applications such as high speed integrators, fast D/A converters, sample and hold circuits and many other circuits requiring low input offset voltage and drift, low input bias current, high input impedance, high slew rate and wide bandwidth. Typical Connection Figure 1. 8LD Ceramic Dual-in Line Package See Package Number NAB0008A (Top View) 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. BI-FET II is a trademark of dcl_owner. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2013, Texas Instruments Incorporated LF411JAN Not Recommended For New Designs SNOSAQ4A – OCTOBER 2005 – REVISED MARCH 2013 www.ti.com Simplified Schematic Detailed Schematic These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LF411JAN Not Recommended For New Designs www.ti.com LF411JAN SNOSAQ4A – OCTOBER 2005 – REVISED MARCH 2013 Absolute Maximum Ratings (1) Supply Voltage ±18V Differential Input Voltage ±30V Input Voltage Range (2) ±15V Output Short Circuit Duration Continuous Power Dissipation (3) (4) 400mW TJmax 175°C θJA Thermal Resistance Still Air 162°C/W 400LF/Min Air Flow 65°C/W θJC 20°C/W Operating Temperature Range −55°C ≤ TA ≤ 125°C Storage Temperature Range −65°C ≤ TA ≤ 150°C Lead Temperature (Soldering, 10 seconds) 300°C Package Weight (Typical) TBD ESD Tolerance (5) (1) (2) (3) (4) (5) 750V Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The specified specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage. The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), θJA (package junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax = (TJmax - TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. Max. Power Dissipation is defined by the package characteristics. Operating the part near the Max. Power Dissipation may cause the part to operate outside specified limits. Human body model, 100pF discharged through 1.5KΩ. Quality Conformance Inspection Table 1. Mil-Std-883, Method 5005 - Group A Subgroup Description Temp °C 1 Static tests at 25 2 Static tests at 125 3 Static tests at -55 4 Dynamic tests at 25 5 Dynamic tests at 125 6 Dynamic tests at -55 7 Functional tests at 25 8A Functional tests at 125 8B Functional tests at -55 9 Switching tests at 25 10 Switching tests at 125 11 Switching tests at -55 12 Settling time at 25 13 Settling time at 125 14 Settling time at -55 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LF411JAN 3 Not Recommended For New Designs LF411JAN SNOSAQ4A – OCTOBER 2005 – REVISED MARCH 2013 www.ti.com Electrical Characteristics DC Parameters The following conditions apply to all the following parameters, unless otherwise specified. DC: VCC = ±15V, VCM = 0V Symbol Parameter VIO Conditions Notes Max Unit +VCC = 26V, -VCC = -4V, VCM = -11V -5.0 5.0 mV 1 -7.0 7.0 mV 2, 3 +VCC = 4V, -VCC = -26V, VCM = 11V -5.0 5.0 mV 1 -7.0 7.0 mV 2, 3 -5.0 5.0 mV 1 -7.0 7.0 mV 2, 3 -5.0 5.0 mV 1 -7.0 7.0 mV 2, 3 -0.4 0.2 nA 1 -10 50 nA 2 -0.2 0.2 nA 1 -10 50 nA 2 -0.2 1.2 nA 1 -10 70 nA 2 -0.1 0.1 nA 1 -20 20 nA 2 Input Offset Voltage ±VCC = ±5V ±IIB +VCC = 26V, -VCC = -4V, VCM = -11V, t ≤ 25mS Input Bias Current t ≤ 25mS +VCC = 4V, -VCC = -26V, VCM = 11V, t ≤ 25mS IIO +PSRR Input Offset Current t ≤ 25mS Power Supply Rejection Ratio +VCC = 10V to 20V, -VCC = -15V 80 dB 1, 2, 3 +VCC = 15V, -VCC = -10V to -20V 80 dB 1, 2, 3 dB 1, 2, 3 mV 1, 2, 3 mV 1, 2, 3 -PSRR Power Supply Rejection Ratio CMR Input Voltage Common Mode Rejection VIO Adj+ Adjustment for Input Offset Voltage VIO Adj- Adjustment for Input Offset Voltage VCM = -11V to +11V -8.0 Output Short Circuit Current t ≤ 25mS IOS- Output Short Circuit Current t ≤ 25mS +VOP -VOP +AVS -AVS (1) (2) 4 -80 Supply Current ΔVIO / ΔT AVS 80 8.0 IOS+ ICC Subgroups Min Input Offset Voltage Output Voltage Swing Output Voltage Swing mA 1, 2, 3 80 mA 1, 2, 3 3.5 mA 1, 2 4.0 mA 3 2 25°C ≤ TA ≤ +125°C See (1) -30 30 µV/°C -55°C ≤ TA ≤ 25°C See (1) -30 30 µV/°C 3 V 4, 5, 6 RL = 10KΩ 12 RL = 2KΩ 10 RL = 10KΩ RL = 2KΩ V 4, 5, 6 -12 V 4, 5, 6 -10 V 4, 5, 6 (2) 50 K 4 See (2) 25 K 5, 6 Open Loop Voltage Gain RL = 2KΩ, VO = 0 to 10V See Open Loop Voltage Gain RL = 2KΩ, VO = 0 to -10V See (2) 50 K 4 See (2) 25 K 5, 6 Open Loop Voltage Gain RL = 10KΩ, VO = ±2V, ±VCC = ±5V See (2) 20 K 4, 5, 6 Calculated parameter. For calculation use VIO test at ±VCC = ±15V Datalog in K = V/mV. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LF411JAN Not Recommended For New Designs www.ti.com LF411JAN SNOSAQ4A – OCTOBER 2005 – REVISED MARCH 2013 Electrical Characteristics AC Parameters The following conditions apply to all the following parameters, unless otherwise specified. AC: VCC = ±15V, VCM = 0V Symbol SR+ Parameter Conditions Subgroups 7 V/µS 8A, 8B 7.0 V/µS 7 5.0 V/µS 8A, 8B 200 nS 7, 8A, 8B AV = 1, VI = 50mV, CL = 100pF, RL = 2KΩ 40 % 7, 8A, 8B Noise Broadband BW of 10Hz to 15KHz 15 µVRMS 7 Noise Popcorn BW of 10Hz to 15KHz, RS = 100KΩ 80 µVPK 7 Settling Time AV = 1 1,50 0 nS 12 Settling Time AV = 1 1,50 0 nS 12 Min Max Unit Subgroups VI = +5V to -5V TRTR Transient Response Rise Time AV = 1, VI = 50mV, CL = 100pF, RL = 2KΩ TROS Transient Response Overshoot NIBB -tS Unit V/µS Slew Rate +tS Max 5.0 VI = -5V to +5V NIPC Min 7.0 Slew Rate SR- Notes Electrical Characteristics DC Drift Parameters The following conditions apply to all the following parameters, unless otherwise specified. DC: VCC = ±15V, VCM = 0V Delta Calculations performed at Group B, subgroup 5, Only Symbol Parameter Conditions Notes VIO Input Offset Voltage -1.0 1.0 mV 1 ±IIB Input Bias Current -0.1 0.1 nA 1 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LF411JAN 5 Not Recommended For New Designs LF411JAN SNOSAQ4A – OCTOBER 2005 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics 6 Input Bias Current Input Bias Current Figure 2. Figure 3. Supply Current Positive Common-Mode Input Voltage Limit Figure 4. Figure 5. Negative Common-Mode Input Voltage Limit Positive Current Limit Figure 6. Figure 7. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LF411JAN Not Recommended For New Designs www.ti.com LF411JAN SNOSAQ4A – OCTOBER 2005 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Negative Current Limit Output Voltage Swing Figure 8. Figure 9. Output Voltage Swing Gain Bandwidth Figure 10. Figure 11. Bode Plot Slew Rate Figure 12. Figure 13. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LF411JAN 7 Not Recommended For New Designs LF411JAN SNOSAQ4A – OCTOBER 2005 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) 8 Distortion vs Frequency Undistorted Output Voltage Swing Figure 14. Figure 15. Open Loop Frequency Response Common-Mode Rejection Ratio Figure 16. Figure 17. Power Supply Rejection Ratio Equivalent Input Noise Voltage Figure 18. Figure 19. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LF411JAN Not Recommended For New Designs www.ti.com LF411JAN SNOSAQ4A – OCTOBER 2005 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Open Loop Voltage Gain Output Impedance Figure 20. Figure 21. Inverter Settling Time Figure 22. Pulse Response RL=2 kΩ, CL10 pF Figure 23. Small Signal Inverting Figure 24. Small Signal Non-Inverting Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LF411JAN 9 Not Recommended For New Designs LF411JAN SNOSAQ4A – OCTOBER 2005 – REVISED MARCH 2013 www.ti.com Pulse Response (continued) Figure 25. Large Signal Inverting Figure 26. Large Signal Non-Inverting Figure 27. Current Limit (RL=100Ω) 10 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LF411JAN Not Recommended For New Designs www.ti.com LF411JAN SNOSAQ4A – OCTOBER 2005 – REVISED MARCH 2013 APPLICATION HINTS The LF411JAN series of internally trimmed JFET input op amps ( BI-FET II™ ) provide very low input offset voltage and ensured input offset voltage drift. These JFETs have large reverse breakdown voltages from gate to source and drain eliminating the need for clamps across the inputs. Therefore, large differential input voltages can easily be accommodated without a large increase in input current. The maximum differential input voltage is independent of the supply voltages. However, neither of the input voltages should be allowed to exceed the negative supply as this will cause large currents to flow which can result in a destroyed unit. Exceeding the negative common-mode limit on either input will force the output to a high state, potentially causing a reversal of phase to the output. Exceeding the negative common-mode limit on both inputs will force the amplifier output to a high state. In neither case does a latch occur since raising the input back within the common-mode range again puts the input stage and thus the amplifier in a normal operating mode. Exceeding the positive common-mode limit on a single input will not change the phase of the output; however, if both inputs exceed the limit, the output of the amplifier may be forced to a high state. The amplifier will operate with a common-mode input voltage equal to the positive supply; however, the gain bandwidth and slew rate may be decreased in this condition. When the negative common-mode voltage swings to within 3V of the negative supply, an increase in input offset voltage may occur. The LF411 is biased by a zener reference which allows normal circuit operation on ±4.5V power supplies. Supply voltages less than these may result in lower gain bandwidth and slew rate. The LF411 will drive a 2 kΩ load resistance to ±10V over the full temperature range. If the amplifier is forced to drive heavier load currents, however, an increase in input offset voltage may occur on the negative voltage swing and finally reach an active current limit on both positive and negative swings. Precautions should be taken to ensure that the power supply for the integrated circuit never becomes reversed in polarity or that the unit is not inadvertently installed backwards in a socket as an unlimited current surge through the resulting forward diode within the IC could cause fusing of the internal conductors and result in a destroyed unit. As with most amplifiers, care should be taken with lead dress, component placement and supply decoupling in order to ensure stability. For example, resistors from the output to an input should be placed with the body close to the input to minimize “pick-up” and maximize the frequency of the feedback pole by minimizing the capacitance from the input to ground. A feedback pole is created when the feedback around any amplifier is resistive. The parallel resistance and capacitance from the input of the device (usually the inverting input) to AC ground set the frequency of the pole. In many instances the frequency of this pole is much greater than the expected 3 dB frequency of the closed loop gain and consequently there is negligible effect on stability margin. However, if the feedback pole is less than approximately 6 times the expected 3 dB frequency, a lead capacitor should be placed from the output to the input of the op amp. The value of the added capacitor should be such that the RC time constant of this capacitor and the resistance it parallels is greater than or equal to the original feedback pole time constant. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LF411JAN 11 Not Recommended For New Designs LF411JAN SNOSAQ4A – OCTOBER 2005 – REVISED MARCH 2013 www.ti.com Typical Applications Figure 28. High Speed Current Booster PNP=2N2905 NPN=2N2219 unless noted TO-5 heat sinks for Q6-Q7 Figure 29. 10-Bit Linear DAC with No VOS Adjust where AN=1 if the AN digital input is high AN=0 if the AN digital input is low 12 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LF411JAN Not Recommended For New Designs www.ti.com LF411JAN SNOSAQ4A – OCTOBER 2005 – REVISED MARCH 2013 Figure 30. Single Supply Analog Switch with Buffered Output Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LF411JAN 13 Not Recommended For New Designs LF411JAN SNOSAQ4A – OCTOBER 2005 – REVISED MARCH 2013 www.ti.com Table 2. Revision History 14 Date Released Revision Section Originator Changes 10/11/05 A New Release to corporate format L. Lytle 1 MDS data sheet was converted into the corporate data sheet format. MDS MJLF411-X Rev 0C1 will be archived. 3/27/2013 A All Sections Submit Documentation Feedback Changed layout of National Data Sheet to TI format Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LF411JAN PACKAGE OPTION ADDENDUM www.ti.com 17-Aug-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) JL411BPA LIFEBUY CDIP NAB 8 40 TBD Call TI Call TI -55 to 125 JL411BPA Q JM38510/ 11904BPA ACO 11904BPA >T JM38510/11904BPA LIFEBUY CDIP NAB 8 40 TBD Call TI Call TI -55 to 125 JL411BPA Q JM38510/ 11904BPA ACO 11904BPA >T M38510/11904BPA LIFEBUY CDIP NAB 8 40 TBD Call TI Call TI -55 to 125 JL411BPA Q JM38510/ 11904BPA ACO 11904BPA >T M38510/11904BPX LIFEBUY CDIP NAB 8 40 TBD Call TI Call TI -55 to 125 JL411BPA Q JM38510/ 11904BPA ACO 11904BPA >T (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 17-Aug-2016 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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