Mitsubishi MH28D72KLG-75 9,663,676,416-bit (134,217,728-word by 72-bit) double data rate synchronous dram module Datasheet

Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
DESCRIPTION
The MH28D72KLG is 134217728 - word x 72-bit Double
Data Rate(DDR) Sy nchronous DRAM mounted module.
This consists of 36 industry standard 64M x 4 DDR
Sy nchronous DRAMs in TSOP with SSTL_2 interf ace which
achiev es v ery high speed data rate up to 133MHz.
This socket-ty pe memory m odule is suitable f or main
memory in computer systems and easy to interchange or
add modules.
93pin
1pin
144pin
52pin
145pin
53pin
184pin
92pin
FEATURES
Type name
Max.
Frequency
CLK
Access Time
[component level]
MH28D72KLG-75
133MHz
+ 0.75ns
MH28D72KLG-10
100MHz
+ 0.8ns
- Utilizes industry standard 64M X 4 DDR Synchronous DRAMs
in TSOP package , industry standard Registered Buffer in
TSSOP package , and industry standard PLL in TSSOP package.
- Vdd=Vddq=2.5v ±0.2V
- Double data rate architecture; two data transf ers per
clock cy c le
- Bidirectional, data strobe (DQS) is transmitted/receiv ed
with data
- Dif f erential clock inputs (CLK and /CLK)
- data ref erenced to both edges of DQS
- /CAS latency - 2.0/2.5 (programmable)
- Burst length- 2/4/8 (programmable)
- Auto precharge / All bank precharge controlled by A10
- 8192 ref resh cy c les /64ms
- Auto ref resh and Self ref resh
- Row address A0-12 / Column address A0-9,11
- SSTL_2 Interf ace
- Module 2bank Conf igration
- Burst Ty pe - sequential/interleav e(programmable)
- Commands entered on each positiv e CLK edge
APPLICATION
Main memory unit for PC, PC server, Server, W S.
MIT-DS-0412-0.1
MITSUBISHI ELECTRIC
21.Mar.2001
1
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
PIN CONFIGURATION
PIN
NO.
1
PIN
NAME
PIN
NAME
PIN
NO.
84
DQ57
PIN
NO.
126
85
VDD
127
PIN
NAME
PIN
NO.
167
PIN
NAME
NC
DQ29
VDDQ
168
169
VDD
DQS15
PIN
NAME
DQ0
44
A1
CB0
3
VSS
45
CB1
86
DQS7
128
4
DQ1
46
VDD
87
DQ58
129
DQS12
170
DQ54
5
DQS0
47
DQS8
88
DQ59
130
A3
171
DQ55
6
DQ2
48
A0
89
DQ30
172
7
VDD
49
90
132
VSS
173
VDDQ
NC
8
DQ3
50
CB2
VSS
VSS
NC
131
91
SDA
133
DQ31
174
DQ60
NC
51
CB3
92
SCL
134
CB4
175
DQ61
52
BA1
93
VSS
135
CB5
176
94
VSS
DQS16
2
9
10
VREF
PIN
NO.
43
RESET
DQ28
11
VSS
DQ4
136
VDDQ
177
12
DQ8
53
DQ32
95
DQ5
137
CK0
178
DQ62
13
DQ9
54
VDDQ
96
138
/CK0
179
DQ63
14
DQS1
55
DQ33
97
VDDQ
DQS9
VDDQ
15
56
DQS4
98
DQ6
140
181
SA0
16
VDDQ
NC
VSS
DQS17
180
57
DQ34
99
DQ7
141
A10
182
SA1
17
NC
58
VSS
100
CB6
183
18
VSS
59
BA0
101
VSS
NC
142
143
VDDQ
184
19
DQ10
60
DQ35
102
NC
144
CB7
DQ40
103
21
DQ11
CKE0
61
62
104
VDDQ
145
VSS
22
VDDQ
63
VDDQ
/WE
105
DQ12
146
DQ36
23
DQ16
64
DQ41
106
DQ13
147
DQ37
24
DQ17
65
/CAS
107
148
25
DQS2
66
VSS
108
DQS10
VDD
149
VDD
DQS13
26
VSS
67
DQS5
109
DQ14
150
DQ38
27
A9
68
DQ42
110
151
DQ39
28
DQ18
69
DQ43
111
DQ15
CKE1
152
VSS
29
A7
70
VDD
112
153
DQ44
30
71
NC
113
154
/RAS
31
VDDQ
DQ19
VDDQ
NC
72
DQ48
114
DQ20
155
DQ45
32
A5
73
DQ49
115
A12
156
VDDQ
33
DQ24
74
116
VSS
157
34
VSS
75
VSS
NC
117
DQ21
158
/S0
/S1
35
DQ25
76
NC
118
DQS14
VSS
78
DQ46
VDD
79
121
VDD
DQ22
161
38
VDDQ
DQS6
DQ50
160
37
DQS3
A4
119
A11
DQS11
159
77
162
39
DQ26
80
DQ51
122
A8
163
DQ47
NC
40
DQ27
81
VSS
123
DQ23
164
VDDQ
41
42
A2
VSS
82
83
VDDID
DQ56
124
VSS
A6
165
DQ52
DQ53
20
36
KEY
120
125
139
NC
KEY
166
MIT-DS-0412-0.1
MITSUBISHI ELECTRIC
SA2
VDDSPD
NC: No Connect
21.Mar.2001
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Preliminary Spec.
MITSUBISHI LSIs
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MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
Block Diagram
VSS
/RS1
/RS0
DQS0
DQS9
DQ0
DQ1
DM
DQ2
DQ3
/S
DQS
DM
D0
DQS
/S
D18
DM
DQ10
DQ11
/S
DQS
DM
/S
D19
D1
DM
DQ18
DQ19
/S
DM
DQS
DQS
/S
D28
D10
/S
DQS
DM
/S
DQ20
DQ21
DQS
DQ22
DQ23
D20
D2
DM
/S
DM
DQS
DQS
/S
D29
D11
DQS12
DQ24
DQ25
DM
DQ26
DQ27
/S
DQS
DM
/S
DQ28
DQ29
DQS
DM
DQ30
DQ31
D21
D3
DQS4
/S
DM
DQS
/S
DQS
D30
D12
DQS13
DQ32
DQ33
DM
DQ34
DQ35
/S
DQS
DM
/S
DQ36
DQ37
DQS
D22
D4
DM
DQ38
DQ39
DQS5
/S
DM
DQS
/S
DQS
D31
D13
DQS14
DQ40
DQ41
DM
DQ42
DQ43
/S
DQS
DM
/S
DQ44
DQ45
DQS
DM
DQ46
DQ47
D23
D5
/S
DM
DQS
/S
DQS
D32
D14
DQS15
DQS6
DQ48
DQ49
DM
DQ50
DQ51
/S
DQS
DM
/S
DQ52
DQ53
DQS
DM
DQ54
DQ55
D024
D6
/S
DM
DQS
/S
DQS
D33
D15
DQS16
DQS7
DQ56
DQ57
DM
DQ58
DQ59
/S
DQS
DM
/S
DQ60
DQ61
DQS
DM
DQ62
DQ63
D025
D7
/S
DM
DQS
/S
DQS
D34
D16
DQS17
DQS8
CB0
CB1
CB2
CB3
DM
/S
DQS
RBA0-RBA1 -> SDRAMs D0-D35
RA0-RA12 -> SDRAMs D0-D35
/RRAS -> SDRAMs D0-D35
/RCAS -> SDRAMs D0-D35
/RCKE0 -> SDRAMs D0-D17
/RCKE1 -> SDRAMs D18-D35
/RWE -> SDRAMs D0-D35
/RESET
DM
/S
CB4
CB5
DQS
CK0
PLL
/CK0
DM
CB6
CB7
D026
D8
/RS0 -> SDRAMs D0-D17
/RS1 -> SDRAMs D18-D35
PCK
/PCK
DM
DQ14
DQ15
DQS3
/WE
DQS
/S
D27
DQS11
DQ16
DQ17
CKE1
DM
DQS
D9
DQ12
DQ13
DQS
DQS2
/S1
/S
DQS10
DQ8
DQ9
BA0-BA1
A0-A12
/RAS
/CAS
CKE0
DM
DQ6
DQ7
DQS1
/S0
DQ4
DQ5
DM
DQS
/PCK0 -> SDRAMs D0-D35,
Registered Buffer
SERIAL PD
/S
DQS
D35
D17
PCK0 -> SDRAMs D0-D35,
Registered Buffer
SCL
/S
Serial PD
VDDSPD
VDDQ
D0 to D35
VDD
D0 to D35
VREF
D0 to D35
VSS
D0 to D35
VDDID
SDA
WP
A0 A1
A2
VDDID: OPEN -> VDD = VDDQ
VSS -> VDD = VDDQ
SA0 SA1 SA2
MIT-DS-0412-0.1
MITSUBISHI ELECTRIC
21.Mar.2001
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Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
PIN FUNCTION
SYMBOL
CK0,/CK0
CKE0, CKE1
/S0, /S1
/RAS, /CAS, /WE
TYPE
Input
DESCRIPTION
Clock: CK0 and /CK0 are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive edge
of CK0 and negative edge of /CK0. Output (read) data is referenced to
the crossings of CK0 and /CK0 (both directions of crossing).
Input
Clock Enable: CKE0,1 controls SDRAM internal clock. When CKE0 is low, the
internal clock f or the f ollowing cy c le is ceased. CKE0 is also used to select
auto / self ref resh. After self ref resh mode is started, CKE0 becomes
asy nchronous input. Self ref resh is maintained as long as CKE0 is low.
Input
Phy s ical Bank Select: When /S0,1 is high, any command means No Operation.
Input
Combination of /RAS, /CAS, /WE defines basic commands.
A0-12
Input
A0-12 specif y the Row / Column Address in conjunction with BA0,1. The Row
Address is specif ied by A0-12. The Column Address is specif ied by A0-9,11.
A10 is also used to indicate precharge option. When A10 is high at a read / write
command, an auto precharge is perf ormed. When A10 is high at a precharge
command, all banks are precharged.
BA0,1
Input
Bank Address: BA0,1 specifies one of four banks in SDRAM to which a command is applied. BA0,1
must be set with ACT, PRE, READ, WRITE commands.
DQ 0-64
CB 0-7
Input / Output
DQS0-17
Input / Output
Vdd, VddQ
VddQ, VssQ
Vddspd
Data Input/Output: Data bus
Data Strobe: Output with read data, input with write data. Edge-aligned
with read data, centered in write data. Used to capture write data.
Power Supply
Power Supply. Vdd and VddQ are connected on the module.
Power Supply
Power Supply. Vss and VssQ are connected on the module.
Power Supply
Power Supply for SPD
Vref
Input
RESET
Input
SDA
Input / Output
SCL
Input
This signal is used to clock data into and out of the SPD EEPROM. A resistor
may be connected f rom the SCL bus time to VDD to act as a pullup.
SA0-2
Input
These signals are tied at the system planar to either VSS or VDD to conf igure
the serial SPD EEPROM address range.
VDDID
SSTL_2 reference voltage.
This signal is asynchronous and is driven low to the register in order to
guarantee the register outputs are low.
This bidirectional pin is used to transf er data into or out of the SPD EEPROM.
A resistor must be connected f rom the SDA bus line to VDD to act as a pullup.
VDD identif ication f lag
MIT-DS-0412-0.1
MITSUBISHI ELECTRIC
21.Mar.2001
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
BASIC FUNCTIONS
The MH28D72KLG provides basic functions, bank (row) activate, burst read / write, bank (row)
precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS
and /WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip
select, refresh option, and precharge option, respectively. To know the detailed definition of
commands, please see the command truth table.
/CK0
CK0
/S0
Chip Select : L=select, H=deselect
/RAS
Command
/CAS
Command
/WE
Command
CKE0
A10
def ine basic commands
Ref resh Option @ref resh command
Precharge Option @precharge or read/write command
Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA. First output data
appears after /CAS latency. When A10 =H at this command, the bank is deactivated after the
burst read (auto-precharge,READA)
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data length to be
written is set by burst length. When A10 =H at this command, the bank is deactivated after
the burst write (auto-precharge, WRITEA).
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active bank indicated by BA. This command also terminates
burst read /write operation. When A10 =H at this command, all banks are deactivated
(precharge all, PREA).
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE0 =H]
REFA command starts auto-refresh cycle. Refresh address including bank address are
generated internally. After this command, the banks are precharged automatically.
MIT-DS-0412-0.1
MITSUBISHI ELECTRIC
21.Mar.2001
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Preliminary Spec.
MITSUBISHI LSIs
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MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
COM M AND TRUTH TABLE
COMMAND
MNEMONIC
CKE
n-1
CKE
n
/S
/RAS
/CAS
/WE
BA0,1
A10
/AP
Deselect
DESEL
H
X
H
X
X
X
X
X
X
NOP
H
X
L
H
H
H
X
X
X
Row Address Entry &
Bank Activate
ACT
H
X
L
L
H
H
V
V
V
Single Bank Precharge
PRE
H
X
L
L
H
L
V
L
X
Precharge All Banks
PREA
H
X
L
L
H
L
X
H
X
WRIT E
H
X
L
H
L
L
V
L
V
WRITEA
H
X
L
H
L
L
V
H
V
READ
H
X
L
H
L
H
V
L
V
READA
H
X
L
H
L
H
V
H
V
REFA
H
H
L
L
L
H
X
X
X
Self-Refresh Entry
REFS
H
L
L
L
L
H
X
X
X
Self-Refresh Exit
REFSX
L
H
H
X
X
X
X
X
X
L
H
L
H
H
H
X
X
X
Burst Terminate
TERM
H
X
L
H
H
L
X
X
X
1
Mode Register Set
MRS
H
X
L
L
L
L
L
L
V
2
No Operation
Column Address Entry
& Write
Column Address Entry
& Write with
Auto-Precharge
Column Address Entry
& Read
Column Address Entry
& Read with
Auto-Precharge
Auto-Refresh
A0-9,
note
11-12
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number
NOTE:
1. Applies only to read bursts with autoprecharge disabled; this command is undefined (and should
not be used) for read bursts with autoprecharge enabled, and for write bursts.
2. BA0-BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode
Register; BA0 = 1, BA1 = 0 selects Extended Mode Register; other combinations of BA0-BA1 are
reserved; A0-A11 provide the op-code to be written to the selected Mode Register.
MIT-DS-0412-0.1
MITSUBISHI ELECTRIC
21.Mar.2001
6
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
FUNCTION TRUTH TABLE
Current State
/S
IDLE
ROW ACTIVE
READ
(AutoPrecharge
Disabled)
/RAS /CAS /WE
Address
Command
Notes
Action
H
X
X
X
X
DESEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
BA
TERM
ILLEGAL
2
L
H
L
X
BA, CA, A10
READ / WRITE ILLEGAL
2
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, A10
PRE / PREA
L
L
L
H
X
L
L
L
L
H
X
X
X
X
DESEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
BA
TERM
NOP
L
H
L
H
BA, CA, A10
L
H
L
L
BA, CA, A10
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, A10
PRE / PREA
L
L
L
H
X
L
L
L
L
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
L
H
H
H
X
NOP
NOP (Continue Burst to END)
L
H
H
L
BA
TERM
Terminate Burst
Op-Code,
Mode-Add
Op-Code,
Mode-Add
Bank Active, Latch RA
NOP
4
REFA
Auto-Refresh
5
MRS
Mode Register Set
5
READ / READA
Begin Read, Latch CA,
Determine Auto-Precharge
WRITE /
Begin Write, Latch CA,
WRITEA
Determine Auto-Precharge
2
Bank Active / ILLEGAL
Precharge / Precharge All
REFA
ILLEGAL
MRS
ILLEGAL
Terminate Burst, Latch CA,
L
H
L
H
BA, CA, A10
READ / READA Begin New Read, Determine
3
Auto-Precharge
WRITE
L
H
L
L
BA, CA, A10
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, A10
PRE / PREA
L
L
L
H
X
L
L
L
L
Op-Code,
Mode-Add
WRITEA
ILLEGAL
Terminate Burst, Precharge
REFA
ILLEGAL
MRS
ILLEGAL
MIT-DS-0412-0.1
MITSUBISHI ELECTRIC
2
Bank Active / ILLEGAL
21.Mar.2001
7
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
FUNCTION TRUTH TABLE (continued)
Current State
/S
WRIT E
(AutoPrecharge
Disabled)
H
X
X
X
L
H
H
L
H
H
/RAS /CAS /WE
Address
Command
Action
Notes
X
DESEL
NOP (Continue Burst to END)
H
X
NOP
NOP (Continue Burst to END)
L
BA
TERM
ILLEGAL
Terminate Burst, Latch CA,
L
H
L
H
BA, CA, A10
READ / READA Begin Read, Determine AutoPrecharge
WRITE /
3
Terminate Burst, Latch CA,
Begin Write, Determine AutoPrecharge
3
Bank Active / ILLEGAL
2
L
H
L
L
BA, CA, A10
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, A10
PRE / PREA
L
L
L
H
X
L
L
L
L
READ with
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
AUTO
PRECHARGE
L
H
H
H
X
NOP
NOP (Continue Burst to END)
L
H
H
L
BA
TERM
ILLEGAL
L
H
L
H
BA, CA, A10
L
H
L
L
BA, CA, A10
L
L
H
H
BA, RA
ACT
Bank Active / ILLEGAL
2
L
L
H
L
BA, A10
PRE / PREA
PRECHARGE/ILLEGAL
2
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
WRITE with
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
AUTO
PRECHARGE
L
H
H
H
X
NOP
NOP (Continue Burst to END)
L
H
H
L
BA
TERM
ILLEGAL
L
H
L
H
BA, CA, A10
L
H
L
L
BA, CA, A10
L
L
H
H
BA, RA
ACT
Bank Active / ILLEGAL
2
L
L
H
L
BA, A10
PRE / PREA
PRECHARGE/ILLEGAL
2
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
Op-Code,
Mode-Add
WRITEA
Terminate Burst, Precharge
REFA
ILLEGAL
MRS
ILLEGAL
READ / READA ILLEGAL
WRITE /
WRITEA
ILLEGAL
READ / READA ILLEGAL
WRITE /
WRITEA
MIT-DS-0412-0.1
MITSUBISHI ELECTRIC
ILLEGAL
21.Mar.2001
8
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
FUNCTION TRUTH TABLE (continued)
Current State
/S
/RAS /CAS /WE
Address
Command
Action
Notes
PRE -
H
X
X
X
X
DESEL
NOP (Idle after tRP)
CHARGING
L
H
H
H
X
NOP
NOP (Idle after tRP)
L
H
H
L
BA
TERM
ILLEGAL
2
L
H
L
X
BA, CA, A10
READ / WRITE ILLEGAL
2
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, A10
PRE / PREA
L
L
L
H
X
L
L
L
L
H
X
X
X
X
DESEL
NOP (Row Active after tRCD)
L
H
H
H
X
NOP
NOP (Row Active after tRCD)
L
H
H
L
BA
TERM
ILLEGAL
2
L
H
L
X
BA, CA, A10
READ / WRITE ILLEGAL
2
L
L
H
H
BA, RA
ACT
ILLEGAL
2
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL
2
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
MRS
ILLEGAL
WRITE RE-
H
X
X
X
X
DESEL
NOP
COVERING
L
H
H
H
X
NOP
NOP
L
H
H
L
BA
TERM
ILLEGAL
L
H
L
X
BA, CA, A10
L
L
H
H
BA, RA
ACT
ILLEGAL
2
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL
2
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
MRS
ILLEGAL
ROW
ACTIVATING
Op-Code,
Mode-Add
Op-Code,
Mode-Add
Op-Code,
Mode-Add
ILLEGAL
2
NOP (Idle after tRP)
4
REFA
ILLEGAL
MRS
ILLEGAL
2
2
READ / WRITE ILLEGAL
MIT-DS-0412-0.1
MITSUBISHI ELECTRIC
21.Mar.2001
9
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
FUNCTION TRUTH TABLE (continued)
Current State
/S
RE-
H
X
X
X
X
DESEL
NOP (Idle after tRC)
FRESHING
L
H
H
H
X
NOP
NOP (Idle after tRC)
L
H
H
L
BA
TERM
ILLEGAL
L
H
L
X
BA, CA, A10
L
L
H
H
BA, RA
ACT
ILLEGAL
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
MRS
ILLEGAL
MODE
H
X
X
X
X
DESEL
NOP (Idle after tRSC)
REGISTER
L
H
H
H
X
NOP
NOP (Idle after tRSC)
SETTING
L
H
H
L
BA
TERM
ILLEGAL
L
H
L
X
BA, CA, A10
L
L
H
H
BA, RA
ACT
ILLEGAL
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
MRS
ILLEGAL
/RAS /CAS /WE
Address
Op-Code,
Mode-Add
Op-Code,
Mode-Add
Command
Action
Notes
READ / WRITE ILLEGAL
READ / WRITE ILLEGAL
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No Operation
NOTES:
1. All entries assume that CKE0 was High during the preceding clock cycle and the current clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of
that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and/or data-integrity are not guaranteed.
MIT-DS-0412-0.1
MITSUBISHI ELECTRIC
21.Mar.2001
10
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
FUNCTION TRUTH TABLE for CKE
Current State
CKE CKE
n
n-1
/S
/RAS /CAS /WE
Add
Action
Notes
H
X
X
X
X
X
X
INVALID
1
L
H
H
X
X
X
X
Exit Self-Refresh (Idle after tRC)
1
L
H
L
H
H
H
X
Exit Self-Refresh (Idle after tRC)
1
L
H
L
H
H
L
X
ILLEGAL
1
L
H
L
H
L
X
X
ILLEGAL
1
L
H
L
L
X
X
X
ILLEGAL
1
L
L
X
X
X
X
X
NOP (Maintain Self-Refresh)
1
POWER
H
X
X
X
X
X
X
INVALID
DOWN
L
H
X
X
X
X
X
Exit Power Down to Idle
L
L
X
X
X
X
X
NOP (Maintain Self-Refresh)
H
H
X
X
X
X
X
Refer to Function Truth Table
2
H
L
L
L
L
H
X
Enter Self-Refresh
2
H
L
H
X
X
X
X
Enter Power Down
2
H
L
L
H
H
H
X
Enter Power Down
2
H
L
L
H
H
L
X
ILLEGAL
2
H
L
L
H
L
X
X
ILLEGAL
2
H
L
L
L
X
X
X
ILLEGAL
2
L
X
X
X
X
X
X
Refer to Current State =Power Down
2
ANY STATE
H
H
X
X
X
X
X
Refer to Function Truth Table
other than
H
L
X
X
X
X
X
Begin CLK Suspend at Next Cycle
3
listed above
L
H
X
X
X
X
X
Exit CLK Suspend at Next Cycle
3
L
L
X
X
X
X
X
Maintain CLK Suspend
SELFREFRESH
ALL BANKS
IDLE
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
NOTES:
1. CKE0 Low to High transition will re-enable CK0 and other inputs asynchronously
. A minimum setup time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State.
3. Must be legal command.
MIT-DS-0412-0.1
MITSUBISHI ELECTRIC
21.Mar.2001
11
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
SIMPLIFIED STATE DIAGRAM
POWER
APPLIED
POWER
ON
PRE
CHARGE
ALL
PREA
SELF
REFRESH
REFS
MRS
MODE
REGISTER
SET
REFSX
MRS
REFA
AUTO
REFRESH
IDLE
CKEL
CKEH
Active
Power
Down
ACT
POWER
DOWN
CKEL
CKEH
ROW
ACTIVE
WRITE
BURST
STOP
READ
WRITE
READ
WRITEA
READA
READ
WRIT E
READ
WRITEA
TERM
READA
READA
PRE
WRITEA
PRE
READA
PRE
PRE
CHARGE
Automatic Sequence
Command Sequence
MIT-DS-0412-0.1
MITSUBISHI ELECTRIC
21.Mar.2001
12
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM
from damaged or multifunctioning.
1. Apply VDD and VDDQ before or the same time as VTT & Vref
2. Maintain stable condition for 200us after stable power and CLK, apply NOP or DSEL
3. Issue precharge command for all banks of the device
4. Issue EMRS
5. Issue MRS
6. Issue 2 or more Auto Refresh commands
7. Maintain stable condition for 200 cycle
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
CK0
Burst Length, Burst Type and /CAS Latency can be programmed by
setting the mode register (MRS). The mode register stores these data until
/CK0
the next MRS command, which may be issued in idle state.
/S0
After tMRD from a MRS command, the DDR DIMM is ready for new
/RAS
command.
/CAS
BA1 BA0 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
/WE
A1 A0
BA0
0
0
0
0
0
0
DR
0
LTMODE
BT
BL
BA1
V
A11-A0
BL
CL
Latency
Mode *1
(SDRAM
level)
DLL
Reset
000
001
010
011
100
101
110
111
0
NO
1
YES
/CAS Latency
R
R
2
R
R
R
2.5
R
Burst
Length
Burst
Type
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
BT= 0
0
1
0
1
0
1
0
1
R
2
4
8
R
R
R
R
BT= 1
R
2
4
8
R
R
R
R
Sequential
Interleaved
1
R: Reserved for Future Use
*1 In the module, 1latency should be added due to registered DIMM.
MIT-DS-0412-0.1
MITSUBISHI ELECTRIC
21.Mar.2001
13
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
EXTENDED MODE REGISTER
DLL disable / enable mode can be programmed by setting the extended
mode register (EMRS). The extended mode register stores these data
until the next EMRS command, which may be issued in idle state.
After tMRD from a EMRS command, the DDR DIMM is ready for new
command.
CK0
/CK0
/S0
/RAS
/CAS
/WE
BA1 BA0 A12 A11 A10 A9
0
1
0
0
0
0
A8
A7
A6
A5
A4
A3
0
0
0
0
0
0
A2
A1 A0
BA0
BA1
QFC DS DD
A11-A0
DLL
Disable
Drive
Strength
QFC
MIT-DS-0412-0.1
MITSUBISHI ELECTRIC
0
1
V
0
1
DLL enable
DLL disable
0
1
Normal
Weak
Disable
Enable
21.Mar.2001
14
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
( Componennt Level )
/CLK
CLK
Command
Read
Write
Y
Y
Address
DQS
Q0 Q1 Q2 Q3
DQ
Burst
Length
Burst
Length
/CAS
Latency
CL= 2
BL= 4
D0 D1 D2 D3
Initial Address BL
Column Addressing
A2
A1
A0
Sequential
Interleaved
0
0
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
0
1
1
2
3
4
5
6
7
0
1
0
3
2
5
4
7
6
0
1
0
2
3
4
5
6
7
0
1
2
3
0
1
6
7
4
5
0
1
1
3
4
5
6
7
0
1
2
3
2
1
0
7
6
5
4
8
1
0
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
1
0
1
5
6
7
0
1
2
3
4
5
4
7
6
1
0
3
2
1
1
0
6
7
0
1
2
3
4
5
6
7
4
5
2
3
0
1
1
1
1
7
0
1
2
3
4
5
6
7
6
5
4
3
2
1
0
-
0
0
0
1
2
3
0
1
2
3
-
0
1
1
2
3
0
1
0
3
2
4
-
1
0
2
3
0
1
2
3
0
1
-
1
1
3
0
1
2
3
2
1
0
-
-
0
0
1
0
1
1
0
1
0
-
-
1
2
MIT-DS-0412-0.1
MITSUBISHI ELECTRIC
21.Mar.2001
15
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
ABSOLUTE M AXIMUM RATINGS
Symbol
Parameter
Conditions
Ratings
Unit
Vdd
Supply Voltage
with respect to Vss
-0.5 ~ 3.7
V
VddQ
Supply Voltage for Output
with respect to VssQ
-0.5 ~ 3.7
V
VI
Input Voltage
with respect to Vss
VO
Output Voltage
with respect to VssQ
IO
Output Current
Pd
Power Dissipation
-0.5 ~ Vdd+0.5
V
-0.5 ~ VddQ+0.5
V
Ta = 25°C
50
mA
20
W
Topr
Operating Temperature
0 ~ 70
°C
Tstg
Storage Temperature
-40 ~ 100
°C
DC OPERATING CONDITIONS
(Ta=0 ~ 70°C
, unless otherwise noted)
Limits
Symbol
Parameter
Unit Notes
Min.
Typ.
Max.
2.3
2.5
2.7
V
1.25
1.35
V
Vdd/VddQ
Supply Voltage
Vref
Input Reference Voltage
VIH(DC)
High-Level Input Voltage
Vref + 0.18
VddQ+0.3
V
VIL(DC)
Low-Level Input Voltage
-0.3
Vref - 0.18
V
VIN(DC)
Input Voltage Level, CK0 and /CK0
-0.3
VddQ + 0.3
V
VID(DC)
Input Differential Voltage, CK0 and /CK0
0.36
VddQ + 0.6
V
7
VTT
I/O Termination Voltage
Vref - 0.04
Vref + 0.04
V
6
1.15
5
CAPACITANCE
(Ta=0 ~ 70°C
, Vdd = VddQ = 2.5 ± 0.2V, Vss = VssQ = 0V, unless otherwise noted)
Symbol
Parameter
CI(A)
Input Capacitance, address pin
CI(C)
Input Capacitance, control pin
CI(K)
CI/O
Test Condition
Limits(max.)
Unit Notes
17
pF
11
17
pF
11
Input Capacitance, CK0 pin
8
pF
11
Input Capacitance, I/O pin
20
pF
11
f =1MHz
MIT-DS-0412-0.1
MITSUBISHI ELECTRIC
21.Mar.2001
16
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 ~ 70°C
, Vdd = VddQ = 2.5 ± 0.2V, Vss = VssQ = 0V, Output Open, unless otherwise noted)
Sy m bol
Limits(max)
Parameter/Test Conditions
Unit Notes
-75
-10
IDD0
OPERATING CURRENT: One Bank; Activ e-Precharge;
t RC = t RC MIN; t CK = t CK MIN; DQ, DM and DQS inputs changing
twice per clock cy c le; address and control inputs changing once per
clock cy c le
2819
2520
mA
IDD1
OPERATING CURRENT: One Bank; Activ e-Read-Precharge;
Burst = 2; t RC = t RC MIN; CL = 2.5; t CK = t CK MIN; IOUT= 0
mA;Address and control inputs changing once per clock cy c le
2909
2744
mA
IDD2P
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle;
power-down mode; CKE VIL (MAX); t CK = t CK MIN
1289
1214
mA
IDD2N
IDLE STANDBY CURRENT: /CS > VIH (MIN); All banks idle;
CKE > VIH (MIN); t CK = t CK MIN; Address and other control inputs
changing once per clock cy c le
1469
1394
mA
IDD3P
ACTIVE POWER-DOWN STANDBY CURRENT: One bank activ e;
power-down mode; CKE VIL (MAX); t CK = t CK MIN
1469
1394
mA
IDD3N
ACTIVE STANDBY CURRENT: /CS > VIH (MIN); CKE > VIH (MIN);
One bank; Activ e-Precharge; t RC = t RAS MAX; t CK = t CK MIN;
DQ,DM and DQS inputs changing twice per clock cy c le; address and
other control inputs changing once per clock cy c le
2009
1844
mA
IDD4R
OPERATING CURRENT: Burst = 2; Reads; Continuous burst;One
bank activ e; Address and control inputs changing once per clock
cy c le; CL = 2.5; t CK = t CK MIN; IOUT = 0 mA
3629
3374
mA
3269
3104
mA
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One
bank activ e; Address and control inputs changing once per clock
IDD4W
cy c le; CL = 2.5; t CK = t CK MIN; DQ, DM and DQS inputs changing
twice per clock cy c le
IDD5
AUTO REFRESH CURRENT: t RC = t RFC (MIN)
4259
4004
mA
IDD6
SELF REFRESH CURRENT: CKE
983
908
mA
0.2V
9
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 ~ 70°C
Symbol
, Vdd = VddQ = 2.5 ± 0.2V, Vss = VssQ = 0V, unless otherwise noted)
Limits
Parameter/Test Conditions
VIH(AC) High-Level Input Voltage (AC)
Min.
Vref + 0.35
VIL(AC) Low-Level Input Voltage (AC)
IOZ
Ii
Unit Notes
V
Vref - 0.35
V
V DDQ + 0.6
V
7
0.5*V DDQ-0.2
0.5*V DDQ+0.2
8
-5
5
V
µA
-10
10
µA
VID(AC) Input Differential Voltage, CLK and /CLK
VIX(AC) Input Crossing Point Voltage, CLK and /CLK
Max.
0.7
Off-state Output Current /Q floating Vo=0~V DDQ
Input Current / VIN=0 ~ VddQ
MIT-DS-0412-0.1
MITSUBISHI ELECTRIC
21.Mar.2001
17
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
AC TIMING REQUIREMENTS (Component Level)
(Ta=0 ~ 70°C
, Vdd = VddQ = 2.5 ± 0.2V, Vss = VssQ = 0V, unless otherwise noted)
AC Characteristics
-75
Parameter
-10
Min.
Max.
Min.
Max.
Unit
DQ Output Valid data delay time f rom CLK//CLK
-0.75
+0.75
-0.8
+0.8
ns
tDQSCK DQ Output Valid data delay time f rom CLK//CLK
-0.75
+0.75
-0.8
+0.8
ns
Sy m bol
tAC
tCH
CLK High lev el width
0.45
0.55
0.45
0.55
tCK
tCL
CLK Low lev el width
0.45
0.55
0.45
0.55
tCK
tHP
CLK half period
tCK
CLK cy c le time
min
(tCL,tCH)
min
(tCL,tCH)
ns
CL=2.5
7.5
15
8
15
ns
CL=2
10
15
10
15
ns
Notes
20
tDH
Input Setup time (DQ,DM)
0.5
0.6
ns
tDS
Input Hold time(DQ,DM)
0.5
0.6
ns
tDIPW
DQ and DM input pulse width (f or each input)
1.75
2
ns
tHZ
Data-out-high impedance time f rom CLK//CLK
-0.75
+0.75
-0.8
+0.8
ns
14
tLZ
Data-out-low impedance time f rom CLK//CLK
-0.75
+0.75
-0.8
+0.8
ns
14
tDQSQ
DQS-DQ Skew(f or DQS and associated DQ signals)
+0.5
+0.6
ns
tDQSA
DQS-DQ Skew(f or DQS and all DQ signals)
+0.5
+0.6
ns
tQH
DQ/DQS output hold time f rom DQS
tHP-0.75
ns
tHP-1.0
tDQSS
Write command to f irst DQS latching transition
0.75
tDQSH
DQS input High lev el width
0.35
0.35
tCK
tDQSL
DQS input Low lev el width
0.35
0.35
tCK
tDSS
DQS f alling edge to CLK setup time
0.2
0.2
tCK
tDSH
DQS f alling edge hold time f rom CLK
0.2
0.2
tCK
tMRD
Mode Register Set command cy c le time
15
15
ns
0
0
ns
16
tCK
15
tWPRES Write preamble setup time
1.25
0.6
tCK
Write postamble
0.4
tWPRE
Write preamble
0.25
0.25
tCK
tIS
Input Setup time (address and control)
0.9
1.1
ns
19
tIH
Input Hold time (address and control)
0.9
1.1
ns
19
tRPST
Read postamble
0.4
0.6
0.4
0.6
tCK
tRPRE
Read preamble
0.9
1.1
0.9
1.1
tCK
MITSUBISHI ELECTRIC
0.4
1.25
tWPST
MIT-DS-0412-0.1
0.6
0.75
21.Mar.2001
18
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
AC TIMING REQUIREMENTS(Continues)
(Ta=0 ~ 70°C
, Vdd = VddQ = 2.5 ± 0.2V, Vss = VssQ = 0V, unless otherwise noted)
AC Characteristics
-75
Parameter
Symbol
-10
Min.
Max.
Min.
Max.
120,000
50
120,000
Unit Notes
tRAS
Row Active time
45
tRC
Row Cycle time(operation)
65
70
ns
tRFC
Auto Ref. to Active/Auto Ref. command period
75
80
ns
tRCD
Row to Column Delay
20
20
ns
tRP
Row Precharge time
20
20
ns
tRRD
Act to Act Delay time
15
15
ns
tWR
Write Recovery time
15
15
ns
tDAL
Auto Precharge write recovery + precharge time
35
35
ns
tWT R
Internal Write to Read Command Delay
1
1
tCK
tXSNR
Exit Self Ref. to non-Read command
75
80
ns
tXSRD
Exit Self Ref. to -Read command
200
200
tCK
tXPNR
Exit Power down to command
1
1
tCK
tXPRD
Exit Power down to -Read command
1
1
tCK
18
tREFI
Average Periodic Refresh interval
7.8
7.8
us
17
ns
Output Load Condition
(f or component measurement)
VREF
DQS
V TT =V REF
DQ
10cm
VO U T
VREF
50ohm
Zo=50 ohm
30pF
V REF
Output Timing
Measurement
Reference
Point
MIT-DS-0412-0.1
MITSUBISHI ELECTRIC
21.Mar.2001
19
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
Notes
1. All voltages referenced to Vss.
2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply
voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
3. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still
referenced to VREF (or to the crossing point for CK//CK), and parameter specifications are guaranteed for the specified
AC input levels under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range
between VIL(AC) and VIH(AC).
4. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver will effectively switch
as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back
above (below) the DC input LOW (HIGH) level.
5. VREF is expected to be equal to 0.5*VddQ of the transmitting device, and to track variations in the DC level of the
same. Peak-to-peak noise on VREF may not exceed +/-2% of the DC value.
6. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set
equal to VREF, and must track variations in the DC level of VREF.
7. VID is the magnitude of the difference between the input level on CLK and the input level on /CLK.
8. The value of VIX is expected to equal 0.5*VddQ of the transmitting device and must track variations in the DC level of
the same.
9. Enables on-chip refresh and address counters.
10. IDD specification are tested after the device is properly initialized.
11. This parameter is sampled. VddQ = +2.5V+/-0.2V, Vdd = +2.5V+/-0.2V, f =100MHz, Ta = 25 C , VOUT(DC)=
VddQ/2, VOUT(PEAK TO PEAK) = 25mV, DM inputs are grouped with I/O pins - reflecting the fact that they are
matched in laoding (to faciliate trace matching at the board level).
12. The CLK//CLK input reference level (for signals other than CLK//CLK) is the point at which CLK and /CLK cross;
the input reference level for signals other than CLK//CLK, is VREF.
13. Inputs are not recognized as valid until VREF stabilized. Exception: during the period before VREF stabilizes, CKE=<
0.3VddQ is recognized as LOW.
14. t HZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not
referenced to a specific voltage level, but specify when the device output is no longer driving (HZ), or begins driving
(LZ).
15. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this
parameter, but system performance (bus turnaround) will degrade accordingly.
16. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this
CLK edge. A valid transition is defined as monotonic, and meeting the input slew rate specifications of the device. When
no writes were previously in progress on the bus, DQS will be transitioning from High-Z to logic LOW. If a previous
write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on
tDQSS.
17. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.
18. tXPRD should be 200 tCLK in the condition of the unstable CLK operation during the power down mode.
19. For command/address and CLK & /CLK slew rate >1.0V/ns.
20. Min(tCL, tCH)refers to the smaller of the actual clock low time and the actualclock high time as provided to the
device.
O
MIT-DS-0412-0.1
MITSUBISHI ELECTRIC
21.Mar.2001
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
(Component Level)
Read Operation
tCK
tCH
tCL
/CLK
CLK
tIS
Cmd &
Add.
Valid
Data
tDQSCK
tIH
VREF
tRPST
tRPRE
DQS
tDQSQ
tDV
tAC
DQ
Write Operation / tDQSS=max.
/CLK
CLK
tDQSS
DQS
tWPST
tDSS
tWPRES
tDQSH
tDQSL
tWPRE
tDS
tDH
DQ
Write Operation / tDQSS=min.
/CLK
CLK
DQS
tDSH
tDQSS
tWPST
tWPRES
tWPRE
tDQSL
tDS
tDQSH
tDH
DQ
MIT-DS-0412-0.1
MITSUBISHI ELECTRIC
21.Mar.2001
21
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
OPERATIONAL DESCRIPTION
BANK ACTIVATE
The DDR SDRAM has four independent banks. Each bank is activated by the ACT command
with the bank addresses (BA0,1). A row is indicated by the row address A12-0. The minimum
activation interval between one bank and the other bank is tRRD. M aximum 2 ACT commands
are allowed within tRC,although the number of banks which are active concurrently is not limited.
PRECHARGE
The PRE command deactivates the bank indicated by BA0,1. When multiple banks are active,
the precharge all command (PREA,PRE+A10=H) is available to deactivate them at the same
time. After tRP from the precharge, an ACT command to the same bank can be issued.
Bank Activation and Precharge All (BL=8, CL=2 (Discrete level))
Module input and output timing.
/CLK
CLK
2 ACT command / tRCmin
Command
ACT
tRRD
A0-9,11-12
Xa
tRCmin
ACT READ
PRE
tRAS
Xb
tRP
Xb
Y
tRCD
ACT
BL/2
A10
Xa
Xb
0
BA0,1
00
01
00
Xb
1
01
DQS
DQ
Qa0 Qa1
Qa2 Qa3 Qa4 Qa5 Qa6 Qa7
Precharge all
A precharge command can be issued at BL/2(Discrete) from a read command without data loss.
MIT-DS-0412-0.1
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21.Mar.2001
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
READ
After tRCD from the bank activation, a READ command can be issued. 1st Output data is
available after the /CAS Latency from the READ, followed by (BL-1) consecutive data when the
Burst Length is BL. The start address is specified by A11,A9-A0, and the address sequence of burst data
is defined by the Burst Type. A READ command may be applied to any active bank, so the row
precharge time (tRP) can be hidden behind continuous output data by interleaving the
multiple banks. When A10 is high at a READ command, the auto-precharge(READA) is
performed. Any command(READ,WRITE,PRE,ACT) to the same bank is inhibited till the internal
precharge is complete. The internal precharge starts at BL/2(Discrete, In case of module, BL/2+1) after
READA. The next ACT command can be issued after (BL/2+tRP) from the previous READA.
Multi Bank Interleaving READ (BL=8, CL=2(Discrete level))
Module input and output timing.
/CLK
CLK
Command
ACT
A0-9,11-12
Xa
Y
Xb
Y
A10
Xa
0
Xb
0
0
BA0,1
00
00
10
10
00
READ ACT
READ PRE
tRCD
DQS
DQ
Qa0 Qa1 Qa2 Qa3
Qa4 Qa5 Qa6 Qa7 Qb0 Qb1
Qb2 Qb3 Qb4 Qb5 Qb7
Burst Length
Module /CAS latency (Discrete CL + 1)
MIT-DS-0412-0.1
MITSUBISHI ELECTRIC
21.Mar.2001
23
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
READ with Auto-Precharge (BL=8, CL=2(Discrete))
Module input and output timing.
/CLK
CLK
BL/2 + tRP
Command
ACT
READ
ACT
BL/2
tRCD
tRP
A0-9,11-12
Xa
Y
Xb
A10
Xa
1
Xb
BA0,1
00
00
00
DQS
Qa0 Qa1 Qa2 Qa3
DQ
Qa4 Qa5 Qa6 Qa7
Internal precharge start
(BL/2+1 in case of Module)
Module input and output timing.
READ Auto-Precharge Timing (BL=8)
/CLK
CLK
Command
ACT
READ
BL/2
Module
Discrete
CL=3.5
CL=2.5 DQ
CL=3
CL=2
DQ
Qa0 Qa1 Qa2
Qa3 Qa4 Qa5 Qa6 Qa7
Qa0 Qa1 Qa2 Qa3 Qa4
Qa5 Qa6 Qa7
Internal Precharge Start Timing
(In case of module, Precharge start at BL/2+1)
MIT-DS-0412-0.1
MITSUBISHI ELECTRIC
21.Mar.2001
24
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
WRITE
After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set from the
WRITE command with data strobe input, following (BL-1) data are written into RAM , when the Burst
Length is BL. The start address is specified by A11,A9-A0, and the address sequence of burst data is
defined by the Burst Type. A WRITE command may be applied to any active bank, so the row precharge
time (tRP) can be hidden behind continuous input data by interleaving the multiple banks. From the last
data to the PRE command, the write recovery time (tWRP) is required. When A10 is high at a WRITE
command, the auto-precharge(WRITEA) is performed. Any command(READ,WRITE,PRE,ACT) to the
same bank is inhibited till the internal precharge is complete. The next ACT command can be issued after
tDAL from the last input data cycle.
Module input and output timing. Multi
Bank Interleaving WRITE (BL=8)
/CLK
CLK
Command
WRITE
ACT
WRITE ACT
tRCD
Xa
Ya
Xb
Yb
A10
Xa
Xa
0
Xb
BA0,1
00
00
10
A0-9,11-12
PRE
PRE
0
0
0
10
00
10
tRCD
DQS
Da0 Da1 Da2 Da3 Da4 Da5
DQ
Module input and output timing.WRITE with
/CLK
CLK
Command
ACT
Da6 Da7 Db0 Db1 Db2 Db3
Db4 Db5 Db6 Db7
Auto-Precharge (BL=8)
WRITE
ACT
tRCD
tDAL
Xa
Y
Xb
A10
Xa
1
Xb
BA0,1
00
00
00
A0-9,11-12
DQS
DQ
Da0 Da1 Da2 Da3 Da4 Da5
Da6 Da7
MIT-DS-0412-0.1
MITSUBISHI ELECTRIC
21.Mar.2001
25
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
BURST INTERRUPTION
[Read Interrupted by Read]
Burst read operation can be interrupted by new read of any bank. Random column access is allowed.
READ to READ interval is minimum 1CLK.
Module input and output timing.
/CLK
CLK
Command
READ READ
A0-9,11
A10
BA0,1
Read Interrupted by Read (BL=8, CL=2(Discrete))
READ
READ
Yi
Yj
Yk
Yl
0
0
0
0
00
00
10
01
DQS
Qai0 Qai1 Qaj0 Qaj1 Qaj2 Qaj3 Q a k 0 Q a k 1 Q a k 2 Q a k 3 Q a k 4 Q a k 5Qal0 Qal1 Qal2 Qal3 Qal4 Qal5 Qal6 Qal7
DQ
[Read Interrupted by precharge]
Burst read operation can be interrupted by precharge of the same bank. READ to PRE interval is
minimum 1 CLK. A PRE command to output disable latency is equivalent to the /CAS Latency. As
a result, READ to PRE interval determines valid data length to be output. The figure below shows
examples of BL=8.
Module input and output timing.
/CLK
CLK
Command
Read Interrupted by Precharge (BL=8)
READ
PRE
DQS
Module
CL=3.5
Discrete
CL=2.5
DQ
Command
READ
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Q0
Q1
Q4 Q5
PRE
DQS
DQ
Command
READ PRE
DQS
DQ
MIT-DS-0412-0.1
MITSUBISHI ELECTRIC
21.Mar.2001
26
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
Module input and output timing.
Read Interrupted by Precharge (BL=8)
/CLK
CLK
Command
READ
PRE
DQS
Module
CL=3.0
Discrete
CL=2.0
DQ
Command
READ
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Q0
Q1
Q4
Q5
PRE
DQS
DQ
Command
READ PRE
DQS
DQ
MIT-DS-0412-0.1
MITSUBISHI ELECTRIC
21.Mar.2001
27
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
[Read Interrupted by Burst Stop]
Burst read operation can be interrupted by a burst stop command(TERM ). READ to TERM
interval is minimum 1 CLK. A TERM command to output disable latency is equivalent to the /CAS
Latency. As a result, READ to TERM interval determines valid data length to be output. The figure
below shows examples of BL=8.
Module input and output timing.
/CLK
CLK
Command
Read Interrupted by TERM (BL=8)
READ
TERM
DQS
Module
CL=3.5
Discrete
CL=2.5
DQ
Command
READ
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Q4
Q5
TERM
DQS
DQ
Command
READ TERM
DQS
Q0
Q1
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Q0
Q1
DQ
Command
READ
TERM
DQS
Module
CL=3.0
Discrete
CL=2.0
DQ
Command
READ
Q4
Q5
TERM
DQS
DQ
Command
READ TERM
DQS
DQ
MIT-DS-0412-0.1
MITSUBISHI ELECTRIC
21.Mar.2001
28
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
[Read Interrupted by Write with TERM]
Module input and output timing.
Module
CL=3.5
Discrete
CL=2.5
Read Interrupted by TERM (BL=8)
/CLK
CLK
Command
READ
TERM
WRITE
DQS
Q0
DQ
Module
CL=3.0
Discrete
CL=2.0
Command
READ
TERM
Q1
Q2
Q3
D0
D1
D2
D3
D2
D3
D4
D5
WRITE
DQS
DQ
Q0
Q1
MIT-DS-0412-0.1
MITSUBISHI ELECTRIC
Q2
Q3
D0
D1
21.Mar.2001
29
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
[Write interrupted by Write]
Burst write operation can be interrupted by write of any bank. Random column access is
allowed. WRITE to WRITE interval is minimum 1 CLK.
Write Interrupted by Write (BL=8)
Module input and output timing.
/CLK
CLK
Command
A0-9,11
A10
BA0,1
WRITE WRITE
WRITE
WRITE
Yi
Yj
Yk
Yl
0
0
0
0
00
00
10
00
DQS
DQ
Dai0
Dai1 Daj0 Daj1 Daj2 Daj3 D a k 0 D a k 1 D a k 2 D a k 3 D a k 4 D a k 5 Dal0
MIT-DS-0412-0.1
MITSUBISHI ELECTRIC
Dal1 Dal2 Dal3 Dal4 Dal5
Dal6 Dal7
21.Mar.2001
30
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
[Initialize and Mode Register sets]
/CLK
CLK
Command
NOP
PRE
A0-9,11,12
A10
1
BA0,1
EMRS
MRS
Code
Code
Code
Code
10
00
PRE
AR
AR
1
MRS
ACT
Code
Xa
Code
Xa
00
Xa
DQS
DQ
tMRD
tMRD
tRP
tRFC
tRFC
tMRD
[AUTO REFRESH]
Single cycle of auto-refresh is initiated with a REFA(/CS=/RAS=/CAS=L,/WE=CKE=H) command. The
refresh address is generated internally. 8192 REFA cycles within 64ms refresh 256M bits memory cells.
The auto-refresh is performed on 4 banks concurrently. Before performing an auto refresh, all banks must
be in the idle state. Auto-refresh to auto-refresh interval is minimum tRFC . Any command must not be
supplied to the device before tRFC from the REFA command.
Auto-Refresh
/CLK
CLK
/CS
NOP or DESELECT
/RAS
/CAS
/WE
CKE
tRFC
A0-12
BA0,1
Auto Refresh on All Banks
Auto Refresh on All Banks
MIT-DS-0412-0.1
MITSUBISHI ELECTRIC
21.Mar.2001
31
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
[S ELF REFRESH]
Self -refresh mode is entered by issuing a REFS command (/CS=/RAS=/CAS=L,/WE=H,CKE=L). Once
the self-refresh is initiated, it is maintained as long as CKE is kept low. During the self-refresh mode, CKE
is asynchronous and the only enable input, all other inputs including CLK are disabled and ignored, so that
power consumption due to synchronous inputs is saved. To exit the self-refresh, supplying stable CLK
inputs, asserting DESEL or NOP command and then asserting CKE for longer than tXSNR/tXSRD.
Self-Refresh
/CLK
CLK
/CS
/RAS
/CAS
/WE
CKE
A0-12
BA0,1
X
Y
X
Y
tXSRD
tXSNR
Self Refresh Exit
Act
MIT-DS-0412-0.1
MITSUBISHI ELECTRIC
Read
21.Mar.2001
32
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
[Asynchronous S ELF REFRESH]
Asynchronous Self -refresh mode is entered by CKE=L within 2 tCLK after issuing a REFA command
(/CS=/RAS=/CAS=L,/WE=H). Once the self-refresh is initiated, it is maintained as long as CKE is kept
low. During the self-refresh mode, CKE is asynchronous and the only enable input, all other inputs
including CLK are disabled and ignored, so that power consumption due to synchronous inputs is saved.
To exit the self-refresh, supplying stable CLK inputs, asserting DESEL or NOP command and then
asserting CKE for longer than tXSNR/tXSRD.
Asynchronous Self-Refresh
/CLK
CLK
/CS
/RAS
/CAS
/WE
CKE
max 2 tCLK
A0-12
BA0,1
tXSNR
Self Refresh Exit
MIT-DS-0412-0.1
MITSUBISHI ELECTRIC
Act
21.Mar.2001
33
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
[Power DOWN]
The purpose of CLK suspend is power down. CKE is synchronous input except during the self-refresh
mode. A command at cycle is ignored. From CKE=H to normal function, DLL recovery time is NOT
required in the condition of the stable CLK operation during the power down mode.
Power Down by CKE
/CLK
CLK
Standby Power
Down
CKE
Command
PRE
Valid
tXPNR/
tXPRD
Active Power
Down
CKE
Command
NOP
NOP
ACT
NOP
NOP
MIT-DS-0412-0.1
MITSUBISHI ELECTRIC
Valid
21.Mar.2001
34
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
Serial Presence Detect Table I
Byte
Function described
0
Number of Serial PD Bytes Written during Production
SPD enrty data
SPD DATA(hex)
128
80
256 Bytes
08
1
Total # bytes of SPD memory device
2
Fundamental memory type
3
# Row Addresses on this assembly
4
# Column Addresses on this assembly
5
# Module Banks on this assembly
2BANK
02
6
Data Width of this assembly...
x72
48
7
... Data Width continuation
0
00
8
Voltage interface standard of this assembly
SSTL2.5V
04
7.5ns
75
-10
8.0ns
80
-75
+0.75ns
75
-10
+0.8 ns
80
DIMM Configuration type (Non-parity,Parity,ECC)
ECC
02
Refresh Rate/Type
7.8uS/SR
82
x4
04
x4
04
9
SDRAM DDR
SDRAM Cycletime at Max. Supported CAS Latency (CL).
Cycle time for CL=2.5
10
SDRAM Access from Clock
tAC for CL=2.5
11
12
13
SDRAM width,Primary DRAM
14
Error Checking SDRAM data width
15
16
17
-75
MIimum Clock Delay, Random Column Access
Burst Lengths Supported
Number of Device Banks
07
13
0D
11
0B
1 clock
01
2, 4, 8
0E
4bank
04
18
CAS# Latency
2.0, 2.5
0C
19
CS# Latency
0
01
WE Latency
1
02
20
21
SDRAM Module Attributes
22
SDRAM Device Attributes:General
23
Registered with PLL
Differential Clock
VDD + 0.2V
SDRAM Cycle time(2nd highest CAS latency)
Cycle time for CL=2
24
25
26
27
SDRAM Access form Clock(2nd highest CAS latency)
tAC for CL=2
26
00
-75
10ns
A0
-10
10ns
A0
-75
+0.75ns
75
-10
+0.8ns
80
-75
N/A
00
-10
N/A
00
-75
N/A
00
-10
N/A
00
SDRAM Cycle time(3rd highest CAS latency)
SDRAM Access form Clock(3rd highest CAS latency)
Minimum Row Precharge Time (tRP)
20ns
50
28
Minimum Row Active to Row Active Delay (tRRD)
15ns
3C
29
RAS to CAS Delay Minv (tRCD)
30
Active to Precharge Min (tRAS)
20ns
50
-75
45ns
2D
-10
50ns
32
MIT-DS-0412-0.1
MITSUBISHI ELECTRIC
21.Mar.2001
35
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
Serial Presence Detect Table II
31
32
33
34
35
Density of each bank on module
512MByte
Command and Address signal input setup time
Command and Address signal input hold time
Data signal input setup time
Data signal input hold time
36-61
Superset Information (may be used in future)
62
SPD Revision
63
Checksum for bytes 0-62
64-71
90
-10
1.1nS
B0
-75
0.9nS
90
-10
1.1nS
B0
-75
0.5nS
50
-10
0.6nS
60
-75
0.5nS
50
-10
0.6nS
60
option
00
00
Check sum for -75
11
Check sum for -10
97
MITSUBISHI
1CFFFFFFFFFFFFFF
Manufacturing location
Manufacture location
XX
Manufactures Part Number
MH64D72KLG-75
4D4832384437324B4C472D37352020202020
MH64D72KLG-10
4D4832384437324B4C472D31302020202020
72
73-90
0.9nS
0
Manufactures Jedec ID code per JEP-108E
80
-75
91-92
Revision Code
PCB revision
rrrr
93-94
Manufacturing date
year/week code
yyww
serial number
ssssssss
Undefined
00
Undefined
00
95-98
Assembly Serial Number
99-127
128-255
Reserved
Open for Customer Use
MIT-DS-0412-0.1
MITSUBISHI ELECTRIC
21.Mar.2001
36
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
EEPROM Components A.C. and D.C. Characteristics
Symbol
VCC
VSS
VIH
Parameter
Supply Voltage
Supply Voltage
VIL
Input High Voltage
Input Low Voltage
VOL
Output Low Voltage
Limits
Typ.
Min.
2.2
0
Vccx0.7
-1
0
Max.
5.5
Units
0
Vcc+0.5
Vccx0.3
V
V
V
V
0.4
V
EEPROM A.C.Timing Parameters (Ta=0 to 70°C )
Symbol
Limits
Min.
Max.
100
Parameter
SCL Clock Frequency
fSCL
TI
TAA
200
3.5
Noise Supression Time Constant at SCL, SDA inputs
SCL Low to SDA Data Out Valid
TBUF
Time the Bus Must Be Free before a New
Transmission Can Start
Units
KHz
ns
us
4.7
us
THD:STA
Start Condition Hold Time
4.0
us
TLOW
Clock Low Time
4.7
us
THIGH
Clock High Time
4.0
us
TSU:STA
Start Condition Setup Time
4.7
us
us
THD:DAT
Data In Hold Time
0
TSU:DAT
Data In Setup Time
250
TR
SDA and SCL Rise Time
1
us
TF
SDA and SCL Fall Time
300
ns
TSU:STO
Stop Condition Setup Time
4.0
us
TDH
Data Out Hold Time
100
ns
TWR
Write Cycle Time
ns
10
ms
tWR is the time from a valid stop condition of a write sequence to the end of the EEPROM internal erase/program cycle.
TF
T HIGH
TR
T LOW
SCL
T SU:STO
T SU:STA
T HD:DAT
T HD:STA
T SU:DAT
SDA
IN
T AA
T DH
T BUF
SDA
OUT
MIT-DS-0412-0.1
MITSUBISHI ELECTRIC
21.Mar.2001
37
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
133.35
2 - 2.50
6.35Max
1.27+ 0.10
MIT-DS-0412-0.1
MITSUBISHI ELECTRIC
21.Mar.2001
38
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH28D72KLG-75,-10
9,663,676,416-BIT (134,217,728-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products
better and more reliable, but there is always the possibility that trouble may occur with them.
Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with
appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1.These materials are intended as a reference to assist our customers in the selection of the
Mitsubishi semiconductor product best suited to the customer's application; they do not
convey any license under any intellectual property rights, or any other rights, belonging to
Mitsubishi Electric Corporation or a third party.
2.Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement
of any third-party's rights, originating in the use of any product data, diagrams, charts,
programs, algorithms, or circuit application examples contained in these materials.
3.All information contained in these materials, including product data, diagrams, charts,
programs and algorithms represents information on products at the time of publication of
these materials, and are subject to change by Mitsubishi Electric Corporation without notice
due to product improvements or other reasons. It is therefore recommended that customers
contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for the latest product information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other
loss rising from these inaccuracies or errors.
Please also pay attention to information published by Mitsubishi Electric Corporation by
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(http://www.mitsubishichips.com).
4.When using any or all of the information contained in these materials, including product
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Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other
loss resulting from the information contained herein.
5.Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in
a device or system that is used under circumstances in which human life is potentially at stake.
Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor when considering the use of a product contained herein for any specific
purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace,
nuclear, or undersea repeater use.
6.The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or
reproduce in whole or in part these materials.
7.If these products or technologies are subject to the Japanese export control restrictions, they
must be exported under a license from the Japanese government and cannot be imported
into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or
the country of destination is prohibited.
8.Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor for further details on these materials or the products contained therein.
MIT-DS-0412-0.1
MITSUBISHI ELECTRIC
21.Mar.2001
39
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