FEDL22Q553-02 Issue Date: Apr. 25, 2013 ML22Q553-NNNMB/ML22Q553-xxxMB 4-Channel Mixing Speech Synthesis LSI with Built-in FLASH ROM for Automotive GENERAL DESCRIPTION The ML22Q553-NNN and ML22Q553-xxx are 4-channel mixing speech synthesis LSIs with built-in FLASH ROM for voice data. These LSIs incorporate into them an HQ-ADPCM decoder that enables high sound quality, 16-bit D/A converter, low-pass filter, 1.0 W monaural speaker amplifier for driving speakers , and over-current detectible function for Speaker Pins. Since functions necessary for voice output are all integrated into a single chip, a system can be upgraded with audio features by only using one of these LSIs. • Capacity of internal memory and the maximum voice production time (when HQ-ADPCM※1 method used) Product name ML22Q553-NNN/-xxx ROM capacity 4 Mbits Maximum voice production time (sec) fsam = 8.0 kHz fsam = 16.0 kHz fsam = 32.0 kHz 161 80 40 FEATURES • Speech synthesis method: Can be specified for each phrase. HQ-ADPCM / 8-bit non-linear PCM / 8-bit PCM / 16-bit PCM • Sampling frequency: Can be specified for each phrase. 12.0/24.0/48.0 kHz, 8.0/16.0/32.0 kHz, 6.4/12.8/25.6 kHz • Built-in low-pass filter and 16-bit D/A converter • Built-in speaker driver amplifier: 1.0 W, 8Ω (at DVDD = 5 V) (with over-current detectible function for Speaker pins) • External analog voice input (built-in analog mixing function) • CPU command interface: Clock synchronous serial interface • Maximum number of phrases: 1024 phrases, from 000h to 3FFh • Edit ROM • Volume control: CVOL command: Adjustable through 32 levels (including OFF) AVOL command: Adjustable through 50 levels (including OFF) • Repeat function: LOOP command • Channeｌ mixing function: 4 channels • Power supply voltage detection function: Can be controlled at six levels from 2.7 to 4.0 V (including the OFF setting) • Source oscillation frequency: 4.096 MHz • Power supply voltage: 4.5 to 5.5 V • Operating temperature range: –40°C to +105°C※2 • Package: heat sink type 30-pin plastic SSOP(P-SSOP30-56-0.65-Z6K) •Product name: ML22Q553-NNNMB/ML22Q553-xxxMB (“xxx” denotes ROM code number) ※1 HQ-ADPCM is a high sound quality audio compression technology of "Ky's". “Ｋｙ’ｓ” is a Registered trademark of National Universities corporate Kyushu Institute of Technology ※2 The limitation on the operation time changes by the using condition. (Refer to Page66) 1/69 FEDL22Q553-02 ML22Q553 The table below summarizes the differences between the exsisting speech synthesis LSIs (ML225XG and ML22Q573) and the ML22Q553. Item CPU interface ROM type ROM capacity Playback method Maximum number of phrases ML225XG Parallel/Serial MASK 3/4/6 Mbits 2-bit ADPCM2 4-bit ADPCM2 8-bit straight PCM 8-bit non-linear PCM 16-bit straight PCM ML22Q573 Serial FLASH 4 Mbits ML22Q553 ← ← ← HQ-ADPCM 8-bit straight PCM 8-bit non-linear PCM 16-bit straight PCM ← 1024 ← 6.4/8.0/12.0/ 12.8/16.0/24.0/ 25.6/32.0/48.0 ← ← ← 16-bit voltage-type FIR interpolation filter (High-pass interpolation) Built-in 1.0 W (8Ω, DVDD = 5 V) ← No ← Yes 2-channel 4-channel ← Yes 29 levels 20 to 1024 ms (4 ms steps) Yes ← 32 levels ← ← ← ← ← ← No Yes ← Yes No ← No ← ← 2.7 V to 5.5 V ← 4.5 V to 5.5 V −40°C to +105°C ← ← 44-pin QFP 30-pin SSOP ← 256 D/A converter 4.0/5.3/6.4/8.0/ 10.7/12.0/12.8/ 16.0/21.3/24.0/ 25.6/32.0/48.0 4.096 MHz (has a crystal oscillator circuit built-in) 14-bit voltage-type Low-pass filter FIR interpolation filter Speaker driving amplifier No Sampling frequency (kHz) Clock frequency Over-current detectible function for Speaker Pins Simultaneous sound production function (mixing function) Edit ROM Volume control Silence insertion Repeat function External analog input External speech data input Interval at which a seam is silent during continuous playback Power supply voltage Ambient temperature Package ← ← 2/69 FEDL22Q553-02 ML22Q553 BLOCK DIAGRAM TESTI0 TESTI1 TESTI2 TESTI3 TESTI4 TESTO The block diagrams of the ML22Q553-NNN/ML22Q553-xxx are shown below. DVDD DGND VDDL VDDR RESETB CSB SCK SI SO CBUSYB STATUS ERR DIPH TESTI1 Cmd Analyzer JTAG Interface Address Controller 4Mbit FLASH PCM Synthesizer I/O Timing Controller LPF(CVOL) Interface 16bit DAC PLL OSC VPP SP-AMP (AVOL) SPVDD SPGND XT XTB SPM SPP AIN SG Block Diagram of ML22Q553-NNN/ML22Q553-xxx 3/69 FEDL22Q553-02 ML22Q553 PIN CONFIGURATION (TOP VIEW) ● ML22Q553-NNN/ML22Q553-xxx AIN SG V DDR DV DD DGND VDDL DIPH STATUS ERR CSB SCK SI SO CBUSYB DGND 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30-Pin Plastic SSOP SPVDD SPGND SPP SPM TESTO TESTI4 TESTI3 TESTI2 TESTI1 TESTI0 RESETB VPP DVDD XT XTB NC：Unused pin 4/69 FEDL22Q553-02 ML22Q553 PIN DESCRIPTION (1) Pin Symbol 1 AIN 2 SG 3 VDDR 4,18 DVDD 5,15 DGND 6 VDDL 7 DIPH 8 STATUS 9 ERR 10 CSB 11 SCK 12 SI 13 SO I/O Attribute I — Description Speaker amplifier input pin. Built-in speaker amplifier’s reference voltage output pin. O — Connect a capacitor of 0.1 μF or more between this pin and DGND. 2.5 V regulator output pin. O — Acts as an internal power supply (for ROM). Connect a capacitor of 10 μF or more between this pin and DGND. Digital power supply pin. — — Connect a bypass capacitor of 10μF or more between this pin and DGND. — — Digital ground pin 2.5 V regulator output pin. O — Acts as an internal power supply (for logic). Connect a capacitor of 10 μF or more between this pin and DGND. Serial interface switching pin. Pin for choosing between rising edges and falling edges as to the edges of the SCK pulses used for shifting serial data input to the SI pin into the inside of the LSI. When this pin is at a “L” level, SI input data is shifted into the LSI on the rising edges of the SCK clock pulses and a status I Positive signal is output from the SO pin on the falling edges of the SCK clock pulses. When this pin is at a “H” level, SI input data is shifted into the LSI on the falling edges of the SCK clock pulses and a status signal is output from the SO pin on the rising edges of the SCK clock pulses. Channel status output pin. O Positive Outputs the BUSYB or NCR signal for each channel by inputting the OUTSTAT command. Error output pin. O Positive Outputs a “H” level if an error occurs. Chip select pin. A “L” level on this pin accepts the SCK or SI inputs. When I Negative this pin is at a “H” level, neither the SCK nor SI signal is input to the LSI. I Positive Synchronous serial clock input pin. Synchronous serial data input pin. When the DIPH pin is at a “L” level, data is shifted in on the I — rising edges of the SCK clock pulses. When the DIPH pin is at a “H” level, data is shifted in on the falling edges of the SCK clock pulses. Channel status serial output pin. Outputs a status signal on the falling edges of the SCK clock pulses when the DIPH pin is at a ”L” level; outputs a status signal on the rising edges of the SCK clock pulses when the O Positive DIPH pin is at a ”H” level. When the CSB pin is at a ”L” level, the status of each channel is output serially in sync with the SCK clock. When the CSB pin is at a ”H” level, this pin goes into a high impedance state. analog Initial value 0 analog 0 analog 0 power — gnd — power 0 digital 0 digital 1 digital 0 digital 1 clk 0 digital 0 digital Hi-Z Attribute 5/69 FEDL22Q553-02 ML22Q553 PIN DESCRIPTION (2) Pin Symbol I/O Attribute Description 14 CBUSYB O Negative 16 XTB O Negative 17 XT I Positive 19 VPP I — 20 RESETB I Negative 21 TESTI0 (MODE) I Positive 22 TESTI1 (nTRST) I Negative Command processing status signal output pin. This pin outputs a “L” level during command processing. Be sure to enter commands with the CBUSYB pin driven at a “H” level. Connects to a crystal or a ceramic resonator. When using an external clock, leave this pin open. If a crystal or a ceramic resonator is used, connect it as close to the LSI as possible. Connects to a crystal or a ceramic resonator. A feedback resistor of around 1 MΩ is built in between this XT pin and the XTB pin. When using an external clock, input the clock from this pin. If a crystal or a ceramic resonator is used, connect it as close to the LSI as possible. Pin for FLASH analysis. Should be connected to DGND. Reset input pin. At “L” level input, the LSI enters the initial state. After a reset input, the entire circuit is stopped and enters a power down state. Upon power-on, input a “L” level to this pin. After the power supply voltage is stabilized, drive this pin at a “H” level. This pin has a pull-up resistor built in. Input pin for testing. Also acts as a Flash rewrite enable pin. Has a pull-down resistor built in. Used as either an input pin for testing or a reset input pin for Flash rewriting. Has a pull-down resistor built in. 23 TESTI2 (TMS) I Positive Used as either an input pin for testing or a state transition pin for Flash rewriting. Has a pull-up resistor built in. I Positive I Positive O Positive O — 27 TESTI3 (TDI) TESTI4 (TCK) TESTO (TSO) SPM 28 SPP O — 29 SPGND — — 30 SPVDD — — 24 25 26 Used as either an input pin for testing or a data input pin for Flash rewriting. Has a pull-up resistor built in. Used as either an input pin for testing or a clock input pin for Flash rewriting. Has a pull-up resistor built in. Used as either an output pin for testing or a data output pin for Flash rewriting. Output pin of the built-in speaker amplifier. Output pin of the built-in speaker amplifier. Can be configured as an AOUT amplifier output by command setting. Speaker amplifier ground pin. Speaker amplifier power supply pin. Connect a bypass capacitor of 10μF or more between this pin and SPGND. Attribute digital Initial (*1) value 0 (*1) clk 1 clk 0 analog 0 digital 0 (*1) digital 0 digital 0 digital 1 digital 1 digital 0 digital Hi-Z analog Hi-Z analog 0 gnd — power — *1: Indicates the initial value at reset input or during power down. 6/69 FEDL22Q553-02 ML22Q553 ABSOLUTE MAXIMUM RATINGS Parameter Power supply voltage Input voltage Symbol DVDD SPVDD VIN Power dissipation PD Output short-circuit current IOS Storage temperature TSTG Condition DGND = SPGND = 0 V, Ta = 25°C Rating Unit — −0.3 to +7.0 V — When the LSI is mounted on JEDEC 4-layer board. When SPVDD = 5V Applies to all pins except SPM, SPP, VDDL, and VDDR. Applies to SPM and SPP pins. Applies to VDDL and VDDR pins. — −0.3 to DVDD+0.3 V 1000 mW 10 mA 500 50 −55 to +150 mA mA °C RECOMMENDED OPERATING CONDITIONS Parameter Symbol Condition DVDD, SPVDD Power supply voltage DVDD SPVDD — Operating temperature Top — Master clock frequency DGND = SPGND = 0 V Range Unit 4.5 to 5.5 Min. 3.5 V −40 to +105 Typ. Max. 4.096 4.5 °C fOSC — MHz Parameter Symbol Condition Range Operating temperature TOP At write/erase 0 to +70 °C At read −40 to +105 °C Maximum rewrite count CEP ― 10 times Data retention period YDR ― 10 years FLASH CONDITIONS DGND = SPGND = 0 V Unit 7/69 FEDL22Q553-02 ML22Q553 ELECTRICAL CHARACTERISTICS DC Characteristics Parameter “H” input voltage “L” input voltage “H” output voltage 1 “H” output voltage 2 (*1) “L” output voltage 1 Output leakage current(*2) “L” output voltage 2 (*1) “H” input current 1 “H” input current 2 (*3) “H” input current 3 (*4) “L” input current 1 “L” input current 2 (*3) “L” input current 3 (*5) Symbol VIH VIL VOH1 VOH2 VOL1 IOOH IOOL VOL2 IIH1 IIH2 IIH3 IIL1 IIL2 IIL3 Supply current during playback 1 IDD1 Supply current during playback 3 IDD3 Power-down supply current (*6) IDDS1 DVDD = SPVDD = 4.5 to 5.5 V, DGND = SPGND = 0 V, Ta = −40 to +105°C Condition Min. Typ. Max. Unit — 0.8×DVDD — DVDD V — 0 — 0.2×DVDD V IOH = −1 mA DVDD−0.4 — — V IOH = −50 µA DVDD−0.4 — — V IOL = 2 mA — — 0.4 V VOH = DVDD (CSB=“H”) — — 10 µA VOL = DGND (CSB=“H”) IOL = 50 µA VIH = DVDD VIH = DVDD VIH = DVDD VIL = DGND VIL = DGND VIL = DGND fOSC = 4.096 MHz fs=48kHz, f=1kHz, When 16bitPCM Playback No output load fOSC = 4.096 MHz During silence playback No output load Ta = −40 to +55°C Ta = −40 to +105°C −10 — — 0.8 20 –10 –20 –400 — — — 5 100 — −5.0 –100 — 0.4 10 20 400 — −0.8 –20 µA V µA µA µA µA µA µA — — 55 mA — — 48 mA — — — — 50 100 µA µA *1: Applies to the XTB pin. *2: Applies to the SO and TESTO pins. *3: Applies to the XT pin. *4: Applies to the TESTI0 and TESTI1 pins. *5: Applies to the RESETB, TEST2, TEST3 and TEST4 pins. *6: Applies to the ML22Q553. 8/69 FEDL22Q553-02 ML22Q553 Analog Section Characteristics Parameter AIN input resistance Symbol RAIN AIN input voltage range VAIN Line output resistance LINE output load resistance LINE output voltage range RLA SG output voltage SG output resistance SPM, SPP output load resistance Speaker amplifier output power Output offset voltage between SPM and SPP with no signal present Regulator output voltage DVDD = SPVDD = 4.5 to 5.5 V, DGND = SPGND = 0 V, Ta = −40 to +105°C Condition Min. Typ. Max. Unit Input gain: 0 dB 10 20 30 kΩ SPVDD× Vp-p — — 2/3 At 1/2SPVDD output — — 100 Ω RLA At SPGND10kΩ load 10 — — kΩ VAO At SPGND10kΩ load SPVDD /6 — SPVDD× 5/6 V VSG — RSG — SPVDD /2 57 RLSP — PSPO 0.95x SPVDD /2 1.05x V 96 SPVDD /2 135 kΩ 6 8 — Ω SPVDD = 5.0V, f = 1 kHz RSPO = 8Ω, THD≦ 10% 800 1000 — mW VOF SPIN–SPM gain = 0 dB With a load of 8Ω −50 — +50 mV VDDL VDDR Output load current = −35 mA 2.25 2.5 2.75 V 9/69 FEDL22Q553-02 ML22Q553 AC Characteristics (1) Parameter Master clock duty cycle RESETB input pulse width Reset noise rejection pulse width Noise rejection pulse width Command input interval time1 Command input interval time2 Command input enable time At PUP command input CBUSYB “L” level output time At AMODE command input CBUSYB “L” level output time（*3） At AMODE command input CBUSYB “L” level output time At AMODE command input CBUSYB “L” level output time At PDWN command input CBUSYB “L” level output time DVDD = SPVDD = 4.5 to 5.5 V, DGND = SPGND = 0 V, Ta = −40 to +105°C Symbol Condition Min. Typ. Max. Unit fduty — 40 50 60 % tRST — 10 — — μs tNRST RESETB pin — — 0.1 μs tNINP CSB, SCK, and SI pins — — 5 ns fOSC = 4.096 MHz At STOP/SLOOP/CLOOP/ 10 — — μs tINT VOL command input After status read fOSC = 4.096 MHz After input first command at 0 — — μs tINTC two-time command input mode fOSC = 4.096 MHz During continuous playback — — 10 ms tcm At SLOOP input 4.096 MHz tPUP — — 4 ms At external clock input 4.096 MHz At external clock input 39 41 43 ms tPUPA1 POP = “0” DAEN = “0”→”1” or SPEN = “0”→”1” 4.096 MHz At external clock input 72 74 76 ms tPUPA2 POP = “1” DAEN = “0”→”1” (SPEN = “0”) 4.096 MHz At external clock input 32 34 36 ms tPUPA3 POP = “0” DAEN = “0”→”1” (SPEN = “0”) tPD At AMODE command input CBUSYB “L” level output time（*3） tPDA1 At AMODE command input CBUSYB “L” level output time tPDA2 At AMODE command input CBUSYB “L” level output time tPDA3 fOSC = 4.096 MHz 4.096 MHz At external clock input POP = “0” DAEN = “1”→”0” or SPEN = “1”→”0” 4.096 MHz At external clock input POP = “1” DAEN = “1”→”0” (SPEN = “0”) 4.096 MHz At external clock input POP = “0” DAEN = “1”→”0” (SPEN = “0”) — — 10 μs 106 108 110 ms 143 145 147 ms 103 105 107 ms 10/69 FEDL22Q553-02 ML22Q553 CBUSYB “L” level output time 1 (*1) CBUSYB “L” level output time 2 (*2) CBUSYB “L” level output time 3 (*4) tCB1 tCB2 tCB3 fOSC = 4.096 MHz fOSC = 4.096 MHz fOSC = 4.096 MHz — — — — — — 10 2 200 μs ms μs Note: Output pin load capacitance = 45 pF (Max.) *1: Applies to cases where a command is input, except after the PUP, PDWN, PLAY, START or AMODE command input. *2: Applies to cases where the PLAY or START command is input. *3: When FAD3-0 is initial value (8h) *4: Applies to cases where the STOP command is input. 11/69 FEDL22Q553-02 ML22Q553 AC Characteristics (2) DVDD = SPVDD = 4.5 to 5.5 V, DGND = SPGND = 0 V, Ta = −40 to +105°C Parameter Symbol Condition Min. Typ. Max. Unit SCK input enable time from CSB fall tESCK — 100 — — ns SCK hold time from CSB rise tCSH — 100 — — ns Data floating time from CSB rise tDOZ RL = 3 kΩ — — 100 ns Data setup time from SCK rise tDIS1 DIPH = “L” 50 — — ns Data hold time from SCK rise tDIH1 DIPH = “L” 50 — — ns Data output delay time from SCK rise tDOD1 RL = 3 kΩ — — 90 ns Data setup time from SCK fall tDIS2 DIPH = “H” 50 — — ns Data hold time from SCK fall tDIH2 DIPH = “H” 50 — — ns Data output delay time from SCK rise tDOD2 RL = 3 kΩ — — 90 ns SCK “H” level pulse width tSCKH — 100 — — ns SCK “L” level pulse width tSCKL — 100 — — ns CBUSYB output delay time from SCK rise tDBSY1 DIPH = “L” — — 90 ns CBUSYB output delay time from SCK fall tDBSY2 DIPH = “H” — — 90 ns Note: Output pin load capacitance = 45 pF (Max.) 12/69 FEDL22Q553-02 ML22Q553 TIMING DIAGRAMS Serial Interface Data Input Timing (When DIPH = “L”) CSB VIH VIL t ESCK SCK VIL tDIS1 SI t CSH tSCKH VIH tDIH1 t SCKL VIH VIL tDBSY1 CBUSYB VOH VOL Serial Interface Data Input Timing (When DIPH = “H”) CSB VIH VIL t ESCK SCK VIH VIL tDIS2 SI t CSH t SCKL tDIH2 t SC KH VIH VIL t DBSY2 CBUSYB VOH VOL Serial Interface Data Output Timing (When DIPH = “L”) CSB VIH VIL t ESCK SCK VIL t SCKL tDOD1 SO t CSH tSCKH VIH t DOZ VIH VIL tDBSY1 CBUSYB VOH VOL Serial Interface Data Output Timing (When DIPH = “H”) CSB VIH VIL t ESCK SCK VIH VIL t DOD2 SO t CSH t SCKL t SCKH t DOZ VIH VIL t DBSY2 CBUSYB VOH VOL 13/69 FEDL22Q553-02 ML22Q553 Power-On Timing (for the power down state, see the section on “5. PDWN command” described later.) 5V SPVDD 5V DVDD tRST VIH RESETB VIL Status Power down Oscillation is stopped after power-on. Be sure to set “L”level the RESETB pin before the first command input. Power-Up Timing CSB SCK SI tPUP CBUSYB VOH VOL NCRn (internal) VOH BUSYBn (internal) VOH XTxXTB Status VOL VOL Oscillation stopped Power down Oscillating Oscillation stabilized Performing reset processing Awaiting command 14/69 FEDL22Q553-02 ML22Q553 Power-Down Timing CSB SCK SI tPD CBUSYB VOH VO L NCRn VOH (internal) VO L BUSYBn VOH (internal) VO L XTxXTB Status Oscillation stopped Oscillating Awaiting command Command is being processed Power down Reset Input Timing RESETB t RS T XTxXTB Oscillating VDDLxSG GND SPM Hi-Z GND SPP Status Oscillation stopped Playing Power down Note: The same timing applies in cases where the Reset signal is input during waiting for command. 15/69 FEDL22Q553-02 ML22Q553 Playback Start Timing by the PLAY Command PLAY command 1 st byte PLAY command 2 nd byte CSB SCK SI tCB1 t CB2 CBUSYB VOH VOL NCRn (internal) VOH BUSYBn (internal) VOH VOL (*1) VOL SPM 1/2VDD SPP 1/2VDD Status Command s tandby Awaiting command Addres s is being cont rolled Playing Awaiting c ommand Command is being processed *1: Length of the “L” interval of BUSYBn is = tCB2 + voice production time length. Playback Stop Timing STOP command CSB SCK SI tCB3 CBUSYB VOH VOL NCRn (internal) VOH BUSYBn (internal) VOH VOL VOL 1/2VDD SPM 1/2VDD SPP Status Playing Awaiting command Command is being processed 16/69 FEDL22Q553-02 ML22Q553 Continuous Playback Timing by the PLAY Command PLAY command 2nd byte PLAY command PLAY command 2nd byte 1s t byte CSB SCK tcm SI tCB1 tCB2 tC B1 CBUSYBVO H VO L NCRn VO H VO L (internal) BUSYBn (internal) SPM 1/2VD D SPP 1/2VD D Status Awaiting command Playing phrase 1 Playing phrase 2 Address is being controlled Silence Insertion Timing by the MUON Command PLAY command 2nd byte MUON command MUON command 1st byte 2nd byte PLAY command PLAY command 1s t byte 2nd byte t cm tcm CSB SCK SI t CB2 CBUSYB VOH NCRn (internal) VOH tCB1 tCB1 tCB1 tCB1 VOL (*1) VOL (*1) BUSYBn (internal) SPM 1/ 2VDD SPP 1/ 2VDD Status Awaiting command Address is being controlled Playing Silence is being inserted Playing Waiting for silence insertion to be finished *1: The “L” level period of the NCR pin during playback or silence insertion operation varies depending on the timing at which the MUON command is input. 17/69 FEDL22Q553-02 ML22Q553 Repeat Playback Set/Release Timing by the SLOOP and CLOOP Commands VIH CSB SLOOP command PLAY command 2n d byte VIL CLOOP command t INT SCK SI tCB2 CBUSYB t cm VOH VOL NCRn (internal) VOH VOL BUSYBn (internal) SPM 1/2VDD SPP 1/2VDD Status Awaiting command Playing Address is being controlled Playing Address is being controlled Awaiting command Command is being processed Timing of Volume Change by the CVOL Command CVOL command st 1 byte CVOL command nd 2 byte CSB SCK SI tCB1 CBUSYB tCB1 VOH VOL NCRn VOH (internal) VOL BUSYBn VOH (internal) VOL Status Awaiting command Command is being processed Awaiting command Awaiting command Command is being processed 18/69 FEDL22Q553-02 ML22Q553 FUNCTIONAL DESCRIPTION Synchronous Serial Interface The CSB, SCK, SI, and SO pins are used to input various commands or read the status of the device. For command input, after inputting a “L” level to the CSB pin, input data through the SI pin with MSB first in sync with the SCK clock signal. The data input through the SI pin is shifted into the LSI in sync with the SCK clock signal, then the command is executed at the eighth pulse of the rising or falling edge of the SCK clock. For status reading, after a “L” level is input to the CSB pin, stauts is output from the SO pin in sync with the SCK clock signal. Choosing between rising edges and falling edges of the clock pulses input through the SCK pin is determined by the signal input through the DIPH pin: - When the DIPH pin is at a “L” level, the data input through the SI pin is shifted into the LSI on the rising edges of the SCK clock pulses and a status signal is output from the SO pin on the falling edges of the SCK clock pulses. - When the DIPH pin is at a “H” level, the data input through the SI pin is shifted into the LSI on the falling edges of the SCK clock pulses and a status signal is output from the SO pin on the rising edges of the SCK clock pulses. It is possible to input commands even with the CSB pin tied to a “L” level. However, if unexpected pulses caused by noise etc. are induced through the SCK pin, SCK clock pulses are incorrectly counted, causing a failure in normal input of command. In addition, the serial interface can be brought back to its initial state by driving the CSB pin at a “H” level. When the CSB pin is at ta “L” level, the status of each channel is output serially in sync with the SCK clock. When the CSB pin is at a ”H” level, the SO pin goes into a high impedance state. • C om ma nd In pu t Timi ng : SCK r isin g e dge ope ra tion (wh e n D IPH p in = “L” le vel ) CSB SCK SI D7 D6 D5 D4 D3 D2 D1 (MSB) D0 (LSB ) • C om ma nd In pu t Timi ng : SCK fa lling edg e o pe ra tio n (whe n DIPH pin = “H” le vel ) CSB SCK SI D7 D6 D5 D4 D3 D2 D1 (MSB) D0 (LSB ) • C om ma nd O u tpu t T imi ng : SC K fa llin g ed g e o pe ra tio n (w he n D IPH pin = “L ” le ve l) CSB SCK (MSB) SO D7 (LSB ) D6 D5 D4 D3 D2 D1 D0 Co m ma nd O utp ut Tim in g: S CK ris ing ed g e op era tio n ( wh en DIPH pi n = “H ” le vel ) CSB SCK (MSB) SO D7 (LSB ) D6 D5 D4 D3 D2 D1 D0 19/69 FEDL22Q553-02 ML22Q553 To prevent malfunction caused by serial interface pin noise, the ML22Q553 is provided with the two-time command input mode, where the user inputs one command two times. Use the PUP command to set the two-time command input mode. For the method of setting the two-time command input mode, see the the section on “1. PUP command” described later. In two-time command input mode, input one command two times in succession. Then, the command becomes valid only when the data input first matches the data input second. After the first data input, if a data mismatch occurs when the second data is input, a ”H” level is output from the ERR pin. An error, if occurred, can be cleared by the ERCL command. PLAY command 1st byte PLAY command 1 st byte PLAY command 2nd byte PLAY command 2nd byte CSB SCK SI t CB1 tCB2 CBUSYB VOH VOL NCRn (internal) VOH BUSYBn (internal) VOH VOL VOL SPM 1/2VDD SPP 1/2VDD Status Awaiting command Command is being processed Awaiting command Command is being processed Awaiting command Awaiting command Address is being controlled Playing Awaiting command Command is being processed 20/69 FEDL22Q553-02 ML22Q553 Voice Synthesis Algorithm The ML22Q553 contains four algorithm types to match the characteristic of playback voice: HQ-ADPCM algorithm, 8-bit straight PCM algorithm, 8-bit non-linear PCM algorithm, and 16-bit straight PCM algorithm. Key feature of each algorithm is described in the table below. Voice synthesis algorithm HQ-ADPCM 8-bit Nonlinear PCM 8-bit PCM 16-bit PCM Feature Algorithm that enables high sound quality and high compression, which have been achieved by the improved 4-bit ADPCM that uses variable bit-length coding. Algorithm that plays back mid-range of waveform as 10-bit equivalent voice quality. Normal 8-bit PCM algorithm Normal 16-bit PCM algorithm 21/69 FEDL22Q553-02 ML22Q553 Memory Allocation and Creating Voice Data The ROM is partitioned into four data areas: voice (i.e., phrase) control area, test area, voice area, and edit ROM area. The voice control area manages the ROM’s voice data. It contains data for controlling the start/stop addresses of voice data for 1024 phrases, use/non-use of the edit ROM function and so on. The test area contains data for testing. The voice area contains actual waveform data. The edit ROM area contains data for effective use of voice data. For the details, refer to the section on “Edit ROM Function.” No edit ROM area is available unless the edit ROM is used. The ROM data is created using a dedicated tool. Configuration of ROM data 0x00000 0x01FFF 0x02000 0x0206F 0x02070 Voice control area (Fixed 64 Kbits) Test area Voice area max: 0x7FEBF max: 0x7FEBF 0x7FEC0 max: 0x7FFFF Edit ROM area Depends on creation of ROM data. Filter area Playback Time and Memory Capacity The playback time depends on the memory capacity, sampling frequency, and playback method. The equation showing the relationship is given below. The equation below gives the playback time when the edit ROM function is not used. Playback time = 1.024 × (Memory capacity − 64) (Kbits) Sampling frequency (kHz) × Bit length (sec) Example: Let the sampling frequency be 16 kHz and HQ-ADPCM algorithm. approx. 80 seconds, as shown below. Playback time = 1.024 × (4096 − 64) (Kbits) 16 (kHz) × 3.2 (bits) (average) Then the playback time is ≅ 80 (sec) 22/69 FEDL22Q553-02 ML22Q553 Edit ROM Function With the edit ROM function, multiple phrases can be played in succession. configured using the edit ROM function: The following functions can be x Continuous playback: There is no limit to the continuous playback count that can be specified. depends on the memory capacity only. x Silence insertion: 20 to 1024 ms It Using the edit ROM function enables an effective use of the memory capacity of voice ROM. Below is an example of the ROM configuration in the case of using the edit ROM function. Examples of Phrases Using the Edit ROM Function Phrase 1 A B D Phrase 2 A C D Phrase 3 E B D Phrase 4 E C D Phrase 5 A B D Silence E B D Example of ROM Data Where the Contents Above Are Stored in ROM Address control area A B D C E Editing area 23/69 FEDL22Q553-02 ML22Q553 Mixing Function The ML22Q553 can perform simultaneous mixing of four channels. STOP, and CVOL for each channel separately. It is possible to specify FADR, PLAY, • Precautions for Waveform Clamp at the Time of Channel Mixing If channel mixing is done, the possibility of an occurrence of a clamp increases from the mixing calculation point of view. If it is known beforehand that a clamp will occur, then adjust the sound volume of each channel using the VOL command. • Mixing of Different Sampling Frequency It is not possible to perform channel mixing by a different sampling frequency group. When performing channel mixing, the sampling frequency group of the first playback channel is selected. Therefore, note that if channel mixing is performed by a sampling frequency group other than the selected sampling frequency group, then the playback will not be of constant speed: some times faster and at other times slower. The available sampling groups for channel mixing by a different sampling frequency are listed below. 8.0 kHz, 16.0 Hz, 32.0 kHz … (Group 1) 12.0 kHz, 24.0 kHz, 48 kHz … (Group 2) 6.4 kHz, 12.8 kHz, 25.6 kHz … (Group 3) Figures below show cases where a phrase is played at a sampling frequency belonging to a different sampling frequency group. fs＝16.0kHz fs＝16.0kHz（Invalid、Will be played as fs＝12.8kHz） Channel 1 fs＝25.6kHz Channel 2 Figure 1 Case where a phrase is played at a sampling frequency belonging to a different sampling frequency group during playback on channels 1 and 2 fs = 16.0 kHz Channel 1 Played normally if not being played by other channel. fs = 25.6 kHz (Valid) Channel 2 End of channel 1 Figure 2 Case where a phrase is played at a sampling frequency belonging to a different sampling frequency group after playback is finished at the other channel 24/69 FEDL22Q553-02 ML22Q553 Over-current detectible function at Speaker pins The over-current detectible function for the Speaker pins detect a short between SPP and SPM, and a short between SPP/SPM and GND. The over-current detectible function is effective on speaker power-up by the AMODE command. Serial I/F AMODE spkr_mode powerup PUP AMODE spkr_mode powerdown PLAY PDWN AMODE spkr_mode powerup PUP SPVDD SPP SPGND SPVDD SPM Status HiZ SPGND analog powerup speaker powerup analog powerdown speaker powerdown analog powerdown speaker powerdown analog powerup speaker powerup DVDD ERR over-current detectible function active over-current detectible function active over-current detectible function for Speaker pins When the over-current is detected, the speaker amplifier output pin(SPP/SPM) go to power-down forcibly, and a short error is informed by the ERR pin “H”. In the case of error outbreak, please confirm a status of error by the RDSTAT command, stop playback, and set the speaker power-down by the AMODE command. Afterwards, please clear an error by the ERCL command. If performing playback again, set the speaker power-up by the AMODE command, and next set the PLAY command. However, when shorting to GND is going on, even if the following operation is done, the speaker amplifier output pin(SPP/SPM) go to power-down forcibly, and the ERR pin becomes “H”. (1)After setting power-down by the AMODE command , do power-up by the AMODE command (2)After detect a short error, when input ERCL command without power-down operation of speaker amplifier by the AMODE command Serial I/F AMODE spkr_mode powerup PUP RDSTAT ERR read AMODE spkr_mode powerdown AMODE spkr_mode powerup ERCL SPVDD SPP SPGND SPVDD SPM SPGND HiZ HiZ detect a short Status analog powerdown speaker powerdown analog powerup speaker powerup analog powerup speaker powerdown analog powerdown speaker powerdown analog powerup speaker powerup ERR over-current detectible function active over-current detectible function active over-current detectible function Operation Flow (Example) 25/69 FEDL22Q553-02 ML22Q553 Command List Each command is configured in 1-byte (8-bit) units. Each of the AMODE, AVOL FADR, PLAY, MUON, and CVOL commands forms one command by two bytes.Be sure to input the following commands only. Input each command with CBUSYB set to a ”H” level. Command PUP AMODE AVOL FAD PDWN FADR PLAY START D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 WCM 0 0 0 0 0 1 HPF1 HPF0 0 DAG1 DAG0 AIG1 AIG0 DAEN SPEN POP 0 0 0 0 1 0 0 0 — — AV5 AV4 AV3 AV2 AV1 AV0 0 0 0 0 1 1 0 0 0 0 0 0 FAD3 FAD2 FAD1 FAD0 0 0 1 0 0 0 0 0 0 0 1 1 C1 C0 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0 0 1 0 0 C1 C0 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0 0 1 0 1 CH3 CH2 CH1 CH0 Description Shifts the device currently powered down to a command wait state. Also the two-time command input mode is set by this command. Analog section control command. Configures settings for power-up operation and analog input/output. Selects the type of HPF. Analog mixing signal volume setting command. Use the data of the 2nd byte to specify volume. Sets the fade-in time in cases where the speaker amplifier is enabled by the AMODE command. Shifts the device from a command wait state to a power-down state. Playback phrase specification command. Can be specified for each channel. Playback start command. Use the data of the 2nd byte to specify a phrase number. Can be specified for each channel. Playback start command without phrase specification. Used to start playback on multiple channels at the same time after phrases are specified with the FADR command. After a phrase is played with the PLAY command, the same phrase can be played with this command. 26/69 FEDL22Q553-02 ML22Q553 Command STOP D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 0 CH3 CH2 CH1 CH0 0 1 1 1 CH3 CH2 CH1 CH0 M7 M6 M5 M4 M3 M2 M1 M0 SLOOP 1 0 0 0 CH3 CH2 CH1 CH0 CLOOP 1 0 0 1 CH3 CH2 CH1 CH0 1 0 1 0 CH3 CH2 CH1 CH0 — — — CV4 CV3 CV2 CV1 CV0 RDSTAT 1 0 1 1 0 0 0 ERR OUTSTAT 1 1 0 0 0 BUSY/NCR C1 C0 1 1 0 1 0 0 0 0 TM2 TM1 TM0 TSD1 TSD0 BLD2 BLD1 BLD0 1 1 1 1 1 1 1 1 MUON CVOL SAFE ERCL Description Playback stop command. Can be specified for each channel. Silence insertion command. Use the data of the 2nd byte to specify the length of silence. Can be specified for each channel. Repeat playback mode setting command. The setting is enabled during playback. Can be specified for each channel. Repeat playback mode release command. When the STOP command is input, repeat playback mode is released automatically. Can be specified for each channel. Volume setting command. Use the data of the 2nd byte to specify volume. Can be specified for each channel. Status serial read command. This command reads the command status and the status of the fail safe function for each channel. Status output command. This command outputs the command status of each channel from the STATUS pin. Fail safe setting command. Sets settings for power supply voltage detection, temperature detection, and monitoring time. This command clears error while the fail safe function is operating. 27/69 FEDL22Q553-02 ML22Q553 Description of Command Functions 1. PUP command x command 0 0 0 0 0 0 0 WCM The PUP command is used to shift the ML22Q553 from a power down state to a command waiting state. The ML22Q553 can only accept the PUP command while it is in a power down state. Therefore, in a power down state, the device will ignore any other command if entered. The ML22Q553 enters a power down state under any of the following conditions: 1) When power is turned on 2) At RESETB input 3) When CBUSYB go to a “H” level after inputting the power down command CS B SCK t P UP SI C BUS YB X T xXT B S ta t u s O s c ill a t io n s t o pp ed P ow er d ow n O sc i ll a ti n g R es et be in g pr o c es s ed A w a it in g co m m a n d O sc illa t io n st a b ilize d The WCM bit is used to set the two-time command input mode. When set to ”1”, the command input thereafter will be processed in two-time command input mode and becomes valid only when the first data input matches the second one. WCM 0 1 Two-time command input mode No (initial value) Yes The regulator starts operating after the PUP command is entered. Any command will be ignored if entered while oscillation is stabilized. However, if a “L” level is input to the RESETB pin, the LSI enters a power down state immediately. Neither line output nor speaker output is enabled by the PUP command. AMODE command. Power up the analog section by the 28/69 FEDL22Q553-02 ML22Q553 2. AMODE command x command 0 0 0 DAG1 0 DAG0 0 AIG1 0 AIG0 1 DAEN HPF1 SPEN HPF0 POP 1st byte 2nd byte The AMODE command is used to configure various settings for the analog section. If the PDWN command is input while the analog section is in the power-up state, the analog section enters a power down state under the setting conditions that were in effect when the analog section was powered up by the AMODE command. To perform a power-down operation using different conditions from those used at analog section power-up, set settings by the AMODE command. To change the setting of DAEN/SPEN while the analog section is in the power-up state, first put the analog section into the power-down state and then put the analog section into the power-up state again by the AMODE command. The detailed command settings are shown below. Each setting is initialized upon reset release or by the PUP command. Don’t input the STOP command during the AMODE command is being proccessed (CBUSYB=”L”). Input the AMODE command for analog section into the power-down state before the PDWN command is input. The HPF1/HPF0 bits set the cut-off frequency of the HPF. HPF1 HPF0 0 0 1 1 0 1 0 1 Cut-off frequency Off (initial value) 200 Hz 300 Hz 400 Hz The POP bit specifies whether to suppress generation of “pop” noise. - If the bit is “0” (no pop noise suppression) and the DAEN bit is “1”, the LINE output rises from the DGND level to the SG level in about 35 ms, at which time the analog section enters the power-up state. If the DAEN bit is “0”, the LINE output falls from the SG level to the DGND level in about 110 ms, at which time the analog section enters the power down state. - If the bit is “1” (with pop noise suppression) and the DAEN bit is “1”, the LINE output rises from the DGND level to the SG level in about 90 ms, at which time the analog section enters the power-up state. If the DAEN bit is “0”, the LINE output falls from the SG level to the DGND level in about 140 ms, at which time the analog section enters the power down state. POP 0 1 Pop noise suppression No (initial value) Yes 29/69 FEDL22Q553-02 ML22Q553 x When powering up the speaker amplifier and line amplifier (without pop noise suppression) Setting values: POP bit = “0”, DAEN and SPEN bits = “0” → “1” AMODE command 1st byte AMODE command 2nd byte CSB SCK SI tCB1 CBUSYB VOH NCR (internal) VOH BUSYB (internal) VOH tPUPA1 VOL VOL VOL 1/2DVDD LINE output GND (internal) SPM Hi-Z SPP GND 1/2SPVDD 1/2SPVDD Status Awaiting command Awaiting command Command is being processed Awaiting command Command is being processed x When powering up the line amplifier (with pop noise suppression) Setting values: POP bit = “1”, DAEN bit = “0” → “1” (SPEN bit = “0”) AMODE command 1st byte AMODE command 2nd byte CSB SCK SI tCB1 CBUSYB VOH NCR (internal) VOH BUSYB (internal) VOH tPUPA2 VOL VOL VOL 1/2DVDD SPP GND (LINE output) Status Awaiting command Command is being processed Awaiting command POP noise suppressed Awaiting command Command is being processed 30/69 FEDL22Q553-02 ML22Q553 x When putting the line amplifier into the power down state (without pop noise suppression) and putting the speaker amplifier into the power down state Setting values: PUP bit = “0”, DAEN and SPEN bits = “1” → “0” AMODE command 1st byte AMODE command 2nd byte CSB SCK SI tCB1 CBUSYB VOH NCR (internal) VOH BUSYB (internal) VOH tPDA1 VOL VOL VOL 1/2DVDD LINE output GND 1/2SPVDD Hi-Z SPM 1/2SPVDD SPP GND Status Awaiting command Awaiting command Command is being processed Awaiting command Command is being processed x When putting the line amplifier into the power down state (with pop noise suppression) Setting values: POP bit = “1”, DAEN bit = “1” → “0” (SPEN bit = “0”) AMODE command 1st byte AMODE command 2nd byte CSB SCK SI tCB1 CBUSYB VOH NCR (internal) VOH BUSYB (internal) VOH tPDA2 VOL VOL VOL 1/2DVDD SPP (LINE output) Status GND Awaiting command Command is being processed Awaiting command POP noise suppressed Awaiting command Command is being processed 31/69 FEDL22Q553-02 ML22Q553 The DAG1,0 bits are used to set the gain of the internal DAC signal. The AIG1,0 bits are used to set the gain of an analog signal from the AIN pin. DAG1,0 and AIG1,0 are only enabled when the speaker amplifier is used. DAG1 DAG0 Volume 0 0 1 1 0 1 0 1 Input OFF Input ON (–6 dB) Input ON (0 dB) (initial value) Input ON (0 dB) (Setting prohibited) AIG1 AIG0 Volume 0 0 1 1 0 1 0 1 Input OFF (initial value) Input ON (–6 dB) Input ON (0 dB) Input ON (0 dB) (Setting prohibited) Input the analog signal from the AIN pin after the AMODE command (CBUSYB=”H”). The DAEN bit takes power-up and power-down control of the DAC section. DAEN 0 1 Status of the DAC section Power-down state (initial value) Power-up state The SPEN bit takes power-up and power-down control of the speaker section. When the SPEN bit = “0”, the SPP pin is configured as a LINE output. SPEN 0 1 Status of the speaker section Power-down state (initial value) Power-up state Relationship between DAEN, SPEN, and POP signals and the analog section DAEN SPEN POP Mode 0 0 0 0 0 1 ― 1 ― Speaker output Power-down (without pop noise suppression) Power-down Power-down (with pop noise suppression) DAC/speaker power-up 1 0 0 LINE output DAC power-up (without pop noise suppression) 1 0 1 LINE output DAC power-up (with pop noise suppression) At speaker output At LINE output At speaker output At LINE output Status Power-down (initial value) Pin status during power down The status of each output pin during power down by the AMODE command is shown below. Analog output pin State VDDL VDDR SG SPM SPP DGND DGND DGND Hi-Z DGND 32/69 FEDL22Q553-02 ML22Q553 3. AVOL command x command 0 0 0 0 0 AV5 0 AV4 1 AV3 0 AV2 0 AV1 0 AV0 1st byte 2nd byte The AVOL command is used to adjust the volume of the speaker amplifier. It is possible to input the AVOL command regardless of the status of the NCR signal. The command enables 50-level adjustment of volume, as shown in the table below. When the PUP or AMODE command is input, the value set by the AVOL command is initialized (0 dB). AV5–0 3F 3E 3D 3C 3B 3A 39 38 37 36 35 34 33 32 31 30 2F 2E 2D 2C 2B 2A 29 28 27 26 25 24 23 22 21 20 Volume +12dB +11.5 +11.0 +10.5 +10.0 +9.5 +9.0 +8.5 +8.0 +7.5 +7.0 +6.5 +6.0 +5.5 +5.0 +4.5 +4.0 +3.5 +3.0 +2.5 +2.0 +1.5 +1.0 +0.5 +0.0 (initial value) −1.0 −2.0 −3.0 −4.0 −5.0 −6.0 −7.0 AV5–0 1F 1E 1D 1C 1B 1A 19 18 17 16 15 14 11 12 11 10 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 00 01 00 Volume −8.0 −9.0 −10.0 −11.0 −12.0 −13.0 −14.0 −16.0 −18.0 −20.0 −22.0 −24.0 −26.0 −28.0 −30.0 −32.0 −34.0 OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF 33/69 FEDL22Q553-02 ML22Q553 4. FAD command x command 0 0 0 0 0 0 0 0 1 FAD3 1 FAD2 0 FAD1 0 FAD0 1st byte 2nd byte The FAD command is used to set the fade-in time for the speaker amplifier. The fade-in time cna be adjusted through 16 levels, as shown in the table below. The initial value after reset is 298 μs. When the PUP command is input, the value set by the FAD command is initialized (298 μs). FAD3–0 Fade-in time (μs) F E D C B A 9 8 7 6 5 4 3 2 1 0 442 422 401 381 360 340 319 298 (initial value) 278 257 237 216 195 175 154 134 34/69 FEDL22Q553-02 ML22Q553 5. PDWN command x command 0 0 1 0 0 0 0 0 The PDWN command is used to shift the ML22Q553 from a command waiting state to the power down state. However, since every setting will be initialized after entering the power down state, initial settings need to be set after power-up. This command is invalid during playback. To resume playback after the ML22Q553 has shifted to the power down state, first input the PUP and AMODE commands and then input the PLAY command. CSB SCK SI CBUSYB NCR (internal) BUSYB (internal) Oscillation stopped XT•XTB Oscillating Status Awaiting command Command is being processed Power down Oscillation stops after a lapse of command processing time after the PDWN command is input. The regulator stops operation after a lapse of command processing time after the PDWN command is input. At this time, the SPM output of the speaker amplifier goes into a Hi-Z state to prevent generation of pop noise. Initial stauts at reset input and status during power down The status of each output pin is as follows: Analog output pin State VDDL VDDR SG SPM SPP DGND DGND DGND Hi-Z DGND 35/69 FEDL22Q553-02 ML22Q553 6. FADR command x command 0 F7 0 F6 1 F5 1 F4 C1 F3 C0 F2 F9 F1 F8 F0 1st byte 2nd byte The FADR command is used to specify a phrase to be played. A playback channel and a playback phrase are set by this command. The FADR command can be set for each channel; however, the command cannot be input for multiple channels simultaneously. Input the FADR command with each NCR set to a ”H” level. When a playback phrase is specified for each channel, use the START command to start playback. Since it is possible to specify a playback phrase (F9–F0) at the time of creating a ROM that stores voice data, specify the phrase that was specified when the ROM was created. Channel settings C1 C0 Channel 0 0 1 1 0 1 0 1 Channel 0 Channel 1 Channel 2 Channel 3 The diagram below shows the timing for specifying (F9–F0) = 02H as the phrase to play on channel 1. FADR command FADR command 1st byte 2nd byte CSB SCK SI CBUSYB NCR (internal) BUSYB (internal) Status Awaiting command Command is being processed Awaiting command Awaiting command Command is being processed 36/69 FEDL22Q553-02 ML22Q553 7. PLAY command x command 0 F7 1 F6 0 F5 0 F4 C1 F3 C0 F2 F9 F1 F8 F0 1st byte 2nd byte The PLAY command is used to start playback with phrase specified. This command can be input when the NCR signal on the target channel is at a “H” level. Since it is possible to specify a playback phrase (F9–F0) at the time of creating a ROM that stores voice data, specify the phrase that was specified when the ROM was created. The figure below shows the timing of phrase (F9–F0 = 01H) playback. PLAY command 1st byte PLAY command 2nd byte CSB SCK SI CBUSYB NCR (internal) BUSYB (internal) 1/2VDD SPM 1/2VDD SPP Status Awaiting command Awaiting command Address is being controlled Playing Awaiting command Command is being processed When the 1st byte of the PLAY command is input, the device enters a state awaiting input of the 2nd byte of the PLAY command after a lapse of command processing time. When the 2nd byte of PLAY command is input, after a lapse of command processing time, the device starts reading from the ROM the address information of the phrase to be played. Thereafter, playback operation starts, the playback is performed up to the specified ROM address, and then the playback terminates automatically. The NCR signal is at a “L” level during address control, and goes “H” when the address control is finished and playback starts. When the NCR signal on the target channel goes “H”, it is possible to input the PLAY command for the next playback phrase. During address control, the BUSYB signal is at a “L” level during playback and goes “H” when playback is finished. Whether the playback is going on can be known by the BUSYB signal. Channel settings C1 C0 Channel 0 0 1 1 0 1 0 1 Channel 0 Channel 1 Channel 2 Channel 3 37/69 FEDL22Q553-02 ML22Q553 PLAY Command Input Timing for Continuous Playback The diagram below shows the PLAY command input timing in cases where one phrase is played and then the next phrase is played in succession. PLAY command 2nd byte PLAY command PLAY command 1st byte 2nd byte CSB SCK tcm SI CBUSYB NCR (internal) BUSYB (internal) SPM 1/2VDD SPP 1/2VDD Status Awaiting command Address is being controlled Playing phrase 1 Playing phrase 2 Address is being controlled As shown in the diagram above, if performing continuous playback, input the PLAY command for the second phrase within 10 ms (tcm) after the NCR signal on the target channel goes “H”. Please input the following PLAY command after checking that playback is completed by the RDSTAT command, when it is not continuous playback. 38/69 FEDL22Q553-02 ML22Q553 8. START command x command 0 1 0 1 CH3 CH2 CH1 CH0 The START command is a channel synchronization start (i.e., starts phrase playback on multiple channels simultaenously) command. It is necessary to specify playback phrases using the FADR command before inputting the START command. Setting any bit(s) from CH0 to CH3 to “1” starts playback on the corresponding channel(s). Input the START command with each NCR set to a ”H” level. The figure below shows the timing when starting playback on channel 00 and channel 1 simultaneously. Channel settings Channel CH0 CH1 CH2 CH3 Setting this bit to “1” starts playback on channel 0. Setting this bit to “1” starts playback on channel 1. Setting this bit to “1” starts playback on channel 2. Setting this bit to “1” starts playback on channel 3. Be sure to set the channel setting bits( CH0-CH3). START command CSB SCK SI tcB2 CBUSYB NCR0 (internal) NCR1 (internal) BUSYB0 (internal) BUSYB1 (internal) SPP output Status Awaiting command Address is being controlled Playing Awaiting command 39/69 FEDL22Q553-02 ML22Q553 START Command Input Timing for Continuous Playback The diagram below shows the START command input timing in cases where one phrase is played and then the next phrase is played in succession. START command START command CSB SCK tcm SI CBUSYB NCR (internal) BUSYB (internal) SPM 1/2VDD SPP 1/2VDD Status Awaiting command Playing phrase 1 Playing phrase 2 Address is being controlled As shown in the diagram above, if performing continuous playback, input the START command for the second phrase within 10 ms (tcm) after the NCR signal on the target channel goes “H”. Please input the following START command after checking that playback is completed by the RDSTAT command, when it is not continuous playback. 40/69 FEDL22Q553-02 ML22Q553 9. STOP command x command 0 1 1 0 CH3 CH2 CH1 CH0 The STOP command is used to stop playback. It can be set for each channel. Setting any bit(s) from CH0 to CH3 to “1” stops playback on the corresponding channel(s). If the speech synthesis processing for all channels stops, the AOUT output goes to the VSG level and the NCR and BUSYB signals go to a “H” level. Although it is possible to input the STOP command regardless of the status of NCR during playback, a prescribed command interval time needs taking. STOPcommand CSB SCK SI CBUSYB NCR (internal) fs×29cycle BUSYB (internal) SPM 1/2VDD SPP 1/2VDD Status Playing Co mmand is be ing pro cesse d Awaiting Channel settings Channel CH0 CH1 CH2 CH3 Setting this bit to “1” stops playback on channel 0. Setting this bit to “1” stops playback on channel 1. Setting this bit to “1” stops playback on channel 2. Setting this bit to “1” stops playback on channel 3. Be sure to set the channel setting bits( CH0-CH3). The STOP command allows specifying multiple channels at one time. 41/69 FEDL22Q553-02 ML22Q553 10. MUON command x command 0 M7 1 M6 1 M5 1 M4 CH3 M3 CH2 M2 CH1 M1 CH0 M0 1st byte 2nd byte The MUON command allows inserting a silence between two playback phrases. The command can be input when the NCR signal on the target channel is at a “H” level. Set the silence time length after inputting this command. It can be set for each channel. The MUON command allows specifying multiple channels at one time. Setting any bit(s) from CH0 to CH3 to “1” plays silence on the corresponding channel(s). Channel settings Channel CH0 CH1 CH2 CH3 Setting this bit to “1” inserts a silence on channel 0. Setting this bit to “1” inserts a silence on channel 1. Setting this bit to “1” inserts a silence on channel 2. Setting this bit to “1” inserts a silence on channel 3. Be sure to set the channel setting bits( CH0-CH3). As the silence length (M7–M0), a value between 20 ms and 1024 ms can be set at 4 ms intervals (252 steps in total). The equation to set the silence time length is shown below. The silence length (M7–M0) must be set to 04h or higher. 7 6 5 4 3 2 1 0 tmu=(2 ×(M7)+2 ×(M6)+2 ×(M5)+2 ×(M4)+2 ×(M3)+2 ×(M2)+2 ×(M1)+2 ×(M0)+1)×4ms The figure below shows the timing of inserting a silence of 20 ms between the repetitions of a phrase of (F7–F0) = 01h. PLAY command 2nd byte MUON command MUON command 1st byte 2nd byte PLAY c ommand PLAY command 1st byte 2nd byte CSB SCK tcm t cm Playing Silence is being inserted SI CBUSYB NCR (internal) BUSYB (internal) SPM SPP Status 1/2VDD 1/2VDD Awaiting c ommand Address is being controlled Waiting for playback to be finished Playing Waiting for sil ence inserti on to be finished 42/69 FEDL22Q553-02 ML22Q553 When the PLAY command is input, the address control over phrase 1 ends, the phrase playback starts, and the CBUSYB and NCR signals go to a “H” level. Input the MUON command after this CBUSYB signal changes to a “H” level. After the MUON command input, the NCR signal remains “L” until the end of phrase 1 playback, and the device enters a state waiting for the phrase 1 playback to terminate. When the phrase 1 playback is terminated, the silence playback starts and the NCR signal goes to a “H” level. After the NCR signal has gone to a “H” level, re-input the PLAY command in order to play phrase 1. After the PLAY command input, the NCR signal once again goes to a “L” level and the device enters a state waiting for the termination of silence playback. When the silence playback is terminated and then the phrase 1 playback starts, the NCR signal goes “H”, and the device enters a state where it is possible to input the next PLAY or MUON command. The BUSYB signal remains “L” until the end of a series of playback. As shown in the diagram above, if performing continuous playback, input the MUON/PLAY/START command for the second phrase within 10 ms (tcm) after the NCR signal on the target channel goes “H”. Please input the following MUON/PLAY/START command after checking that playback is completed by the RDSTAT command, when it is not continuous playback. 43/69 FEDL22Q553-02 ML22Q553 11. SLOOP command x command 1 0 0 0 CH3 CH2 CH1 CH0 The SLOOP command is used to set repeat playback mode. The command can be input for each channel. The SLOOP command allows specifying multiple channels at one time. Setting any bit(s) from CH0 to CH3 to “1” repeats playback on the corresponding channel(s). Input the SLOOP command with each NCR set to a ”H” level. Channel settings Channel CH0 CH1 CH2 CH3 Setting this bit to “1” repeats playback on channel 0. Setting this bit to “1” repeats playback on channel 1. Setting this bit to “1” repeats playback on channel 2. Setting this bit to “1” repeats playback on channel 3. Be sure to set the channel setting bits( CH0-CH3). Once repeat playback mode is set, the current phrase is repeatedly played until the repeat playback setting is released by the SLOOP command or until playback is stopped by the STOP command. In the case of a phrase that was edited using the edit function, the edited phrase is repeatedly played. Following shows the SLOOP command input timing. PLAY command 2nd byte SLOOP command CLOOP command CSB SCK SI CBUSYB NCR (internal) t cm BUSYB (internal) SPM SPP Status 1/2VDD 1/2VDD Awaiting command Address is being controlled Playi ng Address is being controlled Playing Awai ting command Command is being processed Effective Range of SLOOP Command Input The SLOOP command is only enabled during playback. After the PLAY command is input, input the SLOOP command within 10 ms (tcm) after the NCR signal on the target channel goes “H”. This will enable the SLOOP command, so that repeat playback will be carried out. The NCR signal remains “L” during repeat playback mode. 44/69 FEDL22Q553-02 ML22Q553 12. CLOOP command x command 1 0 0 1 CH3 CH2 CH1 CH0 The CLOOP command releases repeat playback mode. The command can be input for each channel. The CLOOP command allows specifying multiple channels at one time. Setting any bit(s) from CH0 to CH3 to “1” releases repeat playback on the corresponding channel(s). When repeat playback mode is released, the NCR signal goes “H”. It is possible to input the CLOOP command regardless of the status of the NCR signal during playback, but a prescribed command interval needs taking. Channel settings Channel CH0 CH1 CH2 CH3 Setting this bit to “1” releases repeat playback on channel 0. Setting this bit to “1” releases repeat playback on channel 1. Setting this bit to “1” releases repeat playback on channel 2. Setting this bit to “1” releases repeat playback on channel 3. Be sure to set the channel setting bits( CH0-CH3). CSB PLAY command 2nd byte SLOOP command CLOOP command SCK SI CBUSYB NCR (internal) tcm BUSYB (internal) SPM SPP Status 1/2VDD 1/2VDD Awaiting command Address being controlled Playing Command being processed Playing Awaiting command Command being processed 45/69 FEDL22Q553-02 ML22Q553 13. CVOL command x command 1 0 0 0 1 0 0 CV4 CH3 CV 3 CH2 CV 2 CH1 CV 1 CH0 CV 0 1st byte 2nd byte The CVOL command is used to adjust the playback volume on each channel. It is possible to input the VOL command regardless of the status of the NCR signal. The CVOL command can be set for each channel. The CVOL command allows specifying multiple channels at one time. Setting any bit(s) from CH0 to CH3 to “1” sets the playback volume on the corresponding channel(s). The volume setting is initialized by the AMODE command. Channel settings Channel CH0 CH1 CH2 CH3 Setting this bit to “1” sets the volume on channel 0. Setting this bit to “1” sets the volume on channel 1. Setting this bit to “1” sets the volume on channel 2. Setting this bit to “1” sets the volume on channel 3. Be sure to set the channel setting bits( CH0-CH3). The command enables 32-level adjustment of volume, as shown in the table below. The initial value after reset release is set to 0 dB. Upon reset release or when the PUP command is input, the values set by the CVOL command are initialized. CV4–0 1F 1E 1D 1C 1B 1A 19 18 17 16 15 14 13 12 11 10 Volume 0 dB (initial value) −0.28 −0.58 −0.88 −1.20 −1.53 −1.87 −2.22 −2.59 −2.98 −3.38 −3.81 −4.25 −4.72 −5.22 −5.74 CV4–0 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01 00 Volume −6.31 −6.90 −7.55 −8.24 −9.00 −9.83 −10.74 −11.77 −12.93 −14.26 −15.85 −17.79 −20.28 −23.81 −29.83 OFF 46/69 FEDL22Q553-02 ML22Q553 14. RDSTAT command x command 1 0 1 1 0 0 0 ERR The RDSTAT command enables reading the status of internal operation. It is possible to input the CLOOP command regardless of the status of the NCR signal during playback, but a prescribed command interval needs taking. The ERR bit selects reading the playback status for each channel or reading the status of the fail-safe function. Keep the SI pin to “L” when read the status. ERR Content of data to read 0 NCR and BUSYB signals for each channel (Initial value) 1 Status of the fail-safe function If the ERR bit is set to ”0”, the following status will be read: Output bit Output data D7 D6 D5 D4 D3 D2 D1 D0 BUSYB3 BUSYB2 BUSYB1 BUSYB0 NCR3 NCR2 NCR1 NCR0 When the ERR bit = ”0”, the NCR and BUSYB signals of each channel are read. The NCR signal outputs a “L” level while this LSI is performing command processing and goes to a “H” level when the LSI enters a command waiting state. The BUSY signal outputs a “L” level during voice playback. The table below shows the contents of each data output at a status read. Output status signal BUSY3 Channel 3 BUSYB output BUSY2 Channel 2 BUSYB output BUSY1 Channel 1 BUSYB output BUSY0 Channel 0 BUSYB output NCR3 Channel 3 NCR output NCR2 Channel 2 NCR output NCR1 Channel 1 NCR output NCR0 Channel 0 NCR output If the ERR bit is set to ”1”, the following status will be read: Output bit Output data D7 0 D6 0 D5 0 D4 0 D3 0 D2 TSDERR D1 BLDERR D0 WCMERR When the ERR bit = ”1”, the status of each fail-safe function is read. If any of the following three fail-safe functions is activated, the ERR pin is set to a “H” level and the corresponding error bit is set to “1”. If the ERR pinis set to a “H” level, check the error contents using the RDSTAT command and take appropriate measures. Error signal TSDERR BLDERR WCMERR Error contents High temperature error bit. This bit is set to “1” if the temperature of the LSI reaches or exceeds the temperature set by the SAFE command. For details see the section on the SAFE command. Power supply voltage error bit. This bit is set to “1” if the power supply voltage level reaches or falls below the voltage set by the SAFE command. For details see the section on the SAFE command. Command tansfer errro bit. This bit is set to “1” if a transfer error occurs in two-time command input mode. 47/69 FEDL22Q553-02 ML22Q553 If the ERR bit is set to “1”, the following status will be read Output bit OutPut data D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 SPMERR SPPERR TSDERR BLDERR WCMERR When the ERR bit=”1”, the state of five fail-safe Function is read. If any of fail-safe function is activated,the ERR pin is set to a “H” level and the corresponding error bit is set to “1”. If the ERR pins set to a “H” level, check the error contents using the RDSTAT command and take appropriate measures. ERR bit is cleared by ERCL command Error signal SPMERR SPPERR TSDERR BLDERR WCMERR Error contents SPM pin short error bit. This bit is set to “1” if the SPM pin is short to SPP pin or GND SPP pin short error bit This bit is set to “1” if the SPP pin is short to SPM pin or GND High temperature error bit. This bit is set to “1” if the temperature of the LSI reaches or exceeds the temperature set by the SAFE command. For details see the section on the SAFE command. Power supply voltage error bit. This bit is set to “1” if the power supply voltage level reaches or falls below the voltage set by the SAFE command. For details see the section on the SAFE command. Command tansfer errro bit. This bit is set to “1” if a transfer error occurs in two-time command input mode. If the ERR bit is set to “1”, the following status will be read Output bit OutPut data D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 SPMERR SPPERR TSDERR BLDERR WCMERR When the ERR bit=”1”, the state of five fail-safe functions is read. If any of fail-safe function is activated, the ERR pin is set to a “H” level and the corresponding error bit is set to “1”. If the ERR pins set to a “H” level, check the error contents using the RDSTAT command and take appropriate measures. ERR bit is cleared by ERCL command Error signal SPMERR SPPERR TSDERR BLDERR WCMERR Error contents SPM pin short error bit. This bit is set to “1” if the SPM pin is short to SPP pin or GND SPP pin short error bit This bit is set to “1” if the SPP pin is short to SPM pin or GND High temperature error bit. This bit is set to “1” if the temperature of the LSI reaches or exceeds the temperature set by the SAFE command. For details see the section on the SAFE command. Power supply voltage error bit. This bit is set to “1” if the power supply voltage level reaches or falls below the voltage set by the SAFE command. For details see the section on the SAFE command. Command tansfer errro bit. This bit is set to “1” if a transfer error occurs in two-time command input mode. 48/69 FEDL22Q553-02 ML22Q553 15. OUTSTAT command x command 1 1 0 0 0 BUSY/NCR C1 C0 The OUTSTAT command is used to output the BUSYB or NCR signal on the specified channel from the STATUS pin. It is possible to input the CLOOP command regardless of the status of the NCR signal during playback, but a prescribed command interval needs taking. OUTSTAT command OUTSTAT command CSB CSB SCK SCK SI SI CBUSYB CBUSYB NCR (internal) NCR (internal) BUSYB (internal) BUSYB (internal) STATUS STATUS BUSY/NCR STATUS pin status 0 Outputs the NCR signal on the specified channel. 1 Outputs the BUSYB signal on the specified channel. Channel settings C1 C0 Channel 0 0 1 1 0 1 0 1 Channel 0 (initial value) Channel 1 Channel 2 Channel 3 49/69 FEDL22Q553-02 ML22Q553 16. SAFE command x command 1 TM2 1 TM1 0 TM0 1 TSD1 0 TSD0 0 BLD2 0 BLD1 0 BLD0 The SAFE command is sets the settings for the low-voltage detection and temperature detection functions. The BLD2–0 bits are used to set the power supply voltage detection level. The judgment voltage can be selected from among six levels from 2.7 to 4.0 V. The power supply voltage is monitored each time it reaches the value set by TM2–0, and if the power supply voltage reaches or falls below the set detection voltage two times or more, the ERR pin outputs a ”H” level and the RDSTAT command’s BLDERR bit is set to ”1”. If the ERR pin is set to a ”H” level, check the error contents using the RDSTAT command. If the BLDERR bit is at ”1”, it is possibly a power supply related failure. BLD2 BLD1 BLD0 Judgment power supply voltage 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 OFF 2.7V±5% (initial value) 3.0V±5% 3.3V±5% 3.6V±5% 4.0V±5% (4.0V±5%) (4.0V±5%) The TSD1–0 bits are used to set the temperature detection level. Tj=140°C or OFF can be selected as the judgment temperature. The temperature is monitored each time it reaches the value set by TM2–0, and if the temperature reaches or exceeds the set value two times or more, the ERR pin outputs a ”H” level and the RDSTAT command’s TSDERR bit is set to ”1”. If the ERR pin is set to a ”H” level, check the error contents using the RDSTAT command. If the TSDERR bit is at ”1”, reduce the volume using the AVOL command or put the analog section into the power down state using the AMODE command. TSD1 TSD0 Judgment temperature (Tj) 0 0 OFF 0 1 Setting prohibited 1 1 0 1 Setting prohibited 140±10°C (initial valle,) The judgment temperature(Tj) is 140±10°C. This LSI is beyond Tj=130°C in the operating temperature(-40°C +150°C) depending on a operating condition and occurs by a high temperature error. The ambient temperature at that case is as follows. VDD Power supply(D 4.5V 5.0V 5.5V VDD =SP ) Power dissipation(PD) 0.686W 0.861W 1.055W Amient temperature(Ta) Not detect in the operating temperature detect more than 104°C detect more than 98°C *θja＝31.2[°C/W](JEDEC 2layers(refer to 67pages)), 1W/8ohm-Speaker 50/69 FEDL22Q553-02 ML22Q553 θja changes by an implementation condition. The maximum ambient temperature(Tamax) that this LSI does not detect the high temperature error is calculated in the following expressions in using the power dissipation. Tamax = 130[°C] - θja[°C/W] × PD[W] The maximum ambient temperature(Tamax) in power supply voltage 5.0V and θja=36[°C/W] is as follows. Tamax = 130[°C] - 36 × 0.861 ≒ 99[°C] The TM2–0 bits are used to set the monitor interval to detect a low voltage or temperature. TM2 0 0 0 0 1 1 1 1 TM1 0 0 1 1 0 0 1 1 TM0 0 1 0 1 0 1 0 1 Monitor interval Constantly monitors 2 ms (initial value) 4 ms 8 ms 16 ms 32 ms 64 ms 128 ms 51/69 FEDL22Q553-02 ML22Q553 17. ERCL command x command 1 1 1 1 1 1 1 1 The ERCL command is used to clear an error if it occurs. If an error occurs, a “H” level is outputted from the ERR pin. When the ERCL command is inputted, the ERR pin outputs a ”L” level. However, when the high temperature error and the power-supply voltage error continue, TSDERR of the RDSTAT command , BLDERR of the RDSTAT command and the ERR pin keep outputting "H" even if the ERCL command is inputted. Timing diagram for when an error occurs at the time of setting the two-time command input mode CSB START command ERCL command 2nd times 1st time VIH VIL ERCL command 2nd times tINTC SCK SI tCB1 CBUSYB VO H VOL NCRn (internal) VOH VOL BUSYBn (internal) ERR RDSTAT ERR register (internal) 00h 01h 00h 52/69 FEDL22Q553-02 ML22Q553 If a power supply voltage error occurs and then the power supply voltage is returned (when the SAFE command’s BLD2–0 bits = 001h) ERCL command CSB SCK SI tCB1 CBUSYB VOH VOL RDSTAT ERR register (internal) 00h 02h 00h ERR DVDD 3.0V 2.6V 3.0V If a power supply voltage error occurs but the power supply voltage is not returned ERCL command CSB SCK SI tCB1 CBUSYB RDSTAT ERR register (internal) VOH VOL 00h 02h ERR DVDD 3.0V 2.6V 53/69 FEDL22Q553-02 ML22Q553 When Speaker-short situation is released before Error Clear Flow(*1) Serial I/F RDSTAT ERR reg (internal) AMODE spkr_powerup RDSTAT 00h AMODE spkr_powerdown ERCL AMODE spkr_powerup 00h 10h (*2) ERR Speaker State short When Speaker-short situation is continued after Error Clear Flow(*1). Serial I/F RDSTAT ERR reg (internal) AMODE spkr_powerup RDSTAT 00h AMODE spkr_powerdown ERCL 10h (*2) AMODE spkr_powerup 00h 10h ERR Speaker State short When ERCL is inputed before Error Clear Flow(*1). Serial I/F RDSTAT ERRreg (internal) AMODE spkr_powerup 00h ERCL 10h (*2) RDSTAT 00h AMODE spkr_powerdown 10h (*2) ERCL 00h ERR State Speaker short *1:Error Clear Flow:RDSTAT=>AMODE(Speaker Power-down) => ERCL *2: SPM pin short error 54/69 FEDL22Q553-02 ML22Q553 Command Flow Charts 1-Byte Command Input Flow (applied to the PUP, PDWN, START, STOP, SLOOP, CLOOP, OUTSTAT, and ERCL commands) Start CBUSYB “H”? N Y Input command CBUSYB “H”? N Y End 2-Byte Command Input Flow (applied to the AMODE, AVOL, FAD, FADR, PLAY, MUON, CVOL, and SAFE commands) Start CBUSYB “H”? N Y Input the 1st byte of command CBUSYB “H”? N Y Input the 2nd byte of command CBUSYB “H”? N Y End Status Read Flow RDSTAT command CBUSYB “H”? N Y Read status (SI=”L”) 55/69 FEDL22Q553-02 ML22Q553 Power-On Flow Apply power, Drive RESETB “L” Waited for 10 μs? N Y Drive RESETB “H” Example of Power-Up Flow Power-down state PUP command AMODE command Example of Playback Start Flow Power-up state Idle (not playback)? Single-channel playback Y N Multi-channel playback FADR command PLAY command START command Example of Playback Stop Flow Playing STOP command 56/69 FEDL22Q553-02 ML22Q553 Continuous Playback Start Flow Playing Playback Within 10mS SLOOP command Loop Start Flow Playing Playback Within 10mS SLOOP command Loop Stop Flow Stop after playback is finished all the way through the phrase Looping Stop playback forcibly STOP command CLOOP command Power-Down Flow Power-up state PDWN command 57/69 FEDL22Q553-02 ML22Q553 Detailed Flow of “Power-Up ⇒ Playback ⇒ Power-Down” Power-down state CBUSYB “H”? A N Y RDSTAT command N Y CBUSYB “H”? N Y 1st byte of AMODE command CBUSYB “H”? N Y PUP command CBUSYB “H”? CBUSYB “H”? Read status N BUSYB “H”? Y N Y 2nd byte of AMODE command 1st byte of AMODE command CBUSYB “H”? N CBUSYB “H”? Y N Y 1st byte of PLAY command 2nd byte of AMODE command CBUSYB “H”? Y 2nd byte of PLAY command N CBUSYB “H”? N Y PDWN command A CBUSYB “H”? N Y Power-down state 58/69 FEDL22Q553-02 ML22Q553 Detailed flow of “SPP/SPM Short detecting” SPPERR/SPMERR ERR ”H” RDSTAT command CBUSYB ”H” N Y *It is confirmed that SPMERR or SPPERR is "H". Read status Playback end N STOP command Y 1st byte of AMODE command CBUSYB ”H” N Y 2nd byte of AMODE command CBUSYB ”H” * Speaker-Mode is set Power-Down. N Y ERCL command CBUSYB ”H” * Err-bit and Err-port are cleared. N Y waiting for command 59/69 FEDL22Q553-02 ML22Q553 1-Byte Command input flow of two-time command input mode （applied to the PDWN,STOP,SLOOP,CLOOP,RDSTAT,OUTSTAT,and ERCL commands） One-time command input One-time ERCL command input Two-time command input ERR ”L” Two-time ERCL command input N Y CBUSYB ”H” ERR N ”L” N Y Y CBUSYB ”H” End N Y One-time command input(Re-input) Two-time command input(Re-input) N ERR ”L” CBUSYB ”H” N Y End 60/69 FEDL22Q553-02 ML22Q553 2-Byte Command input flow of two-time command input mode （applied to the AMODE,AVOL,FAD,FADR,PLAY,MUON,CVOL, and SAFE commands） One-time command input (1Byte) Two-time command input (1Byte) One-time ERCL command input ERR ”L” N Two-time ERCL command input Y ERR N CBUSYB ”H” ”L” Y Y CBUSYB ”H” N Y One-time command input(1Byte)(Re-input) Two-time command input(1Byte) (Re-input) N ERR ”L” CBUSYB ”H” N Y One-time command input (2Byte) Two-time command input (2Byte) ERR ”L” N One-time ERCLcommand input Y CBUSYB ”H” Two-time ERCLcommand input N N Y End ERR ”L” Y CBUSYB ”H” N Y 61/69 FEDL22Q553-02 ML22Q553 Handling of the SG Pin The SG pin is the signal ground pin for the built-in speaker amplifier. Connect a capacitor between this pin and the analog ground so that this pin will not carry noise. The recommended capacitance value is shown below; however, it is recommended that the user determine the capacitance value after evaluation. Always start playback after each output voltage is stabilized. Pin Recommended capacitance value Remarks SG 0.1 μF ±20% The larger the connection capacitance, the longer the speaker amplifier output pin (SPM and SPP) voltage stabilization time. Handling of the VDDL and VDDR Pins The VDDL and VDDR pins are the power supply pins for the internal circuits. Connect a capacitor between each of these pins and the ground in order to prevent noise generation and power fluctuation. The recommended capacitance value is shown below; however, it is recommended that the user determine the capacitance value after evaluation. Always start the next operation after each output voltage is stabilized. Pin Recommended capacitance value VDDL, VDDR 10 μF ±20% Remarks The larger the connection capacitance, the longer the stabilization time. 62/69 FEDL22Q553-02 ML22Q553 Power Supply Wiring The power supplies of this LSI are divided into the following two: • Digital power supply (DVDD) and Digital ground(DGND) • Speaker amplifier power supply (SPVDD) and Speaker amplifier ground(SPGND) As shown in the figure below, be sure to diverge the wiring of DVDD and SPVDD from the root of the same power supply. DGND/SPGND is similar, too. DVDD DGND 5V SPVDD SPGND 63/69 FEDL22Q553-02 ML22Q553 APPLICATION CIRCUIT At using internal speaker amplifier (speaker output) RESETB CSB SCK SI SO CBUSYB ERR STATUS MCU SPM SPP speaker SG AIN 0.1μF 0.1μF DIPH VPP TESTI1 15pF XT 4.096MHz XTB 15pF VDDL VDDR DVDD SPVDD 0.1μF DGND 10μF 10μF 10μF 0.1μF 10μF 5V SPGND At using external speaker amplifier (line output) RESETB CSB SCK SI SO CBUSYB ERR STATUS MCU SPM SPP 0.1μF SP-AMP speaker SG 0.1μF AIN 0.1μF DIPH VPP TESTI1 15pF XT VDDL VDDR DVDD SPVDD 0.1μF 4.096MHz XTB DGND 15pF 10μF 10μF 0.1μF 10μF 10μF 5V SPGND 64/69 FEDL22Q553-02 ML22Q553 RECOMMENDED CERAMIC OSCILLATION Recommended ceramic resonators for oscillation and conditions are shown below for reference. KYOCERA Corporation Optimal load capacity Freq [Hz] Type 4.096M PBRV4.096MR50Y000 C1 [pF] C2 [pF] 15(internal) Rf Rd Supply voltage [Ohm] [Ohm] Range [V] --- -- 4.5 to 5.5 Operating Temperature Range [°C] -40 to +125 MURATA Corporation Optimal load capacity Freq [Hz] Type 4M CSTCR4M00G55B-R0 4.096M CSTCR4M09G55B-R0 C1 [pF] C2 [pF] 39(internal) Rf Rd Supply voltage [Ohm] [Ohm] Range [V] --- -- 4.5 to 5.5 Operating Temperature Range [°C] -40 to +125 Circuit diagram VDD DVDD/SPVDD DGND/ SPGND GND XT C1 XTB C2 65/69 FEDL22Q553-02 ML22Q553 LIMITATION ON THE OPERATION TIME (PLAY-BACK TIME) ML22Q553’s operating temperature is 105°C. But the average ambient temperature at 1W play-back (8ohm drive) during 10 years in the reliability design is Ta=70°C. (max ( the package heat resistance θ ja=24.6[°C/W]) ) When ML22Q553 operates 1W play-back(8ohm drive) consecutively, the product life changes by the package temperature rise by the consumption. This limitation does not matter in the state that a speaker amplifier does not play. The factor to decide the operation time ( play-back time ) is the average ambient temperature( Ta ), play-back Watts( at the speaker drive mode), the soldering area ratio*1, and so on. In addition, the limitation on the operation time changes by the heat designs of the board. PACKAGE HEAT RESISTANCE VALUE (REFERENCE VALUE) The following table is the package heat resistance value θja (reference value). This value changes the condition of the board (size, layer number, and so on) The board θja The condition *1 JEDEC 4layers （W/L/t＝76.2/114.5/1.6（mm）） 24.6[°C /W] *2 JEDEC 2layers （W/L/t＝76.2/114.5/1.6（mm）） 31.2[°C /W] No wind (0m/sec) the soldering area ratio*3：100% *1 : The wiring density : 1st layer(Top) 60% / 2nd layer 100% / 3rd layer 100% / 4th layer(Bottom) 60%. *2 : The wiring density : 1st layer(Top) 60% / 2nd layer(Bottom) 100%. *3 : The soldering area ratio is the ratio that the heat sink area of ML22Q553 and a land pattern on the board are soldered. 100% mean that the heat sink area of ML22Q553 is completely soldered to the land pattern on the board. About the land pattern on the board, be sure to refer to the next clause (PACKAGE DIMENSIONS). 66/69 FEDL22Q553-02 ML22Q553 PACKAGE DIMENSIONS Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact ROHM’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). Notes for heat sink type Package This LSI adopts a heat sink type package to raise a radiation of heat characteristic. Be sure to design the land pattern corresponding to the heat sink area of the LSI on a board, and solder each other. The heat sink area of the LSI solder open or GND on the board. 67/69 FEDL22Q553-02 ML22Q553 Revision History Document No. Date FEDL22Q553FULL-01 Jun. 19, 2012 FEDL22Q553-02 Apr. 25, 2013 Page Previous Current Edition Edition Description – – Formally edition 1. 11 11 Add tCB3. 16 16 Change Playback Stop Timing. 68/69 FEDL22Q553-02 ML22Q553 NOTES No copying or reproduction of this document, in part or in whole, is permitted without the consent of LAPIS Semiconductor Co., Ltd. The content specified herein is subject to change for improvement without notice. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, LAPIS Semiconductor shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. LAPIS Semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by LAPIS Semiconductor and other parties. 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If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law. Copyright 2012-2013 LAPIS Semiconductor Co., Ltd. 69/69