a min i l e Pr c. Spe MITSUBISHI LSIs ry Rev. 1.0 Oct./4/95 MH1M144CXTJ-6 FAST PAGE MODE 150994944-BIT (1048576-WORD BY 144-BIT)DYNAMIC RAM 2pin 1pin 99pin The MH1M144CXTJ is 1048576-word by 144-bit dynamic RAM module. This consists of nine industry standard 1Mx16 dynamic RAMs in TSOP and one industry standard input buffer in T-SSOP. The mounting of TSOP on a card edge Dual Read Out package provides any application where high densities and large quantities of memory are required. This is a socket type - memory modules, suitable for easy interchange or addition of modules. 100pin DESCRIPTION FEATURES RAS CAS Address Cycle access access time time (max.ns) (max.ns) -6 65 20 access time (max.ns) 35 time (min.ns) 110 single 5V±5% supply All input, output TTL compatible and low capacitance 101pin 199pin APPLICATION 102pin Includes decoupling capacitor(0.22µFx19) 200pin 1024 refresh cycle every 16.4ms(A0~A9) Main memory unit for computer,Microcomputer memory MITSUBISHI ELECTRIC ( 1 /14 ) a min i l e Pr c. Spe MITSUBISHI LSIs ry Rev. 1.0 Oct./4/95 MH1M144CXTJ-6 FAST PAGE MODE 150994944-BIT (1048576-WORD BY 144-BIT)DYNAMIC RAM BLOCK DIAGRAM 10 ohm Input Buffer : ABT16244 OR SAME EQUIPMENT /WE /CAS1 /CAS0 /RAS0 D0 D1 D2 D3 D32 D33 D34 D35 D8 D9 D10 D11 D40 D41 D42 D43 D7 D6 D5 D4 D39 D38 D37 D36 D15 D14 D13 D12 D47 D46 D45 D44 D16 D17 D18 D19 D48 D49 D50 D51 D24 D25 D26 D27 D56 D57 D58 D59 D23 D22 D21 D20 D55 D54 D53 D52 D31 D30 D29 D28 D63 D62 D61 D60 CBW0 CBW1 CBW2 CBW3 CBW4 CBW5 CBW6 CBW7 A0-A9 /RAS /UCAS /WE /OE & /LCAS /OE /WE /UCAS /RAS & /LCAS M5M418160CTP IC1 M5M418160CTP IC6 /RAS /UCAS /WE /OE & /LCAS /OE /WE /UCAS /RAS & /LCAS M5M418160CTP IC2 M5M418160CTP IC7 /RAS /UCAS /WE /OE & /LCAS /OE /WE /UCAS /RAS & /LCAS M5M418160CTP IC3 M5M418160CTP IC8 /RAS /UCAS /WE /OE & /LCAS /OE /WE /UCAS /RAS & /LCAS M5M418160CTP IC4 M5M418160CTP IC9 /RAS /LCAS /WE /OE DQ1 - DQ8 /UCAS M5M418160CTP IC5 IC1 to IC9 VCC VSS IC1 to IC9 0.22uF x2 per each IC BUffer 0.22uF MITSUBISHI ELECTRIC ( 2 /14 ) DQ9 - DQ16 D64 D65 D66 D67 D96 D97 D98 D99 D72 D73 D74 D75 D104 D105 D106 D107 D71 D70 D69 D68 D103 D102 D101 D100 D79 D78 D77 D76 D111 D110 D109 D108 D80 D81 D82 D83 D112 D113 D114 D115 D88 D89 D90 D91 D120 D121 D122 D123 D87 D86 D85 D84 D119 D118 D117 D116 D95 D94 D93 D92 D127 D126 D125 D124 CBW8 CBW9 CBW10 CBW11 CBW12 CBW13 CBW14 CBW15 a min i l e Pr c. Spe MITSUBISHI LSIs ry Rev. 1.0 Oct./4/95 MH1M144CXTJ-6 FAST PAGE MODE 150994944-BIT (1048576-WORD BY 144-BIT)DYNAMIC RAM PIN CONFIGURATION PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PIN NAME VSS VSS D0 D7 D1 D6 D2 D5 D3 D4 D32 D39 D33 D38 D34 D37 VCC VCC D35 D36 D8 D15 D9 D14 D10 D13 D11 D12 D40 D47 D41 D46 VSS VSS D42 D45 D43 D44 D16 D23 D17 D22 D18 D21 D19 D20 D48 D55 VCC VCC PIN NO. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 PIN NAME D49 D54 D50 D53 D51 D52 D24 D31 D25 D30 D26 D29 D27 D28 VSS VSS D56 D63 D57 D62 D58 D61 D59 D60 CBW0 CBW7 CBW1 CBW6 CBW2 CBW5 VCC VCC CBW3 CBW4 CAS0 CAS1 RAS0 NC NC NC NC NC A0 A1 A2 A3 A4 A5 VSS VSS PIN NO. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 MITSUBISHI ELECTRIC ( 3 /14 ) PIN NAME VSS VSS A6 A7 A8 A9 NC NC NC WE NC NC VSS VSS VSS VSS CBW8 CBW15 VCC VCC CBW9 CBW14 CBW10 CBW13 CBW11 CBW12 D64 D71 D65 D70 D66 D69 D67 D68 VSS VSS D96 D103 D97 D102 D98 D101 D99 D100 D72 D79 D73 D78 D74 D77 PIN NO. 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 PIN NAME VCC VCC D75 D76 D104 D111 D105 D110 D106 D109 D107 D108 D80 D87 D81 D86 VSS VSS D82 D85 D83 D84 D112 D119 D113 D118 D114 D117 D115 D116 D88 D95 VCC VCC D89 D94 D90 D93 D91 D92 D120 D127 D121 D126 D122 D125 D123 D124 VSS VSS a min i l e Pr c. Spe MITSUBISHI LSIs ry Rev. 1.0 Oct./4/95 MH1M144CXTJ-6 FAST PAGE MODE 150994944-BIT (1048576-WORD BY 144-BIT)DYNAMIC RAM FUNCTION a number of other functions, e.g., fast page mode, RASonly refresh.The input conditions for each are shown in Table 1. The MH1M144CXTJ provide, in addition to normal read, write operation, Table 1. Input conditions for each mode Inputs Operation Input/Output NAC Row address APD Column address APD ACT APD APD NAC DNC APD ACT ACT NAC ACT ACT DNC NAC DNC DNC RAS CAS W Read ACT ACT Write (Early write) ACT ACT RAS-only refresh ACT Hidden refresh CAS before RAS refresh Standby Refresh Input Output OPN VLD YES APD OPN YES DNC DNC OPN YES DNC DNC OPN VLD YES DNC DNC DNC OPN YES DNC DNC DNC OPN NO Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid,APD : applied, OPN : open MITSUBISHI ELECTRIC ( 4 /14 ) Remark Fast page mode identical a min i l e Pr c. Spe MITSUBISHI LSIs ry Rev. 1.0 Oct./4/95 MH1M144CXTJ-6 FAST PAGE MODE 150994944-BIT (1048576-WORD BY 144-BIT)DYNAMIC RAM ABSOLUTE MAXIMUM RATINGS Symbol Parameter Ratings Unit -1 ~ 7 V V Output voltage -1 ~ 7 -1 ~ 7 I0 Output current 50 mA Pd Power dissipation Topr Operating temperature Tstg Storage temperature Vcc Supply voltage VI V0 Input voltage Conditions With respect to Vss Ta=25°C RECOMMENDED OPERATING CONDITIONS Symbol 21.6 W 0 ~ 70 °C -40 ~ 100 °C (Ta=0 ~ 70°C, unless otherwise noted) (Note 1) Limits Parameter V Min Nom Max Unit Vcc Supply voltage 4.75 5 5.25 V Vss Supply voltage 0 0 0 V VIH High-level input voltage, I/O pins 2.4 5.5 V VIH High-level input voltage, non I/O pins 2.0 5.5 V VIL Low-level input voltage, I/O pins -1.0 0.8 V VIL Low-level input voltage, non I/O pins -0.5 0.8 V Note 1 : All voltage values are with respect to Vss ELECTRICAL CHARACTERISTICS Symbol (Ta=0 ~ 70°C , Vcc=5.0V ± 5%, Vss=0V, unless otherwise noted) (Note 2) Parameter Test conditions VOH High-level output voltage IOH=-5.0mA VOL Low-level output voltage IOL=4.2mA IOZ Off-state output current Input current II Icc(note 3) Operating Current Average Limits Min Typ Max Unit 2.4 Vcc 0 0.4 V Q floating 0V ≤ VOUT ≤ 5.5V -10 10 µA 0V ≤ VIN ≤ 6.5V, Other inputs pins=0V -10 10 3.3 µA A 13%Fase Page mode and 87% CBR Refresh mode V Note 2: Current flowing into an IC is positive, out is negative. 3: tRC = tRC(min.) Icc is depend on cycle rate. CAPACITANCE Symbol (Ta=0 ~ 70 °C, Vcc=5.0V ± 5%, Vss=0V, unless otherwise noted) Parameter Test conditions Limits Min Typ Max Unit CI1 Input capacitance, address inputs VI=Vss 17 pF CI2 Input capacitance, clocks inputs 15 pF CI3 Input/Output capacitance f=1MHZ Vi=25mVrms 17 pF MITSUBISHI ELECTRIC ( 5 /14 ) a min i l e Pr c. Spe MITSUBISHI LSIs ry Rev. 1.0 Oct./4/95 MH1M144CXTJ-6 FAST PAGE MODE 150994944-BIT (1048576-WORD BY 144-BIT)DYNAMIC RAM AC CHARACTERISTICS Symbol (Ta=0 ~70 °C, Vcc=5.0V ± 5%, Vss=0V, unless otherwise noted , see notes 4,5,6) Parameter Min Max Unit Notes ns tRC Random Read or Write Cycle Time 110 tPC Fast Page Mode Cycle Time tRAC Access time from /RAS 65 ns 7 tCAC tAA Access time from /CAS 20 ns 7 Access Time from Column Address 35 ns 7 tCPA Access time from /CAS precharge 40 ns tCLZ tOFF CAS to Output in Low Z Output Buffer Turn-Off Delay time 5 1 20 ns 10 tT Transition Time(Rise And Fall) 3 12 ns 4 tRP /RAS Precharge Time 40 tRAS /RAS Pulse Width 60 tRSH /RAS Hold Time 18 tCSH /CAS Hold Time 60 tCAS /CAS Pulse Width 10K ns tRCD /RAS to /CAS Delay Time 20 20 43 ns tRAD /RAS to Column Address Delay Time 15 30 ns 8 9 tCRP /CAS to /RAS Precharge Time 10 ns 11 tCP /CAS Precharge Time 10 ns tASR Row Address Setup Time 0 ns tRAH Row Address Hold Time 10 ns tASC Column Address Setup Time 0 ns tCAH Column Address Hold Time 15 ns tAR Column Address Hold Time Ref to /RAS 50 ns tRAL Column Address Lead Time Ref to /RAS 30 ns tCAL Column Address Lead Time Ref to /CAS 30 ns tRCS 0 ns tRCH Read Command Setup Time Read Command Hold Time Ref to /CAS 0 ns 12 tRRH Read Command Hold Time Ref to /RAS 10 ns tWCS Write Command Setup Time 0 12 14 tWCH Write Command Hold Time 15 ns ns tWCR Write Command Hold Time Ref to /RAS 45 ns tWP Write Commnad Pulse Width 15 ns tRWL Write Command to /RAS Lead Time 15 ns tCWL Write Command to /CAS Lead Time 15 ns tDS Data Setup Time 0 ns 13 tDH 20 ns 13 tDHR Data Hold Time Data Hold Time Ref to /RAS 45 ns tREF Refresh Period tCSR /CAS Setup Time(CBR) 10 ns tCHR /CAS Hold Time(CBR) 20 ns tRPC /RAS to /CAS Precharge Time 10 ns tCPN /CAS Precharge Time(Non Page Mode) 10 ns tWRP /WE Setup(CBR Refresh) 10 ns tWRH /WE Hold(CBR Refresh) 10 ns tRHP Write to RAS Hold Time 35 ns 40 ns ns ns 10K ns ns ns 16.4 ms 15 Note 4: VIH Min and VIL Max are reference levels for measuring timing of inputs signals.Also,transition times are measured between VIH and VIL 5: An initial pause of 500us is required after power-up followed by 8 CBR cycles before proper device operation is achived. 6: AC measurements assume tT = 5ns. 7: Load = 2TTL loads and 100pF. 8: Operation within the tRCD Max limit insures that tRAC Max can be met.tRCD Max is specified as a reference point only.If tRCD is greater than the specified tRCD Max limit,then access time is controlled by tCAC. 9: Operation within the tRAD Max limit insures that tRAC Max can be met.tRAD Max is specified as a reference point only.If tRAD is greater than the specified tRAD Max limit,then access time is controlled by tAA. 10: tOFF Max defines the time at which the output achieves the open circuit conditon and is not referenced to VOH or VOL. 11: The tCRP requirement should be applicable for /RAS-/CAS cycles preceeded by any cycle. 12: Either tRRH or tRCH must be satisfied for a read cycle. 13: These parameters are referenced to the falling edge of /CAS for early write cycles. MITSUBISHI ELECTRIC ( 6 /14 ) a min i l e Pr c. Spe MITSUBISHI LSIs ry Rev. 1.0 Oct./4/95 MH1M144CXTJ-6 FAST PAGE MODE 150994944-BIT (1048576-WORD BY 144-BIT)DYNAMIC RAM Note 14 : If tWCS ≥ tWCS Min,the cycle is an early write cycle and dataout pin will remain open circuit(high impedance). 15 : 1024 refresh cycle for 16M. MITSUBISHI ELECTRIC ( 7 /14 ) a min i l e Pr c. Spe MITSUBISHI LSIs ry Timing Diagrams Read Cycle Rev. 1.0 Oct./4/95 MH1M144CXTJ-6 FAST PAGE MODE 150994944-BIT (1048576-WORD BY 144-BIT)DYNAMIC RAM (Note 16) tRC tRAS RAS tRP VIH VIL tCSH tCRP CAS tRCD tRPC tRSH tCAS tCRP VIH VIL tASR VIH A0~A9 VIL tRAD tRAL tRAH tASC ROW ADDRESS tASR tCAH tCPN ROW ADDRESS COLUMN ADDRESS tRRH tRCH tRCS W VIH VIL tCAC tAA tOFF tCLZ VOH DQ Hi-Z DATA VALID Hi-Z VOL tRAC Indicates the don't care input. VIH(min)≤VIN≤VIH(max) or VIL(min)≤VIN≤VIL(max) Note 16 Indicates the invalid output. MITSUBISHI ELECTRIC ( 8 /14 ) a min i l e Pr c. Spe MITSUBISHI LSIs ry Rev. 1.0 Oct./4/95 MH1M144CXTJ-6 FAST PAGE MODE 150994944-BIT (1048576-WORD BY 144-BIT)DYNAMIC RAM Write Cycle (Early write) tWC tRAS RAS tRP VIH VIL tCSH tCRP CAS tRCD tRSH tCAS tRPC tCRP VIH VIL tASR VIH A0~A9 VIL tASR tRAH tCAH tASC ROW ADDRESS tWCS W ROW ADDRESS COLUMN ADDRESS tWCH VIH VIL tDH tDS DQ VIH DATA VALID VIL MITSUBISHI ELECTRIC ( 9 /14 ) a min i l e Pr c. Spe MITSUBISHI LSIs ry Rev. 1.0 Oct./4/95 MH1M144CXTJ-6 FAST PAGE MODE 150994944-BIT (1048576-WORD BY 144-BIT)DYNAMIC RAM RAS-only Refresh Cycle tRC tRAS RAS tRP VIH VIL tRPC tCRP tCRP VIH CAS VIL tASR VIH A0~A9 VIL W tRAH tASR ROW ADDRESS ROW ADDRESS VIH VIL DQ VOH Hi-Z VOL MITSUBISHI ELECTRIC (10 /14 ) a min i l e Pr c. Spe MITSUBISHI LSIs ry Rev. 1.0 Oct./4/95 MH1M144CXTJ-6 FAST PAGE MODE 150994944-BIT (1048576-WORD BY 144-BIT)DYNAMIC RAM CAS before RAS Refresh Cycle tRC tRP RAS tRC tRAS tRAS tRP VIH VIL tRPC tCSR tCHR tRPC tCSR tCHR tRPC tCRP VIH CAS VIL tCPN tASR VIH ROW ADDRESS A0~A9 VIL tRCH VIH W VIL tOFF VOH DQ Hi-Z VOL MITSUBISHI ELECTRIC (11 /14 ) COLUMN ADDRESS a min i l e Pr c. Spe MITSUBISHI LSIs ry Rev. 1.0 Oct./4/95 MH1M144CXTJ-6 FAST PAGE MODE 150994944-BIT (1048576-WORD BY 144-BIT)DYNAMIC RAM Hidden Refresh Cycle (Read) (Note 17) tRC tRC tRAS RAS tRP tRAS tRP VIH VIL tCRP CAS tRCD tRSH tCHR VIH VIL tRAD tASR VIH A0~A9 VIL tRAH tASC ROW ADDRESS tASR tCAH ROW ADDRESS COLUMN ADDRESS tRCS tRAL W tRRH VIH VIL tCAC tAA tOFF tCLZ DQ VOH Hi-Z DATA VALID VOL tRAC Note 17: Early write is applicable instead of read cycle. Timing requirements and output state are the same as that of each cycle shown above. MITSUBISHI ELECTRIC (12 /14 ) Hi-Z a min i l e Pr c. Spe MITSUBISHI LSIs ry Rev. 1.0 Oct./4/95 MH1M144CXTJ-6 FAST PAGE MODE 150994944-BIT (1048576-WORD BY 144-BIT)DYNAMIC RAM Fast Page Mode Read Cycle tRAS RAS tRP VIH VIL tCSH tCRP CAS tPC tRCD tCAS tCP tCAS tRSH tCAS tCP VIH VIL tASR A0~A9 VIH VIL tRAD tRAH tCPRH tASC ROW ADDRESS tASC tCAH tCAH tASC COLUMN-2 COLUMN-1 tCAH W tRCH ROW ADDRESS COLUMN-3 tRAL tRCS tASR tRCS tRCH tRCS tRRH tRCH VIH VIL tCAC tCAC tCAC tAA tAA tAA tCLZ DQ VOH tOFF tCLZ VOL tRAC tCPA MITSUBISHI ELECTRIC (13 /14 ) tCLZ DATA VALID-2 DATA VALID-1 Hi-Z tOFF tOFF DATA VALID-3 tCPA a min i l e Pr c. Spe MITSUBISHI LSIs ry Rev. 1.0 Oct./4/95 MH1M144CXTJ-6 FAST PAGE MODE 150994944-BIT (1048576-WORD BY 144-BIT)DYNAMIC RAM Fast Page Mode Write Cycle (Early Write) tRAS RAS tRP VIH VIL tCSH tCRP tRCD tPC tCAS tCP tCAS tRSH tCAS tCP VIH CAS VIL tASR VIH A0~A9 VIL W tRAH ROW ADDRESS tCAH tASC tCAH tASC COLUMN-2 COLUMN-1 tCAH tASC COLUMN-3 tWCS tWCH tWCS tWCH tWCS tDS tDH tDS tDH tDS tWCH VIH VIL DQ VIH VIL DATA VALID-1 DATA VALID-2 MITSUBISHI ELECTRIC (14 /14 ) tDH DATA VALID-3 tASR ROW ADDRESS