TI1 LM3560TLX/NOPB Synchronous boost flash driver Datasheet

LM3560
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SNOSB43B – SEPTEMBER 2011 – REVISED AUGUST 2013
Synchronous Boost Flash Driver
With Dual 1-A High-Side Current Sources (2-A Total Flash Current)
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FEATURES
APPLICATIONS
•
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1
2
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•
•
•
•
•
•
•
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•
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Dual High-Side Current Sources Allow for
Grounded Cathode LED Operation
Accurate and Programmable LED Current from
31.25 mA to 2 A
Independent LED Current Source
Programmability
Up to 90% Efficient
Ultra-Small Solution Size: < 26 mm2
Four Operating Modes: Torch, Flash, Privacy
Indicate, and Message Indicator
4-Bit ADC for VLED Monitoring
LED Thermal Sensing and Current Scale-Back
Hardware Flash and Torch Enable
Dual Synchronization Inputs for RF Power
Amplifier Pulse Events
LED and Output Disconnect During Shutdown
Open and Short LED Detection
400-kHz I2C-Compatible Interface
Active Low Hardware Reset
16-Bump (1.97mm x 1.97mm x 0.6mm) DSBGA
Camera Phone LED Flash
White LED Biasing
DESCRIPTION
The LM3560 is a 2MHz fixed frequency synchronous
boost converter with two 1000 mA constant current
drivers for high-current white LEDs. The dual highside current sources allow for grounded cathode LED
operation and can be tied together for providing flash
currents at up to 2A through a single LED. An
adaptive regulation method ensures the current for
each LED remains in regulation and maximizes
efficiency.
Typical Application Circuit
1 PH/2.2 PH
SW
IN
2.5V to 5.5V
10 PF
OUT
10 PF
LM3560
LED1
HWEN
STROBE
LED2
LEDI/NTC
SCL
Flash
LED1
Flash
LED2
TX1/TORCH
TX2
SDA
GND
Optional Indicator Current
Source or Thermistor
Sensing Circuit
Table 1. Application Circuit Component List
Component
Manufacturer
Value
Part Number
Size (mm)
Rating
L
Toko
1µH
FDSD0312-1R0
3 x 3 x 1.2
3.4A
COUT
Murata
10 µF
GRM188R60J106M
1.6 × 0.8 × 0.8 (0603)
6.3V
1.6 × 0.8 × 0.8 (0603)
CIN
Murata
10 µF
GRM188R60J106M
LEDs
Lumiled
Flash LED
PWF-4
6.3V
VF = 3.6V @1A
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2013, Texas Instruments Incorporated
LM3560
SNOSB43B – SEPTEMBER 2011 – REVISED AUGUST 2013
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DESCRIPTION (CONTINUED)
The LM3560 is controlled via an I2C-compatible interface. Features include: an internal 4-bit ADC to monitor the
LED voltage, independent LED current control, a hardware flash enable allowing a logic input to trigger the flash
pulse, dual TX inputs which force the flash pulse into a low-current torch mode allowing for synchronization to RF
power amplifier events or other high-current conditions, and an integrated comparator designed to monitor an
NTC thermistor and provide an interrupt to the LED current. Additionally, an active high HWEN input provides a
hardware shutdown during system software failures.
The 2MHz switching frequency, over-voltage protection and adjustable current limit allow for the use of tiny, lowprofile (1 µH and 2.2 µH) inductors and (10 µF) ceramic capacitors. The device is available in a ultra-small 16bump (1.97mm x 1.97mm x 0.6mm) DSBGA package and operates over the −40°C to +85°C temperature range.
Connection Diagram
Top View
A1
A2
A3
A4
B1
B2
B3
B4
C1
C2
C3
C4
D1
D2
D3
D4
16-Bump 1.97 mm x 1.97 mm x 0.6 mm DSBGA Package YZR0016
PIN DESCRIPTIONS
Pin
Name
A1
LED1
High Side Current Source Output for Flash LED.
A2, B2
OUT
Step-Up DC/DC Converter Output. Connect a 10 µF ceramic capacitor between this pin and GND.
A3, B3
SW
Drain Connection for Internal NMOS and Synchronous PMOS Switches.
A4, B4
GND
Ground
LED2
High-Side Current Source Output for Flash LED.
B1
C1
LEDI/NTC
Function
Configurable as a High-Side Current Source Output for Indicator LED or Comparator Input for LED
Temperature Sensing.
C2
TX1/TORCH/
GPIO1
Configurable as a Dual-Polarity RF Power Amplifier Synchronization Input, an Interrupt Output, or as
a General Purpose Logic I/O. This pin has an internal 300kΩ pull down to GND.
C3
STROBE
Active High Hardware Flash Enable. Drive STROBE high to turn on the Flash pulse. This pin has an
internal 300 kΩ pull down to GND.
C4
IN
Input Voltage Connection. Connect IN to the input supply, and bypass to GND with a minimum 10
µF ceramic capacitor.
D1
TX2/INT/GPIO2
Configurable as a Dual-Polarity Power Amplifier Synchronization Input, an Interrupt Output, or as a
General Purpose Logic I/O. This pin has an internal 300 kΩ pull down to GND.
D2
SDA
Serial Data Input/Output. High impedance in shutdown or in power down.
D3
SCL
Serial Clock Input. High impedance in shutdown or in power down.
D4
HWEN
Logic High Hardware Enable. HWEN is a high impedance input and is normally connected with an
external pull up resistor to a logic high voltage.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
2
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ABSOLUTE MAXIMUM RATINGS
(1) (2) (3)
−0.3V to 6V
VIN, VSW, VOUT
VSCL, VSDA, VHWEN, VSTROBE, VTX1, VTX2, VLED1, VLED2, VLED1/NTC
−0.3V to the lesser of (VIN+0.3V) or 6.0V
Continuous Power Dissipation (4)
Internally Limited
Junction Temperature (TJ-MAX)
+150°C
−65°C to +150°C
Storage Temperature Range
(5)
Maximum Lead Temperature (Soldering)
(1)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings are conditions under
which operation of the device is specified. Operating Ratings do not imply specified performance limits. For performance limits and
associated test conditions, see the Electrical Characteristics table.
All voltages are with respect to the potential at the GND pin.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ=+150°C (typ.) and
disengages at TJ=+135°C (typ.). Thermal shutdown is specified by design.
For detailed soldering specifications and information, see Application Note AN1112 DSBGA Wafer Level chip Scale Package.
(2)
(3)
(4)
(5)
OPERATING RATINGS
(1) (2)
VIN
2.5V to 5.5V
−40°C to +125°C
Junction Temperature (TJ)
Ambient Temperature (TA)
(1)
(3)
−40°C to +85°C
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings are conditions under
which operation of the device is specified. Operating Ratings do not imply specified performance limits. For performance limits and
associated test conditions, see the Electrical Characteristics table.
All voltages are with respect to the potential at the GND pin.
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP =
+125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the
part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX).
(2)
(3)
THERMAL PROPERTIES
Thermal Junction-to-Ambient Resistance (θJA) (1)
(1)
50.4°C/W
Junction-to-ambient thermal resistance (θJA) is taken from a thermal modeling result, performed under the conditions and guidelines set
forth in the JEDEC standard JESD51-7. The test board is a 4-layer FR-4 board measuring 102 mm x 76 mm x 1.6 mm with a 2x1 array
of thermal vias. The ground plane on the board is 50 mm x 50 mm. Thickness of copper layers are 36 µm/18 µm/18 µm/36 µm (1.5
oz/1oz/1oz/1.5 oz). Ambient temperature in simulation is 22°C, still air. Power dissipation is 1W.
ELECTRICAL CHARACTERISTICS
(1) (2)
Limits in standard typeface are for TA = +25°C. Limits in boldface type apply over the full operating ambient temperature
range (−40°C ≤ TA ≤ +85°C). Unless otherwise specified, VIN = 3.6V, VHWEN = VIN.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
Current Source Specifications
Current Source
Accuracy
ILED
VOUT VLED1/2
(1)
(2)
Current Source
Regulation Voltage
ILED1+ILED2,
VOUT = 4.5V,
3.0V ≤ VIN ≤ 4.2V
−40°C ≤ TA ≤
1000mA Flash
Current Setting, per +85°C
current source
TA = +25°C
31.25mA Torch
−40°C ≤ TA ≤
Current Setting, per
+85°C
current source
ILED = 2A, (ILED1 + ILED2)
VOUT = 4.5V
-5%
2000
−3.5%
−10%
+5%
+3.5%
62.5
mA
+10%
300
mV
All voltages are with respect to the potential at the GND pin.
Min and Max limits are specified by design, test, or statistical analysis. Typical (Typ) numbers represent the most likely norm. Unless
otherwise specified, conditions for typical specifications are: VIN = 3.6V and TA = +25°C.
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ELECTRICAL CHARACTERISTICS
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(1) (2)
(continued)
Limits in standard typeface are for TA = +25°C. Limits in boldface type apply over the full operating ambient temperature
range (−40°C ≤ TA ≤ +85°C). Unless otherwise specified, VIN = 3.6V, VHWEN = VIN.
Symbol
Parameter
Output OverVoltage Protection
Trip Point (3)
VOVP
Test Conditions
ON Threshold
Min
Typ
Max
4.925
5
5.075
OFF Threshold
Unit
V
4.8
Step-Up DC/DC Converter Specifications
RPMOS
PMOS Switch OnResistance
IPMOS = 1A
80
mΩ
RNMOS
NMOS Switch OnResistance
INMOS = 1A
65
mΩ
Switch Current
Limit (4)
ICL
CL bits = 00, 3.0V ≤ VIN ≤ 4.2V
1.44
1.6
1.76
CL bits = 01, 3.0V ≤ VIN ≤ 4.2V
2.02
2.3
2.58
CL bits = 10, 3.0V ≤ VIN ≤ 4.2V
2.64
3.0
3.36
CL bits = 11, 3.0V ≤ VIN ≤ 4.2V
3.17
3.6
4.03
IOUT_SC
Output Short
Circuit Current
Limit
VOUT < 2.3V
ILED/NTC
Indicator Current
Message Indicator Register, bits[2:0] = 111, 3.0V ≤ VIN ≤ 4.2V,
VLEDI/NTC = 2V
VTRIP
Comparator Trip
Threshold
fSW
300
A
mA
16
18
20
mA
Configuration Register 1, bit4 = 1, 3.0V ≤ VIN ≤ 4.2V
0.97
1
1.03
V
Switching
Frequency
3.0V ≤ VIN ≤ 4.2V
1.8
2
2.2
MHz
tTIMEOUT
Timeout Duration
(5) (6)
,
3.0V ≤ VIN ≤ 4.2V
−10%
+10%
ms
IQ
Quiescent Supply
Current
Device Not Switching, VOUT = 3V
900
µA
Device Switching, VOUT = 4.5V
1.97
mA
Indicate Mode, Message Indicator Register, bits[2:0] = 111,
3.0V ≤ VIN ≤ 4.2V
590
µA
ISHDN
Shutdown Supply
Current
VHWEN = GND, 3.0V ≤ VIN ≤ 4.2V
0.02
1.25
ISTBY
Standby Supply
Current
VHWEN = VIN , 3.0V ≤ VIN ≤ 4.2V
1.25
2
VIN_TH
VIN Monitor
Threshold
VIN Monitor Register = 0x01
2.85
2.9
2.95
V
VIN_FLASH_TH
VIN Flash Monitor
Threshold
VIN Monitor Register = 0x08
2.85
2.9
2.95
V
tTX
(3)
(4)
(5)
(6)
4
µA
Flash to Torch LED
TX_ Low to High,
Current Settling
ILED1 + ILED2 = 2A to 187.5 mA
Time
2
Torch to Flash LED
TX_ High to Low,
Current Settling
ILED1 + ILED2 = 187.5mA to 2A
Time
160
µs
The typical curve for Over-Voltage Protection (OVP) is measured in closed loop using the typical application circuit . The OVP value is
found by forcing an open circuit in the LED1 and LED2 path and recording the peak value of VOUT. The value given in the Electrical
Table is found in an open loop configuration by ramping the voltage at OUT until the OVP comparator trips. The closed loop data can
appear higher due to the stored energy in the inductor being dumped into the output capacitor after the OVP comparator trips. At worst
case is an open circuit condition where the output voltage can continue to rise after the OVP comparator trips by approximately
IIN×sqrt(L/COUT).
The typical curve for Current Limit is measured in closed loop using the typical application circuit by increasing IOUT until the peak
inductor current stops increasing. The value given in the Electrical Table is measured open loop and is found by forcing current into SW
until the current limit comparator threshold is reached. Closed loop data appears higher due to the delay between the comparator trip
point and the NFET turning off. This delay allows the closed loop inductor current to ramp higher after the trip point by approximately
20ns × VIN/L
Specified by design. Not production tested.
The timeout period is a divided down representation of the 2MHz clock and thus the accuracy spec is the same as the switching
frequency.
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ELECTRICAL CHARACTERISTICS
(1) (2)
(continued)
Limits in standard typeface are for TA = +25°C. Limits in boldface type apply over the full operating ambient temperature
range (−40°C ≤ TA ≤ +85°C). Unless otherwise specified, VIN = 3.6V, VHWEN = VIN.
Symbol
Parameter
Test Conditions
tD
Time from when
ADC Delay Register Bit [5] = 1
ILED hits target until
ADC Delay Register Bit [5] = 0
VLED data is
ADC Delay Register Bits [4:0] = 0000
available
VF_ADC
ADC Threshold
3.0V ≤ VIN ≤ 4.2V, VLED Monitor Register Bits [3:0] = 1111
Min
Typ
Max
Unit
16
µs
250
4.05
4.2
4.35
V
HWEN, STROBE, TX1/TORCH/GPIO1, TX2/INT/GPIO2 Voltage Specifications
VIL
Input Logic Low
2.7V ≤ VIN ≤ 4.2V
0
0.4
V
VIH
Input Logic High
2.7V ≤ VIN ≤ 4.2V
1.2
VIN
V
RPD
Internal Pull Down
Resistance on TX1,
TX2, STROBE
300
kΩ
I2C-Compatible Voltage Specifications (SCL, SDA)
VIL
Input Logic Low
2.7V ≤ VIN ≤ 4.2V
0
0.4
V
VIH
Input Logic High
2.7V ≤ VIN ≤ 4.2V
1.2
VIN
V
VOL
Output Logic Low
(SDA)
ILOAD = 3mA, 2.7V ≤ VIN ≤ 4.2V
400
mV
0
400
kHz
I2C-Compatible Timing Specifications (SCL, SDA)
(7)
, see Figure 42
fSCL
SCL(Clock
Frequency)
tRISE
Rise Time of Both
SDA and SCL
20ns +
0.1 ×
CBUS
300
ns
tFALL
Fall Time of Both
SDA and SCL
20ns +
0.1 ×
CBUS
300
ns
tLOW
Low Period of SCL
Clock
1.3
µs
tHIGH
High Period of SCL
Clock
600
ns
tHD;STA
Hold Time for Start
(or Repeated
Start)Condition
600
ns
tSU;STA
Set-up Time for a
Repeated Start
600
ns
tHD;DAT
Data Hold Time
0
ns
tSU;DAT
Data Setup Time
100
ns
tSU;STO
Set-up Time for
Stop Condition
600
ns
tVD;DAT
Data Valid Time
900
ns
tVD;ACK
Data Valid
Acknowledge Time
900
ns
tBUF
Bus Free Time
Between a Start
and a Stop
Condition
(7)
1.3
µs
Specified by design. Not production tested.
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TYPICAL PERFORMANCE CHARACTERISTICS
(VIN = 3.6V, COUT = 10 µF, CIN = 10 µF, L = 1µH (TOKO FDSD0312-1R0, RL = 43 mΩ), TA = 25°C, ILED = ILED1 + ILED2,
unless otherwise noted).
LED Efficiency vs VIN
LED1 + LED2
Highest 4 Flash Brightness Codes
LED Efficiency vs VIN
LED1 + LED2
Upper Middle 4 Flash Brightness Codes
88
89
Code 1100
86
82
Efficiency (%)
Efficiency (%)
85
79
76
Code 1111
Code 1110
Code 1000
83
80
77
Code 1010
74
73
Code 1101
Code 1011
Code 1001
71
70
2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5
68
2.5
2.8
3.1
VIN (V)
4.0
4.3
4.6
VIN (V)
Figure 2.
LED Efficiency vs VIN
LED1 + LED2
Lower Middle 4 Flash Brightness Codes
LED Efficiency vs VIN
LED1 + LED2
Lowest 4 Flash Brightness Codes
100
Code 0100
87
95
84
90
81
85
Efficiency (%)
Efficiency (%)
3.7
Figure 1.
90
78
75
Code 0101
72
Code 0110
Code 0111
69
Code 0010
80
75
70
65
60
Code 0001
Code 0000
50
63
60
2.5
Code 0011
55
66
45
2.8
3.1
3.4
3.7
4.0
4.3
40
2.5
4.6
VIN (V)
3.0
3.5
4.1
4.6
VIN (V)
Figure 3.
6
3.4
Figure 4.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
(VIN = 3.6V, COUT = 10 µF, CIN = 10 µF, L = 1µH (TOKO FDSD0312-1R0, RL = 43 mΩ), TA = 25°C, ILED = ILED1 + ILED2,
unless otherwise noted).
ILED vs VIN
ILED1 + ILED2
Highest 4 Flash Brightness Codes
ILED vs VIN
ILED1 + ILED2
Upper Middle 4 Flash Brightness Codes
1.60
2.03
Code 1111
1.55
1.99
1.95
Code 1110
1.45
1.91
ILED (A)
ILED (A)
1.83
Code 1101
1.79
1.75
1.71
1.35
1.30
1.67
1.15
1.63
1.10
1.59
1.05
2.9
3.3
3.7
4.1
Code 1001
1.25
1.20
Code 1100
1.00
2.5
4.5
Code 1000
2.9
3.3
3.7
4.1
4.5
4.9
VIN (V)
VIN (V)
Figure 5.
Figure 6.
ILED vs VIN
ILED1 + ILED2
Lower Middle 4 Flash Brightness Codes
ILED vs VIN
ILED1 + ILED2
Lowest 4 Flash Brightness Codes
1.10
0.530
Code 0111
1.05
0.490
1.00
0.450
0.95
0.410
Code 0110
0.85
0.80
Code 0011
0.370
ILED (A)
0.90
ILED (A)
Code 1010
1.40
1.87
1.55
2.5
Code 1011
1.50
Code 0101
0.75
0.330
Code 0010
0.290
0.250
0.210
0.70
0.130
0.60
0.090
0.55
2.5
0.050
2.5
2.9
3.3
3.7
4.1
4.5
Code 0001
0.170
Code 0100
0.65
4.9
Code 0000
2.9
3.3
3.7
4.1
VIN (V)
VIN (V)
Figure 7.
Figure 8.
4.5
4.9
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
(VIN = 3.6V, COUT = 10 µF, CIN = 10 µF, L = 1µH (TOKO FDSD0312-1R0, RL = 43 mΩ), TA = 25°C, ILED = ILED1 + ILED2,
unless otherwise noted).
Indicator Current vs Headroom voltage
VLED = 2.5V
Indicate codes 100 - 111
Indicator Currents vs Headroom voltage
VLED = 2.5V
Indicate codes 000 - 011
10.0
20.0
9.0
Code 111
19.0
17.0
Indicate Current (mA)
Indicate Current (mA)
Code 011
8.0
18.0
Code 110
16.0
15.0
Code 101
14.0
13.0
12.0
7.0
Code 010
6.0
5.0
4.0
Code 001
3.0
2.0
Code 100
Code 000
1.0
11.0
10.0
0.20
0.24
0.28
0.32
0.36
0.40
0.0
0.00 0.03 0.05 0.08 0.10 0.13 0.15 0.18 0.20
Headroom Voltage (VIN - VLED)
Headroom Voltage (VIN - VLED)
Figure 9.
Figure 10.
Closed Loop Current Limit vs VIN ( (1))
3.6A setting
Closed Loop Current Limit vs VIN ( (1))
3A setting
3.90
3.34
3.31
3.85
3.80
-40°C
3.75
25°C
3.26
2.9
3.2
3.6
3.9
4.2
3.13
2.6
VIN (V)
85°C
2.9
3.2
3.6
3.9
4.2
VIN (V)
Figure 11.
8
25°C
3.21
3.16
85°C
(1)
-40°C
3.23
3.18
3.70
3.65
2.6
Current Limit (A)
Current Limit (A)
3.29
Figure 12.
The typical curve for Current Limit is measured in closed loop using the typical application circuit by increasing IOUT until the peak
inductor current stops increasing. The value given in the Electrical Table is measured open loop and is found by forcing current into SW
until the current limit comparator threshold is reached. Closed loop data appears higher due to the delay between the comparator trip
point and the NFET turning off. This delay allows the closed loop inductor current to ramp higher after the trip point by approximately
20ns × VIN/L
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
(VIN = 3.6V, COUT = 10 µF, CIN = 10 µF, L = 1µH (TOKO FDSD0312-1R0, RL = 43 mΩ), TA = 25°C, ILED = ILED1 + ILED2,
unless otherwise noted).
Closed Loop Current Limit vs VIN ( (2))
2.3A setting
Closed Loop Current Limit vs VIN ( (2))
1.6A setting
1.91
2.75
1.87
-40°C
2.70
1.84
Current Limit (A)
Current Limit (A)
-40°C
2.65
2.60
25°C
2.55
1.81
1.78
25°C
1.75
85°C
1.71
2.50
1.68
85°C
2.45
2.6
2.9
3.2
3.6
3.9
4.2
1.65
2.6
2.9
3.2
3.6
3.9
VIN (V)
VIN (V)
Figure 13.
Figure 14.
Switching Frequency vs VIN
Stand-by Supply Current vs VIN
HWEN = VIN
4.2
1.7
2.00
1.5
1.96
Stand-by Current (#A)
Switching Frequency (MHz)
25°C
1.98
-40°C
1.94
85°C
2.8
3.2
3.5
3.9
4.2
1.0
25°C
-40°C
0.6
2.5
3.0
3.5
4.1
4.6
5.1
VIN (V)
VIN (V)
Figure 15.
(2)
1.3
0.8
1.92
1.90
2.5
85°C
Figure 16.
The typical curve for Current Limit is measured in closed loop using the typical application circuit by increasing IOUT until the peak
inductor current stops increasing. The value given in the Electrical Table is measured open loop and is found by forcing current into SW
until the current limit comparator threshold is reached. Closed loop data appears higher due to the delay between the comparator trip
point and the NFET turning off. This delay allows the closed loop inductor current to ramp higher after the trip point by approximately
20ns × VIN/L
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
(VIN = 3.6V, COUT = 10 µF, CIN = 10 µF, L = 1µH (TOKO FDSD0312-1R0, RL = 43 mΩ), TA = 25°C, ILED = ILED1 + ILED2,
unless otherwise noted).
10
Shutdown Supply Current vs VIN
HWEN = GND
STROBE to Flash LED Current Response
Figure 17.
Figure 18.
VIN Monitor Operation
VIN_TH = 3.2V
Force Torch Mode, TX2 set for Interrupt Output (INT)
Circuit of Figure 37 (Note B)
Vin Flash Monitor Operation
VIN_FLASH_TH = 3.2V
TX2 set for Interrupt Output (INT)
Circuit of Figure 37 (Note A)
Figure 19.
Figure 20.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
(VIN = 3.6V, COUT = 10 µF, CIN = 10 µF, L = 1µH (TOKO FDSD0312-1R0, RL = 43 mΩ), TA = 25°C, ILED = ILED1 + ILED2,
unless otherwise noted).
NTC Operation
NTC set to force torch mode
TX2 set for Interrupt Output (INT)
Circuit of Figure 45, R3 = 1.3 kΩ, RNTC = 10 kΩ @+25°C,
Beta = 3380K
AET Operation
Figure 21.
Figure 22.
HWEN Operation
Device Enabled in Flash Mode
TX1 Interrupt (Force Torch)
Figure 23.
Figure 24.
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BLOCK DIAGRAM
SW
Over Voltage
Comparator
2 MHz
Oscillator
VREF
+
-
IN
80 m?
VIN Flash
Monitor
Threshold
VIN Monitor
Threshold
V OVP
OUT
ILED1
ILED2
+
-
+
-
PWM
Control
LED1
65 m?
ILEDI
Thermal
Shutdown
o
+150 C
LEDI/NTC
+
-
Error
Amplifier
LED2
V HR
+
-
+
-
Current Sense/
Current Limit
Max
VLED
1V
Slope
Compensation
SDA
2
SCL
I C
Interface
Soft-Start
Control
Logic/
Registers
ADC
4 Bits
HWEN
12
TX1/TORCH/
GPIO1
STROBE
TX2/INT/
GPIO2
GND
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DEVICE INFORMATION
Overview
The LM3560 is a high-power white LED flash driver capable of delivering up to 2A of LED current into a single
LED, or up to 1A into two parallel LEDs. The device incorporates a 2MHz constant frequency, synchronous boost
converter, and two high-side current sources to regulate the LED current over the 2.5V to 5.5V input voltage
range.
During operation when the output voltage is greater than VIN – 150 mV the boost converter switches and
maintains at least 300 mV across both current sources (LED1 and LED2). This minimum headroom voltage
ensures that the current sources remain in regulation. When the input voltage rises above the LED voltage +
current source headroom voltage, the device stops switching and turns the PFET on continuously (Pass mode).
In Pass mode the difference between (VIN - ILED x RON_P) and the voltage across the LED's is dropped across the
current sources.
Four hardware control pins provide control of the LM3560. These include a hardware Flash Enable (STROBE),
Dual Flash Interrupt inputs (TX1 and TX2) designed to interrupt the flash pulse during high battery current
conditions, and a logic high hardware enable (HWEN) that can be pulled low to rapidly place the device into
shutdown. Additional features of the LM3560 include an internal 4-bit ADC for LED voltage monitoring, an
internal comparator for LED thermal sensing via an external NTC thermistor, an input voltage monitor that can
reduce the Flash current during input undervoltage conditions, a low-power message indicator LED current
source, and a mode for utilizing the flash LEDs as a privacy indicator.
Control of the LM3560 is done via an I2C-compatible interface. This includes adjustment of the Flash and Torch
current levels, adjustment of the indicator LED currents, changing the Flash Timeout Duration, changing the
switch current limit, and reading back the ADC results. Additionally, there are 8 flag bits that indicate flash current
time-out, LED over-temperature, LED failure (LED short or output OVP condition), device thermal shutdown, VIN
under voltage condition, VIN Flash Monitor undervoltage condition, and the occurrence of a TX1 or TX2 interrupt.
STARTUP (ENABLING THE DEVICE)
Turn-on of the LM3560 is done through bits [1:0] of the Enable Register. These bits enable the device in Torch
mode, Flash mode, or Privacy Indicate mode. Additionally, bit 6 of the Enable Register enables the message
indicator at the LEDI/NTC pin. On startup, when VOUT is less than VIN, the internal synchronous PFET turns on
as a current source and delivers 350 mA to the output capacitor. During this time both current sources (LED1,
and LED2) are off. When the voltage across the output capacitor reaches 2.2V the current sources can turn on.
At turn-on the current sources step through each FLASH and TORCH level until their target LED current is
reached (32 µs/step). This gives the device a controlled turn-on and limits inrush current from the VIN supply.
INDEPENDENT LED CONTROL
Bits [4:3] of the Enable register provide for independent turn-on and turn-off of the LED1 or LED2 current
sources. Once enabled, the LED current is adjusted by writing to the Torch Brightness or Flash Brightness
Registers depending on whether Flash or Torch mode is selected. Both the Torch Brightness and the Flash
Brightness Registers provide for independent current programming for the LED currents in either LED1 or LED2.
(See TORCH BRIGHTNESS REGISTER DESCRIPTIONS (Address 0xA0) and FLASH BRIGHTNESS
REGISTER (Address 0xB0).)
PASS MODE
On turn-on when the output voltage charges up to ( VIN – 150 mV), the LM3560 will decide if the part operates in
Pass Mode or Boost mode. If the voltage difference between VOUT and VLED is less then 300 mV, the device
operates in Boost Mode. If the difference between VOUT and VLED is greater then 300 mV, the device operates in
Pass Mode. In Pass Mode the boost converter stops switching and the synchronous PFET turns fully on bringing
VOUT up to (VIN – IIN x RPMOS) where RPMOS = 80 mΩ. In Pass Mode the inductor current is not limited by the
peak current limit. In this situation the output current must be limited to 3A.
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OVER-VOLTAGE PROTECTION
The output voltage is limited to typically 5V (5.075V max). In situations such as the current source open, the
LM3560 will raise the output voltage to try to keep the LED current at its target value. When VOUT reaches 5V the
over-voltage comparator will trip and turn off both the internal NFET and PFET. When VOUT falls below 4.8V
(typical), the LM3560 will begin switching again.
CURRENT LIMIT
The LM3560 features 4 selectable current limits of 1.6A, 2.3A, 3.0A, and 3.6A. These are programmable through
the I2C-compatible interface via bits [6:5] of the Flash Duration Register. When the current limit is reached, the
LM3560 stops switching for the remainder of the switching cycle.
Since the current limit is sensed in the NMOS switch there is no mechanism to limit the current when the device
operates in Pass Mode. In situations where there could potentially be large load currents at OUT, and the
LM3560 is operating in Pass mode, the load current must be limited to 3A. In Boost mode or Pass mode if VOUT
falls below approximately 2.3V, the part stops switching and the PFET operates as a current source, limiting the
current to typically 350 mA. This prevents damage to the LM3560 and excessive current draw from the battery
during output short-circuit conditions.
THERMAL SHUTDOWN
The LM3560 features a thermal shutdown threshold of typically +150°C. When the devices die temperature
reaches +150°C the active current sources (LED1 and/or LED2) will shut down, and the TSD flag in the Flags
register is written high. The device cannot be started up again until the Flags register is read back. Once the
Flags register is read back either current source can be re-enabled into Privacy, Torch, or Flash Mode. The
thermal shutdown (TSD) circuitry has an internal 250 µs de-glitch timer which helps prevent unwanted noise from
falsely triggering a TSD event. However, when the LM3560 is in boost mode at higher flash currents, the deglitch timer can get reset by the high currents in the LM3560's GND. As a result the thermal shutdown's internal
de-glitch timer can be reset before the TSD event can get latched in. This prevents a TSD event from being
triggered until the LM3560's flash pulse reaches the end of the flash duration, when the noisy currents have
dropped to a lower level. However, once the noise is lower, and a TSD event is triggered, the next flash pulse is
not allowed until the flags register is read back. In pass mode the boost switcher is off and the lower noise
environment allows the devices TSD circuitry to shut down immediately when the die temperature reaches
+150°C.
FLASH MODE
In Flash mode the LED current sources (LED1 and LED2) each provide 16 different current levels from typically
62.5 mA (total) to 2A (total) in steps of 62.5 mA. The Flash currents are adjusted via the Flash Brightness
Register. Flash mode is activated by writing a (1, 1) to bits [1:0] of the Enable Register or by enabling the
hardware flash input (STROBE) via bit [2] of Configuration Register 1, and then pulling the STROBE pin high
(high polarity). Once the Flash sequence is activated the active current sources (LED1 and/or LED2) will ramp up
to their programmed Flash current level by stepping through all Torch and Flash levels (32 µs/step) until the
programmed current is reached.
Bit [5] of the Enable Register (STROBE Level/Edge bit) determines how the Flash pulse terminates after
STROBE goes high. With the Level/Edge bit = 1, the Flash current will only terminate when it reaches the end of
the Flash Timeout period. With the Level/Edge bit = 0, Flash mode can be terminated by pulling STROBE low,
programming bits [1:0] of the Enable Register with (0,0), or by allowing the Flash Timeout period to elapse. If the
Level/Edge bit = 0 and STROBE is toggled before the end of the Flash Timeout period, the Timeout period will
reset. Figure 25 and Figure 26 detail the Flash pulse termination for the different Level/Edge bit settings.
14
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Timeout Duration
32 Ps
LED Current
STROBE
(Level/Edge Bit
set to Level)
Figure 25. LED Current for STROBE (Level Triggered, Enable Register Bit 5 = 0)
Timeout Duration
32 Ps
LED
Current
STROBE
(Level/Edge Bit
Set to Edge)
Figure 26. LED Current for STROBE (Edge Triggered, Enable Register Bit 5 = 1)
After the Flash pulse terminates, either by a flash timeout, pulling STROBE low, or disabling it via the I2Ccompatible interface, LED1 and LED2 turn completely off. This happens even when Torch is enabled via the I2Ccompatible interface and the Flash pulse is turned on by toggling STROBE. After a Flash event ends, bits [1:0] of
the Enable Register are automatically reset with (0, 0). The exception occurs when the Privacy Terminate Bit is
low (bit [3]) in the Privacy Register. In this case, the specific current source that is enabled for privacy mode will
turn back on after the flash pulse.
FLASH TIMEOUT
The Flash Timeout period sets the maximum amount of time that the Flash Current will be sourced from current
sources LED1 and LED2. Bits [4:0] of the Flash Duration Register set the Flash Timeout period. There are 32
different Flash Timeout durations in steps of 32 ms giving a Flash Timeout range of 32 ms to 1024 ms (see
Table 16).
TORCH MODE
In Torch mode the current sources LED1 and LED2 each provide 8 different current levels (Table 14). Torch
mode is activated by setting Enable Register bits [1:0] to (1, 0). Once Torch mode is enabled, the current
sources will ramp up to the programmed Torch current level by stepping through all of the Torch currents at (32
µs/step) until the programmed Torch current level is reached.
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PRIVACY INDICATOR MODE
The current sources (LED1 and/or LED2) can also be used as a privacy indicator before and after flash mode.
Privacy indicate mode is enabled by setting the Enable Register bit [1:0] to (0, 1). Privacy mode is configured via
the Privacy Register. This allows the selection of which current source to use as the privacy indicator (either
LED1, LED2, or both), whether or not the privacy indicate mode turns off at the end of the flash pulse, the 3
selectable privacy blink periods (tBLINK), and the 8 duty cycle settings for the privacy indicator average current.
The intensity of the LEDs in privacy indicate mode is set by PWM controlling either the lowest Torch current level
(31.25 mA per current source) or the highest Torch current level (250 mA per current source). Bit [2] in the
Enable register selects between these two levels. Bits [2:0] in the Privacy Register select the 8 different duty
cycles of 10%, 20%, 30%, 40%, 50%, 60%, 70%, and 80%. This enables privacy mode to have a PWMcontrolled torch current with a wide number of values (see Table 2 ). The privacy blink options (tBLINK) are set via
bit [7:6] of the Privacy Register. Selectable options are 128 ms, 256 ms, 512 ms, or always on. The blink pulse
period is set to 2 x tBLINK. Figure 27 details the timing for the Privacy Indicate Mode timing on ILED1 or ILED2.
tBLINK
Duty
Cycle
tPWM
ITORCH_MIN
or ITORCH_MAX
x
x
tBLINK set via bits [7:6] of Privacy Register
Duty cycle set via bits [2:0] of Privacy Register
x
tPWM set via bits[2:0] of the Privacy PWM Register
Figure 27. Privacy Indicate Timing
Table 2. Privacy Indicate (PWM'd Torch) Possible Current Settings (1)
(1)
16
Privacy Current Setting
(Enable Register Bit [2])
0 = 31.25mA peak
1 = 250mA peak
Privacy Indicate Duty Cycle
Privacy Register Bits[2:0]
see (Table 5)
ILED1 or ILED2
(Single LED)
0
000
3.125 mA
0
001
6.25 mA
0
010
9.375 mA
0
011
12.5 mA
0
100
15.625 mA
The listed current is with 1 current source active
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Table 2. Privacy Indicate (PWM'd Torch) Possible Current
Settings(1) (continued)
Privacy Current Setting
(Enable Register Bit [2])
0 = 31.25mA peak
1 = 250mA peak
Privacy Indicate Duty Cycle
Privacy Register Bits[2:0]
see (Table 5)
ILED1 or ILED2
(Single LED)
0
101
18.75 mA
0
110
21.875 mA
0
111
25 mA
1
000
25 mA
1
001
50 mA
1
010
75 mA
1
011
100 mA
1
100
125 mA
1
101
150 mA
1
110
175 mA
1
111
200 mA
POWER AMPLIFIER SYNCHRONIZATION (TX1)
The TX1/TORCH/GPIO1 pin has a triple function. With Configuration Register 1 Bit [7] = 0 (default)
TX1/TORCH/GPIO1 is a Power Amplifier Synchronization input (TX1 mode). This mode is designed to reduce
the flash LED current when TX1 is driven high (active high polarity) or driven low (active low polarity). When the
LM3560 is engaged in a Flash event and TX1/TORCH is driven high, the active current sources (LED1 and/or
LED2) are forced into Torch mode at the programmed Torch current setting. If TX1 is then pulled low before the
Flash pulse terminates, the LED current will return to the previous Flash current level. At the end of the Flash
timeout, whether the TX1/TORCH pin is high or low, the LED current will turn off.
The polarity of TX1 can be changed from active high to active low by writing a 0 to bit [5] of Configuration
Register 1. With this bit set to ‘0’ the LM3560 will be forced into Torch mode when TX1/TORCH is pulled low.
Figure 28 details the functionality of the TX1 Interrupt.
TX1 Shutdown
TX1 also has the capability to force shutdown. Bit [4] of Configuration Register 2 set to a '1', changes TX1 from a
force Torch when active to a force shutdown when active. For example, if TX1/TORCH/GPIO1 is configured for
TX1 mode with active high polarity, and bit[4] of Configuration Register 2 is set to '1' , then when TX1 is driven
high, the active current sources (LED1 and/or LED2) will be forced into shutdown. Once the active current
sources are forced into shutdown by activating TX1, the current sources can only be re-enabled into flash mode
if TX1 is pulled low and the Flags Register is read back. If only the Flags register is read back and TX1 is kept
high the device will be re-enabled into torch mode and not shutdown. This occurs because the TX1 shutdown
feature is an edge-triggered event. With active high polarity the TX1 shutdown requires a rising edge at TX1 in
order to force the current source into shutdown. Once shut down, it takes a read back of the flags Register and
another rising edge at TX1 to force shutdown again. Figure 30 details the different responses of the TX1
shutdown mode.
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Flash Timeout
IFLASH
ITORCH
STROBE
TX1 or TX2 set
for Active High
Figure 28. TX1 or TX2 Interrupt (Force Torch) Response
HARDWARE TORCH
With Configuration Register 1 Bit [7] = 1, TX1/TORCH/GPIO1 is configured as a hardware Torch mode enable. In
this mode, a high at TX1/TORCH turns on the LED current at the programmed Torch current setting. The
STROBE input and I2C Enabled flash takes precedence over TORCH mode. In hardware torch mode, both LED1
and LED2 current sources will turn off after a flash event and Configuration Register 1 Bit [7] will be reset to 0. In
this situation, to re-enter torch mode via hardware torch, the hardware torch enable bit (Configuration Register 1
Bit [7]) must be reset to 1. Figure 29 details the functionality of hardware torch mode.
Flash Duration
IFLASH
ITORCH
STROBE
TORCH
Figure 29. Hardware Torch Mode
GPIO1 MODE
With Bit [0] of the GPIO Register set to 1, the TX1/TORCH/GPIO1 pin is configured as a logic I/O. In this mode
the TX1/TORCH/GPIO1 pin is readable and writable as a logic input/output via bits [2:1] of the GPIO Register.
See GPIO REGISTER (Address 0x20) for programming the GPIO1 output.
TX2/INT/GPIO2
The TX2/INT/GPIO2 pin has a triple function. In TX2 mode (Default) the TX2/INT/GPIO2 pin is an active high
Flash interrupt. With GPIO Register bit [3] = 1 the TX2/INT/GPIO2 pin is configured as general purpose logic I/O
(GPIO2). With GPIO Register bit [6] = 1 and with GPIO2 set for GPIO output, the TX2/INT/GPIO2 pin is an
interrupt output
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TX2 MODE
In TX2 mode, when Configuration Register 1, bit [6] = 0, TX2 is an active low flash interrupt. Under this condition
when the LM3560 is engaged in a Flash event and TX2 is pulled low, the active current source (LED1 and/or
LED2) are forced into Torch mode. In TX2 mode with Configuration Register 1, bit [6] = 1, TX2 is configured for
active high polarity. Under this condition, when the LM3560 is engaged in a Flash event and TX2 is driven high,
the active current source (LED1 and/or LED2) are forced into Torch mode. During a TX2 interrupt event, if the
TX2 input is disengaged, the LED current will return to the previous flash current level. Figure 28 details the
functionality of the TX2 Interrupt.
TX2 Shutdown
TX2 also has the capability to force shutdown. When bit [0] of Configuration Register 2 is set to a '1', TX2 will
force shutdown when active. For example, if TX2 is configured for TX2 mode with active high polarity, and bit [0]
of Configuration Register 2 is set to '1' then when TX2 is driven high, the active current sources (LED1 and/or
LED2) will be forced into shutdown. Once the active current sources are forced into shutdown by activating TX2,
the current sources can only be re-enabled in flash mode if TX2 is pulled low and the Flags register is read back.
If only the Flags register is read back and TX2 is kept high, the device will be re-enabled into torch mode and not
shutdown. This occurs because the TX2 shutdown feature is an edge-triggered event. With active high polarity
the TX2 shutdown requires a rising edge at TX2 in order to force the current sources into shutdown. Once shut
down, it takes a read back of the flags Register and another rising edge at TX2 to force shutdown again.
Figure 30 details TX2 shutdown mode.
STROBE
Programmed Flash
Setting
32 Ps per step
Programmed Torch
Setting
ILED
32 Ps per step
TX1/TX2
Flags Register Read
Back
Figure 30. TX1 or TX2 (Force Shutdown) Response
GPIO2 MODE
With Bit [3] of the GPIO Register set to 1, the TX2/INT/GPIO2 pin is configured as a logic I/O. In this mode the
TX2/INT/GPIO2 pin is readable and writable as a logic input/output via bits [5:4] of the GPIO Register. See
Table 9 for programming the GPIO2 output.
INTERRUPT OUTPUT (INT MODE)
The TX2/INT/GPIO2 pin can be reconfigured as an active low interrupt output by setting bit [6] in the GPIO
Register to ‘1’ and configuring TX2/INT/GPIO2 as a GPIO2 output (bits [4:3] of GPIO Register = 11). In this
mode, TX2/INT/GPIO2 will pull low when any of these conditions exist.
1. The LM3560 is configured for NTC mode (Configuration Register 1 bit [4] = 1), and the voltage at LEDI/NTC
has fallen below VTRIP (1V typical).
2. The LM3560 is configured for VIN Monitor mode (VIN Monitor Register bit [0] = 1), and VIN falls below the
programmed VIN Monitor Threshold.
3. The LM3560 is configured for VIN Flash Monitor mode (VIN Monitor Register bit [3] = 1), and VIN falls below
the programmed VIN Flash Monitor Threshold.
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Once INT is pulled low due to any of the above conditions having been met, INT will only go high again if any of
the conditions are no longer true and the Flags Register is read.
250 Ps
Deglitch Time
Flash Timeout
IFLASH
LED Current
ITORCH
STROBE
TX2
(Interrupt Output)
LEDI/NTC
(Comparator Input)
VLEDI/NTC
(1V Typical)
Figure 31. TX2 As an Interrupt Output (During an NTC Event)
INDICATOR LED/THERMISTOR (LED1/NTC)
The LEDI/NTC pin serves a dual function: either as a programmable LED message indicator driver, or as a
comparator input for negative temperature coefficient (NTC) thermistors.
MESSAGE INDICATOR CURRENT SOURCE (LEDI/NTC)
LEDI/NTC is configured as a message indicator current source by setting Configuration Register 1 bit [4] = (0)
default. The indicator current source is enabled/disabled via the Enable Register bit [6] = (1). Bit [7] of the Enable
Register enables the Message Indicator in blink mode. If the message indicator is set for blinking mode, the
pattern programmed into the Indicator Register, and Indicator Blinking Register is output on the Indicator current
source.
The Indicator Blinking Register controls the following (see Table 7 ):
1. Number of blank periods (BLANK #). This has 16 settings. tBLANK = tACTIVE × BLANK# , where tACTIVE =
tPERIOD × PERIOD#
2. Pulse width (tPULSE) has 16 settings between 0 and 480 ms in steps of 32 ms. The pulse width is the duration
that the indicator current is at its programmed set point at the end of the ramp-up time.
The Indicator Register controls the following (see Table 6 ):
1. Indicator current level (IIND). There are 8 indicator current levels from 2.25 mA to 18 mA in steps of 2.25 mA.
2. Number of periods (PERIOD #). This has 8 steps. A period (tPERIOD) is found by (tPERIOD = tR + tF + 2 x
tPULSE). (see Figure 32 for indicator timing).
3. Ramp times (tR or tF) for turn-on and turn-off of the indicator current source. Four programmable times of 78
ms, 156 ms, 312 ms, and 624 ms are available. The ramp times apply for both ramp-up and ramp-down and
are not independently changeable.
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tPERIOD
tBLANK
tPERIOD
tPULSE
tPULSE
IIND
tR
tF
tR
tPULSE
tF
tPULSE
Figure 32. Message Indicator Timing Diagram
MESSAGE INDICATOR EXAMPLE 1 (Single Pulse with Dead Time):
As an example, to set up the message indicator for a 312 ms ramp-up and ramp-down, 192 ms pulse width, and
1 pulse followed by a 5s delay. The indicator settings will be as follows. tR = tF = 312 ms, tWIDTH = 192 ms (tPERIOD
= 312 ms x 2 + 192 ms x 2 = 1016 ms). BLANK# setting will be: 5s/1016 ms x 1 (PERIOD# = 1). Giving a
BLANK# setting of 5. The resulting waveform will appear as:
tPERIOD
tBLANK
(5.08s)
(1.016s)
Figure 33. Message Indicator Example 1
MESSAGE INDICATOR EXAMPLE 2 (Multiple Pulses with Dead Time):
Another example has the same tR, tF, tPULSE, and tBLANK times as before, but this time the PERIOD# is set to 3.
Now the tACTIVE time is tPERIOD × 3 = 1016 ms × 3 = 3048 ms. This results in a blank time of tBLANK = tACTIVE ×
BLANK# = 3.048s × 5 = 15.24s
tACTIVE
(3.048s)
tPERIOD
(1.016s)
tPERIOD
(1.016s)
tPERIOD
(1.016s)
tBLANK
(15.24s)
Figure 34. Message Indicator Example 2
UPDATING THE MESSAGE INDICATOR
The best way to update the message indicator is to disable the Message Indicator output via the Enable Register
bit [6], then write the new sequence to the Indicator Register and/or Indicator Blinking Register, and then reenable the Message Indicator. Updating the Indicator Registers while it is active can lead to long delays between
pattern changes. This is especially true if the PERIOD#, or BLANK# setting is changed from a high setting to a
lower setting.
NTC MODE
Writing a (1) to Configuration Register 1 bit [4] configures the LEDI/NTC pin for NTC mode. In this mode the
indicator current source is disabled, and LEDI/NTC becomes the positive input to the an internal comparator.
NTC mode operates as a LED current interrupt that is triggered when the voltage at LEDI/NTC goes below 1V.
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Two actions can be taken when the NTC comparator is tripped. With Configuration Register 2 bit [1] set to ‘0’ the
NTC interrupt will force the LED current from Flash mode into Torch mode. With Configuration Register 2 bit [1]
set to ‘1’, the NTC interrupt will force the LED current into shutdown.
Whether in NTC force torch or NTC shutdown, in order to re-enter flash mode after an NTC event, two things
must occur. First, the NTC input must be above the 1V threshold. Secondly, the Flags Register must be read.
To avoid noise from falsely triggering the NTC Comparator, this mode incorporates a 250 µs de-glitch timer. With
NTC mode active, VLEDI/NTC must go below the trip point (VTRIP) and remain below it for 250 µs before the LEDs
are forced into Torch mode (or shutdown) and the NTC Flag is written.
ALTERNATE EXTERNAL TORCH (AET MODE)
With Configuration Register 2 bit [2] set to '1', the LM3560 is configured for AET mode, and the operation of
TX1/TORCH becomes dependent on its occurrence relative to the STROBE input. In this mode, if TX1/TORCH
goes high first, then STROBE goes high, the LEDs are forced into Torch mode with no timeout. In this mode, if
TX1/TORCH goes high after STROBE has gone high, then the TX1/TORCH pin operates as a normal LED
current interrupt (TX1), and the LEDs will turn off at the end of the timeout duration (see Figure 35).
Timeout Duration
IFLASH
LED Current
ITORCH
TX1/TORCH
STROBE
Figure 35. AET Mode Timing
INPUT VOLTAGE MONITOR
The LM3560 has an internal comparator at IN which monitors the input voltage and can force the LED current
into Torch mode or into shutdown if VIN falls below the programmable VIN Monitor Threshold. Bit 0 in the VIN
Monitor Register enables or disables this feature. When enabled, Bits [2:1] program the 4 adjustable thresholds
of 2.9V, 3.0V, 3.1V, and 3.2V. Bit 3 in Configuration Register 2 selects whether a VIN Monitor event forces Torch
mode or forces LED1 and/or LED2 into shutdown. See Table 12 for additional information. When the input
voltage monitor is active, and VIN falls below the programmed VIN Monitor threshold, the LEDs will either turn off
or be forced into the Torch current setting. To reset the LED current to its previous level, two things must occur.
First, VIN must go above the VIN Monitor threshold, and the Flags register must be read back. See Figure 36 for
the VIN Monitor Timing Waveform.
To avoid noise from falsely triggering the VIN Monitor, this mode incorporates a 250 µs de-glitch timer. With the
VIN Monitor active, VIN must go below the VIN Monitor Threshold (VIN_TH), and remain below it, for 250 µs before
the LEDs are forced into Torch mode (or shutdown) and the VIN Monitor Flag is written.
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Deglitch Time
(250 Ps)
Flash Timeout
IFLASH
LED
Current
ITORCH
Input
Voltage
VIN_MON_TH
STROBE
Figure 36. VIN Monitor Waveform
RS
SW
IN
RPU
RL
OUT
LM3560
COUT
2A
+
-
VBATT
Q1
CIN
TX2/
INT
ILED1
ILED2
GND
Note A: For the VIN flash monitor test, when the 2A flash starts up the voltage at IN begins to drop
via the rising input current ramp and the source resistance RS As soon as the input voltage
crosses the programmed VIN Flash Monitor Threshold the flash current ramp is stopped and the
LM3560 flashes at the reduced current
Note B: For the VIN Monitor test, with a 2A flash current the voltage at IN is VBATT - IBATT x
RS. When Q1 turns on the added load causes VIN to drop by the additional current (VIN/RL)
which flows through RS. When VIN drops the programmed VIN Monitor threshold is crossed and
the flash current pulse steps to the programmed torch current level causing VIN to step up.
Figure 37. VIN Monitor/VIN Flash Monitor Test Circuit
INPUT VOLTAGE FLASH MONITOR (FLASH CURRENT RISING)
A second comparator at the IN terminal is available to monitor the input voltage during the flash current turn-on
(Input Voltage Flash Monitor). Bit [3] of the VIN Monitor Register enables/disables this feature. With this bit set to
‘1’, the VIN Flash Monitor is active, and bits [5:4] of the VIN Monitor Register program the 4 selectable thresholds
of (2.9V, 3.0V, 3.1V, and 3.2V). The VIN Flash Monitor operates as follows: during flash current turn-on the
current sources will transition through each of the lower flash current levels until the target flash current is
reached. With the Input Voltage Flash Monitor active, if during the flash current turn-on the input voltage falls
below the VIN Flash Monitor threshold, the flash current is stopped at the level that the current ramp had risen
to, at the time of the VIN Flash Monitor event. The VIN Flash Monitor only operates during the ramping up of the
flash LED current.
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The VIN Flash Monitor ignores the first 2 flash codes during the flash current turn-on. As a result, if the VIN Flash
Monitor is enabled and VIN were to fall below the VIN Flash Threshold as the LED current ramps up through
either of the first two levels, then the flash pulse would not be halted until code #3 (168.75mA per current
source).
To avoid noise from falsely triggering the VIN Flash Monitor, this mode incorporates an 8µs de-glitch timer as
well as an internal analog filter at the input of the VIN Flash Monitor Comparator. With the VIN Flash Monitor
active, VIN must go below the VIN Flash Monitor Threshold (VIN_FLASH), and remain below it, for 8µs before the
flash current ramp is halted and the VIN Flash Monitor Flag is written.
LAST FLASH REGISTER
Once the VIN Flash Monitor is tripped, the flash code that corresponded to the LED current at which the flash
current ramp was halted is written to the Last Flash Register. The Last Flash Register is a read only register and
has the lower 4 bits available to latch the code for LED1 and the upper 4 bits to latch the code for LED2.
For example, suppose that the LM3560 is set-up for a single LED with a target flash current of 1250 mA and the
VIN Flash Monitor is enabled with the VIN Flash Monitor threshold set to 3.0V (VIN Monitor Register bits [5:4] =
0, 1). When the STROBE input is brought high, the LED current begins ramping up through the torch and flash
current codes at 32 µs/code. As the input current increases, the input voltage at the LM3560’s IN pin begins to
fall due to the source impedance of the battery. By the time the LED current has reached 1000 mA (code 0x77 or
500 mA per current source), VIN falls below 3.0V. The VIN Flash Monitor will then stop the flash current ramp
and the LM3560 will continue to proceed with the flash pulse, but at 1000 mA instead of 1250 mA. Figure 38
details this sequence.
Flash Current Target = 1250 mA
Flash Current Limited to 1000 mA
LED Current
0
32 Ps
VIN
VIN Flash Monitor
Threshold
Figure 38. VIN Flash Monitor Example
LED VOLTAGE MONITOR
The LM3560 includes a 4-bit ADC which monitors the LED forward voltage (VLED) and stores the digitized value
in bits [3:0] of the VLED Monitor Register. The highest voltage of VLED1 or VLED2 is automatically sensed, and
that becomes the sample point for the ADC. Bit 5, the ADC shutdown bit, enables/disables the ADC with the
default state set to enable (bit [5] = 0).
AUTOMATIC CONVERSION MODE
With the ADC enabled, a conversion is performed each time a flash pulse is started. When a flash pulse is
started bit [6] of the VLED Monitor Register (End of Conversion bit) is automatically written with a ‘0’. At the end
of the conversion, bit [6] will go high signaling that the VLED data is valid. A read back of the VLED Monitor
register will clear bit [6]. Figure 39 details the VLED Monitor Automatic Conversion.
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MANUAL CONVERSION MODE
The VLED Monitor can be set up for manual conversion mode by setting bit [4] of the VLED Monitor Register to
'1'. When this bit is set high the EOC bit (bit [6]) goes low, and a conversion is performed. When the conversion
is complete, the EOC bit goes high again. Subsequent conversions are performed in manual mode by reading
back the VLED Monitor register. This resets the EOC bit and starts another conversion (see Figure 40).
ADC DELAY
The ADC Delay register provides for a programmable delay from 250 µs to 8ms in steps of 250 µs. This delay is
the delay from when the EOC bit goes low to when the VLED Monitor samples the LED voltage. In Automatic
Mode the EOC bit goes low when the Flash LED current hits its target. In Manual mode the EOC bit goes low at
the end of a read back of the VLED Monitor Register (or when the manual mode bit (bit 4) is re-written with a 1).
EOC Bit
is set to 0
tCONV = 16 Ps
tDELAY
LED Voltage
(The higher of
VLED1 or VLED2)
EOC Bit
is set to 1
(Data Valid)
STROBE
(Level/Edge Bit
set to Level)
Figure 39. VLED Monitor Automatic Mode
EOC Bit
is set to 1
(Data Valid)
EOC Bit
is set to 0
tDELAY
tDELAY
tCONV = 16 Ps I2C READ ACK
I2C WRITE ACK
EOC Bit
is set to 1
(Data Valid)
EOC Bit
is set to 0
tCONV = 16 Ps
LED Voltage
(The higher of
VLED1 or VLED2)
Figure 40. VLED Monitor Manual Mode
FLAGS REGISTER AND FAULT INDICATORS
Eight fault flags are available in the LM3560. These include a Flash Timeout, a Thermal Shutdown, an LED
Failure Flag (LED Shorted or Output going OVP indicating LED open), an LED Thermal Flag (NTC threshold
tripping), a VIN Monitor Flag, and a VIN Flash Monitor Flag. Additionally, two LED interrupt flag bits (TX1
interrupt and TX2 interrupt) are set when the corresponding interrupt is activated. Reading back a '1' indicates
the flagged event has happened. A read of the Flags Register resets these bits.
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FLASH TIMEOUT
The Timeout or (TO flag), (bit [0] of the Flags Register) reads back a '1' if the LM3560 is active in Flash mode
and the Timeout period expires before the Flash pulse is terminated. The flash pulse can be terminated before
the Timeout period expires by pulling the STROBE pin low (with Enable Register bit [5] = 0), or by writing a (0,0)
to bit [1:0] of the Enable Register. The TO flag is reset to '0' by pulling HWEN low, removing power to the
LM3560, or reading the Flags Register.
THERMAL SHUTDOWN FLAG
When the thermal shutdown threshold is tripped a '1' gets written to bit [1] of the Flags Register (Thermal
Shutdown bit). The LM3560's flash, torch, or privacy modes cannot be restarted until the Flags Register has
been read back, or when the device is shut down and started up again.
LED FAULT
The LED Fault flag (bit 2 of the Flags Register) reads back a '1' if the part is active in Flash or Torch mode and
either LED1 or LED2 experience an open or short condition. An LED open condition is signaled if the OVP
threshold is crossed at the OUT pin while the device is in Flash, Torch, or Privacy mode. An LED short condition
is signaled if the voltage at LED1 or LED2 goes below 500 mV while the device is in Flash, Torch, or Privacy
mode. In an LED open condition there is a 2µs deglitch time from when the output voltage crosses the OVP
threshold to when the LED Fault Flag is triggered. In an LED short condition there is a 250µs deglitch time from
when the LED voltage falls below 500 mV until the LED Fault Flag is set. The LED Fault Flag can only be reset
to '0' by pulling HWEN low, cycling power, or by removing the fault condition and reading back the Flags
Register.
TX1 AND TX2 INTERRUPT FLAGS
The TX1 and TX2 interrupt flags (bits [3] and [4]) indicate an interrupt event has occurred on the respective TX
inputs. Bit 3 will read back a '1' if TX1 is in TX mode and there has been a TX1 event since the last read of the
Flags Register. Bit 4 will read back a '1' if TX2 is in TX mode and there has been a TX2 event since the last read
of the Flags Register. A read of the Flags Register automatically resets these bits. A TX event on TX1 or TX2,
can be a high-to-low transition or a low-to-high transition depending on the setting of the TX1 and TX2 polarity
bits (see Configuration Register 1 Bits [6:5]).
LED THERMAL FAULT (NTC Flag)
The NTC flag (bit [5] of the Flags Register) reads back a '1' if the LM3560 is active in Flash or Torch mode, the
device is in NTC mode, and the voltage at LEDI/NTC has fallen below VTRIP (1V typical). When this has
happened, and the LM3560 has been forced into Torch mode or LED shutdown (depending on the state of
Configuration Register 2 bit [1), the Flags Register must be read, and VLEDI/NTC must go above 1V in order to
place the device back in normal operation. (see NTC MODE section for more details).
VIN FLASH MONITOR FAULT
The VIN Flash Monitor Flag (bit [6] of the Flags Register) reads back a '1' if the VIN Flash Monitor is enabled and
VIN falls below the programmed VIN Flash Monitor threshold. This flag must be read back in order to resume
normal operation after the LED current has been forced to the lower flash current setting.
VIN MONITOR FAULT
The VIN Monitor Flag (bit [7] of the Flag Register) reads back a '1' when the VIN Monitor is enabled and VIN falls
below the programmed VIN Monitor threshold. This flag must be read back and VIN must go above the VIN
Monitor Threshold in order to resume normal operation after the LED current has been forced to Torch mode or
turned off due to a VIN Monitor event.
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I2C-Compatible Interface
START AND STOP CONDITIONS
The LM3560 is controlled via an I2C-compatible interface. START and STOP conditions classify the beginning
and end of the I2C session. A START condition is defined as SDA transitioning from HIGH-to-LOW while SCL is
HIGH. A STOP condition is defined as SDA transitioning from LOW-to-HIGH while SCL is HIGH. The I2C master
always generates the START and STOP conditions.
SDA
SCL
S
P
Start Condition
Stop Condition
Figure 41. Start and Stop Sequences
The I2C bus is considered busy after a START condition and free after a STOP condition. During data
transmission the I2C master can generate repeated START conditions. A START and a repeated START
condition are equivalent function-wise. The data on SDA must be stable during the HIGH period of the clock
signal (SCL). In other words, the state of SDA can only be changed when SCL is LOW. Figure 42 shows the
SDA and SCL signal timing for the I2C-Compatible Bus. See the Electrical Table for timing values.
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tSU;DAT
tRISE
70%
70%
70%
SDA
30%
30%
30%
30%
tHD;DAT
tRISE
tFALL
70%
tVD;DAT
tHIGH
70%
70%
SCL
30%
30%
30%
30%
9th Clock
Pulse
1/fSCL
tHD;STA
tLOW
Start
tBUF
70%
70%
SDA
(Continued)
70%
30%
30%
tHD;STA
tSU;STA
70%
70%
tVD;ACK
tSU;STO
70%
70%
SCL
(Continued)
30%
h
9t Clock
Pulse
Repeated
Start
Stop
Start
Figure 42. I2C-Compatible Timing
I2C-COMPATIBLE CHIP ADDRESS
The device address for the LM3560 is 1010011 (0xA7 for read and 0xA6 for write). After the START condition,
the I2C master sends the 7-bit address followed by an eighth read or write bit (R/W). R/W = 0 indicates a WRITE
and R/W = 1 indicates a READ. The second byte following the device address selects the register address to
which the data will be written. The third byte contains the data for the selected register.
MSB
1
Bit 7
LSB
0
Bit 6
1
Bit 5
0
Bit 4
0
Bit 3
1
Bit 2
1
Bit 1
R/W
Bit 0
2
I C Slave Address (chip address)
Figure 43. Device Address
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TRANSFERRING DATA
Every byte on the SDA line must be eight bits long, with the most significant bit (MSB) transferred first. Each byte
of data must be followed by an acknowledge bit (ACK). The acknowledge related clock pulse (9th clock pulse) is
generated by the master. The master releases SDA (HIGH) during the 9th clock pulse (write mode). The LM3560
pulls down SDA during the 9th clock pulse, signifying an acknowledge. An acknowledge is generated after each
byte has been received.
Register Descriptions
Table 3. LM3560 Internal Registers
Register Name
Internal Hex Address
Power On/RESET Value
Enable
0x10
0x18
Privacy
0x11
0x58
Indicator
0x12
0x00
Indicator Blinking
0x13
0x00
Privacy PWM
0x14
0xF8
GPIO
0x20
0x80
VLED Monitor (ADC)
0x30
0x80
ADC Delay
0x31
0x90
VIN Monitor
0x80
0xC0
Last Flash
0x81
0x00
Torch Brightness
0xA0
0x52
Flash Brightness
0xB0
0xDD
Flash Duration
0xC0
0xEF
Flags
0xD0
0x00
Configuration 1
0xE0
0x6B
Configuration 2
0xF0
0xE0
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ENABLE REGISTER (Address 0x10)
Bits [1:0] of the Enable Register controls the on/off state of Torch mode, Flash mode, and Privacy Indicate mode.
Bit 2 selects the peak current setting for Privacy Indicate mode (max or min torch current). Bits [4:3] turn on/off
the main current sources (LED1 and LED2). Bit [5] sets the level or edge control for the STROBE input. Bits 7
and 6 control the Indicator current source (see Table 4).
Table 4. Enable Register Descriptions
Bit 7
(EN Blink)
Bit 6
(EN Message
Indicator)
Bit 5
(STROBE
Level/Edge)
0 = Message
Indicator
Blinking
Function is
disabled (1)
(default)
1 = Message
Indicator
Blinking
Function is
enabled. The
message
indicator blinks
the pattern
programmed in
the Indicator
Register and
Indicator
Blinking
Register
0 = Message
Indicator is
disabled
(Default)
1= Message
Indicator is
enabled.
0 = (Level Sensitive)
0 = LED2 off
When STROBE goes
1 = LED2 on
high, the Flash current
(default)
will turn on and remain
on for the duration the
STROBE pin is held high
or when the Flash
Timeout occurs,
whichever comes first.
(default)
1 = (Edge Triggered)
When STROBE goes
high, the Flash current
will turn on and remain
on for the duration of the
Flash Time-out.
(1)
Bit 4
(LED2
ENABLE)
Bit 3
(LED1
Enable)
Bit 2
(Privacy
Mode Peak
Current
Setting)
Bit 1
(EN1)
Bit 0
(EN0)
0 = LED1 off
1 = LED1 on
(default)
0 = 31.25mA
(default)
1 = 250 mA
Enable Bits
00 = Current Sources are
Shutdown (default)
01 = Privacy Indicator Mode
10 = Torch Mode
11 = Flash Mode (bits reset
at timeout)
Bit 7 Enables/Disables the Message Indicator Blinking Function. With this bit set to 0 and Bit 6 set to 1, the Message Indicator turns on
constantly at the programmed current as set in Indicator Register bits [2:0].
PRIVACY REGISTER (Address 0x11)
The Privacy Register contains the bits that control which current source is used for the privacy indicator (LED1 or
LED2 or both), whether the privacy indicator turns off or remains on after the flash pulse terminates, and the duty
cycle settings (between 10% and 80%) for setting the average privacy LED current (see Table 5 ).
Table 5. Privacy Register
Bit 7
(Blink 2)
Bit 6
(Blink 1)
tBLINK
00 = No Blinking
01 = 128 ms Blink Period
(Default)
10 = 256 ms Blink Period
11 = 512 ms Blink Period
30
Bit 5
(LED2 Privacy)
Bit 4
(LED1 Privacy)
Bit 3
(Privacy
Terminate)
Bit 2 (PD2)
0 = LED2 is off
for privacy
mode (Default)
1 = LED2 is on
for privacy
mode
0 = LED1 is off
for privacy
mode
1 = LED1 is on
for privacy
mode (Default)
0 = Privacy
mode turns
back on at the
end of the flash
pulse
1 = Privacy
mode remains
off at the end of
the flash pulse
(Default)
Privacy mode current levels (% of minimum or
maximum torch current, depending on bit [2] of
Enable Register)
000 = 10% (Default)
001 = 20%
010 = 30%
011 = 40%
100 = 50%
101 = 60%
110 = 70%
111 = 80%
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Bit 1 (PD1)
Bit 0 (PD0)
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INDICATOR REGISTER (Address 0x12)
The Indicator Register contains the bits which control the following:
1. Indicator current level
2. Pulse width
3. Ramp times for turn-on and turn-off of the indicator current source (see Figure 44 for the message indicator
timing diagram).
Table 6. Indicator Register
Bit 7 (R2)
Bit 6 (R1)
(tR and tF)
00 = 78 ms (default)
01 = 156 ms
10 = 312 ms
11 = 624 ms
Bit 5 (P3)
Bit 4 (P2)
Bit 3 (P1)
(PERIOD#)
000 = 0 (default)
001 = 1
010 = 2
011 = 3
100 = 4
101 = 5
110 = 6
111 = 7
Bit 2 (I3)
Bit 1 (I2)
Bit 0 (I1)
(IIND)
000 = 2.25 mA (default)
001 = 4.5 mA
010 = 6.75 mA
011 = 9 mA
100 = 11.25 mA
101 = 13.5 mA
110 = 15.75 mA
111 = 18 mA
INDICATOR BLINKING REGISTER (Address 0x13)
The Indicator Blinking Register contains the bits which control the following:
1. Number of periods (tPERIOD = tR + tF + 2 x tPULSE )
2. Active Time (tACTIVE = tPERIOD × PERIOD# )
3. Blank Time (tBLANK = tACTIVE × BLANK#)
– (see Figure 44)
Table 7. Indicator Blinking Register
Bit 7 (N/A)
Not used
Bit 6 (M3)
Bit 5 (M2)
Bit 4 (M1)
BLANK#
0000 = 0 (default)
0001 = 1
0010 = 2
0011 = 3
0100 = 4
0101 = 5
0110 = 6
0111 = 7
1000 = 8
1001 = 9
1010 = 10
1011 = 11
1100 = 12
1101 = 13
1110 = 14
1111 = 15
Bit 3 (PW4)
Bit 2 (PW3)
Bit 1 (PW2)
Bit 0 (PW1)
Pulse Time (tPULSE)
0000 = 0 (default)
0001 = 32 ms
0010 = 64 ms
0011 = 92 ms
0100 = 128 ms
0101 = 160 ms
0110 = 196 ms
0111 = 224 ms
1000 = 256 ms
1001 = 288 ms
1010 = 320 ms
1011 = 352 ms
1100 = 384 ms
1101 = 416 ms
1110 = 448 ms
1111 = 480 ms
tPERIOD
tBLANK
tPERIOD
tPULSE
tPULSE
IIND
tR
tF
tR
tPULSE
tF
tPULSE
Figure 44. Message Indicator Timing Diagram
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PRIVACY PWM PERIOD REGISTER (Address 0x14)
The Privacy PWM Register contains the bits to control the PWM period for the privacy indicate mode (see
Table 8).
Table 8. Privacy PWM Period Register
Bits 7-3
(Not Used)
Bit 2
(P3)
Bit 1
(P2)
Bit 0
(P1)
000 = 5.12 ms (default)
001 = 2.56 ms
010 = 1.28 ms
011 = 640 µs
1XX = 320 µs
GPIO REGISTER (Address 0x20)
The GPIO register contains the control bits which change the state of the TX1/TORCH/GPIO1 pin and the
TX2/INT/GPIO2 pins to general purpose I/O’s (GPIO’s). Additionally, bit 6 of this register contains the interrupt
configuration bit. Table 9 describes the bit description and functionality of the GPIO register. To configure the
TX1 or TX2 pins as GPIO outputs an initial double write is required to register 0x20. For example, to configure
TX2 to output a logic high, an initial write of 0xB8 would need to occur twice, to force GPIO2 low. Subsequent
writes to GPIO2 after the initial set-up, only requires a single write. To read back the GPIO inputs, a write then a
read of register 0x20 must occur each time the data is read. For example, if GPIO2 is set-up as a GPIO input
and the GPIO2 input has then changed state, first a write to 0x20 must occur, then the following read back of
register 0x20 will show the updated data. When configuring TX2 as an interrupt output, the TX2/GPIO2/INT pin
must first be configured as a GPIO output (double write). For example, to configure TX2/GPIO2/INT for INT
mode a write of 0xF8 to register 0x20 must be done twice.
Table 9. GPIO Register
Bit 7
(Not
Used)
Bit 6
Bit 5
(TX2/INT/GPIO2 (TX2/INT/GPI
Interrupt Enable) O2 data)
Bit 4
(TX2/INT/GPI
O2 data
direction)
Bit 3
(TX2/INT/GPIO2
Control)
Bit 2
(TX1/TORCH/G
PIO1 data)
Bit 1
(TX1/TORCH/G
PIO1 data
direction)
Bit 0
(TX1/TORCH/G
PIO1 Control)
N/A
0=
TX2/INT/GPIO2
is configured
according to bit 3
of this register
(default)
0=
TX2/INT/GPIO
2 is a GPIO
Input (default)
0=
TX2/INT/GPIO is
configured as a
TX interrupt
(default)
This bit is the
read or write
data for the
GPIO1 pin in
GPIO mode
0=
TX1/TORCH/GP
IO1 is a GPIO
input (default)
0=
TX1/TORCH/GP
IO1 pin is
configured as
TX
interrupt(default
)
1=
TX2/INT/GPIO
2 is a GPIO
output
1=
TX2/INT/GPIO2
is configured as a
GPIO
This bit is the
read or write
data for the
TX2/INT/GPIO
2 pin in GPIO
mode
1 = with bits [4:3]
= 11,
TX2/INT/GPIO2
is an interrupt
output. See
INTERRUPT
OUTPUT (INT
MODE).
32
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1
1=
TX1/TORCHGPI TX1/TORCH/GP
O1 is an output IO1 pin is
configured as a
GPIO
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LED FORWARD VOLTAGE ADC (VLED MONITOR REGISTER, Address 0x30)
The VLED Monitor Register controls the internal 4 bit analog to digital converter. Bits [3:0] of this register contain
the 4-bit data of the LED voltage. This data is the digitized voltage of the highest of either VLED1 to GND or
VLED2 to GND. Bit [4] is the Manual Mode enable which provides for a manual conversion of the ADC. In
Manual Mode the Automatic Conversion is still performed. In automatic conversion mode a conversion is
performed each time a flash pulse is initiated. Bit [5] is the ADC shutdown bit. Bit [6] signals the end of
conversion. This is a read-only bit that goes high when a conversion is complete and data is ready. A read of the
VLED Monitor Register clears the End of Conversion bit (see Table 10).
Table 10. VLED Monitor Register Descriptions
Bit 7
(Not
Used)
Bit 6
(End of
Conversion)
N/A
0 = Conversion in 0 = ADC is enabled
progress(default) (default)
1 = Conversion
done
Bit 5
(ADC Shutdown)
Bit 4
(Manual Mode
Enable)
Bit 3
(ADC3)
Bit 2
(ADC2)
Bit 1
(ADC1)
Bit 0
(ADC0)
0 = Manual Mode 0000 = (VLED < 2.8V) (default)
Disabled
0001 = (2.8V ≤ VLED < 2.9V)
(default)
0010 = (2.9V ≤ VLED < 3.0V)
0011 = (3.0V ≤ VLED < 3.1V)
1 = ADC is shutdown, 1 = Manual Mode
0100 = (3.1V ≤ VLED < 3.2V)
no conversion is
is Enabled
0101 = (3.2V ≤ VLED < 3.3V)
performed
0110 = (3.3V ≤ VLED < 3.4V)
0111 = (3.4V ≤ VLED < 3.5V)
1000 = (3.5V ≤ VLED < 3.6V)
1001 = (3.6V ≤ VLED < 3.7V)
1010 = (3.7V ≤ VLED < 3.8V)
1011 = (3.8V ≤ VLED < 3.9V)
1100 = (3.9V ≤ VLED < 4.0V)
1101 = (4.0V ≤ VLED < 4.1V)
1110 = (4.1V ≤ VLED < 4.2V)
1111 = (4.2V ≤ VLED)
ADC DELAY REGISTER (Address 0x31)
The ADC Delay Register programs the delay from when the EOC bit goes low to when a conversion is initiated.
This delay applies to both Manual Mode and Automatic Mode. Bit 5 is the No Delay bit and can set the delay to
effectively 0.
Table 11. ADC Delay Register Descriptions
Bit 7
(Not
Used)
Bit 6
(Not used)
Bit 5 (No Delay)
Bit 4 (D1)
Bit 3 (D2)
Bit 2 (D3)
Bit 1 (D4)
Bit 0
(D5)
0 = Delay is set by bits
[4:0](default)
N/A
Bits [4:0] programs the delay from when the EOC bit goes low to when a
conversion is started (250 µs/step).
00000 = 250 µs
1 = no delay from when the EOC
:
goes low to when the conversion is
01111 = 4 ms (default)
started.
:
11111 = 8 ms
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VIN MONITOR REGISTER (Address 0x80)
The VIN Monitor Register controls the Enable bit for the VIN Monitor, the threshold select for the VIN Monitor, the
enable bit for the VIN Flash Monitor, and the threshold select for the VIN Flash Monitor (see Table 12).
Table 12. VIN Monitor Register Descriptions
Bit 7
(Not used)
Bit 6
(Not used)
N/A
Bit 5
(VIN Flash
Monitor
Threshold 1)
Bit 4
(VIN Flash
Monitor
Threshold 2)
00= 2.9V (default)
01 = 3.0V
10 = 3.1V
11 = 3.2V
Bit 3
(VIN Flash
Monitor
enable)
0 = VIN Flash
Monitor is
disabled
(default)
Bit 2
(VIN Monitor
Threshold1)
Bit 1
(VIN Monitor
Threshold0)
00 = 2.9V Default
01= 3.0V
10 = 3.1V
11 = 3.2V
Bit 0
(VIN Monitor
Enable)
0 = VIN Monitor
disabled (default)
1 = VIN Flash
Monitor is
enabled
1 = VIN Monitor is
enabled
LAST FLASH REGISTER (Address 0x81)
The Last Flash Register is a read-only register which is loaded with the flash code corresponding to the flash
level that the LM3560 was at if any of the following events happen:
1. Voltage at LEDI/NTC falling below VTRIP with the device in NTC mode (Configuration Register 1 bit[4] = 1);
2. Input voltage falling below the programmed VIN Monitor Threshold with device in VIN Monitor mode (VIN
Monitor Register bit [0] = 1); or
3. Input voltage falling below the programmed VIN Flash Monitor Threshold with the device in VIN Flash
Monitor mode (VIN Monitor Register bit [3] = 1).
The Last Flash Register is updated at the same time that the corresponding Flag bit is written to the Flags
Register. This results in a delay of 250 µs from when VLEDI/NTC (NTC mode) crosses VTRIP, or VIN (VIN Monitor
enabled) crosses the VIN_TH. During VIN Flash Monitor there is a 8us deglitch time so the VIN Flash Monitor Flag
is written (and the Last Flash Register is updated) 8 µs after VIN falls below VIN_FLASH.
Table 13. Last Flash Register Descriptions
Bit 7
(LF2A)
Bit 6
(LF2B)
Bit 5
(LF2C)
Bit 4
(LF2D)
These bits are read only and represent the Flash Current Code
for LED2 that the LM3560 was at during the interrupt.
0000 = 62.5 mA
0001 = 125 mA
0010 = 187.5 mA
0011 = 250 mA
0100 = 312.5 mA
0101 = 375 mA
0110 = 437.5 mA
0111 = 500 mA
1000 = 562.5 mA
1001 = 625 mA
1010 = 687.5 mA
1011 = 750 mA
1100 = 812.5 mA
1101 = 875 mA
1110 = 937.5 mA
1111 = 1000 mA
34
Bit 3
(LF1A)
Bit 2
(LF1B)
Bit 1
(LF1C)
Bit 0
(LF1D)
These bits are read only and represent the Flash Current Code for
LED1 that the LM3560 was at during the interrupt.
0000 = 62.5 mA
0001 = 125 mA
0010 = 187.5 mA
0011 = 250 mA
0100 = 312.5 mA
0101 = 375 mA
0110 = 437.5 mA
0111 = 500 mA
1000 = 562.5 mA
1001 = 625 mA
1010 = 687.5 mA
1011 = 750 mA
1100 = 812.5 mA
1101 = 875 mA
1110 = 937.5 mA
1111 = 1000 mA
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TORCH BRIGHTNESS REGISTER DESCRIPTIONS (Address 0xA0)
Bits [2:0] of the Torch Brightness Register set the Torch current for LED1. Bits [5:3] set the Torch current for
LED2 (see Table 14).
Table 14. Torch Brightness Register Descriptions
Bit 7
(N/A)
Bit 6
(N/A)
(Not Used)
Bit 5
(TC2A)
Bit 4
(TC2B)
Bit 3
(TC2C)
LED2 Torch Current Select Bits
000 = 31.25 mA (62.5 mA total)
001 = 62.5 mA (125 mA total)
010 =93.75 mA (187.5 mA total) default
011 = 125 mA (250 mA total)
100 = 156.25 mA (312.5 mA total)
101 = 187.5 mA (375 mA total)
110 = 218.75 mA (437.5 mA total)
111 = 250 mA (500 mA total)
Bit 2
(TC1A)
Bit 1
(TC1B)
Bit 0
(TC1C)
LED1 Torch Current Select Bits
000 = 31.25 mA (62.5 mA total)
001 = 62.5 mA (125 mA total)
010 =93.75 mA (187.5 mA total) default
011 = 125 mA (250 mA total)
100 = 156.25 mA (312.5 mA total)
101 = 187.5 mA (375 mA total)
110 = 218.75 mA (437.5 mA total)
111 = 250 mA (500 mA total)
FLASH BRIGHTNESS REGISTER (Address 0xB0)
Bits [3:0] of the Flash Brightness Register set the Flash current for LED1. Bits [7:4] set the Flash current for
LED2 (see Table 15).
Table 15. Flash Brightness Register Descriptions
Bit 7
(FC2A)
Bit 6
(FC2B)
Bit 5
(FC2C )
Flash Current Select Bits
0000 = 62.5 mA
0001 = 125 mA
0010 = 187.5 mA
0011 = 250 mA
0100 = 312.5 mA
0101 = 375 mA
0110 = 437.5 mA
0111 = 500 mA
1000 = 562.5 mA
1001 = 625 mA
1010 = 687.5 mA
1011 = 750 mA
1100 = 812.5 mA
1101 = 875 mA (default)
1110 = 937.5 mA
1111 = 1000 mA
Bit 4
(FC2D)
Bit 3
(FC1A )
Bit 2
(FC1B)
Bit 1
(FC1C)
Bit 0
(FC1D)
Flash Current Select Bits
0000 = 62.5 mA
0001 = 125 mA
0010 = 187.5 mA
0011 = 250 mA
0100 = 312.5 mA
0101 = 375 mA
0110 = 437.5 mA
0111 = 500 mA
1000 = 562.5 mA
1001 = 625 mA
1010 = 687.5 mA
1011 = 750 mA
1100 = 812.5 mA
1101 = 875 mA (default)
1110 = 937.5 mA
1111 = 1000 mA
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FLASH DURATION REGISTER (Address 0xC0)
Bits [4:0] of the Flash Duration Register set the Flash Timeout duration. Bits [6:5] set the switch current limit (see
Table 16).
Table 16. Flash Duration Register Descriptions
Bit 7
(Not used)
N/A
Bit 6
(CL1)
Bit 5
(CL0)
Current Limit Select Bits
00 = 1.6A Peak Current Limit
01 = 2.3A Peak Current Limit
10 = 3.0A Peak Current Limit
11 = 3.6A Peak Current Limit
(default)
Bit 4
(T4)
Bit 3
(T3)
Bit 2
(T2)
Bit 1
(T1)
Bit 0
(T0)
Flash Time-out Select Bits
00000 = 32 ms time-out
00001 = 64 ms time-out
00010 = 96 ms time-out
00011 = 128 ms time-out
00100 = 160 ms time-out
00101 = 192 ms time-out
00110 = 224 ms time-out
00111 = 256 ms time-out
01000 = 288 ms time-out
01001 = 320 ms time-out
01010 = 352 ms time-out
01011 = 384 ms time-out
01100 = 416 ms time-out
01101 = 448 ms time-out
01110 = 480 ms time-out
01111 = 512 ms time-out (default)
10000 = 544 ms time-out
10001 = 576 ms time-out
10010 = 608 ms time-out
10011 = 640 ms time-out
10100 = 672 ms time-out
10101 = 704 ms time-out
10110 = 736 ms time-out
10111 = 768 ms time-out
11000 = 800 ms time-out
11001 = 832 ms time-out
11010 = 864 ms time-out
11011 = 896 ms time-out
11100 = 928 ms time-out
11101 = 960 ms time-out
11110 = 992 ms time-out
11111 = 1024 ms time-out
FLAGS REGISTER (Address 0xD0)
The Flags Register holds the flag bits indicating Flash Timeout, Thermal Shutdown, LED Fault (Open or Short),
TX Interrupts (TX1 and TX2), LED Thermal Fault (NTC), VIN Monitor Trip, and VIN Flash Monitor Trip. All Flags
are cleared on read back of the Flags Register. (See Table 17).
Table 17. Flags Register Descriptions
Bit 7
(VIN Monitor)
Bit 6
(VIN Flash
Monitor)
Bit 5
(NTC Fault)
Bit 4
(TX2
Interrupt)
0 = VIN is
above the VIN
Monitor
Threshold or
VIN Monitor
Threshold is
Disabled
(default)
VIN did not fall
below the VIN
Flash Monitor
threshold
during flash
pulse turn-on
or VIN Flash
Monitor is
disabled
(default)
0 = LEDI/NTC
pin is above
1V(default)
0 = TX2 has
not changed
state (default)
36
Bit 3
(TX1 Interrupt )
0 = TX1 has not
changed state
(default)
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Bit 2
(LED Fault)
0 = Proper
LED Operation
(default)
Bit 1
(Thermal
Shutdown)
Bit 0
(Flash Timeout)
0 = Die
0 = Flash TimeTemperature
Out did not
below Thermal expire (default)
Shutdown Limit
(default)
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Table 17. Flags Register Descriptions (continued)
Bit 7
(VIN Monitor)
1 = VIN
Monitor is
enabled and
VIN has fallen
below the
programmed
threshold
Bit 6
(VIN Flash
Monitor)
1 = VIN Flash
Monitor is
enabled and
VIN fell below
the
programmed
VIN Flash
Monitor
threshold
during flash
pulse turn-on
Bit 5
(NTC Fault)
Bit 4
(TX2
Interrupt)
1 = NTC mode
is enabled and
LEDI/NTC has
fallen below 1V
1 = TX2 has
changed state
(TX2 mode
only)
Bit 3
(TX1 Interrupt )
1 = TX1 has
changed state
(TX1 mode only)
Bit 2
(LED Fault)
Bit 1
(Thermal
Shutdown)
1 = LED Failed 1 = Die
(Open or
Temperature
Short)
has crossed
the Thermal
Shutdown
Threshold
Bit 0
(Flash Timeout)
1 = Flash TimeOut Expired
CONFIGURATION REGISTER 1 (Address 0xE0)
Configuration Register 1 holds the STROBE Enable bit, the STROBE polarity bit, the NTC Enable bit, the polarity
selection bit for TX1 and TX2, and the Hardware Torch Enable bit (see Table 18).
Table 18. Configuration Register 1 Descriptions
Bit 7
(Hardware
Torch Mode
Enable)
Bit 6
(TX2 Polarity)
Bit 5
(TX1 Polarity)
Bit 4
(NTC Mode
Enable)
Bit 3
(STROBE
Polarity)
Bit 2
(STROBE
Input Enable)
0=
TX1/TORCH is
a TX
input(default)
0 = TX2 is
configured for
active low
polarity
0 = TX1 is
configured for
active low
polarity
0 = LEDI/NTC
pin is
configured as
an indicator
output (default)
0 = STROBE
Input Enable is
active low.
Pulling
STROBE low
will turn on
Flash current
0 = STROBE
Input Disabled
(Default)
1=
TX1/TORCH
pin is a
hardware
TORCH
enable. This bit
is reset to 0
after a flash
pulse.
1 =TX2 pin is
configured for
active high
polarity
(default)
1 = TX1 is
configured for
active high
polarity
(default)
1 = LEDI/NTC
is configured as
a comparator
input for an
NTC thermistor
1 = STROBE
Input is active
high. Pulling
STROBE high
will turn on
Flash current
(default)
1 = STROBE
Input Enabled
Bit 1
(Not Used)
N/A
Bit 0
(Not Used)
N/A
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CONFIGURATION REGISTER 2 (Address 0xF0)
Configuration Register 2 holds the TX2 shutdown select bit, the NTC shutdown select bit, the Alternate External
Torch mode select bit, the VIN Monitor Shutdown bit, and the TX1 shutdown bit (see Table 19).
Table 19. Configuration Register 2 Bit Descriptions
Bit 7
(Not used)
N/A
38
Bit 6
(Not used)
N/A
Bit 5
(Not used)
N/A
Bit 4
(TX1
Shutdown)
Bit 3
(VIN Monitor
Shutdown)
Bit 2
(AET mode)
0 = TX1
interrupt will
force the LED
current to the
programmed
torch current
level (default)
0 = VIN falling
below the
programmed
VIN Monitor
Threshold will
force the LED
current into the
programmed
torch current
level (default)
0 = AET Mode
Disabled
(default)
0 = Voltage at
LEDI/NTC
falling below
VTRIP will force
the LED current
to the
programmed
torch current
level.(default)
0 = TX2
interrupt will
force the LED
current to the
programmed
torch current
level (default)
1 = TX1
interrupt will
force the LED
current into
shutdown.
1 = VIN falling
below the
programmed
VIN Monitor
Threshold will
force the LED
current into
shutdown.
1 = AET Mode
Enabled
1 = Voltage at
LEDI/NTC
falling below
VTRIP will force
the LED current
into shutdown.
1 = TX2
interrupt will
force the LED
current into
shutdown.
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Bit 1
(NTC
Shutdown)
Bit 0
(TX2
Shutdown)
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APPLICATIONS INFORMATION
Output Capacitor Selection
The LM3560 is designed to operate with at least a 10 µF ceramic output capacitor. When the boost converter is
running the output capacitor supplies the load current during the boost converters on-time. When the NMOS
switch turns off the inductor energy is discharged through the internal PMOS switch, supplying power to the load
and restoring charge to the output capacitor. This causes a sag in the output voltage during the NFET on-time
and a rise in the output voltage during the NFET off-time. The output capacitor is therefore chosen to limit the
output ripple to an acceptable level depending on load current and input/output voltage differentials and also to
ensure the converter remains stable.
For proper operation the output capacitor must be at least a 10 µF ceramic. Larger capacitors such as a 22 µF or
multiple capacitors in parallel can be used if lower output voltage ripple is desired. To estimate the output voltage
ripple considering the ripple due to capacitor discharge (ΔVQ) and the ripple due to the capacitors ESR (ΔVESR)
use the following equations:
For continuous conduction mode, the output voltage ripple due to the capacitor discharge is:
'VQ =
ILED x (VOUT - VIN)
fSW x VOUT x COUT
(1)
The output voltage ripple due to the output capacitors ESR is found by:
'VESR = R ESR x §
©
where
'IL =
I LED x VOUT·
VIN
¹
+ 'I L
VIN x (VOUT - VIN )
2 x f SW x L x VOUT
(2)
In ceramic capacitors the ESR is very low so a close approximation is to assume that 80% of the output voltage
ripple is due to capacitor discharge and 20% from ESR. Table 20 lists different manufacturers for various output
capacitors and their case sizes suitable for use with the LM3560.
Input Capacitor Selection
Choosing the correct size and type of input capacitor helps minimize the input voltage ripple caused by the
switching of the LM3560’s boost converter, and reduces noise on the boost converters input terminal that can
feed through and disrupt internal analog signals. In the Typical Application Circuit a 10 µF ceramic input
capacitor works well. It is important to place the input capacitor as close as possible to the LM3560’s input (IN)
terminals. This reduces the series resistance and inductance that can inject noise into the device due to the input
switching currents. Table 20 lists various input capacitors that are recommended for use with the LM3560.
Table 20. Recommended Input/Output Capacitors (X5R Dielectric)
Part Number
Value
Case Size
Voltage Rating
TDK Corporation
Manufacturer
C1608JB0J106M
10 µF
0603 (1.6mm×0.8mm×0.8mm)
6.3V
TDK Corporation
C2012JB1A106M
10 µF
0805 (2mm×1.25mm×1.25mm)
10V
GRM21BR61A106KE19
10 µF
0805 (2mm×1.25mm×1.25mm)
10V
Murata
Inductor Selection
The LM3560 is designed to use a 1 µH or 2.2 µH inductor. Table 21 lists various inductors and their
manufacturers that can work well with the LM3560. When the device is boosting (VOUT > VIN) the inductor will
typically be the largest area of efficiency loss in the circuit. Therefore, choosing an inductor with the lowest
possible series resistance is important. Additionally, the saturation rating of the inductor should be greater than
the maximum operating peak current of the LM3560. This prevents excess efficiency loss that can occur with
inductors that operate in saturation. For proper inductor operation and circuit performance, ensure that the
inductor saturation and the peak current limit setting of the LM3560 are greater than IPEAK in the following
calculation:
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IPEAK =
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I LOAD VOUT
V x (VOUT - VIN)
x
+ 'IL where 'IL = IN
K
VIN
2 x f SW x L x VOUT
(3)
where ƒSW = 2MHz, and efficiency can be found in the Typical Performance Characteristics plots.
Table 21. Recommended Inductors
Manufacturer
L
Part Number
Dimensions (L×W×H)
ISAT
RDC
TOKO
2.2 µH
FDSD0312-H-2R02M
3 mm×3.2 mm×1.2 mm
2.3A
105 mΩ
TOKO
1 µH
FDSD0312-H-1R0M
3 mm×3.2 mm×1.2 mm
3.4A
43 mΩ
TDK
1 µH
VLS252012T-1R0N
2 mm×2.5 mm×1.2 mm
2.45A
73 mΩ
TDK
1 µH
VLS4012ET-1R0N
4 mm x 4 mm x 1.2 mm
2.8A
50 mΩ
NTC THERMISTOR SELECTION
Programming bit [4] of Configuration Register 1 with a '1' selects NTC mode and makes the LEDI/NTC pin a
comparator input for flash LED thermal sensing. Figure 45 shows the LM3560 using the NTC thermistor circuit.
The thermal sensor resistor divider is composed of R3 and R(T), where R(T) is the Negative Temperature
Coefficient Thermistor, VBIAS is the bias voltage for the resistive divider, and R3 is used to linearize the NTC's
response around the NTC comparators trip point. CBYP is used to filter noise at the NTC input.
1 PH/2.2 PH
SW
IN
OUT
VBIAS
10 PF
10 PF
LM3560
R3
LED1
LED2
HWEN
STROBE
Flash
LED
TX1/TORCH
TX2
SDA
Low Thermal
Impedance Between
R(T) and LED
R(T)
LEDI/NTC
SCL
GND
CBYP
Figure 45. Typical Application Circuit with Thermistor
In designing the NTC circuit, we must choose values for VBIAS, R(T) and R3. To begin with, NTC thermistors
have a non-linear relationship between temperature and resistance:
E
R(T) = R25°C x e
§ 1 ± 1·
©T °C+ 273 298¹
(4)
where β is given in the thermistor datasheet and R25C is the thermistor's value at +25°C. R3 is chosen so that the
temperature to resistance relationship becomes more linear and can be found by solving for R3 in the R(T) and
R3 resistive divider:
R3 =
RT( TRIP) (VBIAS - VTRIP )
VTRIP
(5)
where R(T)TRIP is the thermistor's value at the temperature trip point and VTRIP = 1V (typical). As an example,
with VBIAS = 2.5V and a thermistor whose nominal value at +25°C is 100 kΩ and a β = 4500K, the trip point is
chosen to be +93°C. The value of R(T) at 93°C is:
40
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R (T ) = 100kW ´ e
R3 is then :
1
1 ö
æ
bç
÷
è 93 + 273 298 ø
= 6.047kW
6.047kW ´ (2.5 V - 1V )
1V
= 9.071kW
(6)
Figure 46 shows the linearity of the thermistor resistive divider of the previous example.
1.5
VBIAS = 2.5V,
RTHERMISTOR = 100 k:
@ +25°C, B = 4500,
R3 = 9 k:
1.4
1.3
V LEDI/NTC (V)
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
70
75
80
85
90
95
100 105 110
TEMPERATURE (°C)
Figure 46. Thermistor Resistive Divider Response vs Temperature
Layout Recommendations
The high switching frequency and large switching currents of the LM3560 make the choice of layout important.
The following steps should be used as a reference to ensure the device is stable and maintains proper LED
current regulation across its intended operating voltage and current range.
1. Place CIN on the top layer (same layer as the LM3560) and as close to the device as possible. The input
capacitor conducts the driver currents during the low side MOSFET turn-on and turn-off and can see current
spikes over 1A in amplitude. Connecting the input capacitor through short wide traces to both the IN and
GND terminals will reduce the inductive voltage spikes that occur during switching and which can corrupt the
VIN line.
2. Place COUT on the top layer (same layer as the LM3560) and as close as possible to the OUT and GND
terminal. The returns for both CIN and COUT should come together at one point, and as close to the GND pin
as possible. Connecting COUT through short wide traces will reduce the series inductance on the OUT and
GND terminals that can corrupt the VOUT and GND line and cause excessive noise in the device and
surrounding circuitry.
3. Connect the inductor on the top layer close to the SW pin. There should be a low-impedance connection
from the inductor to SW due to the large DC inductor current, and at the same time the area occupied by the
SW node should be small so as to reduce the capacitive coupling of the high dV/dt present at SW that can
couple into nearby traces.
4. Avoid routing logic traces near the SW node so as to avoid any capacitively coupled voltages from SW onto
any high-impedance logic lines such as TX1/TORCH/GPIO1, TX2/INT/GPIO2, HWEN, LEDI/NTC (NTC
mode), SDA, and SCL. A good approach is to insert an inner layer GND plane underneath the SW node and
between any nearby routed traces. This creates a shield from the electric field generated at SW.
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Product Folder Links: LM3560
41
LM3560
SNOSB43B – SEPTEMBER 2011 – REVISED AUGUST 2013
www.ti.com
5. Terminate the Flash LED cathodes directly to the GND pin of the LM3560. If possible, route the LED returns
with a dedicated path so as to keep the high amplitude LED currents out of the GND plane. For Flash LEDs
that are routed relatively far away from the LM3560, a good approach is to sandwich the forward and return
current paths over the top of each other on two layers. This will help in reducing the inductance of the LED
current paths.
6. The NTC Thermistor is intended to have its return path connected to the LEDs cathode. This allows the
thermistor resistive divider voltage (VNTC) to trip the comparators threshold as VNTC is falling. Additionally, the
thermistor-to-LED cathode junction should be connected as close as possible in order to reduce the thermal
impedance between the LED and the thermistor. The drawback is that the thermistor's return will see the
switching currents from the LM3560's boost converter. Because of this, it is necessary to have a filter
capacitor at the NTC pin which terminates close to the GND of the LM3560 (see CBYP in Figure 45).
42
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Product Folder Links: LM3560
PACKAGE OPTION ADDENDUM
www.ti.com
5-May-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LM3560TLE-20/NOPB
ACTIVE
DSBGA
YZR
16
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
D73B
LM3560TLX-20/NOPB
ACTIVE
DSBGA
YZR
16
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
D73B
LM3560TLX/NOPB
NRND
DSBGA
YZR
16
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
3560
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
5-May-2014
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Nov-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
LM3560TLE-20/NOPB
DSBGA
YZR
16
250
178.0
8.4
LM3560TLX-20/NOPB
DSBGA
YZR
16
3000
178.0
LM3560TLX/NOPB
DSBGA
YZR
16
3000
178.0
2.08
2.08
0.76
4.0
8.0
Q1
8.4
2.08
2.08
0.76
4.0
8.0
Q1
8.4
2.08
2.08
0.76
4.0
8.0
Q1
Pack Materials-Page 1
W
Pin1
(mm) Quadrant
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Nov-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM3560TLE-20/NOPB
DSBGA
YZR
LM3560TLX-20/NOPB
DSBGA
YZR
16
250
210.0
185.0
35.0
16
3000
210.0
185.0
35.0
LM3560TLX/NOPB
DSBGA
YZR
16
3000
210.0
185.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
YZR0016xxx
D
0.600±0.075
E
TLA16XXX (Rev C)
D: Max = 1.99 mm, Min = 1.93 mm
E: Max = 1.99 mm, Min = 1.93 mm
4215051/A
NOTES:
A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
www.ti.com
12/12
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