Renesas ISL9120IIAZ-T7A Compact high efficiency low power buck-boost regulator Datasheet

DATASHEET
ISL9120
FN8659
Rev.2.00
May 23, 2017
Compact High Efficiency Low Power Buck-Boost Regulator
The ISL9120 is a highly integrated buck-boost switching
regulator that accepts input voltages either above or below the
regulated output voltage. This regulator automatically
transitions between buck and boost modes without significant
output disturbance. The ISL9120 also has automatic bypass
functionality. When the input voltage is generally within 1% to
2% of the output voltage, there will be a direct bypass
connection between the VIN and VOUT pins. In addition to the
automatic bypass functionality, the ISL9120 also has forced
bypass functionality with the use of the BYP pin.
Features
This device is capable of delivering up to 800mA of output
current (VIN = 2.5V, VOUT = 3.3V) and provides excellent
efficiency due to its adaptive current limit Pulse Frequency
Modulation (PFM) control architecture.
• Adaptive multilevel current limit scheme to optimize
efficiency at low and high currents
The ISL9120 is designed for stand-alone applications and
supports a 3.3V fixed output voltage or variable output
voltages with an external resistor divider. The forced bypass
power saving mode can be chosen if voltage regulation is not
required. The device consumes less than 3.5µA of current over
the operating temperature range in forced bypass mode.
The ISL9120 requires only a single inductor and very few
external components. Power supply solution size is minimized
by a 1.41mmx1.41mm WLCSP.
• Accepts input voltages above or below regulated output
voltage
• Automatic bypass mode functionality
• Automatic and seamless transitions between buck and
boost modes
• Input voltage range: 1.8V to 5.5V
• Selectable forced bypass power saving mode
• Output current: up to 800mA (VIN = 2.5V, VOUT = 3.3V)
• High efficiency: up to 98%
• 41µA quiescent current maximizes light-load efficiency
• Fully protected for over-temperature and undervoltage
• Small 1.41m x1.41mm WLCSP
Applications
• Smartphones and tablets
• Portable consumer and wearable devices
Related Literature
• For a full list of related documents, visit our website
- ISL9120 product page
100
C1
10F
VIN = 3.6V
ISL9120IINZ
VIN
95
LX1
L1
1H
LX2
ENABLE
DISABLE
FORCED BYPASS
BUCK-BOOST
EN
VOUT
VOUT = 3.3V
FB
C2
22F TO 47F
BYP
EFFICIENCY (%)
VIN =
1.8V TO 5.5V
90
85
VIN = 3V
VIN = 4V
VIN = 3.4V
VIN = 2.5V
80
75
GND PGND
70
FIGURE 1. TYPICAL FIXED OUTPUT APPLICATION
FN8659 Rev.2.00
May 23, 2017
1
10
100
OUTPUT CURRENT (mA)
1000
FIGURE 2. EFFICIENCY: VOUT = 3.3V, TA = +25°C
Page 1 of 13
ISL9120
Block Diagram
VIN
LX1
LX2
A1
C1
A2
C2
SOFT
DIS CHARGE
-
+
REVERSE
CURRENT
VREF
GATE DRIVERS
AT ANTISHOOT THRU
VOUT
EN
EN
B1 PGND
PVIN
MONITOR
VOUT
CLAMP
THE RMAL
SHUTDOWN
PFM CONTROL
CURRENT
DETECT
EN B2
BYPS A3
VOLTAGE
COMPARATOR
C3
EN
+
VREF
+
ILIM
-
FB
VOLTAGE
PROG.
CURRENT
COMPARATOR
B3
GND
FIGURE 3. BLOCK DIAGRAM
Pin Descriptions
Pin Configuration
ISL9120
9 BUMP WLCSP
BOTTOM VIEW
PIN #
LX2
VOUT
FB
PGND
EN
GND
C
B
LX1
VIN
BYP
1
2
3
A
FN8659 Rev.2.00
May 23, 2017
PIN NAMES
DESCRIPTION
C1
LX2
C2
VOUT
Inductor connection, output side.
C3
FB
Voltage feedback pin, connect directly to
VOUT pin for fixed output version.
B1
PGND
Power ground for high switching current.
B2
EN
B3
GND
Analog ground pin.
A1
LX1
Inductor connection, input side.
A2
VIN
Power supply input. Range: 1.8V to 5.5V.
Connect a 10µF capacitor to PGND.
A3
BYP
Forced bypass mode enable pin. Logic high
for forced bypass mode operation. Logic
low for buck-boost mode operation. Do not
leave floating.
Buck-boost output. Connect a 22µF or 47µF
capacitor to PGND.
Logic input, drive HIGH to enable device. Do
not leave floating.
Page 2 of 13
ISL9120
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
ISL9120IINZ-T
PART
MARKING
VOUT
(V)
TEMP RANGE
(°C)
TAPE AND REEL
QUANTITY
(UNITS)
120N
3.3
-40 to +85
3k
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
9 Bump WLCSP
W3x3.9E
ISL9120IIAZ-T
120A
ADJ.
-40 to +85
3k
9 Bump WLCSP
W3x3.9E
ISL9120IINZ-T7A
120N
ADJ.
-40 to +85
250
9 Bump WLCSP
W3x3.9E
ISL9120IIAZ-T7A
120A
ADJ.
-40 to +85
250
9 Bump WLCSP
W3x3.9E
ISL9120IIN-EVZ
Evaluation Board for ISL9120IINZ
ISL9120IIA-EVZ
Evaluation Board for ISL9120IIAZ
NOTES:
1. Refer to TB347 for details on reel specifications.
2. These Intersil Pb-free WLCSP and BGA packaged products employ special Pb-free material sets, molding compounds/die attach materials, and
SnAgCu -e1 solder ball terminals, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free WLCSP
and BGA packaged products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
3. For Moisture Sensitivity Level (MSL), see the product information page for ISL9120. For more information on MSL, see TB363.
FN8659 Rev.2.00
May 23, 2017
Page 3 of 13
ISL9120
Absolute Maximum Ratings
Thermal Information
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
LX1, LX2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
FB (Adjustable Version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V
FB (Fixed VOUT Version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
GND, PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
ESD Rating
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . .2.5kV
Machine Model (Tested per JESD22-A115C) . . . . . . . . . . . . . . . . . 200V
Charged Device Model (Tested per JESD22-C101F). . . . . . . . . . . . . . 2kV
Latch-Up (Tested per JESD78D; Class 2) . . . . . . . . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
JA (°C/W) JB (°C/W)
1.41x1.41 WLCSP (Notes 4, 5) . . . . . . . . . .
95
27
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+125°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Supply Voltage (VIN) Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8V to 5.5V
Load Current (IOUT) Range (DC) . . . . . . . . . . . . . . . . . . . . . . . . 0A to 800mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach” features. See TB379
5. For JB, the "board temp" is taken on the board near the edge of the package, on a copper trace at the center of one side. See TB379.
Analog Specifications VIN = VEN = 3.6V, VOUT = 3.3V, L1 = 1µH, C1 = 10µF, C2 = 47µF, TA = +25°C. Boldface limits apply across the
recommended operating temperature range, -40°C to +85°C and input voltage range (1.8V to 5.5V).
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
MAX
(Note 6)
UNIT
5.5
V
1.790
V
41
55
µA
0.005
1
µA
0.8
3.5
µA
5.20
V
+4
%
TYP
POWER SUPPLY
Input Voltage Range
VIN Undervoltage Lockout Threshold
VIN
VUVLO
1.8
Rising
Falling
VIN Supply Current
IVIN
VOUT = 3.7V (Note 7)
VIN Supply Current, Shutdown
ISD
EN = GND
VIN Supply Current, Bypass Mode
IBYP
BYP = Logic high, VIN ≤5V
VOUT
ISL9120IIAZ, IOUT = 100mA
FB Pin Voltage Regulation
VFB
For adjustable output version (ISL9120IIAZ)
FB Pin Bias Current
IFB
For adjustable output version (ISL9120IIAZ)
1.725
1.550
1.650
V
OUTPUT VOLTAGE REGULATION
Output Voltage Range
Output Voltage Accuracy
Line Regulation, 500mA
Load Regulation, 500mA
Line Regulation, 100mA
VIN = 3.7V, IOUT = 1mA
1.00
-3
0.80
0.025
VOUT/ VIN IOUT = 500mA, VOUT = 3.3V, VIN step from 2.3V to 5.5V
VOUT/
IOUT
VIN = 3.7V, VOUT = 3.3V, IOUT step from 0mA to 500mA
VOUT/VI IOUT = 100mA, VOUT = 3.3V, VIN step from 2.3V to 5.5V
Load Regulation, 100mA
VOUT/
IOUT
VIN = 3.7V, VOUT = 3.3V, IOUT step from 0mA to 100mA
Output Voltage Clamp
VCLAMP
Rising
V
0.00681
mV/mV
0.0072
mV/mA
0.00273
mV/mV
0.05
mV/mA
5.32
Output Voltage Clamp Hysteresis
µA
5.82
400
V
mV
DC/DC SWITCHING SPECIFICATIONS
LX1 Pin Leakage Current
IPFETLEAK
LX2 Pin Leakage Current
INFETLEAK
FN8659 Rev.2.00
May 23, 2017
VIN = 3.6V
-0.05
+0.05
µA
-0.05
+0.05
µA
Page 4 of 13
ISL9120
Analog Specifications VIN = VEN = 3.6V, VOUT = 3.3V, L1 = 1µH, C1 = 10µF, C2 = 47µF, TA = +25°C. Boldface limits apply across the
recommended operating temperature range, -40°C to +85°C and input voltage range (1.8V to 5.5V). (Continued)
PARAMETER
MIN
(Note 6)
MAX
(Note 6)
SYMBOL
TEST CONDITIONS
tSS
Time from when EN signal asserts to when output voltage
ramp starts.
1
ms
Time from when output voltage ramp starts to when output
voltage reaches 95% of its nominal value with device
operating in buck mode.
VIN = 4V, IOUT = 500mA
1
ms
Time from when output voltage ramp starts to when output
voltage reaches 95% of its nominal value with device
operating in boost mode.
VIN = 3V, IOUT = 500mA
1
ms
TYP
UNIT
SOFT-START AND SOFT DISCHARGE
Soft-Start Time
VOUT Soft-Discharge ON-Resistance
rDISCHG
EN < VIL
110
Ω
P-Channel MOSFET ON-Resistance
rDSON_P
IOUT = 200mA, measured with internal test mode
50
mΩ
N-Channel MOSFET ON-Resistance
rDSON_N
IOUT = 200mA, measured with internal test mode
50
mΩ
2
A
Thermal Shutdown
150
°C
Thermal Shutdown Hysteresis
35
°C
POWER MOSFET
INDUCTOR PEAK CURRENT LIMIT
Maximum Peak Current Limit
ILIM_MAX
THERMAL PROTECTION
LOGIC INPUTS
Input Leakage
ILEAK
Input HIGH Voltage
VIH
Input LOW Voltage
VIL
0.013
0.500
µA
1.4
V
0.4
V
NOTES:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
7. Quiescent current measurements are taken when the output is not switching.
FN8659 Rev.2.00
May 23, 2017
Page 5 of 13
ISL9120
Typical Performance Curves
0.5
-0.5
VIN = 3V
VOUT (%)
VIN = 2.5V
VIN = 4V
-1.5
VIN = 3.4V
-2.5
VIN = 3.6V
-3.5
-4.5
1
10
100
1000
QUIESCENT CURRENT (µA)
70
65
60
55
50
45
40
1.5
2.0
2.5
OUTPUT CURRENT (mA)
FIGURE 4. OUTPUT VOLTAGE vs OUTPUT CURRENT
EN (2V/DIV)
VOUT (1V/DIV)
VOUT (1V/DIV)
IL (500mA/DIV)
IL (500mA/DIV)
EN (2V/DIV)
VOUT (1V/DIV)
VOUT (1V/DIV)
IL (500mA/DIV)
IL (500mA/DIV)
FN8659 Rev.2.00
May 23, 2017
4.5
5.0
5.5
FIGURE 7. SOFT-START (VIN = 4V, VOUT = 3.3V, 0.5A RLOAD)
EN (2V/DIV)
FIGURE 8. SOFT-START (VIN = 3V, VOUT = 3.3V, NO LOAD)
4.0
400µs/DIV
400µs/DIV
400µs/DIV
3.5
VIN (V)
FIGURE 5. QUIESCENT CURRENT vs INPUT VOLTAGE (EN = HIGH)
EN (2V/DIV)
FIGURE 6. SOFT-START (VIN = 4V, VOUT = 3.3V, NO LOAD)
3.0
400µs/DIV
FIGURE 9. SOFT-START (VIN = 3V, VOUT = 3.3V, 0.5A RLOAD)
Page 6 of 13
ISL9120
Typical Performance Curves (Continued)
VOUT (AC, 100mV/DIV)
VOUT (AC, 100mV/DIV)
ILOAD (200mA/DIV)
ILOAD (200mA/DIV)
200µs/DIV
FIGURE 10. 0A TO 0.5A LOAD TRANSIENT (VIN = 4V, VOUT = 3.3V)
VIN (1V/DIV)
200µs/DIV
FIGURE 11. 0.01A TO 0.5A LOAD TRANSIENT (VIN = 4V, VOUT = 3.3V)
VOUT (1V/DIV)
VOUT (1V/DIV)
VIN (1V/DIV)
IL (1A/DIV)
IL (1A/DIV)
VBYP (2V/DIV)
VBYP (2V/DIV)
400µs/DIV
FIGURE 12. BYPASS FUNCTIONALITY (VIN = 4V, VOUT = 3.3,
0.5A RLOAD)
FN8659 Rev.2.00
May 23, 2017
400µs/DIV
FIGURE 13. BYPASS FUNCTIONALITY (VIN = 3V, VOUT = 3.3,
0.5A RLOAD)
Page 7 of 13
ISL9120
Functional Description
Functional Overview
The ISL9120 implements a complete buck-boost switching
regulator with a PFM controller, internal switches, references,
protection circuitry, and control inputs. Refer to the “Block
Diagram” on page 2.
The PFM controller automatically switches between buck and
boost modes as necessary to maintain a steady output voltage
with changing input voltages and dynamic external loads.
Internal Supply and References
As shown in the “Block Diagram” on page 2, the VIN pin supplies
input power to the DC/DC converter and also provides the
operating voltage source required for stable VREF generation.
Separate ground pins (GND and PGND) are provided to avoid
problems caused by ground shift due to the high switching
currents.
Enable Input
A master enable pin, EN, allows the device to be enabled. Driving
EN logic low invokes a power-down mode, where most internal
device functions, including input and output power-good
detection, are disabled.
Undervoltage Lockout
The Undervoltage Lockout (UVLO) feature prevents abnormal
operation if the supply voltage is too low to guarantee proper
operation. When the VIN pin voltage falls below the UVLO
threshold, the regulator is disabled.
Thermal Shutdown
A built-in thermal protection feature protects the ISL9120 if the
die temperature reaches +150°C (typical). At this die
temperature, the regulator is completely shut down. The die
temperature continues to be monitored in this thermal shutdown
mode. When the die temperature falls to +115°C (typical), the
device will resume normal operation.
When exiting thermal shutdown, the ISL9120 will execute its
soft-start sequence.
Buck-Boost Conversion Topology
The ISL9120 operates in either buck or boost mode. When
operating in conditions where VIN is close to VOUT, the ISL9120
alternates between buck mode, boost mode, and automatic
bypass modes of operation as necessary to provide a regulated
output voltage.
L1
LX1
Bypass Input
The BYP pin allows the device to provide a direct connection from
the VIN pin to the VOUT pin. The connection between the VIN and
VOUT pins is through the external inductor and two internal power
transistors. This function, called forced bypass mode operation,
provides a very low quiescent current state.
For forced bypass mode operation, the minimum time required
while in forced bypass operation is 800µs. Also when exiting
forced bypass operation, the minimum time required before
reentering forced bypass mode operation is 1ms.
Soft Discharge
When the device is disabled by driving EN logic low, an internal
resistor between the VOUT and GND pins is activated. This
internal resistor has a typical resistance of 110Ω.
POR Sequence and Soft-Start
Bringing the EN pin logic high allows the device to power-up. A
number of events occur during the start-up sequence. The internal
voltage reference powers up and stabilizes. The device then starts
operating. There is a 1ms (typical) delay between assertion of the
EN pin and the start of the switching regulator soft-start ramp.
The soft-start feature minimizes output voltage overshoot and
input inrush currents. During soft-start, the reference voltage is
ramped to provide a ramping output voltage.
When the target output voltage is higher than the input voltage,
there will be a transition from buck mode to boost mode during
the soft-start sequence. At the time of this transition, the ramp
rate of the reference voltage is decreased, such that the output
voltage slew rate is decreased. This provides a slower output
voltage slew rate.
FN8659 Rev.2.00
May 23, 2017
SWITCH A
LX2
SWITCH D
VIN
VOUT
SWITCH B
SWITCH C
FIGURE 14. BUCK-BOOST TOPOLOGY
Figure 14 shows a simplified diagram of the internal switches
and external inductor.
PFM Operation
During PFM operation in buck mode, Switch D is continuously
closed and Switch C is continuously open. Switches A and B operate
in discontinuous mode during PFM operation. During PFM operation
in boost mode, the ISL9120 closes Switch A and Switch C to
ramp-up the current in the inductor. When the inductor current
reaches the current limit, the device turns OFF Switches A and C,
then turns ON Switches B and D. With Switches B and D closed,
output voltage increases as the inductor current ramps down.
As shown in Figure 15, depending on output current, there will be
multiple PFM pulses to charge up the output capacitor. These pulses
continue until VOUT has reached the upper threshold of the PFM
hysteretic, which is at 1.5% above the nominal output voltage.
Switching then stops and remains stopped until VOUT decays to the
lower threshold of the voltage hysteretic, which is the nominal
output voltage. Then the PFM operation repeats.
Page 8 of 13
ISL9120
Variable Peak Current Limit Scheme
To optimize efficiency across the output current range, the ISL9120
implements a multilevel current limit scheme with 32 levels
between 350mA and 2A. The transition from one level to the other
is determined by the number of pulses in a PFM burst (pulse count)
as shown in Figure 16. At a given peak current limit level, the pulse
count increases as the output current increases. When the pulse
count reaches the upper threshold at the existing current limit, the
current limit will switch to the next higher level. Similarly, if the pulse
count reaches the lower threshold at the existing current limit, the
device will switch to the next lower level of peak current limit. If the
pulse count reaches the upper threshold at the highest current limit,
the current limit will not rise any further. Increasing the output
current beyond this point may cause the output to lose voltage
regulation.
PEAK CURRENT LIMIT
IL
0
1.015 * VOUT_NOMINAL
VOUT
VOUT_NOMINAL
FIGURE 15. PFM MODE OPERATION CONCEPT
IPK_LMT2
IPK_LMT1
IL
0
tMIN
INCREASING IOUT
IOUT
FIGURE 16. PEAK CURRENT LIMIT STEP UP TRANSITION
FN8659 Rev.2.00
May 23, 2017
Page 9 of 13
ISL9120
Automatic Bypass Mode Operation
When the output voltage is close to the input voltage, generally
within 1% to 2%, the ISL9120 will engage automatic bypass
mode operation, which produces a direct connection between
the VIN and VOUT pins. This behavior provides excellent efficiency
and very low output voltage ripple.
Forced Bypass Mode Operation
Forced bypass mode operation is intended for applications where
the output regulation is not important but the device quiescent
current consumption is important. One example is when the
buck-boost regulator is providing power to an LDO and the LDO is
in standby mode with near zero output current. Under this
condition, putting the buck-boost regulator in bypass mode will
have essentially no impact on the LDO but save the 41µA
quiescent current consumption on the buck-boost regulator.
Because the bypass mode is an extreme power saving mode,
there is no overcurrent protection. Therefore, caution must be
taken not to overload or short-circuit the device. Power-up at
bypass mode is not recommended.
Output Voltage Programming
The ISL9120 is available in fixed and adjustable output voltage
versions. To use the fixed output version (ISL9120IINZ), the VOUT
pin must be connected directly to the FB pin.
When designing a PCB, include a GND guard band around the FB
resistor network to reduce noise and improve accuracy and
stability. Resistors R1 and R2 should be positioned close to the
FB pin. The suggested value of the R1 resistor is 187k.
Feed-Forward Capacitor Selection
A small capacitor (C4 in Figure 17) in parallel with resistor R1 is
required to provide the specified load and line regulation. The
suggested value of this capacitor is 22pF for R1 = 187k. An NPO
type capacitor is recommended.
Non-Adjustable Version FB Pin Connection
The fixed output versions of the ISL9120 do not require external
resistors or a capacitor on the FB pin. Simply connect VOUT to FB,
as shown in Figure 18.
FORCED BYPASS
BUCK-BOOST
ISL9120IINZ
VIN
LX1
L1
1H
VOUT
EN
BYP
FB
VOUT = 3.3V
C2
47F
GND PGND
The adjustable ISL9120 versions require three additional
components to program the output voltage. Two external
resistors program the output voltage and a small capacitor is
added to improve transient response.
FIGURE 18. TYPICAL ISL9120IINZ APPLICATION
ISL9120IIAZ
VIN
LX1
L1
1H
LX2
BUCK-BOOST
(EQ. 1)
LX2
The fixed-output version of the ISL9120 requires only three
external power components to implement the buck-boost
converter: an inductor, an input capacitor, and an output
capacitor.
FORCED BYPASS
R 1

VOUT = 0.8V   1 + -------
R

2
ENABLE
DISABLE
Component Selection
ENABLE
DISABLE
Equation 1 can be used to derive the R1 and R2 resistor values:
C1
10F
Applications Information
C1
10F
Setting and controlling the output voltage of the ISL9120IIAZ
(adjustable output version) can be accomplished by selecting the
external resistor values.
VIN =
1.8V TO 5.5V
In the adjustable output voltage version (ISL9120IIAZ), an
external resistor divider is required to program the output
voltage.
VIN =
1.8V TO 5.5V
Output Voltage Programming, Adjustable
Version
VOUT = 3.3V
VOUT
EN
R1
187k 
BYP
C4
22pF
FB
R2
60.4k 
C2
47F
GND PGND
FIGURE 17. TYPICAL ISL9120IIAZ APPLICATION
FN8659 Rev.2.00
May 23, 2017
Page 10 of 13
ISL9120
Inductor Selection
Capacitor Selection
An inductor with high frequency core material (for example,
ferrite core) should be used to minimize core losses and provide
good efficiency. The inductor must be able to handle the peak
switching currents without saturating.
The input and output capacitors should be ceramic X5R type with
low ESL and ESR. The recommended input capacitor value is
10µF. The recommended 10µF input capacitor should have the
following minimum characteristics: 0603 case size, X5R
temperature range, and 10V voltage rating. The recommended
VOUT capacitor values are 22µF or 47µF. The recommended
47µF output capacitor should have the following minimum
characteristics: 0603 case size, X5R temperature range, and
6.3V voltage rating. The recommended 22µF output capacitor
should have the following minimum characteristics: 0603 case
size, X5R temperature range, and 10V voltage rating.
A 1µH inductor with ≥2A saturation current rating is
recommended. Select an inductor with low DCR to provide good
efficiency. In applications where radiated noise must be
minimized, a toroidal or shielded inductor can be used.
TABLE 1. INDUCTOR VENDOR INFORMATION
MANUFACTURER
SERIES
DIMENSION
(mm)
DCR
(mΩ)
TYP
ISAT
(A)
TYP
Toko
DFE201610R-H1R0M
2.0x1.6x1.0
66
2.7
Cyntec
PIFE20161T-1R0MS 2.0x1.6x1.0
65
2.8
3.8
TDK
TFM201610GHM1R0MTAA
2.0x1.6x1.0
50
TABLE 2. CAPACITOR VENDOR INFORMATION
MANUFACTURER
AVX
SERIES
WEBSITE
X5R
www.avx.com
Murata
X5R
www.murata.com
TDK
X5R
www.tdk.com
Recommended PCB Layout
Correct PCB layout is critical for proper operation of the ISL9120.
The input and output capacitors should be positioned as closely
to the IC as possible. The ground connections of the input and
output capacitors should be kept as short as possible and should
be on the component layer to avoid problems that are caused by
high switching currents flowing through PCB vias.
FN8659 Rev.2.00
May 23, 2017
Page 11 of 13
ISL9120
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please visit our website to make sure you have the latest revision.
DATE
REVISION
CHANGE
May 23, 2017
FN8659.2
In the “Absolute Maximum Ratings” table, corrected the voltage rating as follows:
- FB (Adjustable Version) -0.3V to 2.7V
- FB (Fixed VOUT Version) -0.3V to 6.5V
Reordered pin descriptions in the “Pin Descriptions” table.
Added ISL9120IINZ-T7A and ISL9120IIAZ-T7A to the “Ordering Information” table.
Applied new header/footer template.
January 29, 2016
FN8659.1
Page 1 - In “Description”, 3rd paragraph changed the value from 1µA to 3.5µA.
Ordering information table Page 3, added column for Tape and Reel quantity.
Page 4 - Analog Specifications:
Under Power Supply VIN Undervoltage Lockout Threshold, changed Max value from 1.775 to 1.790
VIN Supply Current, Bypass Mode changed Typ from 0.035 to 0.8 and Max from 1 to 3.5.
Under Output Voltage Regulation Output Voltage Accuracy, changed Min/Max from -2 and +2 to -3 and +4.
May 28, 2015
FN8659.0
Initial Release
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing, and high-end consumer markets.
For the most updated datasheet, application notes, related documentation, and related parts, see the respective product information
page found at www.intersil.com.
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Reliability reports are also available from our website at www.intersil.com/support.
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Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
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For information regarding Intersil Corporation and its products, see www.intersil.com
FN8659 Rev.2.00
May 23, 2017
Page 12 of 13
ISL9120
Package Outline Drawing
For the most recent package outline drawing, see W3x3.9E.
W3x3.9E
3x3 ARRAY 9 BALLS WITH 0.40 PITCH WAFER LEVEL CHIP SCALE PACKAGE
Rev 0, 8/14
X
Y
1.410 ± 0.030
0.400
C
9 x 0.265 ± 0.035
1.410 ± 0.030
B
0.305
A
(4X)
0.10
1
TOP VIEW
2
3
PIN 1
(A1 CORNER)
0.305
BOTTOM VIEW
Z
0.05
0.240
Z
SEATING PLANE
3
PACKAGE OUTLINE
0.400
0.265 ± 0.035
0.290
RECOMMENDED LAND PATTERN
0.10
Z X Y
0.05
Z
0.200 ± 0.030
0.500 ± 0.050
SIDE VIEW
NOTES:
1. All dimensions are in millimeters.
2. Dimensions and tolerance per ASMEY 14.5 - 1994, and JESD 95-1 SPP-010.
3. NSMD refers to non-solder mask defined pad design per Intersil Techbrief TB451.
FN8659 Rev.2.00
May 23, 2017
Page 13 of 13