LINER LT8361 Low iq boost/sepic/ inverting converter with 2a, 100v switch Datasheet

LT8361
Low IQ Boost/SEPIC/
Inverting Converter
with 2A, 100V Switch
FEATURES
DESCRIPTION
Wide Input Voltage Range: 2.8V to 60V
nn Ultralow Quiescent Current and Low Ripple
Burst Mode® Operation: IQ = 9µA
nn 2A, 100V Power Switch
nn Positive or Negative Output Voltage Programming
with a Single Feedback Pin
nn Programmable Frequency (300kHz to 2MHz)
nn Synchronizable to an External Clock
nn Spread Spectrum Frequency Modulation for Low EMI
nn BIAS Pin for Higher Efficiency
nn Programmable Undervoltage Lockout (UVLO)
nn Thermally Enhanced 16-lead MSOP packages
The LT®8361 is a current mode DC/DC converter with a
100V, 2A switch operating from a 2.8V to 60V input. With
a unique single feedback pin architecture it is capable of
boost, SEPIC or inverting configurations. Burst Mode
operation consumes as low as 9µA quiescent current to
maintain high efficiency at very low output currents, while
keeping typical output ripple below 15mV.
nn
APPLICATIONS
Industrial and Automotive
Telecom
nn Medical Diagnostic Equipment
nn Portable Electronics
nn
nn
An external compensation pin allows optimization of loop
bandwidth over a wide range of input and output voltages
and programmable switching frequencies between 300kHz
and 2MHz. A SYNC/MODE pin allows synchronization to
an external clock. It can also be used to select between
burst or pulse-skip modes of operation with or without
Spread Spectrum Frequency Modulation for low EMI.
For increased efficiency, a BIAS pin can accept a second
input to supply the INTVCC regulator. Additional features
include frequency foldback and programmable soft-start
to control inductor current during startup.
The LT8361 is available in a thermally enhanced 16-lead
MSOP package with four pins removed for high voltage
pin spacings.
All registered trademarks and trademarks are the property of their respective owners.
TYPICAL APPLICATION
400kHz, 24V Output SEPIC Converter
Efficiency and Power Loss
22µH
SW
1M
EN/UVLO
LT8361
SYNC/MODE
RT
FBX
BIAS
INTVCC
SS
GND
VC
71.5k
1µF
0.22µF
80
70
1.75
60
1.50
50
1.25
40
1.00
30
0.75
POWER LOSS
20
0
6.8nF
2.00
EFFICIENCY
0.50
VIN = 12V
VIN = 48V
10
16.2k
121k
2.25
90
0
0.1
0.2 0.3 0.4 0.5
LOAD CURRENT (A)
POWER LOSS (W)
VIN
10µF
VOUT
24V
200mA AT VIN = 5V
450mA AT VIN = 12V
550mA AT VIN = 24V
600mA AT VIN = 48V
EFFICIENCY (%)
4.7µF
2.50
100
1µF
22µH
VIN
4V TO 48V
0.6
0.25
0
0.7
8361 TA01b
D1: DIODES INC. DFLS2100
L1: WURTH ELEKTRONIK WE-DD 7345 744877220
C5: MURATA GRM32ER71H106KA12L
8361 TA01a
Rev 0
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1
LT8361
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
SW...........................................................................100V
VIN, EN/UVLO............................................................60V
BIAS...........................................................................60V
EN/UVLO Pin Above VIN Pin, SYNC.............................6V
INTVCC .............................................................. (Note 2)
VC................................................................................4V
FBX............................................................................±4V
Operating Junction Temperature (Note 3)
LT8361E, LT8361I............................... –40°C to 125°C
LT8361H............................................. –40°C to 150°C
Storage Temperature Range................... –65°C to 150°C
ORDER INFORMATION
TOP VIEW
EN/UVLO 1
VIN 3
INTVCC
NC
BIAS
VC
5
6
7
8
16 SW1
17
PGND,
GND
14 SW2
12
11
10
9
SYNC/MODE
SS
RT
FBX
MSE PACKAGE
VARIATION: MSE16 (12)
16-LEAD PLASTIC MSOP
θJA = 45°C/W, θJC = 10°C/W
EXPOSED PAD (PIN 17) IS PGND AND GND, MUST BE SOLDERED TO PCB
http://www.linear.com/product/LT8361#orderinfo
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT8361EMSE#PBF
LT8361EMSE#TRPBF
8361
16-Lead Plastic MSOP with 4 Pins Removed
–40°C to 125°C
LT8361IMSE#PBF
LT8361IMSE#TRPBF
8361
16-Lead Plastic MSOP with 4 Pins Removed
–40°C to 125°C
LT8361HMSE#PBF
LT8361HMSE#TRPBF
8361
16-Lead Plastic MSOP with 4 Pins Removed
–40°C to 150°C
Consult ADI Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult ADI Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
2
Rev 0
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LT8361
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, EN/UVLO = 12V unless otherwise noted.
PARAMETER
CONDITIONS
VIN Operating Voltage Range
VIN Quiescent Current at Shutdown
MIN
l
TYP
2.8
VEN/UVLO = 0.2V
MAX
UNITS
60
V
l
1
1
2
15
μA
μA
l
2
2
5
25
μA
μA
l
9
9
15
30
μA
μA
l
1200
1200
1600
1850
µA
µA
l
22
22
40
65
µA
µA
4.4
4
4.65
4.25
V
V
VEN/UVLO = 1.5V
VIN Quiescent Current
Sleep Mode (Not Switching)
Active Mode (Not Switching)
SYNC = 0V
SYNC = 0V or INTVCC, BIAS = 0V
SYNC = 0V or INTVCC, BIAS = 5V
BIAS Threshold
Rising, BIAS Can Supply INTVCC
Falling, BIAS Cannot Supply INTVCC
VIN Falling Threshold to Supply INTVCC
BIAS = 12V
BIAS Falling Threshold to Supply INTVCC
VIN = 12V
BIAS – 2V
V
VIN
V
FBX Regulation
1.568
–0.820
1.6
–0.80
1.632
–0.780
V
V
0.005
0.005
0.015
0.015
%/V
%/V
10
nA
FBX Regulation Voltage
FBX > 0V
FBX < 0V
FBX Line Regulation
FBX > 0V, 2.8V < VIN < 60V
FBX < 0V, 2.8V < VIN < 60V
FBX Pin Current
FBX = 1.6V, –0.8V
l
–10
Switching Frequency (fOSC)
RT = 165k
RT = 45.3k
RT = 20k
l
l
l
273
0.92
1.85
300
1
2
327
1.08
2.15
SSFM Maximum Frequency Deviation
(∆f/fOSC) • 100, RT = 20k
14
20
25
%
Minimum On-Time
Burst Mode, VIN = 24V (Note 6)
Pulse-Skip Mode, VIN = 24V (Note 6)
70
70
95
90
ns
ns
l
l
Oscillator
kHz
MHz
MHz
l
55
75
ns
SYNC/Mode, Mode Thresholds (Note 5)
High (Rising), VIN = 24V
Low (Falling), VIN = 24V
l
l
0.14
1.3
0.2
1.7
V
V
SYNC/Mode, Clock Thresholds (Note 5)
Rising, VIN = 24V
Falling, VIN = 24V
l
l
0.4
1.3
0.8
1.7
V
V
kHz/kHz
Minimum Off-Time
fSYNC/fOSC Allowed Ratio
RT = 20k
SYNC Pin Current
SYNC = 2V
SYNC = 0V, Current Out of Pin
0.95
1
1.25
10
10
25
25
µA
µA
2.5
3.4
A
Switch
Maximum Switch Current Limit Threshold
l
2
Switch Overcurrent Threshold
Discharges SS Pin
3.75
A
Switch RDS(ON)
ISW = 0.5A
375
mΩ
Switch Leakage Current
VSW = 100V
0.1
1
µA
Rev 0
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3
LT8361
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, EN/UVLO = 12V unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
EN/UVLO Logic
EN/UVLO Pin Threshold (Rising)
Start Switching
l
1.576
1.68
1.90
V
EN/UVLO Pin Threshold (Falling)
Stop Switching
l
1.545
1.6
1.645
V
EN/UVLO Pin Current
VEN/UVLO = 1.6V
l
–50
50
nA
Soft-Start
Soft-Start Charge Current
SS = 0.5V
2
µA
Soft-Start Pull-Down Resistance
Fault Condition, SS = 0.1V
220
Ω
Error Amplifier Transconductance
FBX = 1.6V
FBX = –0.8V
75
60
µA/V
µA/V
Error Amplifier Voltage Gain
FBX = 1.6V
FBX = –0.8V
185
145
V/V
V/V
Error Amplifier Max Source Current
VC = 1.1V, Current Out of Pin
7
µA
Error Amplifier Max Sink Current
VC = 1.1V
7
µA
Error Amplifier
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: INTVCC cannot be externally driven. No additional components or
loading is allowed on this pin.
Note 3: The LT8361E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT8361I is guaranteed over the full –40°C to 125°C operating junction
temperature range. The LT8361H is guaranteed over the full –40°C to
150°C operating junction temperature range.
4
Note 4: The IC includes overtemperature protection that is intended to
protect the device during overload conditions. Junction temperature will
exceed 150°C when overtemperature protection is active. Continuous
operation above the specified maximum operating junction temperature
will reduce lifetime.
Note 5: For SYNC/MODE inputs required to select modes of operation see
the Pin Functions and Applications Information sections.
Note 6: The IC is tested in a Boost converter configuration with the output
voltage programmed for 24V.
Rev 0
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LT8361
TYPICAL PERFORMANCE CHARACTERISTICS
FBX Positive Regulation Voltage
vs Temperature
–0.780
1.624
–0.785
1.616
–0.790
1.608
1.600
1.592
1.74
VIN = 12V
1.72
–0.795
–0.800
–0.805
1.584
–0.810
1.576
–0.815
1.568
–50 –25
–0.820
–50 –25
0 25 50 75 100 125 150 175
JUNCTION TEMPERATURE (°C)
2.02
2.00
1.98
1.96
1.94
1.92
0 25 50 75 100 125 150 175
JUNCTION TEMPERATURE (°C)
2.04
2.02
2.00
1.98
1.96
1.94
1.90
100
VIN = 12V
90
0
5 10 15 20 25 30 35 40 45 50 55 60
VIN (V)
125
100
75
50
25
0
–0.8
2.5
2.4
2.3
100
VIN = 12V
90
60
50
40
30
40
30
20
10
8361 G07
VIN = 12V
50
10
0
–50 –25
1.6
60
2.1
10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
1.2
70
20
0
0.0
0.4
0.8
VOLTAGE (V)
80
70
2.2
2.0
–0.4
Switch Minimum Off-Time
vs Temperature
80
2.6
VIN = 12V
8361 G06
MINIMUM OFF TIME (ns)
2.8
2.7
0 25 50 75 100 125 150 175
JUNCTION TEMPERATURE (°C)
8361 G03
Switch Minimum On-Time
vs Temperature
MINIMUM ON TIME (ns)
SWITCH CURRENT LIMIT (A)
1.58
8361 G05
Switch Current Limit
vs Duty Cycle
2.9
EN/UVLO FALLING (TURN–OFF)
1.60
Normalized Switching Frequency
vs FBX Voltage
2.06
8361 G04
3.0
1.62
Switching Frequency vs VIN
1.92
1.90
–50 –25
1.64
NORMALIZED SWITCHING FREQUENCY (%)
2.04
1.66
1.54
–50 –25
0 25 50 75 100 125 150 175
JUNCTION TEMPERATURE (°C)
2.08
SWITCHING FREQUENCY (MHz)
SWITCHING FREQUENCY (MHz)
2.10
VIN = 12V
2.06
1.68
8361 G02
Switching Frequency
vs Temperature
2.08
EN/UVLO RISING (TURN–ON)
1.70
1.56
8361 G01
2.10
EN/UVLO Pin Thresholds
vs Temperature
EN/UVLO PIN VOLTAGE (V)
VIN = 12V
FBX VOLTAGE (V)
FBX VOLTAGE (V)
1.632
FBX Negative Regulation Voltage
vs Temperature
0
25
50
75 100 125 150 175
0
–50 –25
0
25
50
75 100 125 150 175
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
8361 G08
8361 G09
Rev 0
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5
LT8361
TYPICAL PERFORMANCE CHARACTERISTICS
VIN Pin Current (Active Mode,
Not Switching, Bias = 0V)
vs Temperature
2.0
1.8
1.6
50
VIN = 12V
VBIAS = 0V
VSYNC_MODE = FLOAT
46
42
1.4
1.2
1.0
0.8
0.6
VSW
20V/DIV
0 25 50 75 100 125 150 175
JUNCTION TEMPERATURE (°C)
8361 G13
SWITCHING FREQUENCY (MHz)
Switching Waveforms
(in Deep Burst Mode)
VSW
20V/DIV
8361 G14
1µs/DIV
1.5
IOUT
500mA/DIV
1.0
VOUT
1V/DIV
8361 G15
VOUT Transient Response: Load
Current Transients from 390mA to
790mA to 390mA
FRONT PAGE APPLICATION
FRONT PAGE APPLICATION
VIN = 12V
VOUT = 48V
FRONT PAGE APPLICATION
IOUT
500mA/DIV
VIN = 24V
VOUT = 24V
100µs/DIV
40
60
80
LOAD CURRENT (mA)
8361 G12
VOUT Transient Response: Load
Current Transients from 150mA to
790mA to 150mA
0.5
0 25 50 75 100 125 150 175
JUNCTION TEMPERATURE (°C)
IL1 + IL2
200mA/DIV
500ns/DIV
Burst Frequency vs Load Current
20
10
–50 –25
8361 G11
VSW
20V/DIV
0
22
14
IL1 + IL2
200mA/DIV
2.0
26
Switching Waveforms
(in DCM/Light Burst Mode)
IL1 + IL2
500mA/DIV
2.5
30
18
Switching Waveforms
(in CCM)
500ns/DIV
34
0.2
0
–50 –25
VIN = 12V
VBIAS = 5V
VSYNC_MODE = FLOAT
38
0.4
8361 G10
0
VIN Pin Current (Active Mode, Not
Switching, Bias = 5V)
vs Temperature
VIN PIN CURRENT (µA)
30
28 VIN = 12 V
26 VBIAS = 0V
24 VSYNC_MODE = 0V
22
20
18
16
14
12
10
8
6
4
2
0
–75 –50 –25 0 25 50 75 100 125 150 175
JUNCTION TEMPERATURE (°C)
VIN PIN CURRENT (mA)
VIN PIN CURRENT (µA)
VIN Pin Current (Sleep Mode, Not
Switching) vs Temperature
8361 G17
VOUT
500mV/DIV
VIN = 24V
VOUT = 24V
100µs/DIV
8361 G18
100
8361 G16
6
Rev 0
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LT8361
PIN FUNCTIONS
EN/UVLO: Shutdown and Undervoltage Detect Pin. The
LT8361 is shut down when this pin is low and active
when this pin is high. Below an accurate 1.6V threshold,
the part enters undervoltage lockout and stops switching.
This allows an undervoltage lockout (UVLO) threshold to
be programmed for system input voltage by resistively
dividing down system input voltage to the EN/UVLO pin.
An 80mV pin hysteresis ensures part switching resumes
when the pin exceeds 1.68V. EN/UVLO pin voltage below
0.2V reduces VIN current below 1µA. If shutdown and
UVLO features are not required, the pin can be tied directly
to system input.
RT: A resistor from this pin to the exposed pad GND copper (near FBX) programs switching frequency.
VIN: Input Supply. This pin must be locally bypassed. Be
sure to place the positive terminal of the input capacitor as
close as possible to the VIN pin, and the negative terminal
as close as possible to the exposed pad PGND copper
(near EN/UVLO).
INTVCC: Regulated 3.2V Supply for Internal Loads. The
INTVCC pin must be bypassed with a 1µF low ESR ceramic
capacitor to GND. No additional components or loading is
allowed on this pin. INTVCC draws power from the BIAS
pin if 4.4V ≤ BIAS ≤ VIN, otherwise INTVCC is powered by
the VIN pin.
NC: No Internal Connection. Leave this pin open.
BIAS: Second Input Supply for Powering INTVCC. Removes
the majority of INTVCC current from the VIN pin to improve
efficiency when 4.4V ≤ BIAS ≤ VIN. If unused, tie the pin
to GND.
VC: Error Amplifier Output Pin. Tie external compensation
network to this pin.
FBX: Voltage Regulation Feedback Pin for Positive or Negative Outputs. Connect this pin to a resistor divider between
the output and the exposed pad GND copper (near FBX).
FBX reduces the switching frequency during start-up and
fault conditions when FBX is close to 0V.
SS: Soft-Start Pin. Connect a capacitor from this pin to
GND copper (near FBX) to control the ramp rate of inductor
current during converter start-up. SS pin charging current
is 2μA. An internal 220Ω MOSFET discharges this pin
during shutdown or fault conditions.
SYNC/MODE: This pin allows five selectable modes for
optimization of performance.
SYNC/MODE Pin Input
Capable Mode(s) of Operation
(1) GND or <0.14V
Burst
(2) External Clock
Pulse-skip/Sync
(3) 100k Resistor to GND
Burst/SSFM
(4) Float (pin open)
Pulse-skip
(5) INTVCC or >1.7V
Pulse-skip/SSFM
where the selectable modes of operation are,
Burst = low IQ, low output ripple operation at light loads
Pulse-skip = skipped pulse(s) at light load (aligned to clock)
Sync = switching frequency synchronized to external clock
SSFM = Spread Spectrum Frequency Modulation for low EMI
SW1, SW2 (SW): Output of the Internal Power Switch.
Minimize the metal trace area connected to these pins to
reduce EMI.
PGND,GND: Power Ground and Signal Ground for the
IC. The package has an exposed pad underneath the IC
which is the best path for heat out of the package. The pin
should be soldered to a continuous copper ground plane
under the device to reduce die temperature and increase
the power capability of the LT8361. Connect power ground
components to the exposed pad copper exiting near the EN/
UVLO and SW pins. Connect signal ground components to
the exposed pad copper exiting near the VC and FBX pins.
Rev 0
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7
LT8361
BLOCK DIAGRAM
L
VIN
VOUT
R3
OPT
R4
OPT
COUT
CIN
SW
EN/UVLO
VIN
VBIAS (+)
VBIAS – 2V(–)
INTERNAL
REFERENCE
UVLO
+
SW1
+
+
–
–
SW2
BIAS
4.4V(+)
4.0V(–)
1.68V(+)
1.6V(–)
A6
UVLO
D
–
TJ > 170°C
3.2V REGULATOR
INTVCC
INTVCC
UVLO
SYNC/MODE
CVCC
RT
OSCILLATOR
FREQUENCY
FOLDBACK
ERROR AMP
SELECT
FBX
1.6V
BURST
DETECT
ERROR
AMP
+
–
A1
–
+
R2
A7
A5
PWM
COMPARATOR
ERROR
AMP
OVERCURRENT
–
+
M1
DRIVER
A2
–
A3
ISS
2μA
UVLO
OVERCURRENT
M2
Q1
+
SLOPE
RSENSE
A4
–
SS
MAX
ILIMIT
+
–0.8V
1.5×
MAX
ILIMIT
+
VOUT
R1
SWITCH
LOGIC
SLOPE
–
R5
PGND/GND
VC
8361 BD
CSS
RC
CC
8
Rev 0
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LT8361
OPERATION
The LT8361 uses a fixed frequency, current mode control
scheme to provide excellent line and load regulation.
Operation can be best understood by referring to the
Block Diagram. An oscillator (with frequency programmed
by a resistor at the RT pin) turns on the internal power
switch at the beginning of each clock cycle. Current in
the inductor then increases until the current comparator
trips and turns off the power switch. The peak inductor
current at which the switch turns off is controlled by the
voltage on the VC pin. The error amplifier servos the VC
pin by comparing the voltage on the FBX pin with an
internal reference voltage (1.60V or –0.80V, depending
on the chosen topology). When the load current increases
it causes a reduction in the FBX pin voltage relative to
the internal reference. This causes the error amplifier to
increase the VC pin voltage until the new load current
is satisfied. In this manner, the error amplifier sets the
correct peak switch current level to keep the output in
regulation.
The LT8361 is capable of generating either a positive or
negative output voltage with a single FBX pin. It can be
configured as a boost or SEPIC converter to generate a
positive output voltage, or as an inverting converter to
generate a negative output voltage. When configured as
a Boost converter, as shown in the Block Diagram, the
FBX pin is pulled up to the internal bias voltage of 1.60V
by a voltage divider (R1 and R2) connected from VOUT
to GND. Amplifier A2 becomes inactive and amplifier A1
performs (inverting) amplification from FBX to VC. When
the LT8361 is in an inverting configuration, the FBX pin
is pulled down to –0.80V by a voltage divider from VOUT
to GND. Amplifier A1 becomes inactive and amplifier A2
performs (non-inverting) amplification from FBX to VC.
If the EN/UVLO pin voltage is below 1.6V, the LT8361
enters undervoltage lockout (UVLO), and stops switching.
When the EN/UVLO pin voltage is above 1.68V (typical),
the LT8361 resumes switching. If the EN/UVLO pin voltage
is below 0.2V, the LT8361 draws less than 1µA from VIN.
For the SYNC/MODE pin tied to ground or <0.14V, the
LT8361 will enter low output ripple Burst Mode operation for ultra low quiescent current during light loads to
maintain high efficiency. For a 100k resistor from SYNC/
MODE pin to GND, the LT8361 uses Burst Mode operation for improved efficiency at light loads but seamlessly
transitions to Spread-Spectrum Modulation of switching
frequency for low EMI at heavy loads. For the SYNC/
MODE pin floating (left open), the LT8361 uses pulseskipping mode, at the expense of hundreds of microamps,
to maintain output voltage regulation at light loads by
skipping switch pulses. For the SYNC/MODE pin tied to
INTVCC or >1.7V, the LT8361 uses pulse-skipping mode
and performs Spread-Spectrum Modulation of switching
frequency. For the SYNC/MODE pin driven by an external
clock, the converter switching frequency is synchronized
to that clock and pulse-skipping mode is also enabled. See
the Pin Functions section for SYNC/MODE pin.
The LT8361 includes a BIAS pin to improve efficiency
across all loads. The LT8361 intelligently chooses between
the VIN and BIAS pins to supply the INTVCC for best efficiency. The INTVCC supply current can be drawn from
the BIAS pin instead of the VIN pin for 4.4V ≤ BIAS ≤ VIN.
Protection features ensure the immediate disable of
switching and reset of the SS pin for any of the following
faults: internal reference UVLO, INTVCC UVLO, switch current > 1.5× maximum limit, EN/UVLO < 1.6V or junction
temperature > 170°C.
Rev 0
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9
LT8361
APPLICATIONS INFORMATION
ACHIEVING ULTRALOW QUIESCENT CURRENT
To enhance efficiency at light loads the LT8361 uses
a low ripple Burst Mode architecture. This keeps the
output capacitor charged to the desired output voltage
while minimizing the input quiescent current and output
ripple. In Burst Mode operation, the LT8361 delivers single
small pulses of current to the output capacitor followed
by sleep periods where the output power is supplied by
the output capacitor. While in sleep mode, the LT8361
consumes only 9µA.
As the output load decreases, the frequency of single current pulses decreases (see Figure 1) and the percentage of
time the LT8361 is in sleep mode increases, resulting in
much higher light load efficiency than for typical converters. To optimize the quiescent current performance at light
loads, the current in the feedback resistor divider must be
minimized as it appears to the output as load current. In addition, all possible leakage currents from the output should
also be minimized as they all add to the equivalent output
load. The largest contributor to leakage current can be due
to the reverse biased leakage of the Schottky diode (see
Diode Selection in the Applications Information section).
While in Burst Mode operation, the current limit of the
switch is approximately 400mA resulting in the output
voltage ripple shown in Figure 2. Increasing the output
capacitance will decrease the output ripple proportionally.
As the output load ramps upward from zero the switching
frequency will increase but only up to the fixed frequency
defined by the resistor at the RT pin as shown in Figure 1.
SWITCHING FREQUENCY (MHz)
2.5
FRONT PAGE APPLICATION
VIN = 12V
VOUT = 48V
2.0
VOUT
2mV/DIV
10µs/DIV
8361 F02
Figure 2. Burst Mode Operation
The output load at which the LT8361 reaches the fixed
frequency varies based on input voltage, output voltage,
and inductor choice.
PROGRAMMING INPUT TURN-ON AND TURN-OFF
THRESHOLDS WITH EN/UVLO PIN
The EN/UVLO pin voltage controls whether the LT8361 is
enabled or is in a shutdown state. A 1.6V reference and a
comparator A6 with built-in hysteresis (typical 80mV) allow
the user to accurately program the system input voltage
at which the IC turns on and off (see the Block Diagram).
The typical input falling and rising threshold voltages can
be calculated by the following equations:
R3 + R4
R4
R3 + R4
= 1.68 •
R4
VIN(FALLING,UVLO(–)) = 1.60 •
VIN(RISING, UVLO(+))
VIN current is reduced below 1µA when the EN/UVLO pin
voltage is less than 0.2V. The EN/UVLO pin can be connected directly to the input supply VIN for always-enabled
operation. A logic input can also control the EN/UVLO pin.
When operating in Burst Mode operation for light load
currents, the current through the R3 and R4 network can
easily be greater than the supply current consumed by the
LT8361. Therefore, R3 and R4 should be large enough to
minimize their effect on efficiency at light loads.
1.5
1.0
0.5
0
IL
200mA/DIV
0
20
40
60
80
LOAD CURRENT (mA)
100
8361 F01
Figure 1. Burst Frequency vs Load Current
10
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LT8361
APPLICATIONS INFORMATION
INTVCC REGULATOR
Synchronization and Mode Selection
A low dropout (LDO) linear regulator, supplied from VIN,
produces a 3.2V supply at the INTVCC pin. A minimum
1µF low ESR ceramic capacitor must be used to bypass
the INTVCC pin to ground to supply the high transient currents required by the internal power MOSFET gate driver.
To select low ripple Burst Mode operation, for high efficiency at light loads, tie the SYNC/MODE pin below 0.14V
(this can be ground or a logic low output).
No additional components or loading is allowed on this
pin. The INTVCC rising threshold (to allow soft-start and
switching) is typically 2.65V. The INTVCC falling threshold
(to stop switching and reset soft-start) is typically 2.5V.
To improve efficiency across all loads, the majority of
INTVCC current can be drawn from the BIAS pin (4.4V ≤
BIAS ≤ VIN) instead of the VIN pin. For SEPIC applications
with VIN often greater than VOUT, the BIAS pin can be directly connected to VOUT. If the BIAS pin is connected to
a supply other than VOUT, be sure to bypass the pin with
a local ceramic capacitor.
Programming Switching Frequency
The LT8361 uses a constant frequency PWM architecture
that can be programmed to switch from 300kHz to 2MHz
by using a resistor tied from the RT pin to ground. A table
showing the necessary RT value for a desired switching
frequency is in Table 1.
The RT resistor required for a desired switching frequency
can be calculated using:
RT =
51.2
– 5.6
fOSC
where RT is in kΩ and fOSC is the desired switching frequency in MHz.
Table 1. SW Frequency vs RT Value
fOSC (MHz)
RT (kΩ)
0.3
165
0.45
107
0.75
63.4
1
45.3
1.5
28.7
2
20
To synchronize the LT8361 oscillator to an external frequency connect a square wave (with 20% to 80% duty cycle)
to the SYNC pin. The square wave amplitude should have
valleys that are below 0.4V and peaks above 1.7V (up to
6V). The LT8361 will not enter Burst Mode operation at low
output loads while synchronized to an external clock, but
instead will pulse skip to maintain regulation. The LT8361
may be synchronized over a 300kHz to 2MHz range. The
RT resistor should be chosen to set the LT8361 switching
frequency equal to or below the lowest synchronization
input. For example, if the synchronization signal will be
500kHz and higher, the RT should be selected for 500kHz.
For some applications it is desirable for the LT8361 to
operate in pulse-skipping mode, offering two major differences from Burst Mode operation. Firstly, the clock stays
awake at all times and all switching cycles are aligned to
the clock. Secondly, the full switching frequency is maintained at lower output load than in Burst Mode operation.
These two differences come at the expense of increased
quiescent current. To enable pulse-skipping mode, float
the SYNC pin.
To improve EMI/EMC, the LT8361 can provide spread
spectrum frequency modulation (SSFM). This feature varies
the clock with a triangle frequency modulation of 20%. For
example, if the LT8361's frequency was programmed to
switch at 2MHz, spread spectrum mode will modulate the
oscillator between 2MHz and 2.4MHz. The 20% modulation will occur at a frequency: fOSC/256 where fOSC is the
switching frequency programmed using the RT pin.
The LT8361 can also be configured to operate in pulseskipping/SSFM mode by tying the SYNC/MODE pin above
1.7V. The LT8361 can also be configured for Burst Mode
operation at light loads (for improved efficiency) and
SSFM at heavy loads (for low EMI) by tying a 100k from
the SYNC/MODE pin to GND.
Rev 0
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11
LT8361
APPLICATIONS INFORMATION
DUTY CYCLE CONSIDERATION
The LT8361 minimum on-time, minimum off-time and
switching frequency (fOSC) define the allowable minimum
and maximum duty cycles of the converter (see Minimum
On-Time, Minimum Off-Time, and Switching Frequency
in the Electrical Characteristics table).
Minimum Allowable Duty Cycle =
Minimum On-Time(MAX) • fOSC(MAX)
Maximum Allowable Duty Cycle =
1 – Minimum Off-Time(MAX) • fOSC(MAX)
The required switch duty cycle range for a Boost converter
operating in continuous conduction mode (CCM) can be
calculated as:
DMIN = 1 –
DMAX = 1 –
VIN(MAX)
VOUT + VD
VIN(MIN)
VOUT + VD
where VD is the diode forward voltage drop. If the above
duty cycle calculations for a given application violate
the minimum and/or maximum allowed duty cycles
for the LT8361, operation in discontinuous conduction
mode (DCM) might provide a solution. For the same VIN
and VOUT levels, operation in DCM does not demand as
low a duty cycle as in CCM. DCM also allows higher duty
cycle operation than CCM. The additional advantage of
DCM is the removal of the limitations to inductor value
and duty cycle required to avoid sub-harmonic oscillations
and the right half plane zero (RHPZ). While DCM provides
these benefits, the trade-off is higher inductor peak current, lower available output power and reduced efficiency.
SETTING THE OUTPUT VOLTAGE
The output voltage is programmed with a resistor divider
from the output to the FBX pin. Choose the resistor values
for a positive output voltage according to:
⎛V
⎞
R1 = R2 • ⎜ OUT – 1⎟
⎝ 1.60V ⎠
12
Choose the resistor values for a negative output voltage
according to:
⎛ |V | ⎞
R1 = R2 • ⎜ OUT – 1⎟
⎝ 0.80V ⎠
The locations of R1 and R2 are shown in the Block Diagram. 1% resistors are recommended to maintain output
voltage accuracy.
Higher-value FBX divider resistors result in the lowest
input quiescent current and highest light-load efficiency.
FBX divider resistors R1 and R2 are usually in the range
from 25k to 1M.
SOFT-START
The LT8361 contains several features to limit peak switch
currents and output voltage (VOUT) overshoot during
start-up or recovery from a fault condition. The primary
purpose of these features is to prevent damage to external
components or the load.
High peak switch currents during start-up may occur in
switching regulators. Since VOUT is far from its final value,
the feedback loop is saturated and the regulator tries to
charge the output capacitor as quickly as possible, resulting
in large peak currents. A large surge current may cause
inductor saturation or power switch failure.
The LT8361 addresses this mechanism with a programmable soft-start function. As shown in the Block Diagram,
the soft-start function controls the ramp of the power switch
current by controlling the ramp of VC through Q1. This
allows the output capacitor to be charged gradually toward
its final value while limiting the start-up peak currents.
Figure 3 shows the output voltage and supply current for
the first page Typical Application. It can be seen that both
the output voltage and supply current come up gradually.
FAULT PROTECTION
An inductor overcurrent fault (> 3.75A) and/or INTVCC
undervoltage (INTVCC < 2.5V) and/or thermal lockout
(TJ > 170°C) will immediately prevent switching, will
reset the SS pin and will pull down VC. Once all faults are
removed, the LT8361 will soft-start VC and hence inductor
peak current.
Rev 0
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LT8361
APPLICATIONS INFORMATION
IL1 + IL2
1A/DIV
VOUT
10V/DIV
200µs/DIV
8361 F02
Figure 3. Soft-Start Waveforms
FREQUENCY FOLDBACK
During start-up or fault conditions in which VOUT is very low,
extremely small duty cycles may be required to maintain
control of inductor peak current. The minimum on-time
limitation of the power switch might prevent these low duty
cycles from being achievable. In this scenario inductor
current rise will exceed inductor current fall during each
cycle, causing inductor current to “walk up” beyond the
switch current limit. The LT8361 provides protection from
this by folding back switching frequency whenever FBX
or SS pins are close to GND (low VOUT levels or start-up).
This frequency foldback provides a larger switch-off time,
allowing inductor current to fall enough each cycle (see
Normalized Switching Frequency vs FBX Voltage in the
Typical Performance Characteristics section).
THERMAL LOCKOUT
If the LT8361 die temperature reaches 170°C (typical),
the part will stop switching and go into thermal lockout.
When the die temperature has dropped by 5°C (nominal),
the part will resume switching with a soft-started inductor
peak current.
network is usually connected from the VC pin to GND.
The Block Diagram shows the typical VC compensation
network. For most applications, the capacitor should be
in the range of 100pF to 10nF, and the resistor should
be in the range of 5k to 100k. A small capacitor is often
connected in parallel with the RC compensation network
to attenuate the VC voltage ripple induced from the output
voltage ripple through the internal error amplifier. The parallel capacitor usually ranges in value from 2.2pF to 22pF. A
practical approach to designing the compensation network
is to start with one of the circuits in this data sheet that
is similar to your application, and tune the compensation
network to optimize the performance. Stability should then
be checked across all operating conditions, including load
current, input voltage and temperature. Application Note
76 is a good reference.
THERMAL CONSIDERATIONS
Care should be taken in the layout of the PCB to ensure good
heat sinking of the LT8361. Both packages have an exposed
pad underneath the IC which is the best path for heat out
of the package. The exposed pad should be soldered to a
continuous copper ground plane under the device to reduce
die temperature and increase the power capability of the
LT8361. The ground plane should be connected to large
copper layers to spread heat dissipated by the LT8361.
Power dissipation within the LT8361 (PDISS_LT8361) can
be estimated by subtracting the inductor and Schottky
diode power losses from the total power losses calculated
in an efficiency measurement. The junction temperature
of LT8361 can then be estimated by:
TJ(LT8361) = TA + θ JA • PDISS_LT8361
APPLICATION CIRCUITS
COMPENSATION
Loop compensation determines the stability and transient
performance. The LT8361 uses current mode control to
regulate the output which simplifies loop compensation.
The optimum values depend on the converter topology, the
component values and the operating conditions (including
the input voltage, load current, etc.). To compensate the
feedback loop of the LT8361, a series resistor-capacitor
The LT8361 can be configured for different topologies. The
first topology to be analyzed will be the boost converter,
followed by the SEPIC and inverting converters.
Boost Converter: Switch Duty Cycle
The LT8361 can be configured as a boost converter for the
applications where the converter output voltage is higher
than the input voltage. Remember that boost converters are
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13
LT8361
APPLICATIONS INFORMATION
not short-circuit protected. Under a shorted output condition, the inductor current is limited only by the input supply
capability. For applications requiring a step-up converter
that is short-circuit protected, please refer to the Applications Information section covering SEPIC converters.
The conversion ratio as a function of duty cycle is:
VOUT
1
=
VIN
1− D
in continuous conduction mode (CCM).
For a boost converter operating in CCM, the duty cycle
of the main switch can be calculated based on the output
voltage (VOUT) and the input voltage (VIN). The maximum
duty cycle (DMAX) occurs when the converter has the
minimum input voltage:
DMAX =
VOUT − VIN(MIN)
VOUT
Discontinuous conduction mode (DCM) provides higher
conversion ratios at a given frequency at the cost of reduced efficiencies, higher switching currents, and lower
available output power.
Boost Converter: Maximum Output Current Capability
and Inductor Selection
For the boost topology, the maximum average inductor
current is:
I L(MAX)(AVG) = IO(MAX) •
1
1
•
1 − DMAX
η
where η (< 1.0) is the converter efficiency.
Due to the current limit of its internal power switch, the
LT8361 should be used in a boost converter whose maximum output current (IO(MAX)) is:
I O(MAX) ≤
VIN(MIN)
VOUT
• (2A − 0.5 • ΔISW ) • η
Minimum possible inductor value and switching frequency
should also be considered since they will increase inductor
ripple current ∆ISW.
The inductor ripple current ∆ISW has a direct effect on the
choice of the inductor value and the converter’s maximum
14
output current capability. Choosing smaller values of
∆ISW increases output current capability, but requires
large inductances and reduces the current loop gain (the
converter will approach voltage mode). Accepting larger
values of ∆ISW provides fast transient response and
allows the use of low inductances, but results in higher
input current ripple and greater core losses, and reduces
output current capability. It is recommended to choose a
∆ISW of approximately 0.75A.
Given an operating input voltage range, and having chosen
the operating frequency and ripple current in the inductor,
the inductor value of the boost converter can be determined
using the following equation:
L =
VIN(MIN)
ΔISW • fOSC
• DMAX
The peak inductor current is the switch current limit
(maximum 3.4A), and the RMS inductor current is approximately equal to IL(MAX)(AVG).
Choose an inductor that can handle at least 3.4A without
saturating, and ensure that the inductor has a low DCR
(copper-wire resistance) to minimize I2R power losses. Note
that in some applications, the current handling requirements
of the inductor can be lower, such as in the SEPIC topology
where each inductor only carries one-half of the total switch
current. For better efficiency, use similar valued inductors
with a larger volume. Many different sizes and shapes are
available from various manufacturers (see Table 2). Choose a
core material that has low losses at the programmed switching frequency, such as a ferrite core. The final value chosen
for the inductor should not allow peak inductor currents to
exceed 2A in steady state at maximum load. Due to tolerances, be sure to account for minimum possible inductance
value, switching frequency and converter efficiency.
For inductor current operation in CCM and duty cycles
above 50%, the LT8361's internal slope compensation prevents sub-harmonic oscillations provided the
inductor value exceeds a minimum value given by:
L>
VIN
(–5 •D2 +9 •D– 1) • (fOSC )
•
(2 •D– 1)
(1–D)
Lower L values are allowed if the inductor current operates
in DCM or duty cycle operation is below 50%.
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Rev 0
LT8361
APPLICATIONS INFORMATION
tON
Table 2. Inductor Manufacturers
Sumida
(847) 956-0666
www.sumida.com
TDK
(847) 803-6100
www.tdk.com
Murata
(714) 852-2001
www.murata.com
Coilcraft
(847) 639-6400
www.coilcraft.com
Wurth
(605) 886-4385
www.we-online.com
tOFF
ΔVCOUT
VOUT
(AC)
RINGING DUE TO
TOTAL INDUCTANCE
(BOARD + CAP)
ΔVESR
8361 F04
Figure 4. The Output Ripple Waveform of a Boost Converter
BOOST CONVERTER: INPUT CAPACITOR SELECTION
Bypass the input of the LT8361 circuit with a ceramic capacitor of X7R or X5R type placed as close as possible to
the VIN and GND pins. Y5V types have poor performance
over temperature and applied voltage, and should not be
used. A 4.7µF to 10µF ceramic capacitor is adequate to
bypass the LT8361 and will easily handle the ripple current. If the input power source has high impedance, or
there is significant inductance due to long wires or cables,
additional bulk capacitance may be necessary. This can
be provided with a low performance electrolytic capacitor.
A precaution regarding the ceramic input capacitor concerns the maximum input voltage rating of the LT8361.
A ceramic input capacitor combined with trace or cable
inductance forms a high quality (under damped) tank circuit. If the LT8361 circuit is plugged into a live supply, the
input voltage can ring to twice its nominal value, possibly
exceeding the LT8361’s voltage rating. This situation is
easily avoided (see Application Note 88).
BOOST CONVERTER: OUTPUT CAPACITOR SELECTION
Low ESR (equivalent series resistance) capacitors should
be used at the output to minimize the output ripple voltage.
Multilayer ceramic capacitors are an excellent choice, as
they are small and have extremely low ESR. Use X5R or
X7R types. This choice will provide low output ripple and
good transient response. A 4.7µF to 47µF output capacitor
is sufficient for most applications, but systems with very
low output currents may need only a 1µF or 2.2µF output
capacitor. Solid tantalum or OS-CON capacitor can be
used, but they will occupy more board area than a ceramic
and will have a higher ESR. Always use a capacitor with a
sufficient voltage rating.
Contributions of ESR (equivalent series resistance), ESL
(equivalent series inductance) and the bulk capacitance
must be considered when choosing the correct output
capacitors for a given output ripple voltage. The effect of
these three parameters (ESR, ESL and bulk C) on the output
voltage ripple waveform for a typical boost converter is
illustrated in Figure 4.
The choice of component(s) begins with the maximum
acceptable ripple voltage (expressed as a percentage of
the output voltage), and how this ripple should be divided
between the ESR step ∆VESR and the charging/discharging ∆VCOUT. For the purpose of simplicity, we will choose
2% for the maximum output ripple, to be divided equally
between ∆VESR and ∆VCOUT. This percentage ripple will
change, depending on the requirements of the application,
and the following equations can easily be modified. For a
1% contribution to the total ripple voltage, the ESR of the
output capacitor can be determined using the following
equation:
ESRCOUT ≤
0.01 • VOUT
ID(PEAK)
For the bulk C component, which also contributes 1% to
the total ripple:
COUT ≥
IO(MAX)
0.01 • VOUT • fOSC
The output capacitor in a boost regulator experiences high
RMS ripple currents, as shown in Figure 4. The RMS ripple
current rating of the output capacitor can be determined
using the following equation:
IRMS(COUT) ≥ IO(MAX) •
DMAX
1 − DMAX
Rev 0
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15
LT8361
APPLICATIONS INFORMATION
Multiple capacitors are often paralleled to meet ESR
requirements. Typically, once the ESR requirement is
satisfied, the capacitance is adequate for filtering and has
the required RMS current rating. Additional ceramic capacitors in parallel are commonly used to reduce the effect of
parasitic inductance in the output capacitor, which reduces
high frequency switching noise on the converter output.
CERAMIC CAPACITORS
Ceramic capacitors are small, robust and have very low
ESR. However, ceramic capacitors can cause problems
when used with the LT8361 due to their piezoelectric nature.
When in Burst Mode operation, the LT8361’s switching
frequency depends on the load current, and at very light
loads the LT8361 can excite the ceramic capacitor at audio
frequencies, generating audible noise. Since the LT8361
operates at a lower current limit during Burst Mode operation, the noise is typically very quiet to a casual ear.
If this is unacceptable, use a high performance tantalum
or electrolytic capacitor at the output. Low noise ceramic
capacitors are also available.
VIN
Table 3. Ceramic Capacitor Manufacturers
Taiyo Yuden
(408) 573-4150
www.t-yuden.com
AVX
(803) 448-9411
www.avxcorp.com
Murata
(714) 852-2001
www.murata.com
BOOST CONVERTER: DIODE SELECTION
A Schottky diode is recommended for use with the LT8361.
Low leakage Schottky diodes are necessary when low
quiescent current is desired at low loads. The diode leakage
appears as an equivalent load at the output and should be
minimized. Choose Schottky diodes with sufficient reverse
voltage ratings for the target applications.
Table 4. Recommended Schottky Diodes
PART NUMBER
AVERAGE
FORWARD REVERSE REVERSE
CURRENT VOLTAGE CURRENT
(A)
(V)
(µA)
MANUFACTURER
DFLS1100
1
100
1
Diodes, Inc.
B1100/B
1
100
500
Diodes, Inc.
DFLS2100
2
100
1
Diodes, Inc.
VOUT
PGND
SW
°
1 EN
SW1 16
PGND
SW2 14 SW
3 VIN
5 INTVCC
SYNC 12
6 NC
SS 11
7 BIAS
GND
8 VC
RT 10
FBX 9
VOUT
°
8361 F05
Figure 5. Suggested Boost Converter Layout
16
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LT8361
APPLICATIONS INFORMATION
BOOST CONVERTER: LAYOUT HINTS
The high speed operation of the LT8361 demands careful
attention to board layout. Careless layout will result in performance degradation. Figure 5 shows the recommended
component placement for a boost converter. Note the vias
under the exposed pad. These should connect to a local
ground plane for better thermal performance.
The LT8361 can be configured as a SEPIC (single-ended
primary inductance converter), as shown in Figure 6. This
topology allows for the input to be higher, equal, or lower
than the desired output voltage. The conversion ratio as
a function of duty cycle is:
VOUT + VD
D
=
VIN
1− D
D1
VIN
VOUT
CIN
L2
VIN
COUT
SW
LT8361
EN/UVLO
INTVCC
VOUT + VD
VIN(MIN) + VOUT + VD
Conversely, the minimum duty cycle (DMIN) occurs when
the converter operates at the maximum input voltage:
VOUT + VD
VIN(MAX) + VOUT + VD
Be sure to check that DMAX and DMIN obey:
DMAX < 1 – Minimum Off-Time(MAX) • fOSC(MAX)
and
DMIN > Minimum On-Time(MAX) • fOSC(MAX)
where Minimum Off-Time, Minimum On-Time and fOSC
are specified in the Electrical Characteristics table.
in continuous conduction mode (CCM).
CDC
DMAX =
DMIN =
SEPIC CONVERTER APPLICATIONS
L1
The maximum duty cycle (DMAX) occurs when the converter
operates at the minimum input voltage:
SEPIC Converter: The Maximum Output Current
Capability and Inductor Selection
As shown in Figure 6, the SEPIC converter contains two
inductors: L1 and L2. L1 and L2 can be independent, but can
also be wound on the same core, since identical voltages
are applied to L1 and L2 throughout the switching cycle.
For the SEPIC topology, the current through L1 is the
converter input current. Based on the fact that, ideally, the
output power is equal to the input power, the maximum
average inductor currents of L1 and L2 are:
FBX
GND
8361 F06
Figure 6. LT8361 Configured in a SEPIC Topology
In a SEPIC converter, no DC path exists between the input
and output. This is an advantage over the boost converter
for applications requiring the output to be disconnected
from the input source when the circuit is in shutdown.
SEPIC Converter: Switch Duty Cycle and Frequency
For a SEPIC converter operating in CCM, the duty cycle
of the main switch can be calculated based on the output
voltage (VOUT), the input voltage (VIN) and the diode
forward voltage (VD).
IL1(MAX)(AVG) = IIN(MAX)(AVG) = IO(MAX) •
DMAX
1 − DMAX
IL2(MAX)(AVG) = IO(MAX)
In a SEPIC converter, the switch current is equal to IL1 +
IL2 when the power switch is on, therefore, the maximum
average switch current is defined as:
ISW(MAX)(AVG) = IL1(MAX)(AVG) + IL2(MAX)(AVG)
= IO(MAX) •
1
1 − DMAX
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17
LT8361
APPLICATIONS INFORMATION
Given an operating input voltage range, and having chosen ripple current in the inductor, the inductor value (L1
and L2 are independent) of the SEPIC converter can be
determined using the following equation:
and the peak switch current is:
⎛
χ ⎞
1
ISW(PEAK) = ⎜1 + ⎟ • IO(MAX) •
⎝
2 ⎠
1 − DMAX
The variable c in the preceding equations represents the
percentage peak-to-peak ripple current in the switch,
relative to ISW(MAX)(AVG), as shown in Figure 7. Then, the
switch ripple current ∆ISW can be calculated by:
∆ISW = χ • ISW(MAX)(AVG)
The inductor ripple currents ∆IL1 and ∆IL2 are identical:
∆IL1 = ∆IL2 = 0.5 • ∆ISW
ΔISW = χ • ISW(MAX)(AVG)
VIN(MIN)
0.5 • ΔISW • fOSC
• DMAX
For most SEPIC applications, the equal inductor values
will fall in the range of 2.2µH to 100µH.
By making L1 = L2, and winding them on the same core, the
value of inductance in the preceding equation is replaced
by 2L, due to mutual inductance:
L=
ISW
VIN(MIN)
ΔISW • fOSC
• DMAX
This maintains the same ripple current and energy storage
in the inductors. The peak inductor currents are:
ISW(MAX)(AVG)
t
DTS
TS
8361 F07
Figure 7. The Switch Current Waveform of the SEPIC Converter
The inductor ripple current has a direct effect on the
choice of the inductor value. Choosing smaller values of
∆IL requires large inductances and reduces the current
loop gain (the converter will approach voltage mode).
Accepting larger values of ∆IL allows the use of low inductances, but results in higher input current ripple and
greater core losses. It is recommended that c falls in the
range of 0.5 to 0.8.
Due to the current limit of its internal power switch, the
LT8361 should be used in a SEPIC converter whose
maximum output current (IO(MAX)) is:
IO(MAX) < (1 – DMAX ) • (2A – 0.5 • ∆ISW ) • η
where η (< 1.0) is the converter efficiency. Minimum
possible inductor value and switching frequency should
also be considered since they will increase inductor ripple
current ∆ISW.
18
L1 = L2 =
IL1(PEAK) = IL1(MAX) + 0.5 • ∆IL1
IL2(PEAK) = IL2(MAX) + 0.5 • ∆IL2
The maximum RMS inductor currents are approximately
equal to the maximum average inductor currents.
Based on the preceding equations, the user should choose
the inductors having sufficient saturation and RMS current ratings.
Similar to Boost converters, the SEPIC converter also needs
slope compensation to prevent subharmonic oscillations
while operating in CCM. The equation presented in the
Boost Converter section defines the minimum inductance
value to avoid sub-harmonic oscillations when coupled
inductors are used. For uncoupled inductors, the minimum
inductance requirement is doubled.
SEPIC Converter: Output Diode Selection
To maximize efficiency, a fast switching diode with a low
forward drop and low reverse leakage is desirable. The
average forward current in normal operation is equal to
the output current.
Rev 0
For more information www.analog.com
LT8361
APPLICATIONS INFORMATION
It is recommended that the peak repetitive reverse voltage
rating VRRM is higher than VOUT + VIN(MAX) by a safety
margin (a 10V safety margin is usually sufficient).
VIN
+
+
L2
–
–
CIN
COUT
SW
The power dissipated by the diode is:
LT8361
PD = IO(MAX) • VD
D1
GND
where VD is diode’s forward voltage drop, and the diode
junction temperature is:
TJ = TA + PD • RθJA
VOUT
+
+
8361 F10
Figure 8. A Simplified Inverting Converter
Inverting Converter: Switch Duty Cycle and Frequency
The RθJA used in this equation normally includes the RθJC
for the device, plus the thermal resistance from the board,
to the ambient temperature in the enclosure. TJ must not
exceed the diode maximum junction temperature rating.
SEPIC Converter: Output and Input Capacitor Selection
The selections of the output and input capacitors of the
SEPIC converter are similar to those of the boost converter.
SEPIC Converter: Selecting the DC Coupling Capacitor
The DC voltage rating of the DC coupling capacitor (CDC,
as shown in Figure 6) should be larger than the maximum
input voltage:
VCDC > VIN(MAX)
CDC has nearly a rectangular current waveform. During the
switch off-time, the current through CDC is IIN, while approximately –IO flows during the on-time. The RMS rating of the
coupling capacitor is determined by the following equation:
IRMS(CDC) > IO(MAX) •
CDC
L1
For an inverting converter operating in CCM, the duty
cycle of the main switch can be calculated based on the
negative output voltage (VOUT) and the input voltage (VIN).
The maximum duty cycle (DMAX) occurs when the converter
has the minimum input voltage:
DMAX =
VOUT
VOUT − VD
− VD − VIN(MIN)
Conversely, the minimum duty cycle (DMIN) occurs when
the converter operates at the maximum input voltage :
DMIN =
VOUT
VOUT − VD
− VD − VIN(MAX)
Be sure to check that DMAX and DMIN obey :
DMAX < 1 – Minimum Off-Time(MAX) • fOSC(MAX)
and
DMIN > Minimum On-Time(MAX) • fOSC(MAX)
where Minimum Off-Time, Minimum On-Time and fOSC
are specified in the Electrical Characteristics table.
VOUT + VD
VIN(MIN)
A low ESR and ESL, X5R or X7R ceramic capacitor works
well for CDC.
INVERTING CONVERTER APPLICATIONS
The LT8361 can be configured as a dual-inductor inverting
topology, as shown in Figure 8. The VOUT to VIN ratio is:
Inverting Converter: Inductor, Output Diode and Input
Capacitor Selections
The selections of the inductor, output diode and input
capacitor of an inverting converter are similar to those of
the SEPIC converter. Please refer to the corresponding
SEPIC Converter sections.
VOUT − VD
D
= −
VIN
1− D
in continuous conduction mode (CCM).
Rev 0
For more information www.analog.com
19
LT8361
APPLICATIONS INFORMATION
Inverting Converter: Output Capacitor Selection
The inverting converter requires much smaller output
capacitors than those of the boost, flyback and SEPIC
converters for similar output ripples. This is due to the fact
that, in the inverting converter, the inductor L2 is in series
with the output, and the ripple current flowing through the
output capacitors are continuous. The output ripple voltage
is produced by the ripple current of L2 flowing through
the ESR and bulk capacitance of the output capacitor:
⎛
⎞
1
⎟
ΔVOUT(P–P) = ΔIL2 • ⎜⎜ESRCOUT +
⎟
8
•
f
•
C
OSC
OUT
⎝
⎠
After specifying the maximum output ripple, the user can
select the output capacitors according to the preceding
equation.
The ESR can be minimized by using high quality X5R or
X7R dielectric ceramic capacitors. In many applications,
ceramic capacitors are sufficient to limit the output voltage ripple.
20
The RMS ripple current rating of the output capacitor
needs to be greater than:
IRMS(COUT) > 0.3 • ∆IL2
Inverting Converter: Selecting the DC Coupling
Capacitor
The DC voltage rating of the DC coupling capacitor (CDC,
as shown in Figure 8) should be larger than the maximum
input voltage minus the output voltage (negative voltage):
VCDC > VIN(MAX) + VOUT
CDC has nearly a rectangular current waveform. During
the switch off-time, the current through CDC is IIN, while
approximately –IO flows during the on-time. The RMS
rating of the coupling capacitor is determined by the following equation:
IRMS(CDC) > IO(MAX) •
DMAX
1 − DMAX
A low ESR and ESL, X5R or X7R ceramic capacitor works
well for CDC.
Rev 0
For more information www.analog.com
LT8361
TYPICAL APPLICATIONS
400kHz, 4V to 60V Input, 24V SEPIC Converter
C6
1µF
L1
22µH
D1
VIN
4V TO 48V
C1
4.7µF
VIN
L2
22µH
SW
C5
10µF
R1
1M
EN/UVLO
FBX
BIAS
SYNC/MODE
Efficiency
VOUT
INTVCC
SS
GND
R4
121k
100
VC
R3
16.2k
C2
0.22µF
R2
71.5k
C4
1µF
95
90
C3
6.8nF
8361 TA02a
D1: DIODES INC. DFLS2100
L1: WURTH ELEKTRONIK WE-DD 7345 744877220
C5: MURATA GRM32ER71H106KA12L
85
EFFICIENCY (%)
LT8361
RT
VOUT
24V
200mA AT VIN = 5V
450mA AT VIN = 12V
550mA AT VIN = 24V
600mA AT VIN = 48V
80
75
70
65
VIN = 5V
VIN = 12V
VIN = 24V
VIN = 48V
60
55
50
0.001
0.01
0.1
LOAD CURRENT (A)
1
8361 TA02b
450kHz, 3V to 60V Input, 12V SEPIC Converter
C1
4.7µF
VIN
D1
L2
22µH
SW
C5
10µF
×2
R1
1M
EN/UVLO
LT8361
SYNC/MODE
RT
VOUT
Efficiency
INTVCC
SS
R4
107k
FBX
BIAS
GND
C2
10nF
D1: DIODES INC. B1100LB
L1: WURTH ELEKTRONIK WE-DD 1280 744873220
C5: MURATA GRM32ER71H106KA12L
VOUT
12V
150mA AT VIN = 3V
390mA AT VIN = 5V
700mA AT VIN = 12V
900mA AT VIN = 24V
970mA AT VIN = 36V
1.1A AT VIN = 48V
VC
R3
28k
R2
154k
C4
1µF
100
95
90
C3
4.7nF
8361 TA03a
EFFICIENCY (%)
VIN
3V TO 60V
C6
1µF
L1
22µH
85
80
75
70
65
VIN = 5V
VIN = 12V
VIN = 24V
VIN = 48V
60
55
50
0
0.2
0.4
0.6
0.8
LOAD CURRENT (A)
1.0
1.2
8361 TA03b
Rev 0
For more information www.analog.com
21
LT8361
TYPICAL APPLICATIONS
450kHz, 10V to 48V Input, 48V SEPIC Converter
C6
1µF
L1
47µH
D1
C1
4.7µF
VIN
L2
47µH
SW
C5
10µF
R1
1M
EN/UVLO
FBX
LT8361
SYNC/MODE
RT
BIAS
Efficiency
VOUT
100
INTVCC
SS
GND
R4
107k
VOUT
48V
250mA AT VIN = 10V
290mA AT VIN = 12V
460mA AT VIN = 24V
550mA AT VIN = 36V
610mA AT VIN = 48V
VC
C4
1µF
R3
24k
C2
10nF
95
R2
34.8k
C3
3.3nF
8361 TA04a
D1: DIODES INC. DFLS2100
L1: WURTH ELEKTRONIK WE-DD 1280 744873470
C5: MURATA GRM32ER71H106KA12L
90
EFFICIENCY (%)
VIN
10V TO 48V
85
80
75
70
65
60
VIN = 12V
VIN = 24V
VIN = 48V
55
50
0
0.15
0.30
0.45
0.60
LOAD CURRENT (A)
0.75
8361 TA04b
2MHz, 10V to 54V Input, 65V Boost Converter
L1
6.1µH
C1
4.7µF
VIN
D1
R1
1M
SW
EN/UVLO
LT8361
SYNC/MODE
RT
SS
R4
20k
D1: DIODES INC. DFLS2100
L1: WURTH ELEKTRONIK WE-PD 1280 74477006
C5: NIPPON CHEMI-CON KTS101B155M43N0T00
FBX
BIAS
INTVCC
GND
C2
10nF
VOUT
65V
C5
120mA AT VIN = 12V
1.5µF
310mA AT VIN = 24V
×2
470mA AT VIN = 36V
560mA AT VIN = 48V
630mA AT VIN = 54V
C4
1µF
VC
Efficiency
R2
25.5k
100
90
R3
22.1k
80
C3
2.2nF
8361 TA05a
EFFICIENCY (%)
VIN
10V TO 54V
70
60
50
40
30
20
VIN = 12V
VIN = 24V
VIN = 48V
10
0
0
0.1
0.2
0.3
0.4
LOAD CURRENT (A)
0.5
0.6
8361 TA05b
22
Rev 0
For more information www.analog.com
LT8361
TYPICAL APPLICATIONS
450kHz, 5V to 60V Input, 80V Boost Converter
VIN
5V TO 60V
L1
68µH
C1
4.7µF
VIN
D1
R1
1M
SW
EN/UVLO
FBX
LT8361
RT
BIAS
INTVCC
SS
GND
100
90
R3
30k
C2
10nF
R4
107k
C4
1µF
VC
Efficiency
R2
20.5k
80
C3
3.3nF
EFFICIENCY (%)
SYNC/MODE
VOUT
80V
C5
3.3µF 220mA AT VIN = 12V
450mA AT VIN = 24V
×2
500mA AT VIN = 48V
8361 TA06a
D1: DIODES INC. DFLS2100
L1: WURTH ELEKTRONIK WE-PD 1280 744770168
C5: NIPPON CHEMI-CON KTS101B335M55N0T00
70
60
50
40
30
20
VIN = 5V
VIN = 12V
VIN = 24V
10
0
0
0.10
0.20
0.30
0.40
LOAD CURRENT (A)
0.50
8361 TA06b
1.2MHz, 8V to 16V Input, 25V to 80V Output Boost Converter
L1
6.1µH
C1
4.7µF
VIN
D1
R1
1M
SW
EN/UVLO
LT8361
SYNC/MODE
RT
SS
R4
37.4k
D1: DIODES INC. DFLS2100
L1: WURTH ELEKTRONIK WE-PD 1280 74477006
C5: NIPPON CHEMI-CON KTS101B155M43N0T00
FBX
R5
60k
BIAS
INTVCC
GND
C2
10nF
C4
1µF
VC
R3
22.1k
R2
30.4k
VOUT
25V to 80V
C5
1.5µF 25V/480mA AT VIN = 12V
48V/230mA AT VIN = 12V
×3
60V/180mA AT VIN = 12V
80V/100mA AT VIN = 12V
Efficiency
100
VCONTROL
0V to 3.3V
VOUT
80V to 25V
C3
2.2nF
8361 TA07a
90
80
EFFICIENCY (%)
VIN
8V TO 16V
70
60
50
40
30
20
VIN = 12V, VOUT = 80V
VIN = 12V, VOUT = 25V
10
0
0
0.10
0.20
0.30
0.40
LOAD CURRENT (A)
0.50
8361 TA07b
Rev 0
For more information www.analog.com
23
LT8361
TYPICAL APPLICATIONS
450kHz, 4V to 60V Input, –24V Inverting Converter
L1
33µH
L2
33µH
C6
1µF
VIN
4V TO 60V
C1
4.7µF
C5
10µF
D1
VIN
SW
R1
1M
EN/UVLO
100
BIAS
95
INTVCC
SS
GND
VC
R3
36.5k
C2
10nF
R2
34.8k
C4
1µF
90
EFFICIENCY (%)
SYNC/MODE
R4
107k
Efficiency
FBX
LT8361
RT
VOUT
–24V
150mA AT VIN = 5V
500mA AT VIN = 12V
750mA AT VIN = 24V
870mA AT VIN = 36V
920mA AT VIN = 48V
C3
2.2nF
8361 TA08a
D1: DIODES INC. DFLS2100
L1: WURTH ELEKTRONIK WE-PD 1280 744873330
C5: MURATA GRM32ER71H106KA12L
85
80
75
70
65
VIN = 5V
VIN = 12V
VIN = 24V
VIN = 48V
60
55
50
0
0.2
0.4
0.6
LOAD CURRENT (A)
0.8
0.9
8361 TA08b
450kHz, 3V to 60V Input, –12V Inverting Converter
C6
1µF
L1
22µH
L2
22µH
VIN
3V TO 60V
C1
4.7µF
D1
SW
R1
1M
EN/UVLO
LT8361
SYNC/MODE
RT
100
INTVCC
SS
R4
107k
Efficiency
FBX
BIAS
GND
C2
10nF
D1: DIODES INC. DFLS2100
L1: WURTH ELEKTRONIK WE-PD 1280 744873220
C5: MURATA GRM32ER71H106KA12L
VC
R3
59k
95
R2
71.5k
C4
1µF
C3
1.5nF
8361 TA09a
90
EFFICIENCY (%)
VIN
C5
10µF
×2
VOUT
–12V
150mA AT VIN = 3V
380mA AT V IN = 5V
680mA AT V IN = 12V
860mA AT V IN = 24V
920mA AT V IN = 36V
1A AT VIN = 48V
85
80
75
70
65
VIN = 5V
VIN = 12V
VIN = 24V
VIN = 48V
60
55
50
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
LOAD CURRENT (A)
8361 TA09b
24
Rev 0
For more information www.analog.com
LT8361
TYPICAL APPLICATIONS
450kHz, 10V to 48V Input, –48V Inverting Converter
C6
1µF
L1
47µH
C1
4.7µF
D1
VIN
C5
10µF
SW
R1
1M
EN/UVLO
LT8361
SYNC/MODE
RT
R4
107k
Efficiency
FBX
100
BIAS
95
INTVCC
SS
GND
C2
10nF
D1: DIODES INC. B1100LB
L1: WURTH ELEKTRONIK WE-PD 1280 744873470
C5: MURATA GRM32ER71H106KA12L
VOUT
–48V
250mA AT VIN = 10V
290mA AT VIN = 12V
470mA AT VIN = 24V
550mA AT VIN = 36V
610mA AT VIN = 48V
VC
R3
48.7k
R2
16.9k
C4
1µF
C3
2.2nF
8361 TA10a
90
EFFICIENCY (%)
VIN
10V TO 48V
L2
47µH
85
80
75
70
65
60
VIN = 12V
VIN = 24V
VIN = 48V
55
50
0
0.1
0.3
0.4
LOAD CURRENT (A)
0.5
0.7
8361 TA10b
Rev 0
For more information www.analog.com
25
LT8361
TYPICAL APPLICATIONS
Low IQ, Low EMI, 400kHz, 24V Output SEPIC Converter with SSFM
VIN
5V TO 48V C8
4.7µF
×2
50V
1210
INPUT EMI FILTER
L2
470nH
C6
10µF
50V
1206
L1A
22µH
C2
68µF
50V
VIN
C15
1µF
100V
1206
OUTPUT EMI FILTER
FB2
D2
C1
0.1µF
35V
0402
L1B
22µH
SW
LT8361
RT
FBX
GND VC
C13
0.22µF
R9
121k
R8
16.2k
C12
6.8nF
80
60
70
50
60
50
40
30
20
10
0
CLASS 5 PEAK LIMIT
MEASURED EMISSIONS
AMBIENT NOISE
–10
–20
0.1
1
FREQUENCY (MHz)
10
40
30
20
10
0
–10
–20
CLASS 5 AVERAGE LIMIT
MEASURED EMISSIONS
AMBIENT NOISE
–30
8361 TA11b
1
FREQUENCY (MHz)
50
50
40
30
20
10
0
CLASS 5 PEAK LIMIT
MEASURED EMISSIONS
AMBIENT NOISE
700
800
12V INPUT TO 24V OUTPUT AT 500mA, fSW = 400kHz, SSFM ON
900
1000
8361 TA11d
AVERAGE RADIATED EMI (dBµV/m)
PEAK RADIATED EMI (dBµV/m)
60
400
500
600
FREQUENCY (MHz)
30
8361 TA11c
Radiated EMI Performance
(CISPR25 Class 5 Average)
60
300
10
12V INPUT TO 24V OUTPUT AT 500mA, fSW = 400kHz, SSFM ON
Radiated EMI Performance
(CISPR25 Class 5 Peak)
–10
D1: DIODES INC. DFLS2100
L1: WURTH ELEKTRONIK WE-DD 7345 744877220
L2: WURTH ELEKTRONIK 74479876147
C2: PANASONIC EEHZC1H680P
C14: MURATA GRM32ER71H106KA12L
FB2: WURTH ELEKTRONIK 742792040
–40
0.1
30
12V INPUT TO 24V OUTPUT AT 500mA, fSW = 400kHz, SSFM ON
26
VOUT
24V
Conducted EMI Performance
(CISPR25 Class 5 Average)
AVERAGE CONDUCTED EMI (dBµV)
PEAK CONDUCTED EMI (dBµV)
Conducted EMI Performance
(CISPR25 Class 5 Peak)
200
C7
0.1µF
35V
0402
R7
71.5k
C10
1µF
8361 TA11a
100
C3
0.1µF
35V
0402
VOUT
R6
1M
BIAS
INTVCC
SS
R1
100k
0
C14
10µF
50V
1210
EN/UVLO
SYNC/MODE
–20
C4
0.1µF
35V
0402
40
30
20
10
0
CLASS 5 AVERAGE LIMIT
MEASURED EMISSIONS
AMBIENT NOISE
–10
–20
0
100
200
300
400
500
600
FREQUENCY (MHz)
700
800
12V INPUT TO 24V OUTPUT AT 500mA, fSW = 400kHz, SSFM ON
900
1000
8361 TA11e
Rev 0
For more information www.analog.com
LT8361
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LT8361#packaging for the most recent package drawings.
MSE Package
Variation: MSE16 (12)
16-Lead Plastic MSOP with 4 Pins Removed
Exposed Die Pad
(Reference LTC DWG # 05-08-1871 Rev D)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.845 ±0.102
(.112 ±.004)
5.10
(.201)
MIN
2.845 ±0.102
(.112 ±.004)
0.889 ±0.127
(.035 ±.005)
8
1
1.651 ±0.102
(.065 ±.004)
1.651 ±0.102 3.20 – 3.45
(.065 ±.004) (.126 – .136)
16
0.305 ±0.038
(.0120 ±.0015)
TYP
0.50
(.0197)
1.0 BSC
(.039)
BSC
RECOMMENDED SOLDER PAD LAYOUT
0.254
(.010)
0.35
REF
4.039 ±0.102
(.159 ±.004)
(NOTE 3)
0.12 REF
DETAIL “B”
CORNER TAIL IS PART OF
DETAIL “B” THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
9
NO MEASUREMENT PURPOSE
0.280 ±0.076
(.011 ±.003)
REF
16 14 121110 9
DETAIL “A”
0° – 6° TYP
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
4.90 ±0.152
(.193 ±.006)
GAUGE PLANE
0.53 ±0.152
(.021 ±.006)
DETAIL “A”
1.10
(.043)
MAX
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
1
0.50
(.0197)
BSC
3 567 8
1.0
(.039)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL
NOT EXCEED 0.254mm (.010") PER SIDE.
0.86
(.034)
REF
0.1016 ±0.0508
(.004 ±.002)
MSOP (MSE16(12)) 0213 REV D
Rev 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For
is granted
implication or
otherwise under any patent or patent rights of Analog Devices.
moreby
information
www.analog.com
27
LT8361
TYPICAL APPLICATION
450kHz, 4.5V to 12V Input, –150V Output, Automotive LiDAR APD Bias Power Supply
D4
C1
4.7µF
VIN
D2
SW
R5
20Ω
D3
R1
1M
SYNC/MODE
RT
GND
BIAS
C2
10nF
D1, D2, D3, D4: DIODES INC. DFLS2100
L1: WURTH ELEKTRONIK WE-PD 7345 7447779002
C5: NIPPON CHEMI-CON KTS101B155M32N0T00
C4
1µF
VC
R3
56.2k
C3
4.7nF
Efficiency
100
90
80
VOUT
INTVCC
SS
R4
107k
FBX
C7
1.5µF
C5
1.5µF
×2
D1
EN/UVLO
LT8361
R6
20Ω
EFFICIENCY (%)
VIN
4.5V TO 12V
C9
1µF
C6
2.2µF
L1
2.2µH
VOUT
–150V
15mA
R2
5.36k
70
60
50
40
30
20
VIN = 5V
VIN = 8V
VIN = 12V
10
8361 TA12a
0
0
4
8
12
16
LOAD CURRENT (mA)
20
8361 TA12b
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
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LT8362
60V, 2A, Low IQ Boost/SEPIC/Inverting Converter
VIN = 2.8V to 60V, VOUT(MAX) = 60V, IQ = 9µA (Burst Mode
Operation), MSOP-16(12)E 3mm × 3mm DFN-8 packages
LT8364
60V, 4A, Low IQ Boost/SEPIC/Inverting Converter
VIN = 2.8V to 60V, VOUT(MAX) = 60V, IQ = 9µA (Burst Mode
Operation), MSOP-16(12)E 4mm × 3mm DFN-12 packages
LT8494
70V, 2A Boost/SEPIC 1.5MHz High Efficiency Step-Up
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(Burst Mode Operation), ISD = <1µA, 20-Lead TSSOP
LT8570/LT8570-1
65V, 500mA/250mA Boost/Inverting DC/DC Converter
VIN(MIN) = 2.55V, VIN(MAX) = 40V, VOUT(MAX) = ±60V, IQ = 1.2mA,
ISD = <1mA, 3mm × 3mm DFN-8, MSOP-8E
LT8580
1A (ISW), 65V, 1.5MHz, High Efficiency Step-Up DC/DC
Converter
VIN: 2.55V to 40V, VOUT(MAX) = 65V, IQ = 1.2mA, ISD = <1µA,
3mm × 3mm DFN-8, MSOP-8E
28
Rev 0
D16802-0-4/18(0)
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