FEDL9078-002-01 Issue Date: Jan.30, 2012 ML9078-002 LSI for power-saving solar power supply control Outline ML9078-002 is power supply control LSI which performs selection control for a solar cell power supply and a primary battery. This LSI consists of a direct switch circuit and a regulator circuit, and each circuit performs the following operations. ● Direct switch circuit - Primary battery side direct switch circuit (BAT_DIRECT) x This always compare the primary battery side voltage (VBAT) with the output voltage (VDO) of ML9078-002. In case VBAT>VDO, a primary battery side direct switch will be set to ON and the primary battery side voltage (VBAT) is supplied to the output voltage (VDO). - Solar cell side direct switch circuit (SC_DIRECT) x This always compare the solar cell side voltage (VSC) with the output voltage (VDO) of ML9078-002. In case VSC>VDO, a solar cell side direct switch will be set to ON and the primary battery side voltage (VSC) is supplied to the output voltage (VDO). ● Regulator circuit x The solar cell side voltage (Vsc) will be limited to be 1.5V(typ) or 3.0V(typ). Feature ● Comparison of primary battery power supply voltage (VBAT) and solar cell power supply voltage (VSC) is performed, and the power supply source is selected automatically. - When primary battery voltage (VBAT) is higher than solar cell voltage (VSC), it outputs primary battery voltage (VBAT) to the output terminal (VDO) of ML9078-002. - When solar cell voltage (VSC) is higher than primary battery voltage (VBAT), it outputs solar cell voltage (VSC) to the output terminal (VDO) of ML9078-002. ● The adverse current from a solar cell to a primary battery is prevented. - When primary battery voltage is low, the direct switch by the side of a primary battery turns off. The adverse current to a primary battery from a solar cell is prevented, and the primary battery destruction by the adverse current from a solar cell to a primary battery can be prevented. ● Direct power supply from whether a solar cell output or a primary battery output to the external LSI is available. (at the time of SCREG=L) ● The regulator output voltage is selectable by the external input. (at the time of SCREG=H) - In case SCLV=L : regulator output voltage(VLD) will be limited to be 1.5V(typ) (VSC>=2V, ISC<=0.1mA, 25 °C conditions) - In case SCLV=H : regulator output voltage(VLD) will be limited to be 3.0V(typ) (VSC>=3.6V, ISC<=0.8mA, 25 °C conditions) ● Low power operation - Primary-battery side consumption current: Max 80nA at 25°C - SCREG=L,SCLV=X,Solar-cell side consumption current: Max 80nA at 25°C - SCREG=H,SCLV=L,Solar-cell side consumption current: Max 250nA at 25°C - SCREG=H,SCLV=H,Solar-cell side consumption current: Max 1200 nA at 25°C ● A monitor of the use situation of a solar panel is possible. - In case DI_MONI=L, current is supplied from solar cell to external circuit. - In case DI_MONI=H, current is supplied from primary battery to external circuit. 1/19 FEDL9078-002-01 ML9078-002 ● Shipment form - 12-pin plastic WQFN x Part number : ML9078-002GDZ05B - Chip x Part number : ML9078-002WA ● Guaranteed operation range - Operating temperature : -20 to +70°C - Operating voltage : VSC = 0.0 to 4V, VBAT = 1.1 to 3.6V 2/19 FEDL9078-002-01 ML9078-002 Block diagram ML9078-002 block diagram - The block diagram of ML9078-002 is shown in Fig. 1. VBAT VDO bat_direct SW SCREG ※2 VSC DI_MONI regulator VLD sc_direct SCLV ※1 ※1 ※2 VSS Regulator voltage is chosen to 3.0V or 1.5V by SCLV. Regulator can be disabled by SCREG through SW. Fig 1 ML9078-002 block diagram Pin Configuration SCLV SCREG (NC) 9 8 7 ML9078-002GDZ05B terminal arrangement 5 DI_MONI (NC) 12 4 VBAT 3 11 VDO (NC) 2 (NC) VSC 6 1 (NC) 10 VSS (NC): No Connection Fig. 2 ML9078-002 package article terminal arrangement plan 3/19 FEDL9078-002-01 ML9078-002 ML9078-002WA terminal arrangement and outline drawing 4 VBAT 3 VDO 5 DI_MONI 2 VSC 1.1mm 1 VSS 8 SCREG 9 SCLV Y X 1.1mm Chip size : 1.1mm x 1.1mm The number of pads : 7 pins Minimum pad pitch : 120 μm Pad opening : 90 μm x 90 μm Chip thickness : 350 μm The voltage on the back of a chip is VSS level. Fig. 3 ML9078-002 chip outline drawing ML9078-002 chip article pad coordinates Table 1 ML9078-002 pad coordinates table PAD No. 1 2 3 4 5 6 Pad Name VSS VSC VDO VBAT DI_MONI - ML9078-002 X (μm) Y (μm) 432.0 -228.0 432.0 -21.0 432.0 385.0 156.0 432.0 -27.0 432.0 - PAD No. 7 8 9 10 11 12 Pad Name SCREG SCLV - Chip Center: X=0,Y=0 ML9078-002 X (μm) -432.0 -432.0 - Y (μm) -287.0 -407.0 - 4/19 FEDL9078-002-01 ML9078-002 Terminal explanation Table 2 Explanation of terminal Terminal name I/O Explanation Logic Power supply terminal VSS - It is the minus side power supply terminal. - VBAT - It is the primary battery plus side power supply terminal. - VSC - It is the plus side power supply terminal of a solar power supply. It connects with the plus side of a solar power supply. - Regulator setting input terminal SCLV I It is an input port for a regulator voltage setup. In case SCLV=L, regulator output voltage will be limited to be 1.5V(typ) Positive In case SCLV=H, regulator output voltage will be limited to be 3.0V(typ) SCREG I It is an input port for an enabling setup of a regulator. Positive The output terminal of a primary battery and a solar power supply VDO O It is an output terminal of a primary battery and a solar power supply. - The output terminal which displays power supply source DI_MONI O It is an output terminal for displaying power supply source. In case DI_MONI=L, current is supplied from solar cell to external ciruit. Negative In case DI_MONI=H, current is supplied from primary battery to external ciruit. Termination of unused pins Table 3 shows methods of terminating the unused pins. Table 3 Termination of unused pins Terminal output VDO DI_MONI input SCLV(*1) SCREG(*1) Recommendation terminal processing Open Open VSC or VSS VSC or VSS * Note Consider input to fix to VSC or VSS. 5/19 FEDL9078-002-01 ML9078-002 Electrical property Absolute maximum rating (VSS= 0V) Item Sign Conditions Rated value Unit Power supply voltage 1 VBAT Top = 25 °C -0.3 to +4.2 V Power supply voltage 2 VSC Top = 25 °C -0.3 to +5.6 V Power supply voltage 3 VDO Top = 25 °C -0.3 to +5.6 V Input voltage VIN Top = 25 °C - 0.3 to VSC+0.3 V Output voltage VOUT Top = 25 °C -0.3 to VDO+0.3 V Output current 1 IOUT1 VDO, Top = 25 °C 10 mA Permissible loss PD Top = 25 °C 0.88 W Preservation temperature TSTG - -40 to +125 °C Recommendation operation conditions (VSS= 0V) Item Sign Conditions Range Unit Temperature of operation TOP - -20 to +70 °C VSC * Top=-20 to 70 0.0 to 4.0 Top=-20 to 70 1.1 to 3.6 Voltage of operation External capacitance for regulator output voltage stabilization VBAT Cdo Top=-20℃ to 70℃ VSC=0V to 4.0V VBAT=1.1V to 3.6V SCREG=H SCLV=L SCREG=H SCLV=H V 0.01 to 0.1 μF 0.1 to 1 μF * Note VSC power rise time is required to be more than TWUP=125 us/V. Please start after stand-by-time TWAIT=10msec when a VSC power supply is less than 0.5V. Notice of starting speed and stand-by-time for VSC VSC VSS VSC VSC x0.9 VSC x0.1 TWUP TWAIT 6/19 FEDL9078-002-01 ML9078-002 Direct-current characteristic (Input) (VBAT=1.1V to 3.6V, VSC=0.0V to 4.0V, VSS=0V, and Top=-20 to +70 °C, unless otherwise specified) Rating Item Sign Input (SCLV, SCREG) Unit Min. Typ. Max. VSC=1.1 to 4.0V 0.7 xVSC - VSC VSC=1.3 to 4.0V 0 - VSC=1.1 to 4.0V 0 - IIH VSC=1.1 to 4.0V - - 10 IIL VSC=1.1 to 4.0V -10 - - VIH Input voltage (SCLV, SCREG) Conditions 0.3 xVSC 0.2 xVSC VIL Measuring circuit V 1 nA . Direct-current characteristic (power supply control) Item Sign (VBAT=1.1V to 3.6V, VSC=0.0V to 4.0V, VSS=0V, and Top=-20 to +70 °C, unless otherwise specified) Standard value Measuring Conditions Unit Circuit Min. Typ. Max. VBAT=3.6V Top = 25 °C VSC=4V SCREG=L Top = 25 °C Solar power supply VSC=4V SCREG=H side IDDSC(*2) Top = 25 °C SCLV=L Consumption current VSC=4V SCREG=H Top = 25 °C SCLV=H *1 : IDDBAT is consumption current to the current consumed by the primary battery side. *2 : IDDSC is consumption current to the current consumed by the solar power supply side. Primary battery side Consumption current IDDBAT(*1) - - 80 - - 80 - - 250 - - 1200 nA 2 7/19 FEDL9078-002-01 ML9078-002 Item VDO voltage VBAT->VDO (VDO is supplied from VBAT) VDO voltage VSC (VDO) (VDO is supplied from VSC) Regulator through mode Sign VDOBAT VDOSC VDOREG(L1) VDO voltage VSC (VDO) (VDO is supplied from VSC) Regulator operational mode VDOREG(L2) VDOREG(H1) VDOREG(H2) (VBAT=1.1V to 3.6V, VSC=0.0V to 4.0V, VSS=0V, and Top=-20 to +70 °C, unless otherwise specified) Standard value Measuring Conditions Unit Circuit Min. Typ. Max. VSC<VBAT - 50mV 0V<=VBAT<=1.1V IBAT<=2mA VSC<VBAT - 50mV 1.1V<=VBAT<=2V IBAT<=2mA VSC<VBAT - 50mV VBAT>2.0V IBAT<=2mA VSC>VBAT - 50mV 0V<=VSC<=1.1V ISC<=2mA VSC>VBAT - 50mV 1.1V<=VSC<=2V ISC<=2mA VSC>VBAT - 50mV VSC>2.0V ISC<=2mA VSC>VBAT - 50mV 0V<=VSC<=1.1V ISC<=0.1mA Cdo=0.1uF Top = 25 °C VSC>VBAT - 50mV 1.1V<=VSC<=2V ISC<=0.1mA Cdo=0.1uF Top = 25 °C VSC>VBAT - 50mV VSC>2V ISC<=0.1mA Cdo=0.1uF Top = 25 °C VSC>VBAT - 50mV 0V<=VSC<=1.1V ISC<=0.8mA Cdo=0.1uF Top = 25 °C VSC>VBAT - 50mV 1.1V<=VSC<=3.6V ISC<=0.8mA Cdo=0.1uF Top = 25 °C VSC>VBAT - 50mV VSC>3.6V ISC<=0.8mA Cdo=0.1uF Top = 25 °C SCREG=L 0 - - VBAT 0.3 - - VBAT 0.15 - - 0 - - VSC 0.3 - - VSC 0.13 - - 0 - - V SCREG=H SCLV=L SCREG=H SCLV=H 0.8 - 1.6 1.35 1.5 1.6 0 - - 0.8 - 3.1 2.9 3 3.1 3,4 8/19 FEDL9078-002-01 ML9078-002 ● ML9078-002 operation in regulator through mode VDOBAT VDO output VDOREG(L2) VDOREG(H2) VDOREG(L1) VDOREG(H1) VDOBAT VBAT<VSC VSC<VDOREG(L2) VSC<VDOREG(H2) VBAT>VSC VDOREG Conditions VBAT>VSC VBAT<VSC VSC>VDOREG(L2) VSC>VDOREG(H2) Waveform VBAT VSC VDO VSC ΔVSC-VDO ΔVSC-VDO VBAT ΔVBAT-VDO VDO Brightness Dark Very Bright Bright Dark 9/19 FEDL9078-002-01 ML9078-002 ● ML9078-002 operation in regulator mode VDOBAT VDO output VDOREG(L2) VDOREG(H2) VDOREG(L1) VDOREG(H1) VDOBAT VBAT<VSC VSC<VDOREG(L2) VSC<VDOREG(H2) VBAT>VSC VDOREG Conditions VBAT>VSC VBAT<VSC VSC>VDOREG(L2) VSC>VDOREG(H2) VBAT VSC VDO VSC ΔVDOREG(L2)-VDO ΔVDOREG(H2)-VDO ΔVSC-VDO VBAT ΔVBAT-VDO ΔVBAT-VDO VDO Brightness Dark Very Bright Bright Dark 10/19 FEDL9078-002-01 ML9078-002 Direct-current characteristic (DI_MONI) Item (VBAT=1.1V to 3.6V, VSC=0.0V to 4V, VSS=0V, and Top=-20 to +70 °C, unless otherwise specified) Standard value Measuring Conditions Unit Circuit Min. Typ. Max. Sign IOH1=-0.5mA VDO=1.8V ~ 4.0V IOH1=-0.1mA VDO=1.3V ~ 4.0V IOH1=-0.03mA VDO= 1.1V ~ 4.0V IOL1=+0.5mA VDO=1.8V ~ 3.6V IOL1=+0.1mA VDO=1.3V ~ 3.6V IOL1=+0.03mA VDO=1.1V ~ 3.6V VOH1 Output voltage 1 (DI_MONI) VOL1 VSC 0.7 VSC 0.5 VSC 0.5 - - - - - - - - 0.7 - - 0.7 - - 0.5 V 5 V 6 . Alternating-current characteristic (DI_MONI) Item Sign DI_MONI Detection voltage VDM (VBAT=1.1V to 3.6V, VSC=0.0V to 4V, VSS=0V, and Top=-20 to +70 °C, unless otherwise specified) Standard value Measuring Conditions Unit Circuit Min. Typ. Max. VBAT -0.1 Top = 25 °C VBAT VBAT +0.1 V 5 Operation of DI_MONI Dark Bright Dark VBAT VDM VSC DI_MONI 11/19 FEDL9078-002-01 ML9078-002 Measuring circuit ● Measuring circuit 1 For Logic set A SCLV A SCREG DI_MONI VDO VSC VBAT VSS A ● V Measuring circuit 2 For Logic set SCLV DI_MONI SCREG VDO ● VSC VBAT A A VSS V Measuring circuit 3 For Logic set SCLV DI_MONI SCREG VDO VSC VBAT A A VSS A 12/19 FEDL9078-002-01 ML9078-002 ● Measuring circuit 4 For Logic set SCLV DI_MONI SCREG VDO ● VSC VBAT A A VSS V Measuring circuit 5 For Logic set SCLV DI_MONI SCREG VDO ● VSC VBAT A A VSS V Measuring circuit 6 For Logic set SCLV DI_MONI SCREG VDO VSC VBAT A A VSS V 13/19 FEDL9078-002-01 ML9078-002 Appllilcation circuit ● Simple application - SCLV=L, SCREG=L SCLV DI_MONI SCREG MCU VDO c-Si Solar cell(*1) x 3 (1.2 to 1.5V) to x 8 (3.2 to 4.0V) VSC VBAT VDD VSS VSS + a-Si Solar cell(*2) x 2 (1V to 1.4) to x 6 (3V to 4V) ● Primary battery 1.6V to 3.2V - When DI_MONI is used (1.5V battery) - SCLV=L, SCREG=L SCLV DI_MONI SCREG MCU VDO c-Si Solar cell(*1) x 3 (1.2 to 1.5V) to x 4 (1.6 to 2.0V) VSC VSS VBAT VDD VSS + a-Si Solar cell(*2) x 2 (1V to 1.4) to x 4 (2V to 2.8V) - Primary battery 1.6V 14/19 FEDL9078-002-01 ML9078-002 ● When DI_MONI is used (3V battery) - SCLV=L, SCREG=L SCLV DI_MONI SCREG MCU VDO VDD (*1) c-Si Solar cell x 6 (2.4 to 3V) to x 8 (3.2 to 4.0V) VSC VBAT VSS VSS + a-Si Solar cell(*2) x 5 (2.5V to 3.5V) to x 6 (3V to 4V) ● Primary battery 3.2V - When a regulator is used (regulator voltage will be at 1.65 V) - SCLV=L, SCREG=H - When using a regulator by SCLV=L, please insert the external capacitance Cdo = 0.01uF to 0.1uF between VDO and VSS for regulator output voltage stabilization. Operation under 2.5V SCLV DI_MONI SCREG MCU VDO c-Si Solar cell(*1) x 6 (2.4 to 3V) VSC VBAT VSS VDD VSS + a-Si Solar cell(*2) x 2 (1V to 1.4) to x 4 (2V to 2.8V) - Primary battery 1.6V 0.01uF to 0.1uF 15/19 FEDL9078-002-01 ML9078-002 ● When a regulator is used (regulator voltage will be at 3.3 V - SCLV=H, SCREG=H - When using a regulator by SCLV=H, please insert the external capacitance Cdo = 0.1uF to 1uF between VDO and VSS for regulator output voltage stbirization. Operation under 4.2V SCLV DI_MONI SCREG MCU VDO c-Si Solar cell(*1) x 8 (3.2 to 4.0V) VSC VBAT VDD VSS VSS + a-Si Solar cell(*2) x 5 (2.5V to 3.5) to x 6 (3V to 4V) *1 *2 : : - Primary battery 3.2V 0.1uF to 1uF c-Si Solar cell is a Crystal Si type solar cell. (The single crystal Si, the many crystals Si) a-Si Solar cell is an amorphous Si type solar cell. (Amorphous silicon) 16/19 FEDL9078-002-01 ML9078-002 Package dimensions (Unit: mm) P-WQFN12-0303-0.50-63 Package material Lead frame material Lead finish Solder thickness Package weight (g) Rev. No./Last Revised Epoxy resin Cu alloy Ni/Pd/Au Au/Pd Max0.01/Max0.15 0.01980typ. 3 / Oct. 07,2010 Attention on surface mount type package mounting A surface mount type package is a package which is very much easy to receive influence in the heat at the time of reflow mounting, the amount of moisture absorption of the package at the time of storage, etc. Therefore, when inquired by implementation of reflow mounting, please be sure to ask the product name, a package name, the number of pins, a package code and the mounting conditions (the reflow method, temperature, number of times) for which it wishes, storage conditions, etc. to the business assigned to our company. 17/19 FEDL9078-002-01 ML9078-002 Revision history Page Document No. FEDL9078-002-01 Date of issue Before revision After revision Jan.30,2012 - - The contents of change First edition issue 18/19 FEDL9078-002-01 ML9078-002 NOTES No copying or reproduction of this document, in part or in whole, is permitted without the consent of LAPIS Semiconductor Co., Ltd. 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