Cypress CY62126DV30LL-45BVI 1-mbit (64k x 16) static ram Datasheet

CY62126DV30
MoBL
1-Mbit (64K x 16) Static RAM
Features
also has an automatic power-down feature that significantly
reduces power consumption by 90% when addresses are not
toggling. The device can be put into standby mode reducing
power consumption by more than 99% when deselected (CE
HIGH). The input/output pins (I/O0 through I/O15) are placed
in a high-impedance state when: deselected (CE HIGH),
outputs are disabled (OE HIGH), both Byte High Enable and
Byte Low Enable are disabled (BHE, BLE HIGH) or during a
write operation (CE LOW and WE LOW).
• Very high speed: 45 ns
• Wide voltage range: 2.2V to 3.6V
• Pin compatible with CY62126BV
• Ultra-low active power
— Typical active current: 0.85 mA @ f = 1 MHz
— Typical active current: 5 mA @ f = fMAX
• Ultra-low standby power
• Easy memory expansion with CE and OE features
• Automatic power-down when deselected
• Packages offered in a 48-ball FBGA and a 44-lead TSOP
Type II
• Also available in Lead-free packages
Functional Description[1]
The CY62126DV30 is a high-performance CMOS static RAM
organized as 64K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL®) in
portable applications such as cellular telephones. The device
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A15). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A15).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
Logic Block Diagram
64K x 16
RAM Array
2048 x 512
SENSE AMPS
ROW DECODER
DATA IN DRIVERS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
I/O0–I/O7
I/O8–I/O15
BHE
WE
CE
OE
BLE
A14
A15
A12
A13
A11
COLUMN DECODER
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05230 Rev. *E
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised February 2, 2005
CY62126DV30
MoBL
Pin Configurations[2, 3]
FBGA (Top View)
4
5
3
6
A1
A2
NC
A
A3
A4
CE
I/O0
B
I/O10
A5
A6
I/O1
I/O2
C
VSS
I/O11
NC
A7
I/O3
VCC
D
VCC
I/O12 DNU
NC
I/O4
VSS
E
I/O14
I/O13
A14
A15
I/O5
I/O6
F
I/O15
NC
A12
A13
WE
I/O7
G
NC
A8
A9
A10
A11
1
2
BLE
OE
A0
I/O8
BHE
I/O9
TSOP II (Forward)
Top View
NC
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A15
A14
A13
A12
NC
H
1
44
2
3
43
42
4
41
40
39
38
5
6
7
8
9
10
11
12
37
36
35
34
33
32
31
30
29
28
27
13
14
15
16
17
18
19
20
21
22
26
25
24
23
A5
A6
A7
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
Product Portfolio
Power Dissipation
Operating, ICC (mA)
VCC Range (V)
f = 1 MHz
f = fMAX
Standby, ISB2 (µA)
Product
Min.
Typ.
Max.
Speed (ns)
Typ.[4]
Max.
Typ.[4]
Max.
Typ.[4]
Max.
CY62126DV30L
2.2
3.0
3.6
45
0.85
1.5
6.5
13
1.5
5
45
0.85
1.5
6.5
13
1.5
4
55
0.85
1.5
5
10
1.5
5
55
0.85
1.5
5
10
1.5
4
70
0.85
1.5
5
10
1.5
5
70
0.85
1.5
5
10
1.5
4
CY62126DV30LL
CY62126DV30L
2.2
3.0
3.6
CY62126DV30LL
CY62126DV30L
2.2
CY62126DV30LL
3.0
3.6
Notes:
2. NC pins are not connected to the die.
3. E3 (DNU) can be left as NC or VSS to ensure proper operation. (Expansion Pins on FBGA Package: E4 - 2M, D3 - 4M, H1 - 8M, G2 - 16M, H6 - 32M).
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C.
Document #: 38-05230 Rev. *E
Page 2 of 11
CY62126DV30
MoBL
DC Input Voltage[5] ................................ −0.3V to VCC + 0.3V
Maximum Ratings
Output Current into Outputs (LOW)............................. 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ................................. –65°C to +150°C
Latch-up Current .................................................... > 200 mA
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Operating Range
Supply Voltage to Ground
Potential ........................................................... −0.3V to 3.9V
DC Voltage Applied to Outputs
in High-Z State[5.] ...................................−0.3V to VCC + 0.3V
Range
Ambient Temperature (TA)
VCC[6.]
Industrial
−40°C to +85°C
2.2V to 3.6V
DC Electrical Characteristics (Over the Operating Range)
CY62126DV30-45
Parameter Description
Test Conditions
Min.
VOH
Output HIGH 2.2 < VCC < 2.7 IOH = −0.1 mA 2.0
Voltage
2.7 < VCC < 3.6 IOH = −1.0 mA 2.4
VOL
Output LOW 2.2 < VCC < 2.7 IOL = 0.1 mA
Voltage
2.7 < VCC < 3.6 IOL = 2.1 mA
VIH
VIL
Input HIGH
Voltage
Input LOW
Voltage
Typ.[4]
CY62126DV30-55 CY62126DV30-70
Max. Min. Typ.[4] Max. Min Typ.[4] Max. Unit
2.0
2.0
2.4
V
2.4
0.4
0.4
0.4
0.4
0.4
0.4
2.2 < VCC < 2.7
1.8
VCC
+ 0.3
1.8
VCC 1.8
+ 0.3
VCC
+ 0.3
2.7 < VCC < 3.6
2.2
VCC
+ 0.3
2.2
VCC 2.2
+ 0.3
VCC
+ 0.3
2.2 < VCC < 2.7
−0.3
0.6
−0.3
0.6
−0.
3
0.6
2.7 < VCC < 3.6
−0.3
0.8
−0.3
0.8
−0.
3
0.8
V
V
V
IIX
Input
Leakage
Current
GND < VI < VCC
−1
+1
−1
+1
−1
+1
µA
IOZ
Output
Leakage
Current
GND < VO < VCC, Output
Disabled
−1
+1
−1
+1
−1
+1
µA
ICC
VCC
Operating
Supply
Current
f = fMAX = 1/tRC
mA
Automatic
CE
Power-down
Current −
CMOS Inputs
Automatic
CE
Power-down
Current−
CMOS Inputs
ISB1
ISB2
6.5
13
5
10
5
10
0.85
1.5
0.85
1.5
0.85
1.5
CE > VCC − 0.2V,
L
VIN > VCC − 0.2V, VIN < 0.2V,
LL
f = fMAX (Address and Data
Only),
f = 0 (OE, WE, BHE and BLE)
1.5
5
1.5
5
1.5
5
1.5
4
1.5
4
1.5
4
CE > VCC − 0.2V,
VIN > VCC − 0.2V or
VIN < 0.2V,
f = 0, VCC = 3.6V
L
1.5
5
1.5
5
1.5
5
LL
1.5
4
1.5
4
1.5
4
f = 1 MHz
VCC = 3.6V,
IOUT = 0 mA,
CMOS level
µA
µA
Notes:
5. VIL(min.) = −2.0V for pulse durations less than 20 ns., VIH(max.) = VCC + 0.75V for pulse durations less than 20 ns.
6. Full device operation requires linear ramp of VCC from 0V to VCC(min) & VCC must be stable at VCC(min) for 500 µs.
Document #: 38-05230 Rev. *E
Page 3 of 11
CY62126DV30
MoBL
Capacitance[7]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz
VCC = VCC(typ)
Max.
Unit
8
pF
8
pF
Thermal Resistance
Parameter
Description
Test Conditions
θJA
Thermal Resistance (Junction to Ambient)[7]
θJC
Thermal Resistance (Junction to Case)[7]
Still Air, soldered on a 3 x 4.5 inch,
two-layer printed circuit board
TSOP
FBGA
Unit
55
76
°C/W
12
11
°C/W
AC Test Loads and Waveforms[8]
R1
VCC
ALL INPUT PULSES
VCC Typ
OUTPUT
R2
50 pF
GND
Rise TIme: 1 V/ns
90%
10%
90%
10%
Fall Time: 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉVENIN EQUIVALENT
RTH
OUTPUT
Parameters
2.5V
R1
R2
RTH
VTH
VTH
3.0V
Unit
16600
1103
Ohms
15400
1554
Ohms
8000
645
Ohms
1.2
1.75
Volts
Data Retention Characteristics
Parameter
Description
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR
tR[9]
[7]
Conditions
Min.
Typ.[4]
Max.
1.5
VCC=1.5V, CE > VCC − 0.2V,
VIN > VCC − 0.2V or VIN < 0.2V
Chip Deselect to Data
Retention Time
Operation Recovery Time
Unit
V
L
4
LL
3
µA
0
ns
100
µs
Notes:
7. Tested initially and after any design or proces changes that may affect these parameters.
8. Test condition for the 45 ns part is a load capacitance of 30 pF
9. Full device operation requires linear VCC ramp from VDR to VCC(min.) >100 µs.
Document #: 38-05230 Rev. *E
Page 4 of 11
CY62126DV30
MoBL
Data Retention Waveform
VCC(min)
VCC
DATA RETENTION MODE
VCC(min)
VDR > 1.5 V
tR
tCDR
CE
Switching Characteristics (Over the Operating Range)[10]
CY62126DV30-45[8]
Parameter
Description
Min.
Max.
CY62126DV30-55
Min.
Max.
CY62126DV30-70
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
OE LOW to Low Z[11]
tHZOE
tLZCE
OE HIGH to High
CE LOW to Low
45
55
45
10
10
45
Z[11]
10
Z[11, 12]
10
25
5
15
10
70
ns
35
ns
ns
25
10
ns
ns
tHZCE
CE HIGH to High
tPU
CE LOW to Power-up
tPD
CE HIGH to Power-down
45
55
70
ns
tDBE
BLE/BHE LOW to Data Valid
25
25
35
ns
0
Z[11]
tLZBE
BLE/BHE LOW to Low
tHZBE
BLE/BHE HIGH to High-Z[11, 12]
Write
20
ns
ns
5
20
20
ns
70
55
25
5
Z[11, 12]
70
55
0
5
5
15
25
0
ns
5
20
ns
ns
25
ns
Cycle[13]
tWC
Write Cycle Time
45
55
70
ns
tSCE
CE LOW to Write End
40
40
60
ns
tAW
Address Set-up to Write End
40
40
60
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-up to Write Start
0
0
0
ns
tPWE
WE Pulse Width
35
40
50
ns
tBW
BLE/BHE LOW to Write End
40
40
60
ns
tSD
Data Set-up to Write End
25
25
30
ns
tHD
Data Hold from Write End
0
0
0
ns
[11, 12]
tHZWE
WE LOW to High Z
tLZWE
WE HIGH to Low Z[11]
15
10
20
10
25
5
ns
ns
Notes:
10. Test conditions assume signal transition time of 1V/ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the
specified IOL.
11. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE.
12. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
13. The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write.
Document #: 38-05230 Rev. *E
Page 5 of 11
CY62126DV30
MoBL
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[14, 15]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[15, 16]
ADDRESS
tRC
CE
tPD
tHZCE
tACE
OE
BHE/BLE
ttLZOE
LZOE
tHZOE
tDOE
tHZBE
tDBE
tLZBE
DATA OUT
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
tPU
50%
50%
ICC
ISB
Notes:
14. Device is continuously selected. OE, CE = VIL, BHE, BLE = VIL.
15. WE is HIGH for Read cycle.
16. Address valid prior to or coincident with CE, BHE, BLE transition LOW.
Document #: 38-05230 Rev. *E
Page 6 of 11
CY62126DV30
MoBL
Switching Waveforms(continued)
Write Cycle No. 1 (WE Controlled[12, 13, 16, 17, 18]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
WE
tPWE
tBW
BHE/BLE
OE
tSD
DATA I/O
NOTE 19
tHD
DATAIN VALID
tHZOE
Write Cycle No. 2 (CE Controlled)[12, 13, 16, 17, 18]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA I/O
tHD
DATAIN VALID
NOTE 19
tHZOE
Notes:
17. Data I/O is high-impedance if OE = VIH.
18. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
19. During the DON'T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
Document #: 38-05230 Rev. *E
Page 7 of 11
CY62126DV30
MoBL
Switching Waveforms(continued)
Write Cycle No. 3 (WE Controlled, OE LOW)[17, 18]
tWC
ADDRESS
tSCE
CE
tBW
BHE/BLE
tAW
tHA
tSA
tPWE
WE
tSD
DATAI/O
NOTE 19
tHD
DATAIN VALID
tLZWE
tHZWE
Write Cycle No. 4 (BHE-/BLE-controlled, OE LOW)[17, 18]
tWC
ADDRESS
CE
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tSD
DATA I/O
NOTE 19
Document #: 38-05230 Rev. *E
tHD
DATAIN VALID
Page 8 of 11
CY62126DV30
MoBL
Truth Table
CE
WE
OE
BHE
BLE
Inputs/Outputs
Mode
Power
H
X
X
X
X
High Z
Deselect/Power-Down
Standby (ISB)
L
X
X
H
H
High Z
Output Disabled
Active (ICC)
L
H
L
L
L
Data Out (I/OO–I/O15)
Read
Active (ICC)
L
H
L
H
L
Data Out (I/OO–I/O7);
I/O8–I/O15 in High Z
Read
Active (ICC)
L
H
L
L
H
Data Out (I/O8–I/O15);
I/O0–I/O7 in High Z
Read
Active (ICC)
L
H
H
L
L
High Z
Output Disabled
Active (ICC)
L
H
H
H
L
High Z
Output Disabled
Active (ICC)
L
H
H
L
H
High Z
Output Disabled
Active (ICC)
L
L
X
L
L
Data In (I/OO–I/O15)
Write
Active (ICC)
L
L
X
H
L
Data In (I/OO–I/O7);
I/O8–I/O15 in High Z
Write
Active (ICC)
L
L
X
L
H
Data In (I/O8–I/O15);
I/O0–I/O7 in High Z
Write
Active (ICC)
Ordering Information
Speed
(ns)
45
Ordering Code
CY62126DV30LL-45BVI
Package
Name
BV48A
CY62126DV30LL-45BVXI
CY62126DV30LL-45ZSXI
55
48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
ZS44
BV48A
48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
CY62126DV30LL-55BVI
BV48A
48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
CY62126DV30L-55ZSI
ZS44
44-Lead TSOP Type II
CY62126DV30LL-55ZSI
ZS44
44-Lead TSOP Type II
Industrial
44-Lead TSOP Type II (Pb-Free)
CY62126DV30L-70BVI
BV48A
48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
CY62126DV30LL-70BVI
BV48A
48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
CY62126DV30L-70ZSI
ZS44
44-Lead TSOP Type II
CY62126DV30LL-70ZSI
ZS44
44-Lead TSOP Type II
Document #: 38-05230 Rev. *E
Industrial
44-Lead TSOP Type II (Pb-free)
CY62126DV30L-55BVI
CY62126DV30LL-70ZSXI
Operating
Range
48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) (Pb-free)
CY62126DV30LL-55ZSXI
70
Package Type
Industrial
44-Lead TSOP Type II (Pb-Free)
Page 9 of 11
CY62126DV30
MoBL
Package Diagrams
48-Lead VFBGA (6 x 8 x 1 mm) BV48A
51-85150-*B
44-pin TSOP II ZS44
51-85087-*A
MoBL is a registered trademark, and MoBL2 and More Battery Life are trademarks of Cypress Semiconductor. All product and
company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05230 Rev. *E
Page 10 of 11
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY62126DV30
MoBL
Document History Page
Document Title: CY62126DV30 MoBL 1- Mbit (64K x 16) Static RAM
Document Number: 38-05230
REV.
ECN NO. Issue Date
Orig. of
Change
Description of Change
**
117689
08/27/02
JUI
*A
127313
06/13/03
MPR
New Data Sheet
Changed From Advanced Status to Preliminary.
Changed ISB2 to 5 µA (L), 4 µA (LL)
Changed ICCDR to 4 µA (L), 3 µA (LL)
Changed CIN from 6 pF to 8 pF
*B
128340
07/22/03
JUI
Changed from Preliminary to Final
Add 70-ns speed, updated ordering information
*C
129002
08/29/03
CDY
Changed ICC 1 MHz typ from 0.5 mA to 0.85 mA
*D
238050
See ECN
AJU
Fixed typo: Changed tDBE from 70 ns to 35 ns
*E
316039
See ECN
PCI
Added 45-ns Speed Bin in AC, DC and Ordering Information tables
Added Footnote #8 on page #4
Added Pb-Free package ordering information on page # 9
Changed 44-pin TSOP-II package name from Z44 to ZS44
Document #: 38-05230 Rev. *E
Page 11 of 11
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