IR3 829 16A Highly Integrated Single-Input Synchronous SupIRBuck® Regulator Dat as heet Rev 3.7, 03/24/2016 Pow er M anag em ent & M ul ti m ar k et IR3829 Product Overview 1 Product Overview Features Description • Single 5V to 21V application • Wide Input Voltage Range from 1.0V to 21V with external Vcc • Output Voltage Range: 0.6V to 0.86×Vin • Enhanced Line/Load Regulation with Feed-Forward • Programmable Switching Frequency up to 1.2MHz • Internal Digital Soft-Start • Three selectable current limits • Enable input with Voltage Monitoring Capability • Thermally Compensated Internal Over-Current Protection with Three selectable settings The IR3829 SupIRBuck® is an easy-to-use, fully integrated and highly efficient DC/DC regulator. The onboard PWM controller and MOSFETs make IR3829 a space-efficient solution, providing accurate power delivery. IR3829 is a versatile regulator, operating with wide input and output voltage range, which offers programmable switching frequency from 300kHz to 1.2MHz, and three selectable current limits. • Enhanced Pre-Bias Start-Up • Precision Reference Voltage (0.6V+/-0.6%) • Integrated MOSFET drivers and Bootstrap Diode It features important protection functions, such as Pre-Bias startup, thermally compensated current limit, over voltage protection and thermal shutdown to give required system level security in the event of fault conditions. • Thermal Shut Down Applications • Programmable Power Good Output • Server Applications • Monotonic Start-Up • Netcom Applications • Operating temp: -40oC < Tj < 125oC • Storage Applications • Small Size: PQFN 5 mm x 6 mm • Telecom Applications • Lead-free, Halogen-free and RoHS Compliant • Distributed Point of Load Power Architectures Table 1-1 Enterprise Controller Offerings Part Number IR3829 Package Type PQFN 5 mm x 6 mm Standard Pack Part Number Form Quantity Tape and Reel 4000 IR3829MTRPBF Figure 1-1 IR3829 Part Number Configuration Code Datasheet 2 Rev 3.7 03/24/2016 IR3829 Basic Application 2 Figure 2-1 Basic Application IR3829 Basic Application Circuit IR3829, Vin = 12V, Vo= 1.0V, fsw = 600kHz L = FP1107R1-R40-R, No airflow 90 Efficiency (%) 88 86 84 82 80 78 76 74 2 Figure 2-2 Datasheet 4 6 8 10 Iout (A) 12 14 16 IR3829 Efficiency 3 Rev 3.7 03/24/2016 IR3829 Block Diagram 3 Figure 3-1 Datasheet Block Diagram Simplified block diagram 4 Rev 3.7 03/24/2016 IR3829 Pinout Diagram and Pin Description 4 Pinout Diagram and Pin Description Figure 4-1 Table 4-1 Pinout Diagram: PQFN 5 mm x 6 mm (Top View) Pin Description Pin No. Name Pin Type Function 1 Fb I Inverting input to the error amplifier. This pin is connected directly to the output of the regulator via resistor divider to set the output voltage and provide feedback to the error amplifier. 2 NC - Do Not Connect. Must be left floating. 3 Comp O Output of error amplifier. An external resistor and capacitor network is typically connected from this pin to Fb to provide loop compensation. 4 Gnd S Signal ground for internal reference and control circuitry. 5 Rt I Set switching frequency. Use an external resistor from this pin to Gnd to set the free-running switching frequency. 6 ILIM I Current Limit set point. This pin allows the trip point to be set to one of three possible settings by either floating this pin, connecting it to VCC or connecting it to PGnd. 7 PGood O Power Good status output pin is open drain. Connect a pull up resistor from this pin to the voltage lower than or equal to the Vcc. 8 Vsns I Sense pin for over-voltage protection and PGood. Datasheet 5 Rev 3.7 03/24/2016 IR3829 Pinout Diagram and Pin Description Table 4-1 Pin Description Pin No. Name Pin Type 9 Vin S Input voltage for Internal LDO. A 1.0µF capacitor should be connected between this pin and PGnd. If external supply is connected to Vcc/LDO_out pin, this pin should be shorted to Vcc/LDO_out pin. 10 Vcc/LDO_Out I/O Input Bias for external Vcc Voltage/ output of internal LDO. Place a minimum 2.2µF cap from this pin to PGnd 11 PGnd S Power Ground. This pin serves as a separated ground for the MOSFET drivers and should be connected to the system's power ground plane. 12 SW O Switch node. This pin is connected to the output inductor. 13 PVin S Input voltage for power stage. 14 Boot I Supply voltage for high side driver, a 100nF capacitor should be connected between this pin and SW pin. 15 Enable I Enable pin to turn on and off the device, if this pin is connected to PVin pin through a resistor divider, input voltage UVLO can be implemented. 16 NC - Do Not Connect. Must be left floating. 17 GND S Signal ground for internal reference and control circuitry. Datasheet Function 6 Rev 3.7 03/24/2016 IR3829 Specifications 5 Specifications 5.1 Absolute Maximum Ratings Stresses beyond those listed in Table 5-1 may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. Table 5-1 Absolute Maximum Ratings Parameter Min Max Units PVin, Vin -0.3 25 V Vcc / LDO_Out -0.3 8.0 V Boot -0.3 33 V SW -0.3 25 V (DC) -4.0 25 V (AC, 100ns) Boot to SW -0.3 VCC + 0.3 V Note 2 ILIM, PGood -0.3 VCC + 0.3 V Note 2 Other Input/Output Pins -0.3 3.9 V PGnd to Gnd -0.3 0.3 Junction Temperature Range Storage Temperature Range -40 -55 Conditions Note 1 V 150 o 150 o C Note 1 C Note 1: Vcc must not exceed 7.5V for Junction Temperature between -10°C and -40°C Note 2: Must not exceed 8V Table 5-2 Thermal Information Parameter Junction-to-ambient thermal resistance θJA Junction to PCB thermal resistance θJ - PCB Value / Units o 30 C/W Condition Note 3 o 2 C/W Note 3: θJA is measured with components mounted on a high effective thermal conductivity test board in free air. Datasheet 7 Rev 3.7 03/24/2016 IR3829 Specifications 5.2 Recommended Operating Conditions Table 5-3 Recommended Operating Conditions Symbol Parameter Min Max Units Condition PVin Power Stage Input Voltage Range 1 21 V Note 4 Vin Input Voltage Range 5 21 V Note 5 Vcc Supply Voltage Range 4.5 7.5 V Note 6 Boot to SW Boot to Switch Node Voltage Range 4.5 7.5 V VO Output Voltage Range 0.6 0.86xVin V IO Output Current Range 0 16 A FS Switching Frequency 0.3 1.2 MHz TJ Operating Junction Temperature -40 125 o C Note 4: Maximum SW node voltage should not exceed 25V. Note 5: For internally biased single rail operation. When Vin drops below 7.5V, the internal LDO enters dropout mode. Please refer to LDO section and Over Current Protection for detailed application information. Note 6: Vcc/LDO_out can be connected to an external regulated supply. If so, the Vin input should be connected to Vcc/LDO_out pin. 5.3 Electrical Characteristics Unless otherwise specified, these specifications apply over, 7.5V < Vin = PVin < 21V, 0°C < TJ < 125°C. Typical values are specified at Ta = 25°C. Table 5-4 Electrical Characteristics Symbol Parameter Test Conditions Min Typ Max Units Power Stage PLOSS Power Losses Vin = 12V, VO = 1.0V, IO = 16A, Fs = 600kHz, L = 0.4uH,Vcc = 6.9V (internal LDO), Note 7 - 3.3 - W Rds(on)_Top Top Switch VBoot - Vsw= 6.9V, IO = 16A, Tj =25°C - 8.4 10.5 mΩ Rds(on)_Bot Bottom Switch Vcc = 6.9V, IO = 16A Tj =25°C - 3.8 4.9 mΩ Bootstrap Diode Forward Voltage I(Boot) = 15mA 200 300 500 mV SW Leakage Current SW = 0V, Enable = 0V - - 1 μA SW = 0V, Enable = high, No Switching - - 1 Note 7 - 20 - ns ISW Tdb Dead Band Time Supply Current Iin(Standby) Vin Supply Current (standby) EN = Low, No Switching - 100 150 μA Iin(Dyn) Vin Supply Current (dynamic) - 20 25 mA Datasheet EN = High, Fs = 600kHz, Vin = PVin = 21V 8 Rev 3.7 03/24/2016 IR3829 Specifications Table 5-4 Electrical Characteristics Symbol Parameter Test Conditions Min Typ Max Units 6.5 6.9 7.2 V - - 0.88 V - 1.0 - V Rt = 80.6K 270 300 330 Rt = 39.2K 540 600 660 - - - - Vin = 7.5V, Vin slew rate max = 1V/µs, Note 7 - 1.125 - Vin = 12V, Vin slew rate max = 1V/µs, Note 7 - 1.80 - Vin = 21V, Vin slew rate max = 1V/µs, Note 7 - 3.15 - Vcc = Vin = 5V, For external Vcc operation, Note 7 - 0.75 - VCC LDO Output VCC Output Voltage Vin(min) = 7.5V, Icc = 0-50mA, Cload = 2.2uF VCC_drop VCC Dropout Icc=50mA,Cload=2.2uF Oscillator VRt Rt Voltage FS Frequency Range Vramp Ramp Amplitude kHz Vp-p Ramp(OS) Ramp Offset Note 7 - 0.16 - V Tmin(ctrl) Minimum Pulse Width Note 7 - - 60 ns Dmax Maximum Duty Cycle Fs = 300kHz, PVin = Vin = 12V 86 - - % Toff Minimum Off Time Note 7 - 200 250 ns -1 - 1 μA Error Amplifier Ifb (E/A) Input Bias Current GBWP Gain-Bandwidth Product Note 7 20 30 40 MHz Gain DC Gain Note 7 100 110 120 dB Vmax (E/A) Maximum Output Voltage 1.7 2.0 2.3 V Vmin (E/A) Minimum Output Voltage - - 100 mV - 0.6 - V 25°C < Tj < 85°C -0.6 - 0.6 % -40°C < Tj < 125°C, Note 8 -1.2 - 1.2 % 0.16 0.2 0.24 mV/µs Vsns Rising 85 90 95 % Vref VPG (lower) Pgood Lower Turn off Threshold Vsns Falling 80 85 90 % Vref VPG (on)_Dly Vsns Rising, see VPG(on) - 2.5 - ms Reference Voltage (VREF) Vfb Feedback Voltage Accuracy Soft Start Ramp S-Start Soft Start Ramp Rate Power Good VPG(on) Datasheet Pgood Turn on Threshold Pgood Turn on Delay 9 Rev 3.7 03/24/2016 IR3829 Specifications Table 5-4 Symbol Electrical Characteristics Parameter Test Conditions Min Typ Max Units 115 120 125 % Vref VPG (Upper) Pgood Upper Turn off Threshold Vsns Rising VPG (comp)_Dly Vsns < VPG(lower) or Vsns > VPG(upper) 1 2 3.5 μs Ipgood = -5mA - - 0.5 V Pgood Comparator Delay PG (voltage) Pgood Voltage Low Under Voltage Lockout Vcc_UVLO_ Start Vcc-Start Threshold Vcc Rising Trip Level 3.9 4.1 4.3 V Vcc_UVLO_ Stop Vcc-Stop Threshold Vcc Falling Trip Level 3.6 3.8 4.0 V Enable_UVL Enable-Start-Threshold O_Start Supply ramping up 1.14 1.2 1.26 V Enable_UVL Enable-Stop-Threshold O_Stop Supply ramping down 0.95 1 1.05 V - - 1 μA 115 120 125 % Vref 1 2 3.5 μs 22.5 26 30.4 ILIM = f loating, VCC = 6.9V, Tj = 25°C 17.8 21.5 25.2 ILIM = PGnd, VCC = 6.9V, Tj = 25°C 13.9 16.8 19.7 - 20.48 - ms Ien Enable Leakage Current Enable = 3.3V Over Voltage Protection OVP_Vth OVP Trip Threshold OVP_Tdly OVP Comparator Delay Vsns Rising Over Current Protection ILIMIT Tblk_Hiccup Current Limit ILIM = VCC, VCC = 6.9V, Tj = 25°C Hiccup Blanking Time A Over Temperature Protection Ttsd Thermal Shutdown Threshold Note 7 - 145 - o Ttsd_hys Hysteresis Note 7 - 20 - o C C Note 7: Ensured by design but not tested in production. Note 8: Hot and Cold temperature performance is assured via correlation using statistical quality control. Not tested in production. Datasheet 10 Rev 3.7 03/24/2016 IR3829 Specifications 5.4 Typical Efficiency and Power Loss Curves PVin = Vin = 12V, VCC = Internal LDO, IO = 0A - 16A, Room Temperature, No Air Flow. Note that the efficiency and power loss curves include the losses of IR3829, the inductor losses and the losses of the input and output capacitors. The table shows the inductors used for each of the output voltages in the efficiency measurement. Table 5-5 Inductor List for IR3829 Efficiency Measurement: PVin = Vin = 12V VOUT (V) FS (kHz) LOUT (µH) P/N DCR (mΩ) Size (mm) 1.0 600 0.4 FP1107R1-R40-R (Coiltronics) 0.29 11.0 x 7.2 x 7.5 1.2 600 0.4 FP1107R1-R40-R (Coiltronics) 0.29 11.0 x 7.2 x 7.5 1.8 600 0.47 7443330047(Wurth Elektronik) 1.6 10.9 x 10.0 x 9.3 3.3 600 0.88 MPC1040LR88C(NEC/Tokin) 2.3 11.5 x 10.0 x 4.0 5 600 1.0 7443330100(Wurth Elektronik) 2.15 10.9 x 10.0 x 9.3 IR3829, Efficiency, PVin = Vin = 12V, fsw = 600kHz 98 Efficiency (%) 94 90 1V 1.2V 86 1.8V 82 3.3V 5V 78 74 1.6 Figure 5-1 3.2 4.8 6.4 8 9.6 Iout (A) 11.2 12.8 14.4 16 IR3829 Efficiency Curves - PVin = Vin = 12V, VCC = Internal LDO IR3829, Power Losses, Pvin=Vin=12V, fsw=600kHz 6 Power Loss (W) 5 1V 4 1.2V 3 1.8V 3.3V 2 5V 1 0 0 Figure 5-2 Datasheet 2 4 6 8 10 Iout (A) 12 14 16 IR3829 Power Loss Curves- PVin = Vin = 12V, VCC = Internal LDO 11 Rev 3.7 03/24/2016 IR3829 Specifications PVin = Vin = VCC = 5V, IO = 0A-16A, Room Temperature, No Air Flow. Note that the efficiency and power loss curves include the losses of IR3829, the inductor losses and the losses of the input and output capacitors. The table shows the inductors used for each of the output voltages in the efficiency measurement. Table 5-6 Inductor List for IR3829 Efficiency Measurement: PVin = Vin = VCC = 5V VOUT (V) FS (kHz) LOUT (µH) P/N DCR (mΩ) Size (mm) 1.0 600 0.3 FP1107R1-R30-R (Coiltronics) 0.29 11.0 x 7.2 x 7.5 1.2 600 0.3 FP1107R1-R30-R (Coiltronics) 0.29 11.0 x 7.2 x 7.5 1.8 600 0.4 FP1107R1-R40-R (Coiltronics) 0.29 11.0 x 7.2 x 7.5 IR3829, Efficiency, PVin = Vin = Vcc = 5V, fsw = 600kHz 98 Efficiency (%) 94 1V 90 1.2V 1.8V 86 82 78 1.6 3.2 4.8 6.4 8 9.6 11.2 12.8 14.4 16 Iout (A) Figure 5-3 IR3829: Efficiency Curves - PVin = Vin = VCC = 5V Power Loss (W) IR3829, Power Losses, Pvin=Vin=Vcc = 5V, fsw=600kHz 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 1V 1.2V 1.8V 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Iout (A) Figure 5-4 Datasheet IR3829: Power Loss Curves- PVin = Vin = VCC = 5V 12 Rev 3.7 03/24/2016 IR3829 Specifications 5.5 RDS(ON) of MOSFETs over Temperature (mΩ) RDS(on) with Vcc=6.9V 13 12 11 10 9 8 7 6 5 4 3 2 -40 -20 0 20 40 60 80 Temperature (°C) Control FET Figure 5-5 100 120 140 Sync FET RDS(ON) with VCC = 6.9V Over Temperature RDS(on) with Vcc=5V (mΩ) 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 -40 -20 0 20 40 60 80 Temperature (°C) Control FET Figure 5-6 Datasheet 100 120 140 Sync FET RDS(ON) with VCC = 5.0V Over Temperature 13 Rev 3.7 03/24/2016 IR3829 Specifications 5.6 Typical Operating Characteristics -40°C To +125°C Iin (Standby) Iin(Dyn) 150 22 140 21.5 130 21 110 (mA) (μA) 120 100 20.5 90 20 80 V in = 21V 70 V in = 21 V, F s = 600kHz 19.5 60 50 -40 -20 0 20 40 60 Temperature (°C) 80 100 120 19 140 -40 -20 0 20 Switching Frequency 40 60 Temperature (°C) 80 100 120 140 80 100 120 140 80 100 120 140 Vfb 615 610 608 610 606 605 602 (mV) (kHz) 604 600 598 Rt = 39.2kΩ 596 600 595 594 590 592 585 590 -40 -20 0 20 40 60 Temperature (°C) 80 100 120 -40 140 -20 0 20 Vcc UVLO En UVLO 4.3 1.3 1.25 4.2 Enable UVLO Start 1.2 Vcc UVLO Start 4.1 1.15 4 (V) (V) 40 60 Temperature (°C) 1.1 1.05 3.9 3.8 Enable UVLO Stop 1 Vcc UVLO Stop 0.95 0.9 3.7 0.85 3.6 -40 -20 Figure 5-7 Datasheet 0 20 40 60 Temperature (°C) 80 100 120 0.8 140 -40 -20 0 20 40 60 Temperature (°C) Typical Operation Characteristics (Set 1 of 2) 14 Rev 3.7 03/24/2016 IR3829 Specifications Iocp with Vcc=5V ILIM = Vcc (A) (A) Iocp with Vcc=6.9V 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ILIM = Floating ILIM = GND -40 -20 0 20 40 60 Temperature (°C) 80 100 120 140 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ILIM = Vcc ILIM = Floating ILIM = GND -40 -20 0 OVP_Vth 20 40 60 Temperature (°C) 80 100 120 140 80 100 120 140 Power Good Threshold 750 600 590 740 580 570 560 (mV) (mV) 730 720 550 VPG(on) 540 530 520 710 VPG(lower) 510 500 700 490 480 690 -40 -20 0 20 40 60 Temperature (°C) 80 100 120 -40 140 -20 0 20 40 60 Temperature (°C) Vcc Voltage with Vin=7.5V 6.9 Icc = 0mA (V) 6.85 6.8 Icc=50mA 6.75 6.7 -40 Figure 5-8 Datasheet -20 0 20 40 60 Temperature (°C) 80 100 120 140 Typical Operation Characteristics (Set 2 of 2) 15 Rev 3.7 03/24/2016 IR3829 Theory of Operation 6 Theory of Operation The IR3829 uses a PWM voltage mode control scheme with external compensation to provide good noise immunity and maximum flexibility in selecting inductor values and capacitor types. The switching frequency is programmable from 300 kHz to 1.2MHz and provides the capability of optimizing the design in terms of size and performance. IR3829 provides precisely regulated output voltage programmed via two external resistors from 0.6V to 0.86*Vin. The IR3829 operates with an internal bias supply (LDO) which is connected to the Vcc/LDO_out pin. This allows operation with single supply. The IC can also be operated with an external supply from 4.5 to 7.5V, allowing an extended operating input voltage (PVin) range from 1.0V to 21V. For using the internal LDO supply, the Vin pin should be connected to PVin pin. If an external supply is used, it should be connected to Vcc/LDO_Out pin and the Vin pin should be shorted to Vcc/LDO_Out pin. The device utilizes the on-resistance of the low side MOSFET (sync FET) for over current protection. This method enhances the converter’s efficiency and reduces cost by eliminating the need for external current sense resistor. IR3829 includes two low Rds(on) MOSFETs using Infineon’s HEXFET technology. These are specifically designed for high efficiency applications. 6.1 Voltage Loop Compensation Design The IR3829 uses PWM voltage mode control. The output voltage of the POL, sensed by a resistor divider, is fed into an internal Error Amplifier (E/A). The output of the E/R is then compared to an internal ramp voltage to determine the pulse width of the gate signal for the control FET. The amplitude of the ramp voltage is proportional to Vin so that the bandwidth of the voltage loop remains almost constant for different input voltages. This feature is called input voltage feedfoward. It allows the feedback loop design independent of the input voltage. Please refer to the feedforward section for more information. A RC network has to be connected between the FB pin and the COMP pin to form a feedback compensator. The goal of the compensator design is to achieve a high control bandwidth with a phase margin of 45° or above. The high control bandwidth is beneficial for the loop dynamic response, which helps to reduce the number of output capacitors, the PCB size and the cost. A phase margin of 45° or higher is desired to ensure the system stability. The proprietary PWM modulator in IR3829 significantly reduces the PWM jittering, allowing the control bandwidth in the range of 1/10th to 1/5th of the switching frequency. Two types of compensators, Type II (PI) and Type III (PID), are commonly used. The selection of the compensation type is dependent on the ESR of the output capacitors. Electrolytic capacitors have relatively higher ESR. If the ESR pole is located at the frequency lower than the cross-over frequency, FC, the ESR pole will help to boost the phase margin. Thus a type II compensator can be used. For the output capacitors with lower ESR such as ceramic capacitors, type III compensation is often desired. Figure 6-1 Loop Compensators Table 6-1 lists the compensation selection for different types of output capacitors. Datasheet 16 Rev 3.7 03/24/2016 IR3829 Theory of Operation For more detailed design guideline of voltage loop compensation, please refer to the application note AN-1162, “Compensation Design Procedure for Buck Converter with Voltage-Mode Error-Amplifier”. SupBuck design tool is also available at (www.infineon.com) providing the reference design based on user’s design requirements. Table 6-1 Recommended Compensation Type Compensator Location of Cross-Over Frequency Type of Output Capacitors Type II (PI) FLC < FESR < FO < FS / 2 Electrolytic, POS-CAP, SP-CAP Type III-A (PID) FLC < FO < FESR < FS / 2 POS-CAP, SP-CAP Type III-B (PID) FLC < FO < FS / 2 < FESR Ceramic FLC is the resonant frequency of the output LC filter. It is often referred to as double pole. FESR is the ESR zero of the output capacitor. FO is the cross-over frequency of the control loop and FS is the switching frequency. FLC 6.2 1 2 Lo Co FESR 1 2 ESR Co Under-Voltage Lockout and Power On Ready The under-voltage lockout circuit monitors the voltage of Vcc/LDO_Out pin and the Enable input. It assures that the MOSFET driver outputs remain in the off state whenever either of these two signals drop below the set thresholds. Normal operation resumes once Vcc/LDO_Out and Enable rise above their thresholds. The POR (Power On Ready) signal is generated when all these signals reach the valid logic level (see system block diagram). The soft start sequence starts when the POR is asserted. 6.3 Enable The Enable features another level of flexibility for startup. The Enable has precise threshold, which is internally monitored by Under-Voltage Lockout (UVLO) circuit. Therefore, the IR3829 will turn on only when the voltage at the Enable pin exceeds this threshold, typically, 1.2V. If the input to the Enable pin is derived from the bus voltage by a suitably programmed resistive divider, it can be ensured that the IR3829 does not turn on until the bus voltage reaches the desired level (Figure 6-2). Only after the bus voltage reaches or exceeds this level and voltage at the Enable pin exceeds its threshold, IR3829 will be enabled. Therefore, in addition to being a logic input pin to enable the IR3829, the Enable feature, with its precise threshold, also allows the user to implement an Under-Voltage Lockout for the bus voltage (PVin). This is desirable particularly for high output voltage applications, where we might want the IR3829 to be disabled until PVin exceeds the desired output voltage level. Datasheet 17 Rev 3.7 03/24/2016 IR3829 Theory of Operation Figure 6-2 Normal start-up with Enable connected to PVin through a resistor divider at 10.2V When Enable is used as a logic input, the recommended start-up sequence for the normal operation of IR3829 is shown in Figure 6-3. Figure 6-3 Normal start-up with a logic input for Enable signal It is recommended to add a 1kΩ resistor in series with the Enable pin to limit the current flowing into the Enable pin. In addition, the Enable pin should not be left floating. A pull-down resistor in the range of several kilo ohms is recommended to connect between the Enable Pin and Gnd. Datasheet 18 Rev 3.7 03/24/2016 IR3829 Theory of Operation 6.4 Pre-bias Startup IR3829 is able to start up into pre-charged output, without oscillations and disturbances of the output voltage. The output starts in asynchronous fashion and keeps the synchronous MOSFET (Sync FET) off until the first gate signal for control MOSFET (Ctrl FET) is generated. Figure 6-4 shows a typical pre-bias condition at startup. Figure 6-4 Pre-Bias Startup The sync FET always starts with a narrow pulse width (12.5% of a switching period) and gradually increases its duty cycle with a step of 12.5% until it reaches the steady state value. The number of these startup pulses for each step is 16 and it’s internally programmed. Figure 6-5 shows the series of 16x8 startup pulses. Figure 6-5 Pre-bias Startup Pulses 6.5 Soft Start IR3829 has an internal digital soft-start to control the output voltage rise and to limit the current surge at the startup. To ensure correct start-up, the soft-start sequence initiates when the Enable and Vcc rise above their UVLO thresholds and generate the Power On Ready (POR) signal. The internal soft-start (Intl_SS) signal linearly rises with the rate of 0.2mV/µs from 0V to 1.5V. Figure 6-6 shows the waveforms during the soft-start. The normal Vout start-up time is fixed, and is equal to: Tstart 0.75V 0.15V 3.0ms 0.2mV/us During the soft-start, the over-current protection (OCP) and over-voltage protection (OVP) are enabled to protect the device for any short circuit or over voltage condition. Datasheet 19 Rev 3.7 03/24/2016 IR3829 Theory of Operation Figure 6-6 Theoretical Waveforms during Soft-Start 6.6 Operating Frequency The switching frequency can be programmed between 300 kHz – 1.2 MHz by connecting an external resistor from Rt pin to Gnd. Table 2 lists the Rt with each corresponding switching frequency. Table 6-2 Switching Frequency (Fs) vs. External Resistor (Rt) Rt (KΩ) FS (kHz) 80.6 300 60.4 400 48.7 500 39.2 600 34.0 700 29.4 800 26.1 900 23.2 1000 21.0 1100 19.1 1200 6.7 Shutdown IR3829 can be shut down by pulling the Enable pin below its 1.0V threshold. This will put both the high side and the low side driver in a tri-state. 6.8 Over Current Protection The over current (OC) protection is performed by sensing current through the RDS(on) of the Synchronous MOSFET. This method enhances the converter’s efficiency, reduces cost by eliminating a current sense resistor and any layout related noise issues. The over current (OC) limit can be set to one of three possible settings by floating the ILIM pin, by pulling up the ILIM pin to VCC, or pulling down the ILIM pin to PGnd. The current limit is internally compensated according to the IC temperature. So at different ambient temperature, the over-current trip threshold remains almost constant. Datasheet 20 Rev 3.7 03/24/2016 IR3829 Theory of Operation Note that the over current limit is affected by the Vcc voltage. In general, a lower Vcc voltage increases the RDS(on) of the Synchronous MOSFET and hence results in a lower OCP limit. Please refer to the typical performance curves of the OCP current limit with different Vcc voltages. To prevent false tripping induced by noise and transients, the current near the valley of the inductor current is sensed by the Over Current Protection circuit. More precisely, the inductor current is sampled for about 40ns on the downward inductor current slope approximately 12.5% of the switching period before the inductor current valley. When the current exceeds the OCP limit, an over current condition is detected. When an Over Current event is detected, PGood signal is pulled low and the device enters hiccup mode. Hiccup mode is performed by latching an internal OC signal, which keeps both Control FET and Synchronous FET off for 20.48ms (typical) blanking time. OC signal clears after the completion of blanking time and the device attempts to recover to the nominal output voltage with a soft-start, as shown in Figure 6-7. The device will repeat hiccup mode and attempt to recover until the overload or short circuit conditions is removed. Since the current sensing point is near the valley of the inductor current, the actual DC output current limit point will be greater than the valley point by approximately one half of peak to peak inductor ripple current. The DC current limit point can be calculated by the following equation. It should be pointed out that the OCP limits specified in the Electrical Table refer to the over current limit valley point. I OCP I LIMIT I 2 IOCP = DC current limit hiccup point ILIMIT = Over Current limit (valley of inductor current) ΔI = Inductor ripple current Figure 6-7 Timing Diagram for Current Limit Hiccup 6.9 Thermal Shutdown Temperature sensing is provided inside IR3829. The trip threshold is typically set to 145oC. When trip threshold is exceeded, thermal shutdown turns off both MOSFETs and resets the internal soft start. Automatic restart is initiated when the sensed temperature drops within the operating range. There is a 20oC hysteresis in the thermal shutdown threshold. Datasheet 21 Rev 3.7 03/24/2016 IR3829 Theory of Operation 6.10 Feed-Forward Feed-Forward is an important feature, because it can keep the converter stable and preserve its load transient performance when Vin varies in a large range. In IR3829, Feed-Forward function is enabled when Vin pin is connected to PVin pin. In this case, the internal low dropout (LDO) regulator is used. The PWM ramp amplitude (Vramp) is proportionally changed with Vin to maintain Vin/Vramp almost constant throughout Vin variation range as shown in the timing diagram. Thus, the control loop bandwidth and phase margin can be maintained constant. Feed-forward function can also minimize impact on output voltage from fast Vin change. The maximum Vin slew rate is within 1V/µs. If an external bias voltage is used as Vcc, Vin pin should be connected to Vcc/LDO_out pin instead of PVin pin. Then the Feed-Forward function is disabled. A re-calculation of loop compensation parameters is needed. Figure 6-8 Timing diagram for Feed-Forward function Datasheet 22 Rev 3.7 03/24/2016 IR3829 Theory of Operation 6.11 Low Dropout Regulator (LDO) IR3829 has an integrated low dropout (LDO) regulator which can provide gate drive voltage for both drivers. For internally biased single rail operation, Vin pin should be connected to PVin pin. If external bias voltage is used, Vin pin should be connected to Vcc/LDO_Out pin as shown in the figure. Figure 6-9 Internal LDO or External VCC Configurations When the Vin voltage is below 7.5V, the internal LDO may enter the dropout mode. The dropout voltage increases with the switching frequency. The figure shows the LDO voltage for 600kHz and 1000kHz respectively. Vcc Voltage with Vin=5V 5 4.95 4.9 (V) 4.85 4.8 Fsw=600kHz 4.75 4.7 4.65 4.6 Fsw=1000kHz 4.55 4.5 -40 -20 0 20 40 60 Temperature (°C) 80 100 120 140 Figure 6-10 LDO Voltage with Vin = 5V 6.12 Power Good Output IR3829 continually monitors the output voltage via the sense pin (Vsns) voltage. The Vsns voltage is an input to the window comparator with upper and lower turn-off threshold of 120% and 85% of the reference voltage respectively. PGood signal is high whenever Vsns voltage is within the PGood comparator window thresholds. The Datasheet 23 Rev 3.7 03/24/2016 IR3829 Theory of Operation PGood is an open drain output. Hence, a pull-up resistor is needed to limit the current flowing into the PGood pin less than 5mA when the output voltage is not in regulation. A typical value used is 49.9kΩ. High state indicates that output is in regulation. Figure 6-11 shows the timing diagram of the PGood signal. Vsns signal is also used by OVP comparator for detecting output over voltage condition. Figure 6-11 Vsns vs. PGood Relationship Timing Diagram 6.13 Over-Voltage Protection (OVP) OVP is achieved by comparing Vsns voltage to an OVP threshold voltage, 1.2 x Vref. When Vsns exceeds the OVP threshold, an over voltage trip signal asserts after 2us typical delay. Then the control FET is latched off immediately, PGood flags low. The sync FET remains on to discharge the output capacitor. When the Vsns voltage drops below the threshold, the sync FET turns off to prevent the complete depletion of the output capacitor. The control FET remains latched off until either Vcc or Enable signal is re-cycled. OVP comparator becomes active when the enable signal exceeds the start threshold. Vsns voltage is set by the voltage divider connected to the output and it can be programmed externally. Figure 6-12 OVP Timing Diagram Datasheet 24 Rev 3.7 03/24/2016 IR3829 Theory of Operation 6.14 Minimum On Time Considerations The minimum ON time is the shortest amount of time for Control FET to be reliably turned on. This is a very critical parameter for low duty cycle, high frequency applications. Conventional approach limits the pulse width to prevent noise, jitter and pulse skipping. This results in lower closed loop bandwidth. Infineon has developed a proprietary scheme to improve and enhance minimum pulse width that utilizes the benefits of voltage mode control scheme with higher switching frequency, wider conversion ratio and higher closed loop bandwidth, the latter results in reduction of output capacitors. Any design or application using IR3829 must ensure operation with a pulse width that is higher than this minimum on-time. This is necessary for the circuit to operate without jitter and pulse-skipping, which can cause high inductor current ripple and high output voltage ripple. ton D Vout Fs Vin Fs In any application that uses IR3829, the following conditions must be satisfied: ton(min) ton Vout Vin Fs V Vin Fs out ton (min) ton (min) The minimum output voltage is limited by the reference voltage and hence Vout(min) = 0.6 V. Therefore, for Vout(min) = 0.6 V, Vin Fs Vout t on (min) 0.6V 10 V/ s 60 ns Therefore, at the maximum recommended input voltage of 21V and minimum output voltage, the converter should be designed at a switching frequency that does not exceed 476 kHz. Conversely, for operation at the maximum recommended operating frequency (1.2MHz) and minimum output voltage (0.6V), the input voltage (PVin) should not exceed 8.3V. Else pulse skipping will happen. 6.15 Maximum Duty Ratio IR3829 is designed to have a maximum duty ratio of 0.86 for most applications. In addition, there are two other factors to limit the maximum duty ratio. One is the minimum off-time, which is more dominant at high switching frequency. The other factor is the maximum output voltage of the error amplifier. Due to the built-in input voltage feedforward, the ramp voltage of the internal PWM modulator increases with Vin. However the output of the error amplifier is clamped at the maximum voltage as specified in the electrical table, which can result in a max duty ratio smaller than 0.86 at high Vin. The figure shows a plot of the maximum duty ratio vs. the switching frequency with built in input voltage feedforward. Datasheet 25 Rev 3.7 03/24/2016 IR3829 Theory of Operation Max Duty Cycle vs. Switching Frequency 90 Vin=5V-12V Max Duty (%) 85 80 Vin=16V 75 70 65 60 Vin=21V 55 50 300 400 500 600 700 800 fs (kHz) 900 1000 1100 1200 Figure 6-13 Maximum Duty Cycle vs. Switching Frequency with Vin Feedforward Datasheet 26 Rev 3.7 03/24/2016 IR3829 Applications Design Example 7 Applications Design Example The following key parameters shall be used as an example for typical IR3829 applications. The application circuit is shown in Section 7.9. • PVin = Vin = 12V (±10%) • VO = 1.0V • IO = 16A • Peak-to-Peak Ripple Voltage = 1% of VO • ΔVo = ± 4% of VO (for 30% Load Transient) • FS = 600kHz 7.1 Enabling The IR3829 As explained earlier, the precise threshold of the Enable lends itself well to implementation of a UVLO for the Bus Voltage shown by the resistor divider network. Figure 7-1 Using Enable pin for UVLO implementation for a typical Enable threshold of VEN = 1.2 V R2 VEN 1.2V R1 R2 VEN R2 R1 Vin(min) VEN Vin (min) For Vin (min)= 9.2V, R1= 49.9kΩ and R2 = 7.5kΩ is a good choice. 7.2 Programming the Frequency For FS = 600kHz, select Rt = 39.2kΩ, using Table 6-2. 7.3 Output Voltage Programming Output voltage is programmed by reference voltage and external voltage divider. The Fb pin is the inverting input of the error amplifier, which is internally referenced to 0.6V. The divider ratio is set to provide 0.6V at the Fb pin when the output is at its desired value. The output voltage and the external resistor dividers connected to the output are defined by using the equations: Datasheet 27 Rev 3.7 03/24/2016 IR3829 Applications Design Example Vo Vref (1 RF 1 ) RF 2 Vref RF 2 RF 1 V V o ref For the calculated values of RF1 and RF2, see feedback compensation section. Figure 7-2 Output Voltage Programming for Typical Applications of IR3829 7.4 Bootstrap Capacitor Selection To drive the Control FET, it is necessary to supply a gate voltage at least 4V greater than the voltage at the SW pin, which is connected to the source of the Control FET. This is achieved by using a bootstrap configuration, which comprises the internal bootstrap diode and an external bootstrap capacitor (C1). When the sync FET is turned on, the capacitor node connected to SW is pulled down to ground. The capacitor charges towards Vcc through the internal bootstrap diode, which has a forward voltage drop VD. The voltage Vc across the bootstrap capacitor C1 is approximately given as: VC VCC VD When the control FET turns on in the next cycle, the capacitor node connected to SW rises to the bus voltage Vin. However, if the value of C1 is appropriately chosen, the voltage Vc across C1 remains approximately unchanged and the voltage at the Boot pin becomes: VBOOT Vin VCC VD Figure 7-3 Bootstrap Circuit to Generate Vc Voltage. Datasheet 28 Rev 3.7 03/24/2016 IR3829 Applications Design Example 7.5 Input Capacitor Selection The ripple current generated during the on time of the control FET should be provided by the input capacitor. The RMS value of this ripple is expressed by: I RMS Io D (1 D ) D Vo Vin Where: D is the Duty Cycle IRMS is the RMS value of the input capacitor current. Io is the output current. For IO = 16A and D = 0.0833, the IRMS = 4.42A. Ceramic capacitors are recommended due to their peak current capabilities. They also feature low ESR and ESL at higher frequency which enables better efficiency. For this application, it is advisable to have 5x10μF, 25V ceramic capacitors, C3216X5R1E106M from TDK. In addition to these, although not mandatory, a 1x330μF, 25V SMD capacitor EEV-FK1E331P from Panasonic may also be used as a bulk capacitor and is recommended if the input power supply is not located close to the converter. 7.6 Inductor Selection The inductor is selected based on output power, operating frequency and efficiency requirements. A low inductor value causes large ripple current, resulting in the smaller size, faster response to a load transient but poor efficiency and high output noise. Generally, the selection of the inductor value can be reduced to the desired maximum ripple current in the inductor (ΔiL). The optimum point is usually found between 20% and 50% ripple of the output current. For the buck converter, the inductor value for the desired operating ripple current can be determined using the following relations: Vin max Vo L L (Vin max Vo ) i L t t D Fs Vo Vin max iL Fs Where: Vinmax = Maximum input voltage VO = Output Voltage ΔiL = Inductor Peak-to-Peak Ripple Current FS= Switching Frequency Δt = On time for Control FET D = Duty Cycle If ΔiL ≈ 25%*Io, then the output inductor is calculated to be 0.38μH. Select L=0.4μH, FP1107R1-R40-R, from Coiltronics which provides an inductor suitable for this application. 7.7 Output Capacitor Selection The voltage ripple and transient requirements determine the output capacitors type and values. The criterion is normally based on the value of the Effective Series Resistance (ESR). However the actual capacitance value and Datasheet 29 Rev 3.7 03/24/2016 IR3829 Applications Design Example the Equivalent Series Inductance (ESL) are other contributing components. These components can be described as: Vo Vo ( ESR) Vo ( ESL) Vo (C ) Vo( ESR) I L ESR Vin Vo ) ESL L I L 8 Co Fs Vo ( ESL) ( Vo (C ) Where: ΔVO = Output Voltage Ripple ΔIL = Inductor Ripple Current Since the output capacitor has a major role in the overall performance of the converter and determines the result of transient response, selection of the capacitor is critical. The IR3829 can perform well with all types of capacitors. As a rule, the capacitor must have low enough ESR to meet output ripple and load transient requirements. The goal for this design is to meet the voltage ripple requirement in the smallest possible capacitor size. Therefore it is advisable to select ceramic capacitors due to their low ESR and ESL and small size. In this case a good choice is six 47uF ceramic capacitors, C2012X5R0J476M from TDK. The ESR of this type of capacitor is around 3mΩ each. The de-rated capacitance value with 1.0VDC bias and 10mVAC voltage is around 29uF each. It is also recommended to use a 0.1µF ceramic capacitor at the output for high frequency filtering. 7.8 Feedback Compensation For this design, the resonant frequency of the output LC filter, FLC, is: FLC 1 2 Lo Co 1 2 0.4 10 6 29 10 6 19.1kHz 6 The equivalent ESR zero of the output capacitors, FESR, is: FESR 1 2 ESR Co 1 2 3 10 29 10 6 1.8MHz 3 Designing crossover frequency around 1/7th of switching frequency gives FO =80 kHz. According to Table 6-1, Type III B compensation is selected for FLC < FO <FS/2 < FESR. Type III compensator is shown in Figure 7-4 for easy reference. Datasheet 30 Rev 3.7 03/24/2016 IR3829 Applications Design Example Figure 7-4 Type III compensation and its Asymptotic Gain Plot As shown in Figure 7-4, Type III compensator contains two zeros and three poles. The zeros are: 1 2 RC1 CC1 1 2 C F 3 ( RF 3 RF 1 ) FZ 1 FZ 2 The poles are: FP1 0 FP 2 1 2 RF 3 C F 3 FP 3 1 2 RC1 CC 2 To archive the sufficient phase boost near the cross-over frequency, it is desired to place one zero and one pole as follows: FZ 2 F0 FP 2 F0 1 sin 1 sin 70 80 10 3 14.1kHz 1 sin 1 sin 70 1 sin 1 sin 70 80 103 454.0kHz 1 sin 1 sin 70 To compensate the phase lag of the pole at the origin and to provide extra phase boost, the other zero could be placed at one half of the first zero, i.e. FZ1 = 7.05 kHz. The third pole is usually placed at one half of the switching frequency to damp the switching noise. i.e. Fp3 = 300 kHz. Please note that the zeros and poles locations do not necessarily follow the general design guides above and could vary with the design preference. The selected compensation parameters are: RF1=4.02kΩ, RF2=6.04kΩ, RF3=100Ω, CF3=3300pF, RC1=1.5kΩ, CC1=10nF, CC2=220pF. Finally, select the Vsns resistors (R7 / R8 in Section 7.9) to the same ratio of RF1 / RF2 to ensure the proper OVP and Pgood operations. Datasheet 31 Rev 3.7 03/24/2016 IR3829 Applications Design Example 7.9 Application Diagram and Bill of Materials Figure 7-5 Application Circuit for a 12V to 1.0V, 16A Point of Load Converter Table 7-1 Suggested Bill of Materials for the Application Circuit Part Reference Qty Value Description Manufacturer Part Number Cin 1 330μF SMD Electrolytic F size 25V 20% Panasonic EEV-FK1E331P 5 10μF 1206, 25V, X5R, 20% TDK C3216X5R1E106M C1 C5 C6 3 0.1μF 0402, 25V, X7R, 10% Murata GRM155R71E104KE14J C4 1 3300pF 0402, 50V, X7R, 10% Murata GRM155R71H332KA01D C2 1 220pF 0402, 50V, NP0, 5% Murata GRM1555C1H221JA01D C0 6 47μF 0805, 6.3V, X5R, 20% TDK C2012X5R0J476M CVCC 1 2.2μF 0603, 16V, X5R, 20% TDK C1608X5R1C225M C3 1 10nF 0402, 25V, X7R, 10% Murata GRM155R71E103KA01D CVIN 1 1.0μF 0402, 25V, X5R, 10% Murata GRM155R61E105KA12D L0 1 0.4uH SMD 11.0x7.2x7.5mm,0.29mΩ Coiltronics FP1107R1-R40-R R3 1 1.5KΩ Thick Film, 0402, 1/10W, 1% Panasonic ERJ-2RKF1501X R5 R7 2 4.02KΩ Thick Film, 0402, 1/10W, 1% Panasonic ERJ-2RKF4021X R6 R8 2 6.04KΩ Thick Film, 0402, 1/10W, 1% Panasonic ERJ-2RKF6041X R4 1 100Ω Thick Film, 0402, 1/10W, 1% Panasonic ERJ-2RKF1000X Rt 1 39.2kΩ Thick Film, 0402, 1/10W, 1% Panasonic ERJ-2RKF3922X Rboot 1 2Ω Thick Film, 0402, 1/16W, 1% Vishay CRCW04022R00FKED R1 Rpg 2 49.9KΩ Thick Film, 0402, 1/10W, 1% Panasonic ERJ-2RKF4992X R2 1 7.5KΩ Thick Film, 0402, 1/10W, 1% Panasonic ERJ-2RKF7501X U1 1 IR3829 PQFN 5 mm x 6 mm Infineon IR3829MPBF Datasheet 32 Rev 3.7 03/24/2016 IR3829 Applications Design Example Figure 7-6 Application circuit for a 5V to 1.2V, 16A point of load converter Table 7-2 Suggested Bill of Materials for the Application Circuit Part Reference Qty Value Description Manufacturer Part Number Cin 1 330μF SMD Electrolytic F size 25V 20% Panasonic EEV-FK1E331P 6 10μF 1206, 25V, X5R, 20% TDK C3216X5R1E106M C1 C5 C6 3 0.1μF 0603, 25V, X7R, 10% Murata GRM188R71E104KA01B C4 1 2200pF 0603,50V,X7R, 10% Murata GRM188R71H222KA01B C2 1 180pF 0603, 50V, NP0, 5% TDK C1608C0G1H181J C0 6 47μF 0805, 6.3V, X5R, 20% TDK C2012X5R0J476M CVCC 1 2.2μF 0603, 16V, X5R, 20% TDK C1608X5R1C225M C3 1 15nF 0603,50V,X7R, 10% TDK C1608X7R1H153K CVIN 1 1.0μF 0603, 25V, X5R, 10% Murata GRM155R61E105KA12D L0 1 0.3μH SMD 11.0x7.2x7.5mm,0.29mΩ Vitec 59PR9874N R3 1 2.49KΩ Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF2491V R5 R6 R7R8 4 3.32KΩ Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF3321V R4 1 100Ω Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF1000V Rt 1 39.2kΩ Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF3922V Rboot 1 2Ω Thick Film, 0402, 1/16W, 1% Vishay CRCW04022R00FKED Rpg 2 49.9KΩ Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF4992V U1 1 IR3829 PQFN 5x6mm Infineon IR3829MPBF Datasheet 33 Rev 3.7 03/24/2016 IR3829 Applications Design Example 7.10 Typical Operating Waveforms Vin=12.0V, Vout=1.0V, Iout=0-16A, room temperature, No Air Flow. Figure 7-7 Startup at 16A Load (Ch1:Vin, Ch2:Vout, Ch3: PGood, Ch4:Enable) Figure 7-8 Startup at 16A Load (Ch1:Vin, Ch2:Vout, Ch3: PGood, Ch4:VCC) Datasheet 34 Rev 3.7 03/24/2016 IR3829 Applications Design Example Vin=12.0V, Vout=1.0V, Iout=0-16A, room temperature, No Air Flow. Figure 7-9 Start up with pre bias, 0A Load (Ch2:Vout, Ch3: PGood, Ch4:Enable) Figure 7-10 Output voltage ripple, 16A load (Ch2:Vout) Datasheet 35 Rev 3.7 03/24/2016 IR3829 Applications Design Example Vin=12.0V, Vout=1.0V, Iout=0-16A, room temperature, No Air Flow. Figure 7-11 Inductor node at 16A load (Ch3: Switch Node) Figure 7-12 Short circuit (hiccup) recovery (Ch2:Vout, Ch3: PGood) Datasheet 36 Rev 3.7 03/24/2016 IR3829 Applications Design Example Vin=12.0V, Vout=1.0V, Iout=0-16A, room temperature, No Air Flow. (a) Iout = 1.6A to 6.4A (b) Iout = 11.2A to 16A Figure 7-13 Transient response at 4.8A steps @2.5A/us slew rate. Ch2:Vout, Ch4:Iout Datasheet 37 Rev 3.7 03/24/2016 IR3829 Applications Design Example Vin=12.0V, Vout=1.0V, Iout=0-16A, room temperature, No Air Flow. Figure 7-14 Bode plot at 16A load shows a bandwidth of 107.8kHz and phase margin of 51º Max Temperature of IR 3829 = 104.5°C Max Temperature of inductor = 60.1°C Figure 7-15 Thermal Image of the Board at 16A Load Datasheet 38 Rev 3.7 03/24/2016 IR3829 Layout Considerations 8 Layout Considerations The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. Make the connections for the power components on the top layer with wide, copper filled areas or polygons. In general, it is desirable to make proper use of power planes and polygons for power distribution and heat dissipation. The inductor, output capacitors and the IR3829 should be as close to each other as possible. This helps to reduce the EMI radiated by the power traces due to the high switching currents through them. Place the input capacitor directly at the PVin pin of IR3829. The critical bypass components such as capacitors for Vin, Vcc and Vref should be close to their respective pins. The feedback part of the system should be kept away from the inductor and other noise sources. It is important to place the feedback components including feedback resistors and compensation components close to Fb and Comp pins. In a multilayer PCB use one layer as a power ground plane and have a control circuit ground (analog ground), to which all signals are referenced. The goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. These two grounds must be connected together on the PC board layout at a single point. It is recommended to place all the compensation parts over the analog ground plane on top layer. The Power QFN is a thermally enhanced package. Based on thermal performance it is recommended to use at least a 4-layers PCB. To effectively remove heat from the device the exposed pad should be connected to the ground plane using vias. The figures illustrate the implementation of the layout guidelines outlined above, on the IRDC3829 4-layer demo board. Compensation parts should be placed as close as possible to the Comp pin PVin PGnd Resistor Rt should be placed as close as possible to the pin Single point connection between AGND & PGND, should be close to the SupIRBuck® and kept away from noise sources Vout Allow enough copper and minimum ground length path between Input and Output SW node copper is kept only at the top layer to minimize the switching noise AGnd All bypass caps should be placed as close as possible to their connecting pins Figure 8-1 IRDC3829 Demo Board – Top Layer Datasheet 39 Rev 3.7 03/24/2016 IR3829 Layout Considerations PVin PGnd Vout Figure 8-2 IRDC3829 Demo Board – Bottom Layer PGnd Figure 8-3 IRDC3829 Demo Board – Middle Layer 1 Datasheet 40 Rev 3.7 03/24/2016 IR3829 Layout Considerations PGnd Feedback and Vsns trace routing should be kept away from noise sources Figure 8-4 IRDC3829 Demo Board – Middle Layer 2 8.1 PCB Metal and Component Placement Evaluations have shown that the best overall performance is achieved using the substrate/PCB layout as shown in following Figures. PQFN devices should be placed to an accuracy of 0.050mm on both X and Y axes. Selfcentering behavior is highly dependent on solders and processes and experiments should be run to confirm the limits of self-centering on specific processes. For further information, please refer to “SupIRBuck® Multi-Chip Module (MCM) Power Quad Flat No-Lead (PQFN) Board Mounting Application Note.” (AN1132) Datasheet 41 Rev 3.7 03/24/2016 IR3829 Layout Considerations Figure 8-5 PCB metal pad sizing and spacing (all dimensions in mm) Datasheet 42 Rev 3.7 03/24/2016 IR3829 Layout Considerations 8.2 • Solder Resist It is recommended that the larger Power or Land Area pads are Solder Mask Defined (SMD.) – This allows the underlying Copper traces to be as large as possible, which helps in terms of current carrying capability and device cooling capability. • When using SMD pads, the underlying copper traces should be at least 0.05mm larger (on each edge) than the Solder Mask window, in order to accommodate any layer to layer misalignment. (i.e. 0.1mm in X & Y.) • However, for the smaller signal type leads around the edge of the device, it is recommended that these are Non Solder Mask Defined or Copper Defined. • When using NSMD pads, the Solder Resist Window should be larger than the Copper Pad by at least 0.025mm on each edge, (i.e. 0.05mm in X&Y,) in order to accommodate any layer to layer misalignment. • Ensure that the solder resist in-between the smaller signal lead areas are at least 0.15mm wide, due to the high x/y aspect ratio of the solder mask strip. Figure 8-6 Solder Resist Datasheet 43 Rev 3.7 03/24/2016 IR3829 Layout Considerations 8.3 Stencil Design • Stencils for PQFN can be used with thicknesses of 0.100-0.250mm (0.004-0.010"). Stencils thinner than 0.100mm are unsuitable because they deposit insufficient solder paste to make good solder joints with the ground pad; high reductions sometimes create similar problems. Stencils in the range of 0.125mm-0.200mm (0.005-0.008"), with suitable reductions, give the best results. • Evaluations have shown that the best overall performance is achieved using the stencil design shown in following Figure. This design is for a stencil thickness of 0.127mm (0.005"). The reduction should be adjusted for stencils of other thicknesses. Figure 8-7 Stencil pad spacing (all dimensions in mm) Datasheet 44 Rev 3.7 03/24/2016 IR3829 Layout Considerations 8.4 Marking Information Figure 8-8 Marking information 8.5 Package Information Figure 8-9 Package Dimensions Datasheet 45 Rev 3.7 03/24/2016 IR3829 Layout Considerations Figure 8-10 Package Dimensions Table Datasheet 46 Rev 3.7 03/24/2016 IR3829 Layout Considerations 8.6 Environmental Qualifications Table 8-1 Environmental Qualifications† Qualification Level Moisture Sensitivity Level ESD Industrial PQFN 5 mm x 6 mm JEDEC Level 2 @ 260°C Machine Model (JESD22-A115A) Class A Human Body Model (JESD22-A114F) Class 2 < 200V ≥ 2000V to < 4000V Charged Device Model (JESD22-C101D) Class III ≥ 500V to ≤1000V RoHS Compliant Yes † Qualification standards can be found at Infineon web site: www.irf.com Datasheet 47 Rev 3.7 03/24/2016 IR3829 Revision History: Revision / Date Subjects (major changes since previous revision) IR3829 Rev 3.7, 03/24/2016 3.7 03-02-16 S476 Datasheet Initial web release. 48 Rev 3.7 03/24/2016 IR3829 Edition 03/24/2016 Published by Infineon Technologies AG 81726 Munich, Germany © 2016 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com) Datasheet 49 Rev 3.7 03/24/2016 w w w . i n f i n e o n . c o m Published by Infineon Technologies AG Doc_Number