AS7C34098A-8TIN 256K X 16 BIT HIGH SPEED CMOS SRAM Rev. 1.4 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Description Initial Issue “CE# ≧VCC - 0.2V” revised as ”CE# ≦0.2V” for TEST CONDITION of Average Operating Power supply Current Icc1 on page3 Revised VIH(max)/VIL(min) in Issue Date Jul.12.2012 Jul.19.2012 May.7.2013 DC ELECTRICAL CHARACTERISTICS Rev. 1.3 Rev. 1.4 Added in tBA/tBHZ*/tBLZ* in AC ELECTRICAL CHARACTERISTICS Added WRITE CYCLE 3 in TIMING WAVEFORMS 1. Revise “TEST CONDITION” for VOH, VOL on page 5 IOH = -8mA revised as -4mA IOL =4mA revised as 8mA 2. Revise VIH(max) & VIL(min) note on page 5 VIH(max) = VCC + 2.0V for pulse width less than 6ns. VIL(min) = VSS - 2.0V for pulse width less than 6ns. Revised the address pin sequence of TSOP-II pin configuration on page 3 in order to be compatible with industry convention. (No function specifications and applications have been changed and all the characteristics are kept all the same as Rev 1.3 ) Added tBW in AC ELECTRICAL CHARACTERISTICS Revised WRITE CYCLE 1,2 in TIMING WAVEFORMS Alliance Memory, Inc reserves the rights to change the specifications and products without notice. 551 Taylor Way, Suite #1, San Carlos, CA 94070, USA Tel: +1 650 610 6800 Fax: +1 650 620 9211 0 Jun.04.2013 Sep.23.2013 AS7C34098A-8TIN 256K X 16 BIT HIGH SPEED CMOS SRAM Rev. 1.4 FEATURES GENERAL DESCRIPTION Fast access time : 8ns Low power consumption: Operating current: 50mA(TYP.) Standby current: 2mA(TYP.) Single 3.3V power supply All inputs and outputs TTL compatible Fully static operation Industrial temperature -40°~85℃ Tri-state output Data byte control : LB# (DQ0 ~ DQ7) UB# (DQ8 ~ DQ15) Data retention voltage : 1.5V (MIN.) Greenpackage/ROHS compliant (N) Package : 44-pin 400 mil TSOP-II The AS7C34098A is a 4,194,304-bit high speed CMOS static random access memory organized as 262144 words by 16 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The AS7C34098A operates from a single power supply of 3.3V and all inputs and outputs are fully TTL compatible PRODUCT FAMILY Product Family AS7C34098A(I) Operating Temperature Vcc Range Speed -40°~85℃ 3.0 ~ 3.6V 8ns Power Dissipation Standby(ISB1,TYP.) Operating(ICC1,TYP.) 2mA Alliance Memory, Inc reserves the rights to change the specifications and products without notice. 551 Taylor Way, Suite #1, San Carlos, CA 94070, USA Tel: +1 650 610 6800 Fax: +1 650 620 9211 1 50mA AS7C34098A-8TIN 256K X 16 BIT HIGH SPEED CMOS SRAM Rev. 1.4 PIN DESCRIPTION FUNCTIONAL BLOCK DIAGRAM Vcc Vss A0-A17 DQ0-DQ7 Lower Byte DQ8-DQ15 Upper Byte CE# WE# OE# LB# UB# DECODER I/O DATA CIRCUIT 256Kx16 MEMORY ARRAY COLUMN I/O SYMBOL DESCRIPTION A0 - A17 Address Inputs DQ0 – D15 Data Inputs/Outputs CE# Chip Enable Inputs WE# Write Enable Input OE# Output Enable Input LB# Lower Byte Control UB# Upper Byte Control VCC Power Supply VSS Ground NC No Connection CONTROL CIRCUIT Alliance Memory, Inc reserves the rights to change the specifications and products without notice. 551 Taylor Way, Suite #1, San Carlos, CA 94070, USA Tel: +1 650 610 6800 Fax: +1 650 620 9211 2 AS7C34098A-8TIN 256K X 16 BIT HIGH SPEED CMOS SRAM Rev. 1.4 PIN CONFIGURATION 1 44 A17 A1 2 43 A16 A2 3 42 A15 A3 4 41 OE# A4 5 40 UB# CE# 6 39 LB# DQ0 7 38 DQ15 DQ1 8 37 DQ14 DQ2 9 36 DQ13 DQ3 10 35 DQ12 Vcc 11 34 Vss Vss 12 33 Vcc DQ4 13 32 DQ11 DQ5 14 31 DQ10 DQ6 15 30 DQ9 DQ7 16 29 DQ8 WE# 17 28 NC A5 18 27 A14 A6 19 26 A13 A7 20 25 A12 A8 21 24 A11 A9 22 23 A10 AS7C34098A XXXXX XXXXX A0 TSOP II(Top View) Alliance Memory, Inc reserves the rights to change the specifications and products without notice. 551 Taylor Way, Suite #1, San Carlos, CA 94070, USA Tel: +1 650 610 6800 Fax: +1 650 620 9211 3 AS7C34098A-8TIN 256K X 16 BIT HIGH SPEED CMOS SRAM Rev. 1.4 ABSOLUTE MAXIMUM RATINGS* PARAMETER Voltage on VCC relative to VSS Voltage on any other pin relative to VSS Operating Temperature Storage Temperature Power Dissipation DC Output Current SYMBOL VT1 VT2 RATING -0.5 to 4.6 -0.5 to VCC+0.5 UNIT V V TA -40 to 85(I grade) ℃ TSTG PD IOUT -65 to 150 1 50 ℃ W mA *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. TRUTH TABLE MODE Standby Output Disable Read Write Note: CE# OE# H L L L L L L L L X H X L L L X X X WE# LB# X H X H H H L L L X X H L H L L H L UB# X X H H L L H L L I/O OPERATION DQ0-DQ7 DQ8-DQ15 High – Z High – Z High – Z High – Z High – Z High – Z DOUT High – Z High – Z DOUT DOUT DOUT DIN High – Z High – Z DIN DIN DIN SUPPLY CURRENT H = VIH, L = VIL, X = Don't care Alliance Memory, Inc reserves the rights to change the specifications and products without notice. 551 Taylor Way, Suite #1, San Carlos, CA 94070, USA Tel: +1 650 610 6800 Fax: +1 650 620 9211 4 ISB,ISB1 ICC,ICC1 ICC,ICC1 ICC,ICC1 AS7C34098A-8TIN 256K X 16 BIT HIGH SPEED CMOS SRAM Rev. 1.4 DC ELECTRICAL CHARACTERISTICS SYMBOL TEST CONDITION PARAMETER Supply Voltage VCC -8 *1 Input High Voltage VIH *2 Input Low Voltage VIL Input Leakage Current ILI VCC ≧ VIN ≧ VSS Output Leakage VCC ≧ VOUT ≧ VSS, ILO Current Output Disabled Output High Voltage VOH IOH = -4mA Output Low Voltage VOL IOL = 8mA Cycle time = Min. ICC CE# = VIL, II/O = 0mA, -8 Others at VIL or VIH Average Operating Power supply Current CE# ≦0.2, ICC1 Others at 0.2V or Vcc-0.2V -8 II/O = 0mA;f=max ISB CE# =VIH, Others at VIL or VIH Standby Power CE# ≧VCC - 0.2V, Supply Current ISB1 Others at 0.2V or VCC - 0.2V MIN. 3.0 2.2 - 0.3 -1 TYP. 3.3 - *4 MAX. 3.6 VCC+0.3 0.8 1 UNIT V V V µA -1 - 1 µA 2.4 - - 0.4 V V - 65 80 mA - 50 60 mA - - 30 mA - 2 10 mA Notes: 1. VIH(max) = VCC + 2.0V for pulse width less than 6ns. 2. VIL(min) = VSS - 2.0V for pulse width less than 6ns. 3. Over/Undershoot specifications are characterized on engineering evaluation stage, not for mass production test. 4. Typical values are included for reference only and are not guaranteed or tested. Typical valued are measured at VCC = VCC(TYP.) and TA = 25℃ CAPACITANCE (TA = 25℃, f = 1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. - MAX 8 10 Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Speed Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 8ns 0.2V to VCC - 0.2V 3ns 1.5V CL = 30pF + 1TTL, IOH/IOL = -4mA/8mA Alliance Memory, Inc reserves the rights to change the specifications and products without notice. 551 Taylor Way, Suite #1, San Carlos, CA 94070, USA Tel: +1 650 610 6800 Fax: +1 650 620 9211 5 UNIT pF pF AS7C34098A-8TIN 256K X 16 BIT HIGH SPEED CMOS SRAM Rev. 1.4 AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low-Z Output Enable to Output in Low-Z Chip Disable to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change LB#, UB# Access Time LB#, UB# to High-Z Output LB#, UB# to Low-Z Output SYM. tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH tBA tBHZ* tBLZ* AS7C34098A-8 MIN. MAX. 8 8 8 4.5 2 0 3 3 2 4.5 3 0 - UNIT ns ns ns ns ns ns ns ns ns ns ns ns (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High-Z LB#, UB# Valid to End of Write SYM. tWC tAW tCW tAS tWP tWR tDW tDH tOW * tWHZ* tBW AS7C34098A-8 MIN. MAX. 8 6.5 6.5 0 6.5 0 5 0 2 3 6.5 - UNIT ns ns ns ns ns ns ns ns ns ns ns *These parameters are guaranteed by device characterization, but not production tested. Alliance Memory, Inc reserves the rights to change the specifications and products without notice. 551 Taylor Way, Suite #1, San Carlos, CA 94070, USA Tel: +1 650 610 6800 Fax: +1 650 620 9211 6 AS7C34098A-8TIN 256K X 16 BIT HIGH SPEED CMOS SRAM Rev. 1.4 TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA Dout tOH Previous Data Valid Data Valid READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5) tRC Address tAA CE# tACE OE# tOE tOH tOHZ tCHZ tOLZ tCLZ Dout High-Z Data Valid High-Z Notes : 1.WE# is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low. 3.Address must be valid prior to or coincident with CE# = low,; otherwise tAA is the limiting parameter. 4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ. Alliance Memory, Inc reserves the rights to change the specifications and products without notice. 551 Taylor Way, Suite #1, San Carlos, CA 94070, USA Tel: +1 650 610 6800 Fax: +1 650 620 9211 7 AS7C34098A-8TIN 256K X 16 BIT HIGH SPEED CMOS SRAM Rev. 1.4 WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6) tWC Address tAW CE# tCW tBW LB#,UB# tAS tWP tWR WE# tWHZ Dout TOW High-Z (4) tDW Din (4) tDH Data Valid WRITE CYCLE 2 (CE# Controlled) (1,2,5,6) tWC Address tAW CE# tAS tWR tCW tBW LB#,UB# tWP WE# tWHZ Dout High-Z (4) tDW Din tDH Data Valid Alliance Memory, Inc reserves the rights to change the specifications and products without notice. 551 Taylor Way, Suite #1, San Carlos, CA 94070, USA Tel: +1 650 610 6800 Fax: +1 650 620 9211 8 AS7C34098A-8TIN 256K X 16 BIT HIGH SPEED CMOS SRAM Rev. 1.4 WRITE CYCLE 3 (LB#,UB# Controlled) (1,2,5,6) tWC Address tAW tWR CE# tAS tCW tBW LB#,UB# tWP WE# tWHZ Dout High-Z (4) tDW Din tDH Data Valid Notes : 1.WE#,CE#, LB#, UB# must be high during all address transitions. 2.A write occurs during the overlap of a low CE#, low WE#, LB# or UB# = low. 3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE#, LB#, UB# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. Alliance Memory, Inc reserves the rights to change the specifications and products without notice. 551 Taylor Way, Suite #1, San Carlos, CA 94070, USA Tel: +1 650 610 6800 Fax: +1 650 620 9211 9 AS7C34098A-8TIN 256K X 16 BIT HIGH SPEED CMOS SRAM Rev. 1.4 DATA RETENTION CHARACTERISTICS PARAMETER VCC for Data Retention Data Retention Current Chip Disable to Data Retention Time Recovery Time tRC* = Read Cycle Time SYMBOL TEST CONDITION VDR CE# ≧ VCC - 0.2V VCC = 1.5V IDR CE# ≧ VCC - 0.2V Others at 0.2V or Vcc – 0.2V See Data Retention tCDR Waveforms (below) tR MIN. 1.5 TYP. - MAX. 3.6 UNIT V - 2 10 mA 0 - - ns tRC* - - ns DATA RETENTION WAVEFORM VDR ≥ 1.5V Vcc Vcc(min.) Vcc(min.) tCDR CE# VIH tR CE# ≥ Vcc-0.2V VIH Alliance Memory, Inc reserves the rights to change the specifications and products without notice. 551 Taylor Way, Suite #1, San Carlos, CA 94070, USA Tel: +1 650 610 6800 Fax: +1 650 620 9211 10 AS7C34098A-8TIN 256K X 16 BIT HIGH SPEED CMOS SRAM Rev. 1.4 PACKAGE OUTLINE DIMENSION 44-pin 400mil TSOP-Ⅱ Package Outline Dimension SYMBOLS A A1 A2 b c D E E1 e L ZD y Θ DIMENSIONS IN MILLMETERS MIN. NOM. MAX. 1.20 0.05 0.10 0.15 0.95 1.00 1.05 0.30 0.45 0.12 0.21 18.212 18.415 18.618 11.506 11.760 12.014 9.957 10.160 10.363 0.800 0.40 0.50 0.60 0.805 0.076 o o o 0 3 6 DIMENSIONS IN MILS MIN. NOM. MAX. 47.2 2.0 3.9 5.9 37.4 39.4 41.3 11.8 17.7 4.7 8.3 717 725 733 453 463 473 392 400 408 31.5 15.7 19.7 23.6 31.7 3 o o o 0 3 6 Alliance Memory, Inc reserves the rights to change the specifications and products without notice. 551 Taylor Way, Suite #1, San Carlos, CA 94070, USA Tel: +1 650 610 6800 Fax: +1 650 620 9211 11 AS7C34098A-8TIN 256K X 16 BIT HIGH SPEED CMOS SRAM Rev. 1.4 ORDERING INFORMATION Package Type 44Pin(400mil) TSOP-II Access Time (Speed/ns) Temperature Range(℃) 8 -40℃~85℃ Packing Type Alliance Memory Part No. Tray AS7C34098A-8TIN Tape Reel AS7C34098A-8TINTR Copyright © Alliance Memory All Rights Reserved Part Number: AS7C34098A Document Version: v. 1.4 © Copyright 2003 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. 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Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. Alliance Memory, Inc reserves the rights to change the specifications and products without notice. 551 Taylor Way, Suite #1, San Carlos, CA 94070, USA Tel: +1 650 610 6800 Fax: +1 650 620 9211 12 AS7C34098A-8TIN Rev. 1.4 256K X 16 BIT HIGH SPEED CMOS SRAM THIS PAGE IS LEFT BLANK INTENTIONALLY. Alliance Memory, Inc reserves the rights to change the specifications and products without notice. 551 Taylor Way, Suite #1, San Carlos, CA 94070, USA Tel: +1 650 610 6800 Fax: +1 650 620 9211 13