TI1 ISO5451-Q1 High-cmti 2.5-a / 5-a isolated igbt, mosfet gate driver Datasheet

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ISO5451-Q1
SLLSEQ3 – SEPTEMBER 2016
ISO5451-Q1 High-CMTI 2.5-A / 5-A Isolated IGBT, MOSFET Gate Driver
with Active Safety Features
1 Features
2 Applications
•
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1
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Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
– Device HBM Classification Level 3A
– Device CDM Classification Level C6
50-kV/μs Minimum and 100-kV/μs Typical
Common-Mode Transient Immunity (CMTI)
at VCM = 1500 V
2.5-A Peak Source and 5-A Peak Sink Currents
Short Propagation Delay: 76 ns (Typ),
110 ns (Max)
2-A Active Miller Clamp
Output Short-Circuit Clamp
Fault Alarm upon Desaturation Detection is
Signaled on FLT and Reset Through RST
Input and Output Under Voltage Lock-Out (UVLO)
with Ready (RDY) Pin Indication
Active Output Pull-down and Default Low Outputs
with Low Supply or Floating Inputs
3-V to 5.5-V Input Supply Voltage
15-V to 30-V Output Driver Supply Voltage
CMOS Compatible Inputs
Rejects Input Pulses and Noise Transients
Shorter Than 20 ns
Isolation Surge Withstand Voltage 10000-VPK
Safety and Regulatory Certifications:
– 8000-VPK VIOTM and 1420-VPK VIORM
Reinforced Isolation per DIN V VDE V 0884-10
(VDE V 0884-10):2006-12
– 5700-VRMS Isolation for 1 Minute per UL 1577
– CSA Component Acceptance Notice 5A, IEC
60950–1 and IEC 60601–1 End Equipment
Standards
– TUV Certification per EN 61010-1 and EN
60950-1
– GB4943.1-2011 CQC Certification
– All Certifications Complete per UL, VDE, CQC,
TUV and Planned for CSA
Isolated IGBT and MOSFET Drives in:
– HEV and EV Power Modules
– Industrial Motor Control Drives
– Industrial Power Supplies
– Solar Inverters
– Induction Heating
3 Description
The ISO5451-Q1 is a 5.7-kVRMS, reinforced isolated
gate driver for IGBTs and MOSFETs with 2.5-A
source and 5-A sink current. The input side operates
from a single 3-V to 5.5-V supply. The output side
allows for a supply range from minimum 15-V to
maximum 30-V. Two complementary CMOS inputs
control the output state of the gate driver. The short
propagation time of 76 ns assures accurate control of
the output stage.
An internal desaturation (DESAT) fault detection
recognizes when the IGBT is in an overload
condition. Upon a DESAT detect, the gate driver
output is driven low to VEE2 potential, turning the
IGBT immediately off.
Device Information(1)
PART NUMBER
ISO5451-Q1
PACKAGE
BODY SIZE (NOM)
SOIC (16)
10.30 mm × 7.50 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Functional Block Diagram
VCC2
VCC1
VCC1
UVLO1
UVLO2
500 µA
DESAT
IN±
Mute
9V
IN+
GND2
VCC1
VCC2
RDY
Gate Drive
and
Encoder
Logic
Ready
OUT
VCC1
FLT
Q
S
Q
R
VCC1
Decoder
2V
Fault
CLAMP
RST
GND1
VEE2
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISO5451-Q1
SLLSEQ3 – SEPTEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Function ...........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
8
9
9.1
9.2
9.3
9.4
1
1
1
2
3
3
4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
18
18
19
20
10 Application and Implementation........................ 21
10.1 Application Information.......................................... 21
10.2 Typical Applications .............................................. 21
11 Power Supply Recommendations ..................... 30
12 Layout................................................................... 30
Absolute Maximum Ratings ...................................... 4
ESD Ratings ............................................................ 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 4
Power Rating............................................................. 5
Insulation Characteristics .......................................... 5
Safety Limiting Values .............................................. 6
Safety-Related Certifications..................................... 6
Electrical Characteristics........................................... 7
Switching Characteristics ........................................ 8
Safety and Insulation Characteristics Curves ......... 9
Typical Characteristics .......................................... 10
12.1 Layout Guidelines ................................................. 30
12.2 PCB Material ......................................................... 30
12.3 Layout Example .................................................... 30
13 Device and Documentation Support ................. 31
13.1
13.2
13.3
13.4
13.5
13.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
31
31
31
31
31
31
14 Mechanical, Packaging, and Orderable
Information ........................................................... 31
Parameter Measurement Information ................ 16
Detailed Description ............................................ 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
September 2016
*
Initial release
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SLLSEQ3 – SEPTEMBER 2016
5 Description (continued)
When desaturation is active, a fault signal is sent across the isolation barrier, pulling the FLT output at the input
side low and blocking the isolator input. The FLT output condition is latched and can be reset through a lowactive pulse at the RST input.
When the IGBT is turned off during normal operation with bipolar output supply, the output is hard clamp to VEE2.
If the output supply is unipolar, an active Miller clamp can be used, allowing Miller current to sink across a low
impedance path, preventing IGBT to be dynamically turned on during high voltage transient conditions.
The readiness for the gate driver to be operated is under the control of two undervoltage-lockout circuits
monitoring the input side and output side supplies. If either side has insufficient supply the RDY output goes low,
otherwise this output is high.
The ISO5451-Q1 is available in a 16-pin SOIC package. Device operation is specified over a temperature range
from –40°C to 125°C ambient.
6 Pin Configuration and Function
DW Package
16-Pin SOIC
Top View
1
16
GND1
DESAT
2
15
VCC1
GND2
3
14
RST
NC
4
13
FLT
VCC2
5
12
RDY
OUT
6
11
IN-
CLAMP
7
10
IN+
VEE2
8
9
ISOLATION
VEE2
GND1
Pin Functions
PIN
NAME
NO.
VEE2
1, 8
DESAT
GND2
I/O
DESCRIPTION
-
Output negative supply. Connect to GND2 for Unipolar supply application.
2
I
Desaturation voltage input
3
-
Gate drive common. Connect to IGBT emitter.
NC
4
-
Not connected
VCC2
5
-
Most positive output supply potential.
OUT
6
O
Gate drive voltage output
CLAMP
7
O
Miller clamp output
GND1
9, 16
-
Input ground
IN+
10
I
Non-inverting gate drive voltage control input
IN-
11
I
Inverting gate drive voltage control input
RDY
12
O
Power-good output, active high when both supplies are good.
FLT
13
O
Fault output, low-active during DESAT condition
RST
14
I
Reset input, apply a low pulse to reset fault latch.
VCC1
15
-
Positive input supply (3 V to 5.5 V)
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ISO5451-Q1
SLLSEQ3 – SEPTEMBER 2016
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7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
GND1 - 0.3
6
V
(VCC2 – GND2)
–0.3
35
V
Negative supply voltage output side
(VEE2 – GND2)
–17.5
0.3
V
V(SUP2)
Total supply output voltage
(VCC2 - VEE2)
–0.3
35
V
VOUT
Gate driver output voltage
VEE2 - 0.3
VCC2 + 0.3
V
I(OUTH)
Gate driver high output current
2.7
A
I(OUTL)
Gate driver low output current
5.5
A
V(LIP)
Voltage at IN+, IN-, FLT, RDY, RST
I(LOP)
Output current of FLT, RDY
V(DESAT)
Voltage at DESAT
V(CLAMP)
Clamp voltage
TJ
TSTG
VCC1
Supply voltage input side
VCC2
Positive supply voltage output side
VEE2
(1)
Gate driver high output current
(max pulse width = 10 μs, max duty cycle =
0.2%)
GND1 - 0.3
VCC1 + 0.3
V
10
mA
GND2 - 0.3
VCC2 + 0.3
V
VEE2 - 0.3
VCC2 + 0.3
V
Junction temperature
–40
150
°C
Storage temperature
-65
150
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability
7.2 ESD Ratings
VALUE
V(ESD)
(1)
Human-body model (HBM), per AEC Q100-002
Electrostatic discharge
(1)
UNIT
±4000
Charged-device model (CDM), per AEC Q100-011
V
±1500
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VCC1
Supply voltage input side
VCC2
NOM
MAX
UNIT
3
5.5
V
Positive supply voltage output side (VCC2 – GND2)
15
30
V
VEE2
Negative supply voltage output side (VEE2 – GND2)
–15
0
V
V(SUP2)
Total supply voltage output side (VCC2 – VEE2)
15
30
V
VIH
High-level input voltage (IN+, IN-, RST)
0.7 x VCC1
VCC1
V
VIL
Low-level input voltage (IN+, IN-, RST)
0
0.3 x VCC1
tUI
Pulse width at IN+, IN- for full output (CLOAD = 1nF)
tRST
Pulse width at RST for resetting fault latch
800
TA
Ambient temperature
-40
40
V
ns
ns
25
125
°C
7.4 Thermal Information
THERMAL METRIC (1)
DW (SOIC)
16 PINS
RθJA
Junction-to-ambient thermal resistance
99.6
RθJC(top)
Junction-to-case (top) thermal resistance
48.5
RθJB
Junction-to-board thermal resistance
56.5
ψJT
Junction-to-top characterization parameter
29.2
ψJB
Junction-to-board characterization parameter
56.5
(1)
4
UNIT
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SLLSEQ3 – SEPTEMBER 2016
7.5 Power Rating
VALUE
PD
Maximum power dissipation (1)
PID
Maximum input power dissipation
175
POD
Maximum output power dissipation
1080
(1)
UNIT
1255
mW
Full chip power dissipation is de-rated 10.04 mW/°C beyond 25°C ambient temperature. At 125°C ambient temperature, a maximum of
251 mW total power dissipation is allowed. Power dissipation can be optimized depending on ambient temperature and board design,
while ensuring that Junction temperature does not exceed 150°C.
7.6 Insulation Characteristics
SPECIFICATION
UNIT
External clearance (1)
PARAMETER
Shortest terminal-to-terminal distance through air
>8
mm
CPG
External creepage (1)
Shortest terminal-to-terminal distance across the package
surface
>8
mm
DTI
Distance through the insulation
Minimum internal gap (internal clearance)
>21
μm
CTI
Tracking resistance (comparative tracking index)
DIN EN 60112 (VDE 0303-11); IEC 60112;
>600
V
Material Group
According to IEC 60664-1; UL 746A
CLR
TEST CONDITIONS
Overvoltage category (according to IEC 60664-1)
I
Rated Mains Voltage ≤ 300 VRMS
I-IV
Rated Mains Voltage ≤ 600 VRMS
I-III
Rated Mains Voltage ≤ 1000 VRMS
I-II
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 (2)
VIORM
VIOWM
Maximum repetitive peak isolation voltage
AC voltage (bipolar)
1420
VPK
Maximum isolation working voltage
AC voltage. Time dependent dielectric breakdown (TDDB)
Test, see Figure 1
1000
VRMS
DC voltage
1420
VDC
8000
6250
VIOTM
Maximum Transient isolation voltage
VTEST = VIOTM, t = 60 sec (qualification), t = 1 sec (100%
production)
VIOSM
Maximum surge isolation voltage (3)
Test method per IEC 60065, 1.2/50 μs waveform,
VTEST = 1.6 x VIOSM = 10000 VPK (qualification) (3)
qpd
Apparent charge
(4)
Method a: After I/O safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM = 1704 VPK ,
tm = 10 s
≤5
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 × VIORM = 2272 VPK ,
tm = 10 s
≤5
Method b1: At routine test (100% production) and
preconditioning (type test)
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.875× VIORM = 2663 VPK ,
tm = 10 s
≤5
VIO = 500 V, TA = 25°C
RIO
Isolation resistance, input to output
(5)
Barrier capacitance, input to output (5)
CIO
VPK
pC
> 1012
Ω
11
Ω
VIO = 500 V, 100°C ≤ TA ≤ 125°C
> 10
VIO = 500 V at TS = 150°C
> 109
Ω
1
pF
VIO = 0.4 x sin (2πft), f = 1 MHz
Pollution degree
2
UL 1577
VISO
(1)
(2)
(3)
(4)
(5)
Withstanding Isolation voltage
VTEST = VISO, t = 60 sec (qualification),
VTEST = 1.2 × VISO = 6840 VRMS,
t = 1 sec (100% production)
5700
VRMS
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
This coupler is suitable for basic electrical insulation only within the maximum operating ratings. Compliance with the safety ratings shall
be ensured by means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier tied together creating a two-terminal device
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SLLSEQ3 – SEPTEMBER 2016
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7.7 Safety Limiting Values
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of
the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier, potentially leading to secondary system failures.
PARAMETER
IS
TEST CONDITIONS
Safety input, output or supply current
PS
Safety input, output, or total power
TS
Maximum ambient safety temperature
(1)
MIN
TYP
MAX
θJA = 99.6°C/W, VI = 3.6 V, TJ = 150°C,
TA = 25°C
349
θJA = 99.6°C/W, VI = 5.5 V, TJ = 150°C,
TA = 25°C
228
θJA = 99.6°C/W, VI = 15 V, TJ = 150°C,
TA = 25°C
84
θJA = 99.6°C/W, VI = 30 V, TJ = 150°C,
TA = 25°C
42
θJA = 99.6°C/W, TJ = 150°C, TA = 25°C
1255 (1)
UNIT
mA
150
°C
Input, output, or the sum of input and output power should not exceed this value
7.8 Safety-Related Certifications
over operating free-air temperature range (unless otherwise noted)
VDE
Certified according to DIN V
VDE V 0884-10
(VDE V 0884-10):2006-12
and DIN EN 60950-1
(VDE 0805 Teil 1):2011-01
Reinforced Insulation
Maximum Transient isolation
voltage, 8000 VPK;
Maximum surge isolation
voltage, 6250 VPK,
Maximum repetitive peak
isolation voltage, 1420 VPK
Certification completed
Certificate number: 40040142
(1)
CSA
UL
Plan to certify under CSA
Component Acceptance
Notice 5A, IEC 60950-1 and
IEC 60601-1
Certified according to UL
1577 Component Recognition
Program
Isolation Rating of 5700 VRMS;
Reinforced insulation per CSA
60950- 1- 07+A1+A2 and IEC
60950-1 (2nd Ed.), 800 VRMS
max working voltage (pollution
Single Protection, 5700 VRMS
degree 2, material group I) ;
(1)
2 MOPP (Means of Patient
Protection) per CSA 606011:14 and IEC 60601-1 Ed.
3.1, 250 VRMS (354 VPK) max
working voltage
Certification planned
Certification completed
File number: E181974
CQC
Certified according to GB
4943.1-2011
Reinforced Insulation, Altitude
≤ 5000m, Tropical climate,
400 VRMS maximum working
voltage
Certification completed
Certificate number:
CQC16001141761
TUV
Certified according to
EN 61010-1:2010 (3rd Ed)
and
EN 609501:2006/A11:2009/A1:2010/
A12:2011/A2:2013
5700 VRMS Reinforced
insulation per
EN 61010-1:2010 (3rd Ed) up
to working voltage of 600
VRMS
5700 VRMS Reinforced
insulation per
EN 609501:2006/A11:2009/A1:2010/
A12:2011/A2:2013 up to
working voltage of 800 VRMS
Certification completed
Client ID number: 77311
Production tested ≥ 6840 VRMS for 1 second in accordance with UL 1577.
The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolute Maximum
Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the
Thermal Information table is that of a device installed in the High-K Test Board for Leaded Surface-Mount
Packages. The power is the recommended maximum input voltage times the current. The junction temperature is
then the ambient temperature plus the power times the junction-to-air thermal resistance.
6
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7.9 Electrical Characteristics
Over recommended operating conditions unless otherwise noted. All typical values are at TA = 25°C, VCC1 = 5 V,
VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2.25
V
VOLTAGE SUPPLY
VIT+(UVLO1)
Positive-going UVLO1 threshold voltage
input side (VCC1 – GND1)
VIT-(UVLO1)
Negative-going UVLO1 threshold voltage
input side (VCC1 – GND1)
VHYS(UVLO1)
UVLO1 Hysteresis voltage (VIT+ – VIT–)
input side
VIT+(UVLO2)
Positive-going UVLO2 threshold voltage
output side (VCC2 – GND2)
VIT-(UVLO2)
Negative-going UVLO2 threshold voltage
output side (VCC2 – GND2)
VHYS(UVLO2)
UVLO2 Hysteresis voltage (VIT+ – VIT–)
output side
IQ1
Input supply quiescent current
2.8
4.5
mA
IQ2
Output supply quiescent current
3.6
6
mA
1.7
V
0.24
12
9.5
V
13
V
11
V
1
V
LOGIC I/O
VIT+(IN,RST)
Positive-going input threshold voltage (IN+,
IN-, RST)
VIT-(IN,RST)
Negative-going input threshold voltage
(IN+, IN-, RST)
VHYS(IN,RST)
Input hysteresis voltage (IN+, IN-, RST)
IIH
High-level input leakage at (IN+)
IIL
Low-level input leakage at (IN-, RST)
IPU
Pull-up current of FLT, RDY
V(RDY) = GND1, V(FLT) = GND1
VOL
Low-level output voltage at FLT, RDY
I(FLT) = 5 mA
(1)
0.7 x VCC1
0.3 x VCC1
IN+ = VCC1
(2)
IN- = GND1, RST = GND1
V
V
0.15 x VCC1
V
100
µA
-100
µA
100
µA
0.2
V
2
V
GATE DRIVER STAGE
V(OUTPD)
Active output pull-down voltage
IOUT = 200 mA, VCC2 = open
V(OUTH)
High-level output voltage
IOUT = –20 mA
V(OUTL)
Low-level output voltage
IOUT = 20 mA
I(OUTH)
High-level output peak current
IN+ = high, IN- = low,
VOUT = VCC2 - 15 V
1.5
2.5
A
I(OUTL)
Low-level output peak current
IN+ = low, IN- = high,
VOUT = VEE2 + 15 V
3.4
5
A
VCC2 - 0.5
VCC2 - 0.24
VEE2 + 13
V
VEE2 + 50
mV
ACTIVE MILLER CLAMP
V(CLP)
Low-level clamp voltage
I(CLP) = 20 mA
I(CLP)
Low-level clamp current
V(CLAMP) = VEE2 + 2.5 V
V(CLTH)
Clamp threshold voltage
VEE2 + 0.015
VEE2 + 0.08
V
1.6
2.5
1.6
2.1
2.5
A
V
1.3
V
SHORT CIRCUIT CLAMPING
V(CLP_OUT)
Clamping voltage
(VOUT - VCC2)
IN+ = high, IN- = low, tCLP=10 µs,
I(OUTH) = 500 mA
0.8
V(CLP_CLAMP)
Clamping voltage
(VCLP - VCC2)
IN+ = high, IN- = low, tCLP=10 µs,
I(CLP) = 500 mA
1.3
V(CLP_CLAMP)
Clamping voltage at CLAMP
IN+ = High, IN- = Low, I(CLP) = 20 mA
0.7
1.1
V
0.58
mA
V
DESAT PROTECTION
I(CHG)
Blanking capacitor charge current
V(DESAT) - GND2 = 2 V
0.42
0.5
I(DCHG)
Blanking capacitor discharge current
V(DESAT) - GND2 = 6 V
9
14
V(DSTH)
DESAT threshold voltage with respect to
GND2
8.3
9
V(DSL)
DESAT voltage with respect to GND2,
when OUT is driven low
0.4
(1)
(2)
mA
9.5
V
1
V
IIH for IN-, RST pin is zero as they are pulled high internally.
IIL for IN+ is zero, as it is pulled low internally.
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7.10 Switching Characteristics
Over recommended operating conditions unless otherwise noted. All typical values are at TA = 25°C, VCC1 = 5 V,
VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V
MIN
TYP
MAX
tr
Output signal rise time
PARAMETER
12
20
35
ns
tf
Output signal fall time
12
20
37
ns
tPLH, tPHL
Propagation Delay
76
110
ns
tsk-p
Pulse Skew |tPHL – tPLH|
20
ns
tsk-pp
Part-to-part skew
30 (1)
ns
tGF
TEST CONDITIONS
CLOAD = 1 nF, see Figure 38,
Figure 39 and Figure 40
Glitch filter on IN+, IN-, RST
tDESAT
(10%)
DESAT sense to 10% OUT delay
tDESAT
(GF)
DESAT glitch filter delay
tDESAT
(FLT)
DESAT sense to FLT-low delay
see Figure 40
Leading edge blanking time
see Figure 38 and Figure 39
tGF(RSTFLT)
Glitch filter on RST for resetting FLT
CI
Input capacitance (2)
VI = VCC1/2 + 0.4 x sin (2πft),
f = 1 MHz, VCC1 = 5 V
CMTI
Common-mode transient immunity
VCM = 1500 V, see Figure 41
(1)
(2)
8
20
30
40
ns
300
415
500
ns
330
tLEB
UNIT
330
2000
2420
ns
400
500
ns
800
ns
300
2
50
ns
100
pF
kV/μs
Measured at same supply voltage and temperature condition
Measured from input pin to ground.
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7.11 Safety and Insulation Characteristics Curves
1.E+12
Safety Margin Zone: 1200 VRMS,1268 Years
Operating Zone: 1000 VRMS, 676 Years
TDDB Line (<1 PPM Fail Rate)
1.E+11
87.5%
Time to Fail (s)
1.E+10
1.E+9
1.E+8
1.E+7
1.E+6
1.E+5
1.E+4
20%
1.E+3
1.E+2
1.E+1
0
1000
2000 3000
4000
5000
Stress Voltage (VRMS)
6000
7000
TA upto 150°C
Stress-voltage frequency = 60 Hz
Figure 1. Reinforced High-Voltage Capacitor Life Time Projection
400
1400
Safety Limiting Current (mA)
350
300
250
200
150
100
Power
1200
Safety Limiting Power (mW)
VCC1 = 3.6 V
VCC1 = 5.5 V
VCC2 = 15 V
VCC2 = 30 V
1000
800
600
400
200
50
0
0
0
50
100
150
Ambient Temperature (qC)
200
Figure 2. Thermal Derating Curve for Safety Limiting
Current per VDE
0
50
100
150
Ambient Temperature (qC)
200
Figure 3. Thermal Derating Curve for Safety Limiting Power
per VDE
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7.12 Typical Characteristics
0.5
7.0
VCC2 - VOUT = 2.5 V
VCC2 - VOUT = 5 V
VCC2 - VOUT = 10 V
6.0
Output Drive Current (A)
Output Drive Current (A)
0.0
VCC2 - VOUT = 15 V
VCC2 - VOUT = 20 V
-0.5
-1.0
-1.5
-2.0
-2.5
5.0
4.0
3.0
2.0
-3.0
-40
-20
0
20
40
60
80
100
Ambient Temperature (qC)
120
0.0
-40
140
-20
0
D001
VCC2 = 30 V
VOUT - VEE2 = 15 V
VOUT - VEE2 = 20 V
20
40
60
80
100
Ambient Temperature (qC)
120
140
D002
VCC2 = 30 V
Figure 4. Output High Drive Current vs Temperature
Figure 5. Output Low Drive Current vs Temperature
7
0.0
TA = -40qC
TA = 25qC
TA = 125qC
6
Output Drive Current (A)
-0.5
Output Drive Current (A)
VOUT - VEE2 = 2.5 V
VOUT - VEE2 = 5 V
VOUT - VEE2 = 10 V
1.0
-1.0
-1.5
-2.0
-2.5
5
4
3
2
TA = -40qC
TA = 25qC
TA = 125qC
1
-3.0
0
-3.5
0
5
10
15
20
(VCC2 - VOUT) Voltage (V)
25
30
0
5
10
15
20
(VOUT - VEE2) Voltage (V)
D003
Figure 6. Output High Drive Current vs Output Voltage
25
30
D004
Figure 7. Output Low Drive Current vs Output Voltage
9.5
15 V Unipolar
30 V Unipolar
DESAT Threshold Voltage (V)
9.4
9.3
9.2
9.1
9
8.9
8.8
8.7
8.6
8.5
-40
-20
0
20
40
60
80
100
Ambient Temperature (qC)
120
140
D005
Unipolar: VCC2 - VEE2 = VCC2 - GND2
Figure 8. DESAT Threshold Voltage vs Temperature
10
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Typical Characteristics (continued)
3 V/div
3 V/div
CH1: OUT
CH2: DESAT
CH3: /FLT
Time - 50 ns/div
Time - 50 ns/div
CL = 1 nF
RG = 10 Ω
VCC2 - VEE2 = VCC2 - GND2 = 20 V
CL = 1 nF
RG = 0 Ω
VCC2 - VEE2 = VCC2 - GND2 = 20 V
Figure 10. Output Transient Waveform
3 V/div
3 V/div
Figure 9. Output Transient Waveform
Time - 500 ns/div
Time - 500 ns/div
CL = 10 nF
RG = 0 Ω
VCC2 - VEE2 = VCC2 - GND2 = 20 V
CL = 10 nF
RG = 10 Ω
VCC2 - VEE2 = VCC2 - GND2 = 20 V
Figure 12. Output Transient Waveform
3 V/div
3 V/div
Figure 11. Output Transient Waveform
Time - 2 ms/div
Time - 1 ms/div
CL = 100 nF
RG = 10 Ω
VCC2 - VEE2 = VCC2 - GND2 = 20 V
CL = 100 nF
RG = 0 Ω
VCC2 - VEE2 = VCC2 - GND2 = 20 V
Figure 13. Output Transient Waveform
Figure 14. Output Transient Waveform
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Typical Characteristics (continued)
10 V/div
3.5
3
ICC1 Supply Current (mA)
5 V/div
CH1: OUT
3 V/div
CH2: DESAT
CH3: FLT
2.5
2
1.5
1
VCC1 = 3 V
VCC1 = 3.3 V
VCC1 = 5 V
VCC1 = 5.5 V
0.5
Time - 1 ms/div
0
-40
CL = 100 nF
RG = 10 Ω
VCC2 - VEE2 = VCC2 - GND2 = 20 V
-20
0
IN+ = High
Figure 15. Output Transient Waveform DESAT and FLT
20
40
60
80
100
Ambient Temperature (qC)
120
140
D006
IN- = Low
5
1.8
4.5
1.6
ICC2 Supply Current (mA)
ICC1 Supply Current (mA)
Figure 16. ICC1 Supply Current vs Temperature
2
1.4
1.2
1
0.8
0.6
VCC1 = 3 V
VCC1 = 3.3 V
VCC1 = 5 V
VCC1 = 5.5 V
0.4
0.2
0
-40
-20
0
IN+ = Low
20
40
60
80
100
Ambient Temperature (qC)
120
4
3.5
3
2.5
2
1.5
1
VCC2 = 15 V
VCC2 = 20 V
VCC2 = 30 V
0.5
0
-40
140
0
IN- = Low
20
40
60
80
100
Ambient Temperature (qC)
120
140
D008
Input Frequency = 1 kHz
Figure 17. ICC1 Supply Current vs Temperature
Figure 18. ICC2 Supply Current vs Temperature
3
5
VCC1 = 3 V
VCC1 = 5.5 V
4.5
ICC2 Supply Current (mA)
2.5
ICC1 Supply Current (mA)
-20
D007
2
1.5
1
0.5
4
3.5
3
2.5
2
1.5
1
VCC2 = 15 V
VCC2 = 20 V
VCC2 = 30 V
0.5
0
0
0
50
100
150
200
Input Frequency (kHz)
250
300
0
50
D009
100
150
200
Input Frequency (kHz)
250
300
D010
No CL
Figure 19. ICC1 Supply Current vs. Input Frequency
12
Figure 20. ICC2 Supply Current vs Input Frequency
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Typical Characteristics (continued)
100
70
VCC2 = 15 V
VCC2 = 30 V
90
80
Propogation Delay (ns)
ICC2 Supply Current (mA)
60
50
40
30
20
70
60
50
40
30
tpLH at VCC2 = 15 V
tpHL at VCC2 = 15 V
tpLH at VCC2 = 30 V
tpHL at VCC2 = 30 V
20
10
10
0
-40
0
0
10
20
30
40
50
60
70
Load Capacitance (nF)
80
90
100
-20
RG = 10 Ω, 20kHz
20
40
60
80
100
Ambient Temperature (qC)
CL = 1nF
Figure 21. ICC2 Supply Current vs Load Capacitance
RG = 0 Ω
120
140
D012
VCC1 = 5 V
Figure 22. VCC1 Propagation Delay vs Temperature
100
1200
tpLH at VCC2 = 15 V
tpLH at VCC2 = 30 V
tpHL at VCC2 = 15 V
tpHL at VCC2 = 30 V
90
1000
Propagation Delay (ns)
80
Propogation Delay (ns)
0
D025
70
60
50
40
30
tpLH at VCC1 = 3.3 V
tpHL at VCC1 = 3.3 V
tpLH at VCC1 = 5 V
tpHL at VCC1 = 5 V
20
10
0
-40
800
600
400
200
0
-20
0
CL = 1nF
20
40
60
80
100
Ambient Temperature (qC)
RG = 0 Ω
120
140
0
10
20
D013
VCC2 = 15 V
30
40
50
60
70
Load Capacitance (nF)
RG = 10 Ω
Figure 23. VCC2 Propagation Delay vs Temperature
80
90
100
D024
VCC1 = 5 V
Figure 24. Propagation Delay vs Load Capacitance
800
500
700
450
VCC2 = 15 V
VCC2 = 30 V
Transition Time (ns)
Transition Time (ns)
400
600
500
400
300
200
350
300
250
200
150
100
100
VCC2 = 15 V
VCC2 = 30 V
50
0
0
0
10
20
RG = 0 Ω
30
40
50
60
70
Load Capacitance (nF)
80
90
100
0
10
20
D022
VCC1 = 5 V
RG = 0 Ω
Figure 25. tr Rise Time vs Load Capacitance
30
40
50
60
70
Load Capacitance (nF)
80
90
100
D026
VCC1 = 5 V
Figure 26. tf Fall Time v. Load Capacitance
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Typical Characteristics (continued)
4000
2500
VCC2 = 15 V
VCC2 = 30 V
3500
Transition Time (ns)
Transition Time (ns)
2000
3000
2500
2000
1500
1000
1500
1000
500
500
VCC2 = 15 V
VCC2 = 30 V
0
0
0
10
20
RG = 10 Ω
30
40
50
60
70
Load Capacitance (nF)
80
90
100
0
VCC1 = 5 V
20
RG = 10 Ω
Figure 27. tr Rise Time vs Load Capacitance
30
40
50
60
70
Load Capacitance (nF)
80
90
100
D027
VCC1 = 5 V
Figure 28. tf Fall Time vs Load Capacitance
450
500
VCC2 = 15 V
VCC2 = 30 V
480
DESAT Sense to 10% VOUT Delay (ns)
tLEB Leading Edge Blanking Time (ns)
10
D023
460
440
420
400
380
360
340
320
300
-40
-20
0
20
40
60
80
100
Ambient Temperature (qC)
120
VCC2 = 15 V
VCC2 = 30 V
445
440
435
430
425
420
415
410
405
400
-40
140
-20
0
D014
20
40
60
80
100
Ambient Temperature (qC)
120
140
D015
CL = 10 nF
Figure 30. DESAT Sense to VOUT 10% Delay vs Temperature
Figure 29. Leading Edge Blanking Time With Temperature
120
VCC2 = 15 V
VCC2 = 30 V
2.05
100
Reset To Fault Delay (ns)
DESAT Sense to /FLT Low Delay (Ps)
2.1
2
1.95
1.9
1.85
80
60
40
VCC1 = 3 V
VCC1 = 3.3 V
VCC1 = 5 V
VCC1 = 5.5 V
20
1.8
-40
-20
0
20
40
60
80
100
Ambient Temperature (qC)
120
140
0
-40
-20
D016
0
20
40
60
80
100
Ambient Temperature (qC)
120
140
D017
CL = 1 nF
Figure 31. DESAT Sense to FLT Low Delay vs Temperature
14
Figure 32. Reset to Fault Delay Across Temperature
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Typical Characteristics (continued)
2
V(CLAMP) = 2 V
V(CLAMP) = 4 V
V(CLAMP) = 6 V
4
1.8
Active Pull Down Voltage (V)
ICLP Clamp Low-Level Current (A)
5
4.5
3.5
3
2.5
2
1.5
1
0.5
1.4
1.2
1
0.8
0.6
0.4
IOUT = 100 mA
IOUT = 200 mA
0.2
0
-40
-20
0
20
40
60
80
100
Ambient Temperature (qC)
120
0
-40
140
Figure 33. Miller Clamp Current vs Temperature
20
40
60
80
100
Ambient Temperature (qC)
120
140
D019
Figure 34. Active Pull Down Voltage vs Temperature
VOUT_CLAMP - Short Circuit Clamp
Voltage on OUT Across Temperature
1000.0
800.0
600.0
400.0
0.0
-40
0
1200
1200.0
200.0
-20
D018
1400.0
VCLP_CLAMP - Short Circuit Clamp
Voltage on Clamp Across Temperatur
1.6
20mA at VCC2 = 15V
20mA at VCC2 = 30V
250mA at VCC2 = 15V
-20
0
250mA at VCC2 = 30V
500mA at VCC2 = 15V
500mA at VCC2 = 30V
20
40
60
80
100
Ambient Temperature (Cq)
120
140
800
600
20mA at VCC2 = 15V
20mA at VCC2 = 30V
250mA at VCC2 = 15V
250mA at VCC2 = 30V
500mA at VCC2 = 15V
500mA at VCC2 = 30V
400
200
0
-40
-20
0
D021
Figure 35. VCLP_CLAMP - Short Circuit Clamp Voltage on
Clamp Across Temperature
ICHG Blanking Capacitor Charging Current ( PA)
1000
20
40
60
80
100
Ambient Temperature (Cq)
120
140
D020
Figure 36. VOUT_CLAMP - Short Circuit Clamp Voltage on OUT
Across Temperature
-400
-420
-440
-460
-480
-500
-520
-540
-560
-580
-600
-40
VCC2 = 15 V
-20
0
20
40
60
80
100
Ambient Temperature (qC)
120
140
D011
DESAT = 6 V
Figure 37. Blanking Capacitor Charging Current vs Temperature
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8 Parameter Measurement Information
IN-
0V
VCC1
IN+
0V
50 %
50 %
tr
tf
90%
50%
OUT
10%
tPLH
tPHL
DESAT
tLEB
Figure 38. OUT Propagation Delay, Non-Inverting Configuration
VCC1
IN-
0V
50 %
50 %
VCC1
IN+
tr
tf
90%
50%
OUT
10%
tPLH
tPHL
DESAT
tLEB
Figure 39. OUT Propagation Delay, Inverting Configuration
16
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Parameter Measurement Information (continued)
tDESAT (10%)
tDESAT (FLT)
9V
tRST
VDESAT
OUT
10%
FLT
50 %
RST
Figure 40. DESAT, OUT, FLT, RST Delay
ISO 5451 ± Q1
15
5
VCC1
VCC2
1µF
0.1µF
3 V - 5. 5 V
9, 16
GND 2
GND 1
14
1, 8
RST
10
VEE2
I s o l a ti o n B a r r i e r
+
S1
IN +
11
13
15V
3
IN -
OUT
DESAT
RDY
CLAMP
12
NC
VCM
+
CL
FLT
+
6
1 nF
2
Pass - Fail Criterion:
OUT must remain stable
-
7
4
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Figure 41. Common-Mode Transient Immunity Test Circuit
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9 Detailed Description
9.1 Overview
The ISO5451-Q1 is an isolated gate driver for IGBTs and MOSFETs. Input CMOS logic and output power stage
are separated by a capacitive, silicon dioxide (SiO2), isolation barrier.
The IO circuitry on the input side interfaces with a micro controller and consists of gate drive control and RESET
(RST) inputs, READY (RDY) and FAULT (FLT) alarm outputs. The power stage consists of power transistors to
supply 2.5-A pull-up and 5-A pull-down currents to drive the capacitive load of the external power transistors, as
well as DESAT detection circuitry to monitor IGBT collector-emitter overvoltage under short circuit events. The
capacitive isolation core consists of transmit circuitry to couple signals across the capacitive isolation barrier, and
receive circuitry to convert the resulting low-swing signals into CMOS levels. The ISO5451-Q1 also contains
under voltage lockout circuitry to prevent insufficient gate drive to the external IGBT, and active output pull-down
feature which ensures that the gate-driver output is held low, if the output supply voltage is absent. The
ISO5451-Q1 also has an active Miller clamp function which can be used to prevent parasitic turn-on of the
external power transistor, due to Miller effect, for unipolar supply operation.
9.2 Functional Block Diagram
VCC2
VCC1
VCC1
UVLO1
UVLO2
500 µA
DESAT
IN±
Mute
9V
IN+
GND2
VCC1
VCC2
RDY
Gate Drive
and
Encoder
Logic
Ready
OUT
VCC1
FLT
Q
S
Q
R
VCC1
Decoder
2V
Fault
CLAMP
RST
GND1
18
VEE2
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9.3 Feature Description
9.3.1 Supply and active Miller clamp
The ISO5451-Q1 supports both bipolar and unipolar power supply with active Miller clamp.
For operation with bipolar supplies, the IGBT is turned off with a negative voltage on its gate with respect to its
emitter. This prevents the IGBT from unintentionally turning on because of current induced from its collector to its
gate due to Miller effect. In this condition it is not necessary to connect CLAMP output of the gate driver to the
IGBT gate, but connecting CLAMP output of the gate driver to the IGBT gate is also not an issue. Typical values
of VCC2 and VEE2 for bipolar operation are 15 V and -8 V with respect to GND2.
For operation with unipolar supply, typically, VCC2 is connected to 15 V with respect to GND2, and VEE2 is
connected to GND2. In this use case, the IGBT can turn-on due to additional charge from IGBT Miller
capacitance caused by a high voltage slew rate transition on the IGBT collector. To prevent IGBT to turn on, the
CLAMP pin is connected to IGBT gate and Miller current is sinked through a low impedance CLAMP transistor.
Miller CLAMP is designed for miller current up to 2 A. When the IGBT is turned-off and the gate voltage
transitions below 2 V the CLAMP current output is activated.
9.3.2 Active Output Pull-down
The Active output pull-down feature ensures that the IGBT gate OUT is clamped to VEE2 to ensure safe IGBT offstate when the output side is not connected to the power supply.
9.3.3 Undervoltage Lockout (UVLO) with Ready (RDY) Pin Indication Output
Undervoltage Lockout (UVLO) ensures correct switching of IGBT. The IGBT is turned-off, if the supply VCC1
drops below VIT-(UVLO1), irrespective of IN+, IN- and RST input till VCC1 goes above VIT+(UVLO1).
In similar manner, the IGBT is turned-off, if the supply VCC2 drops below VIT-(UVLO2), irrespective of IN+, IN- and
RST input till VCC2 goes above VIT+(UVLO2).
Ready (RDY) pin indicates status of input and output side Under Voltage Lock-Out (UVLO) internal protection
feature. If either side of device have insufficient supply (VCC1 or VCC2), the RDY pin output goes low; otherwise,
RDY pin also serves as an indication to the micro-controller that the device is ready for operation.
9.3.4 Fault (FLT) and Reset (RST)
During IGBT overload condition, to report desaturation error FLT goes low. If RST is held low for the specified
duration, FLT is cleared at rising edge of RST. RST has an internal filter to reject noise and glitches. By asserting
RST for at-least the specified minimum duration, device input logic can be enabled or disabled.
9.3.5 Short Circuit Clamp
Under short circuit events it is possible that currents are induced back into the gate-driver OUT and CLAMP pins
due to parasitic Miller capacitance between the IGBT collector and gate terminals. Internal protection diodes on
OUT and CLAMP help to sink these currents while clamping the voltages on these pins to values slightly higher
than the output side supply.
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9.4 Device Functional Modes
In ISO5451-Q1 OUT to follow IN+ in normal functional mode, RST and RDY needs to be in high state.
Table 1. Function Table (1)
VCC1
VCC2
IN+
IN-
RST
RDY
OUT
PU
PD
X
X
X
Low
Low
PD
PU
X
X
X
Low
Low
PU
PU
X
X
Low
High
Low
PU
Open
X
X
X
Low
Low
PU
PU
Low
X
X
High
Low
PU
PU
X
High
X
High
Low
PU
PU
High
Low
High
High
High
(1)
20
PU: Power Up (VCC1 ≥ 2.25-V, VCC2 ≥ 13-V), PD: Power Down (VCC1 ≤ 1.7-V, VCC2 ≤ 9.5-V), X: Irrelevant
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The ISO5451-Q1 is an isolated gate driver for power semiconductor devices such as IGBTs and MOSFETs. It is
intended for use in applications such as motor control, industrial inverters and switched mode power supplies. In
these applications, sophisticated PWM control signals are required to turn the power devices on and off, which at
the system level eventually may determine, for example, the speed, position, and torque of the motor or the
output voltage, frequency and phase of the inverter. These control signals are usually the outputs of a micro
controller, and are at low voltage levels such as 3.3-V or 5-V. The gate controls required by the MOSFETs and
IGBTs, on the other hand, are in the range of 30-V (using Unipolar Output Supply) to 15-V (using Bipolar Output
Supply), and need high current capability to be able to drive the large capacitive loads offered by those power
transistors. Not only that, the gate drive needs to be applied with reference to the Emitter of the IGBT (Source for
MOSFET), and by construction, the Emitter node in a gate drive system may swing between 0 to the DC bus
voltage, that can be several 100s of volts in magnitude.
The ISO5451-Q1 is thus used to level shift the incoming 3.3-V and 5-V control signals from the microcontroller to
the 30-V (using Unipolar Output Supply) to 15-V (using Bipolar Output Supply) drive required by the power
transistors while ensuring high-voltage isolation between the driver side and the microcontroller side.
10.2 Typical Applications
Figure 42 shows the typical application of a three-phase inverter using six ISO5451-Q1 isolated gate drivers.
Three-phase inverters are used for variable-frequency drives to control the operating speed and torque of AC
motors and for high power applications such as High-Voltage DC (HVDC) power transmission.
The basic three-phase inverter consists of six power switches, and each switch is driven by one ISO5451-Q1.
The switches are driven on and off at high switching frequency with specific patterns that to converter dc bus
voltage to three-phase AC voltages.
Figure 42. Typical Motor Drive Application
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Typical Applications (continued)
10.2.1 Design Requirements
Unlike optocoupler based gate drivers which need external current drivers and biasing circuitry to provide the
input control signals, the input control to the ISO5451-Q1 is CMOS and can be directly driven by the
microcontroller. Other design requirements include decoupling capacitors on the input and output supplies, a
pullup resistor on the common drain FLT output signal and RST input signal, and a high-voltage protection diode
between the IGBT collector and the DESAT input. Further details are explained in the subsequent sections.
Table 2 shows the allowed range for Input and Output supply voltage, and the typical current output available
from the gate-driver.
Table 2. Design Parameters
PARAMETER
VALUE
Input supply voltage
3-V to 5.5-V
Unipolar output supply voltage (VCC2 - GND2 = VCC2 - VEE2)
15-V to 30-V
Bipolar output supply voltage (VCC2 - VEE2)
15-V to 30-V
Bipolar output supply voltage (GND2 - VEE2)
0-V to 15-V
Output current
2.5-A
10.2.2 Detailed Design Procedure
10.2.2.1 Recommended ISO5451-Q1 Application Circuit
The ISO5451-Q1 has both, inverting and non-inverting gate control inputs, an active low reset input, and an open
drain fault output suitable for wired-OR applications. The recommended application circuit in Figure 43 illustrates
a typical gate driver implementation with Unipolar Output Supply and Figure 44 illustrates a typical gate driver
implementation with Bipolar Output Supply using the ISO5451-Q1.
A 0.1-μF bypass capacitor, recommended at input supply pin VCC1 and 1-μF bypass capacitor, recommended at
output supply pin VCC2, provide the large transient currents necessary during a switching transition to ensure
reliable operation. The 220 pF blanking capacitor disables DESAT detection during the off-to-on transition of the
power device. The DESAT diode (DDST) and its 1-kΩ series resistor are external protection components. The RG
gate resistor limits the gate charge current and indirectly controls the IGBT collector voltage rise and fall times.
The open-drain FLT output and RDY output has a passive 10-kΩ pull-up resistor. In this application, the IGBT
gate driver is disabled when a fault is detected and will not resume switching until the micro-controller applies a
reset signal.
10 R
10 R
15
VCC1
ISO 5451 ± Q1
VCC2
15
5
1µF
0 . 1 µF
3 V- 5. 5 V
15 V
9 ,16
GND 1
5
VCC2
VCC1
1 µF
GND 2
3 V - 5.5 V
ISO 5451 ± Q1
0.1 µF
15 V
9 , 16
3
3
GND 1
GND 2
1µF
10
10 k
10 k
IN +
VEE2
10
1, 8
D DST
1 kŸ
11
12
IN -
DESAT
RDY
CLAMP
2
10 k
10 k
12
7
RG
13
14
FLT
OUT
RST
NC
6
13
4
14
VEE2
IN -
DESAT
RDY
CLAMP
FLT
OUT
RST
NC
2
DDST
1 NŸ
7
RG
6
4
Copyright © 2016, Texas Instruments Incorporated
Copyright © 2016, Texas Instruments Incorporated
Figure 43. Unipolar Output Supply
IN +
220 pF
220
pF
22
11
15 V
1, 8
Figure 44. Bipolar Output Supply
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10.2.2.2 FLT and RDY Pin Circuitry
There is 50k pull-up resistor internally on FLT and RDY pins. The FLT and RDY pin is an open-drain output. A
10-kΩ pull-up resistor can be used to make it faster rise and to provide logic high when FLT and RDY is inactive,
as shown in Figure 45.
Fast common mode transients can inject noise and glitches on FLT and RDY pins due to parasitic coupling. This
is dependent on board layout. If required, additional capacitance (100 pF to 300 pF) can be included on the FLT
and RDY pins.
10 R
ISO 5451 ± Q1
15
VCC1
0. 1 µ F
3 V - 5V
9 , 16
GND 1
10 k
10 k
12
RDY
13
FLT
µC
14
RST
10
IN +
11
IN Copyright © 2016, Texas Instruments Incorporated
Figure 45. FLT and RDY Pin Circuitry for High CMTI
10.2.2.3 Driving the Control Inputs
The amount of common-mode transient immunity (CMTI) can be curtailed by the capacitive coupling from the
high-voltage output circuit to the low-voltage input side of the ISO5451-Q1. For maximum CMTI performance, the
digital control inputs, IN+ and IN-, must be actively driven by standard CMOS, push-pull drive circuits. This type
of low-impedance signal source provides active drive signals that prevent unwanted switching of the ISO5451-Q1
output under extreme common-mode transient conditions. Passive drive circuits, such as open-drain
configurations using pull-up resistors, must be avoided. There is a 20 ns glitch filter which can filter a glitch up to
20 ns on IN+ or IN-.
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10.2.2.4 Local Shutdown and Reset
In applications with local shutdown and reset, the FLT output of each gate driver is polled separately, and the
individual reset lines are asserted low independently to reset the motor controller after a fault condition.
10 R
15
ISO 5451 ± Q1
10 R
VCC1
0 . 1 µF
3 V - 5V
9 , 16
10 k
ISO 5451 ± Q1
VCC1
0 . 1 µF
3 V- 5V
9 , 16
GND
10 k
10 k
12
15
GND
10 k
12
RDY
13
13
FLT
RDY
FLT
µC
µC
14
14
RST
10
10
RST
IN +
IN +
11
11
IN -
IN -
Copyright © 2016, Texas Instruments Incorporated
Figure 46. Local Shutdown and Reset for Noninverting (left) and Inverting Input Configuration (right)
10.2.2.5 Global-Shutdown and Reset
When configured for inverting operation, the ISO5451-Q1 can be configured to shutdown automatically in the
event of a fault condition by tying the FLT output to IN+. For high reliability drives, the open drain FLT outputs of
multiple ISO5451-Q1 devices can be wired together forming a single, common fault bus for interfacing directly to
the micro-controller. When any of the six gate drivers of a three-phase inverter detects a fault, the active low FLT
output disables all six gate drivers simultaneously.
10 R
ISO 5451 - Q1
15
VCC1
0 .1 µF
3 V- 5V
9 , 16
10 k
GND 1
10 k
12
13
RDY
FLT
µC
14
10
11
to other
to other
RSTs
FLTs
RST
IN +
IN -
Copyright © 2016, Texas Instruments Incorporated
Figure 47. Global Shutdown with Inverting Input Configuration
24
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10.2.2.6 Auto-Reset
In this case, the gate control signal at IN+ is also applied to the RST input to reset the fault latch every switching
cycle. Incorrect RST makes output go low. A fault condition, however, the gate driver remains in the latched fault
state until the gate control signal changes to the 'gate low' state and resets the fault latch.
If the gate control signal is a continuous PWM signal, the fault latch will always be reset before IN+ goes high
again. This configuration protects the IGBT on a cycle by cycle basis and automatically resets before the next
'on' cycle.
10 R
15
10 k
VCC1
0. 1 µ F
3 V - 5V
9 , 16
9 , 16
GND 1
10 k
10 k
12
ISO 5451 - Q1
15
VCC1
0. 1 µ F
3 V- 5V
10 R
ISO 5451 - Q1
10 k
12
RDY
13
13
FLT
µC
GND 1
RDY
FLT
µC
14
10
11
14
RST
10
IN +
RST
IN +
11
IN -
IN Copyright © 2016, Texas Instruments Incorporated
Figure 48. Auto Reset for Non-inverting and Inverting Input Configuration
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10.2.2.7 DESAT Pin Protection
Switching inductive loads causes large instantaneous forward voltage transients across the freewheeling diodes
of IGBTs. These transients result in large negative voltage spikes on the DESAT pin which draw substantial
current out of the device. To limit this current below damaging levels, a 100-Ω to 1-kΩ resistor is connected in
series with the DESAT diode.
Further protection is possible through an optional Schottky diode, whose low forward voltage assures clamping of
the DESAT input to GND2 potential at low voltage levels.
ISO 5451 ± Q1
VCC2
5
1 µF
15 V
GND 2
3
1 µF
VEE2
DESAT
15 V
1, 8
2
DDST
RS
7
CLAMP
OUT
RG
6
V FW-Inst
4
NC
220 pF
VFW
Copyright © 2016, Texas Instruments Incorporated
Figure 49. DESAT Pin Protection with Series Resistor and Schottky Diode
10.2.2.8 DESAT Diode and DESAT Threshold
The DESAT diode’s function is to conduct forward current, allowing sensing of the IGBT’s saturated collector-toemitter voltage, V(CESAT), (when the IGBT is "on") and to block high voltages (when the IGBT is "off"). During the
short transition time when the IGBT is switching, there is commonly a high dVCE/dt voltage ramp rate across the
IGBT. This results in a charging current I(CHARGE) = C(D-DESAT) x dVCE/dt, charging the blanking capacitor. C(D-DESAT)
is the diode capacitance at DESAT.
To minimize this current and avoid false DESAT triggering, fast switching diodes with low capacitance are
recommended. As the diode capacitance builds a voltage divider with the blanking capacitor, large collector
voltage transients appear at DESAT attenuated by the ratio of 1+ C(BLANK) / C(D-DESAT).
Because the sum of the DESAT diode forward-voltage and the IGBT collector-emitter voltage make up the
voltage at the DESAT-pin, VF + VCE = V(DESAT), the VCE level, which triggers a fault condition, can be modified by
adding multiple DESAT diodes in series: VCE-FAULT(TH) = 9 V – n x VF (where n is the number of DESAT diodes).
When using two diodes instead of one, diodes with half the required maximum reverse-voltage rating may be
chosen.
26
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10.2.2.9 Determining the Maximum Available, Dynamic Output Power, POD-max
The ISO5451-Q1 maximum allowed total power consumption of PD = 251 mW consists of the total input power,
PID, the total output power, POD, and the output power under load, POL:
PD = PID + POD + POL
(1)
PID = VCC1-max × ICC1-max = 5.5 V × 4.5 mA = 24.75 mW
(2)
POD = (VCC2 – VEE2) x ICC2-max = (15V – ( –8V)) × 6 mA = 138 mW
(3)
POL = PD – PID – POD = 251 mW – 24.75 mW – 138 mW = 88.25 mW
(4)
With:
and:
then:
In comparison to POL, the actual dynamic output power under worst case condition, POL-WC, depends on a variety
of parameters:
POL-WC = 0.5 ´ fINP ´ QG ´
(VCC2
æ ron-max
ö
roff-max
+
- VEE2 ) ´ ç
÷
r
+
R
r
+
R
G
off-max
G ø
è on-max
where
•
•
•
•
•
•
•
fINP = signal frequency at the control input IN+
QG = power device gate charge
VCC2 = positive output supply with respect to GND2
VEE2 = negative output supply with respect to GND2
ron-max = worst case output resistance in the on-state: 4Ω
roff-max = worst case output resistance in the off-state: 2.5Ω
RG = gate resistor
(5)
Once RG is determined, Equation 5 is to be used to verify whether POL-WC < POL. Figure 50 shows a simplified
output stage model for calculating POL-WC.
ISO 5451 - Q1 VCC2
ron-max
OUT
15 V
RG
QG
roff-max
8V
VEE2
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Figure 50. Simplified Output Model for Calculating POL-WC
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10.2.2.10 Example
This examples considers an IGBT drive with the following parameters:
ION-PK = 2 A, QG = 650 nC, fINP = 20 kHz, VCC2 = 15V, VEE2 = –8 V
(6)
Apply the value of the gate resistor RG = 10 Ω.
Then, calculating the worst-case output power consumption as a function of RG, using Equation 5 ron-max = worst
case output resistance in the on-state: 4Ω, roff-max = worst case output resistance in the off-state: 2.5Ω, RG = gate
resistor yields
4Ω
2.5 Ω
æ
ö
POL-WC = 0.5 ´ 20 kHz ´ 650 nC ´ (15 V - ( - 8 V) )´ ç
+
÷ = 72.61 mW
è 4 Ω + 10 Ω 2.5 Ω + 10 Ω ø
(7)
Because POL-WC = 72.61 mW is below the calculated maximum of POL = 88.25 mW, the resistor value of RG = 10
Ω is suitable for this application.
28
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10.2.2.11 Higher Output Current Using an External Current Buffer
To increase the IGBT gate drive current, a non-inverting current buffer (such as the npn/pnp buffer shown in
Figure 51) may be used. Inverting types are not compatible with the desaturation fault protection circuitry and
must be avoided. The MJD44H11/MJD45H11 pair is appropriate for currents up to 8 A, the D44VH10/ D45VH10
pair for up to 15 A maximum.
ISO 5451 ± Q1
VCC2
5
1 µF
15 V
GND 2
3
1 µF
VEE2
1,8
1 NŸ
DESAT
CLAMP
OUT
NC
15 V
DDST
2
7
rG
10 Ÿ
6
4
220 pF
Copyright © 2016, Texas Instruments Incorporated
Figure 51. Current Buffer for Increased Drive Current
10.2.3 Application Curve
CL = 1 nF
VCC2 - GND2 = 15 V
(VCC2 - VEE2 = 23 V)
CL = 1 nF
RG = 10 Ω
VCC2 - VEE2 = VCC2 - GND2 = 20 V
RG = 10 Ω
GND2 - VEE2 = 8 V
Figure 52. Normal Operation - Bipolar Supply
Figure 53. Normal Operation - Unipolar Supply
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11 Power Supply Recommendations
To ensure reliable operation at all data rates and supply voltages, a 0.1-μF bypass capacitor is recommended at
input supply pin VCC1 and 1-μF bypass capacitor is recommended at output supply pin VCC2. The capacitors
should be placed as close to the supply pins as possible. Recommended placement of capacitors needs to be
2-mm maximum from input and output power supply pin (VCC1 and VCC2).
12 Layout
12.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 54). Layer stacking should
be in the following order (top-to-bottom): high-current or sensitive signal layer, ground plane, power plane and
low-frequency signal layer.
• Routing the high-current or sensitive traces on the top layer avoids the use of vias (and the introduction of
their inductances) and allows for clean interconnects between the gate driver and the microcontroller and
power transistors. Gate driver control input, Gate driver output OUT and DESAT should be routed in the top
layer.
• Placing a solid ground plane next to the sensitive signal layer provides an excellent low-inductance path for
the return current flow. On the driver side, use GND2 as the ground plane.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/inch2. On the gate-driver VEE2 and VCC2 can be used as power planes. They can share
the same layer on the PCB as long as they are not connected together.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
For more detailed layout recommendations, including placement of capacitors, impact of vias, reference planes,
routing etc. see Application Note SLLA284, Digital Isolator Design Guide.
12.2 PCB Material
For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace
lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper
alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength and
stiffness, and the self-extinguishing flammability-characteristics.
12.3 Layout Example
High-speed traces
10 mils
Ground plane
40 mils
Keep this
space free
from planes,
traces, pads,
and vias
FR-4
0r ~ 4.5
Power plane
10 mils
Low-speed traces
Figure 54. Recommended Layer Stack
30
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation see the following:
• ISO5851 Evaluation Module (EVM) User’s Guide, SLLU218
• Digital Isolator Design Guide, SLLA284
• Isolation Glossary (SLLA353)
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
DW0016B
SOIC - 2.65 mm max height
SCALE 1.500
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 1.27
16
1
2X
8.89
10.5
10.1
NOTE 3
8
9
0.51
0.31
0.25
C A
16X
7.6
7.4
NOTE 4
B
2.65 MAX
B
0.38
TYP
0.25
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 -8
1.27
0.40
DETAIL A
(1.4)
TYPICAL
4221009/A 08/2013
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MO-013, variation AA.
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EXAMPLE BOARD LAYOUT
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
16X (1.65)
SEE
DETAILS
1
SEE
DETAILS
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
0.07 MAX
ALL AROUND
METAL
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221009/A 08/2013
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (2)
1
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
(9.3)
(9.75)
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4221009/A 08/2013
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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PACKAGE OPTION ADDENDUM
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2-Oct-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ISO5451QDWQ1
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO5451Q
ISO5451QDWRQ1
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO5451Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
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provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
2-Oct-2016
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ISO5451-Q1 :
• Catalog: ISO5451
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Oct-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
ISO5451QDWRQ1
Package Package Pins
Type Drawing
SOIC
DW
16
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
16.4
Pack Materials-Page 1
10.75
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
10.7
2.7
12.0
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Oct-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ISO5451QDWRQ1
SOIC
DW
16
2000
367.0
367.0
38.0
Pack Materials-Page 2
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