TI1 LP2996MRX/NOPB Ddr termination regulator Datasheet

LP2996-N
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LP2996-N DDR Termination Regulator
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FEATURES
DESCRIPTION
•
•
•
•
•
•
•
•
The LP2996-N linear regulator is designed to meet
the JEDEC SSTL-2 specifications for termination of
DDR-SDRAM. The device contains a high-speed
operational amplifier to provide excellent response to
load transients. The output stage prevents shoot
through while delivering 1.5A continuous current and
transient peaks up to 3A in the application as
required for DDR-SDRAM termination. The LP2996-N
also incorporates a VSENSE pin to provide superior
load regulation and a VREF output as a reference for
the chipset and DIMMs.
1
2
Source and Sink Current
Low Output Voltage Offset
No External Resistors Required
Linear Topology
Suspend to Ram (STR) Functionality
Low External Component Count
Thermal Shutdown
Available in SOIC-8, SO PowerPAD-8 or
WQFN-16 packages
An additional feature found on the LP2996-N is an
active low shutdown (SD) pin that provides Suspend
To RAM (STR) functionality. When SD is pulled low
the VTT output will tri-state providing a high
impedance output, but, VREF will remain active. A
power savings advantage can be obtained in this
mode through lower quiescent current.
APPLICATIONS
•
•
•
DDR-I and DDR-II Termination Voltage
SSTL-2 and SSTL-3 Termination
HSTL Termination
Typical Application Circuit
LP2996
VREF = 1.25V
VREF
SD
SD
+
0.01PF
VDDQ = 2.5V
VDDQ
VDD = 2.5V
AVIN
VSENSE
PVIN
VTT
+
PF
GND
VTT = 1.25V
+
220PF
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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LP2996-N
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4
3
GND
2
N/C
SD
N/C
Connection Diagram
5
1
16
N/C
6
15
VREF
VDDQ
7
VSENSE
14
N/C
VTT
VTT
13
12
N/C
9
10
11
N/C
AVIN
PVIN
8
1
8
VTT
SD
VSENSE
2
7
PVIN
3
6
VREF
4
5
AVIN
VDDQ
Figure 2. SOIC-8 Layout
PVIN
GND
GND
GND
1
8
VTT
SD
VSENSE
2
7
PVIN
3
6
VREF
4
5
AVIN
VDDQ
GND
Figure 1. WQFN-16 Layout (Top View)
Figure 3. SO PowerPAD-8 Layout
PIN DESCRIPTIONS
SOIC-8 Pin
or SO
PowerPAD-8
Pin
WQFN Pin
Name
1
2
GND
2
4
SD
3
5
VSENSE
4
7
VREF
Buffered internal reference voltage of VDDQ/2
5
8
VDDQ
Input for internal reference equal to VDDQ/2
6
10
AVIN
Analog input pin
7
11, 12
PVIN
Power input pin
8
14, 15
VTT
Output voltage for connection to termination resistors
-
1, 3, 6, 9, 13, 16
NC
No internal connection
EP
EP
Exposed pad thermal connection. Connect to Ground.
Function
Ground
Shutdown
Feedback pin for regulating VTT.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2)
AVIN to GND
−0.3V to +6V
PVIN to GND
-0.3V to AVIN
VDDQ (3)
−0.3V to +6V
−65°C to +150°C
Storage Temp. Range
Junction Temperature
150°C
SOIC-8 Thermal Resistance (θJA)
151°C/W
SO PowerPAD-8 Thermal Resistance (θJA)
43°C/W
WQFN-16 Thermal Resistance (θJA)
51°C/W
Lead Temperature (Soldering, 10 sec)
260°C
ESD Rating (4)
(1)
(2)
(3)
(4)
2
1kV
Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating range indicates conditions for which
the device is intended to be functional, but does not ensure specific performance limits. For ensured specifications and test conditions
see Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
VDDQ voltage must be less than 2 x (AVIN - 1) or 6V, whichever is smaller.
The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin.
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Operating Range
Junction Temp. Range (1)
0°C to +125°C
AVIN to GND
2.2V to 5.5V
PVIN Supply Voltage
0 to AVIN
SD Input Voltage
0 to AVIN
(1)
At elevated temperatures, devices must be derated based on thermal resistance. The device in the SOIC-8 package must be derated at
θJA = 151.2° C/W junction to ambient with no heat sink.
Electrical Characteristics
Specifications with standard typeface are for TJ = 25°C and limits in boldface type apply over the full Operating
Temperature Range (TJ = 0°C to +125°C) (1). Unless otherwise specified, AVIN = PVIN = 2.5V, VDDQ = 2.5V (2).
Symbol
VREF
Parameter
VREF Voltage
Conditions
VIN = VDDQ = 2.3V
VIN = VDDQ = 2.5V
VIN = VDDQ = 2.7V
Min
Typ
Max
Units
1.135
1.235
1.335
1.158
1.258
1.358
1.185
1.285
1.385
V
ZVREF
VREF Output Impedance
IREF = -30 to +30 μA
VTT
VTT Output Voltage
IOUT = 0A
VIN = VDDQ = 2.3V
VIN = VDDQ = 2.5V
VIN = VDDQ = 2.7V
1.125
1.225
1.325
1.159
1.259
1.359
1.190
1.290
1.390
IOUT = ±1.5A (3)
VIN = VDDQ = 2.3V
VIN = VDDQ = 2.5V
VIN = VDDQ = 2.7V
1.125
1.225
1.325
1.159
1.259
1.359
1.190
1.290
1.390
-20
-25
-25
0
0
0
20
25
25
320
500
VosTT/VTT
VTT Output Voltage Offset
(VREF-VTT)
IOUT = 0A
IOUT = -1.5A (3)
IOUT = +1.5A (3)
IQ
Quiescent Current (4)
IOUT = 0A (1)
ZVDDQ
VDDQ Input Impedance
ISD
Quiescent Current in
Shutdown (4)
SD = 0V
IQ_SD
Shutdown Leakage Current
SD = 0V
VIH
Minimum Shutdown High
Level
VIL
Maximum Shutdown Low
Level
IV
VTT Leakage Current in
Shutdown
ISENSE
VSENSE Input Current
TSD
Thermal Shutdown
TSD_HYS
Thermal Shutdown Hysteresis
(1)
(2)
(3)
(4)
(5)
2.5
kΩ
100
V
mV
µA
kΩ
115
150
µA
2
5
µA
1.9
SD = 0V
VTT = 1.25V
See (5)
V
1
0.8
V
10
µA
13
nA
165
Celcius
10
Celcius
Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using
Statistical Quality Control (SQC) methods. The limits are used to calculate Texas Instruments' Average Outgoing Quality Level (AOQL).
VIN is defined as VIN = AVIN = PVIN.
VTT load regulation is tested by using a 10 ms current pulse and measuring VTT.
Quiescent current defined as the current flow into AVIN.
The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction to ambient thermal
resistance, θJA, and the ambient temperature, TA. Exceeding the maximum allowable power dissipation will cause excessive die
temperature and the regulator will go into thermal shutdown.
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Typical Performance Characteristics
Iq vs AVIN
1050
350
900
300
750
250
600
IQ (uA)
IQ (uA)
Iq vs AVIN in SD
400
200
450
150
300
100
150
50
0
2
2.5
3
3.5
4
4.5
5
5.5
2
2.5
3
3.5
4
4.5
AVIN (V)
AVIN (V)
Figure 4.
Figure 5.
VIH and VIL
5
5.5
20
30
VREF vs IREF
4
1.40
3.5
1.35
3
VREF (V)
VSD (V)
1.30
2.5
2
1.25
1.20
1.5
1.15
1
0.5
2
2.5
3
3.5
4
4.5
5
1.10
-30
5.5
-20
-10
AVIN (V)
IREF (uA)
Figure 7.
VTT vs IOUT
1.275
2.5
1.270
2
1.265
VTT (V)
VREF (V)
VREF vs VDDQ
1.5
1.255
0.5
1.250
0
4
1.260
1
1
2
10
Figure 6.
3
0
0
3
4
5
6
1.245
-100 -75
-50
-25
0
25
VDDQ (V)
IOUT (mA)
Figure 8.
Figure 9.
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50
75
100
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Typical Performance Characteristics (continued)
VTT vs VDDQ
Iq vs AVIN in SD Temperature
400
3
350
2.5
0oC
300
IQ (uA)
VTT (V)
2
1.5
125oC
250
200
1
150
0.5
100
50
0
0
1
2
3
4
5
2
6
2.5
3
3.5
4
4.5
5
5.5
AV IN (V)
VDDQ (V)
Figure 10.
Figure 11.
Iq vs AVIN Temperature
Maximum Sourcing Current vs AVIN
(VDDQ = 2.5V, PVIN = 1.8V)
1.4
1050
85oC
1.2
IQ (uA)
750
OUTPUT CURRENT (A)
900
25oC
600
0oC
450
300
1
0.8
0.6
0.4
0.2
150
0
0
2
2.5
3
3.5
4
4.5
5
2
5.5
2.5
AVIN (V)
3
3.5
4
4.5
5
5.5
AVIN (V)
Figure 12.
Figure 13.
Maximum Sourcing Current vs AVIN
(VDDQ = 2.5V, PVIN = 2.5V)
Maximum Sourcing Current vs AVIN
(VDDQ = 2.5V, PVIN = 3.3V)
1.8
3
1.7
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
2.8
1.6
1.5
1.4
1.3
2.6
2.4
2.2
1.2
1.1
2
2
2.5
3
3.5
4
4.5
5
5.5
AVIN (V)
3
3.5
4
4.5
5
5.5
AVIN (V)
Figure 14.
Figure 15.
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Typical Performance Characteristics (continued)
Maximum Sourcing Current vs AVIN
(VDDQ = 1.8V, PVIN = 1.8V)
3.0
1.4
2.8
1.2
2.6
1
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Maximum Sinking Current vs AVIN
(VDDQ = 2.5V)
2.4
2.2
2.0
1.8
0.8
0.6
0.4
0.2
1.6
0
2
2.5
3
3.5
4
4.5
5
5.5
2
2.5
3
3.5
AVIN (V)
4
4.5
5
5.5
AVIN (V)
Figure 16.
Figure 17.
Maximum Sinking Current vs AVIN
(VDDQ = 1.8V)
Maximum Sourcing Current vs AVIN
(VDDQ = 1.8V, PVIN = 3.3V)
2.4
3
2.2
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
2.8
2
1.8
1.6
1.4
2.6
2.4
2.2
1.2
1
2
2
2.5
3
3.5
4
4.5
5
5.5
3
3.5
4
AVIN (V)
4.5
5
5.5
AVIN (V)
Figure 18.
Figure 19.
BLOCK DIAGRAM
VDDQ
SD
AVIN
PVIN
50k
VREF
+
-
50k
+
VTT
VSENSE
GND
6
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Description
The LP2996-N is a linear bus termination regulator designed to meet the JEDEC requirements of SSTL-2. The
output, VTT is capable of sinking and sourcing current while regulating the output voltage equal to VDDQ / 2. The
output stage has been designed to maintain excellent load regulation while preventing shoot through. The
LP2996-N also incorporates two distinct power rails that separates the analog circuitry from the power output
stage. This allows a split rail approach to be utilized to decrease internal power dissipation. It also permits the
LP2996-N to provide a termination solution for the next generation of DDR-SDRAM memory (DDRII). For new
designs, the LP2997 or LP2998 is recommended for DDR-II applications. The LP2996-N can also be used to
provide a termination voltage for other logic schemes such as SSTL-3 or HSTL.
Series Stub Termination Logic (SSTL) was created to improve signal integrity of the data transmission across the
memory bus. This termination scheme is essential to prevent data error from signal reflections while transmitting
at high frequencies encountered with DDR-SDRAM. The most common form of termination is Class II single
parallel termination. This involves one RS series resistor from the chipset to the memory and one RT termination
resistor. Typical values for RS and RT are 25 Ohms, although these can be changed to scale the current
requirements from the LP2996-N. This implementation can be seen below in Figure 20.
VDD
VTT
RT
RS
MEMORY
CHIPSET
VREF
Figure 20. SSTL-Termination Scheme
PIN DESCRIPTIONS
AVIN AND PVIN
AVIN and PVIN are the input supply pins for the LP2996-N. AVIN is used to supply all the internal control
circuitry. PVIN, however, is used exclusively to provide the rail voltage for the output stage used to create VTT.
These pins have the capability to work off separate supplies depending on the application. Higher voltages on
PVIN will increase the maximum continuous output current because of output RDSON limitations at voltages
close to VTT. The disadvantage of high values of PVIN is that the internal power loss will also increase, thermally
limiting the design. For SSTL-2 applications, a good compromise would be to connect the AVIN and PVIN
directly together at 2.5V. This eliminates the need for bypassing the two supply pins separately. The only
limitation on input voltage selection is that PVIN must be equal to or lower than AVIN. It is recommended to
connect PVIN to voltage rails equal to or less than 3.3V to prevent the thermal limit from tripping because of
excessive internal power dissipation. If the junction temperature exceeds the thermal shutdown than the part will
enter a shutdown state identical to the manual shutdown where VTT is tri-stated and VREF remains active.
VDDQ
VDDQ is the input used to create the internal reference voltage for regulating VTT. The reference voltage is
generated from a resistor divider of two internal 50kΩ resistors. This ensures that VTT will track VDDQ / 2
precisely. The optimal implementation of VDDQ is as a remote sense. This can be achieved by connecting
VDDQ directly to the 2.5V rail at the DIMM instead of AVIN and PVIN. This ensures that the reference voltage
tracks the DDR memory rails precisely without a large voltage drop from the power lines. For SSTL-2
applications VDDQ will be a 2.5V signal, which will create a 1.25V termination voltage at VTT (See Electrical
Characteristics Table for exact values of VTT over temperature).
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VSENSE
The purpose of the sense pin is to provide improved remote load regulation. In most motherboard applications
the termination resistors will connect to VTT in a long plane. If the output voltage was regulated only at the output
of the LP2996-N then the long trace will cause a significant IR drop resulting in a termination voltage lower at
one end of the bus than the other. The VSENSE pin can be used to improve this performance, by connecting it to
the middle of the bus. This will provide a better distribution across the entire termination bus. If remote load
regulation is not used then the VSENSE pin must still be connected to VTT. Care should be taken when a long
VSENSE trace is implemented in close proximity to the memory. Noise pickup in the VSENSE trace can cause
problems with precise regulation of VTT. A small 0.1uF ceramic capacitor placed next to the VSENSE pin can help
filter any high frequency signals and preventing errors.
SHUTDOWN
The LP2996-N contains an active low shutdown pin that can be used to tri-state VTT. During shutdown VTT
should not be exposed to voltages that exceed AVIN. With the shutdown pin asserted low the quiescent current
of the LP2996-N will drop, however, VDDQ will always maintain its constant impedance of 100kΩ for generating
the internal reference. Therefore to calculate the total power loss in shutdown both currents need to be
considered. For more information refer to the Thermal Dissipation section. The shutdown pin also has an internal
pull-up current, therefore to turn the part on the shutdown pin can either be connected to AVIN or left open.
VREF
VREF provides the buffered output of the internal reference voltage VDDQ / 2. This output should be used to
provide the reference voltage for the Northbridge chipset and memory. Since these inputs are typically an
extremely high impedance, there should be little current drawn from VREF. For improved performance, an output
bypass capacitor can be used, located close to the pin, to help with noise. A ceramic capacitor in the range of
0.1 µF to 0.01 µF is recommended. This output remains active during the shutdown state and thermal shutdown
events for the suspend to RAM functionality.
VTT
VTT is the regulated output that is used to terminate the bus resistors. It is capable of sinking and sourcing
current while regulating the output precisely to VDDQ / 2. The LP2996-N is designed to handle peak transient
currents of up to ± 3A with a fast transient response. The maximum continuous current is a function of VIN and
can be viewed in the Typical Performance Characteristics section. If a transient is expected to last above the
maximum continuous current rating for a significant amount of time then the output capacitor should be sized
large enough to prevent an excessive voltage drop. Despite the fact that the LP2996-N is designed to handle
large transient output currents it is not capable of handling these for long durations, under all conditions. The
reason for this is the standard packages are not able to thermally dissipate the heat as a result of the internal
power loss. If large currents are required for longer durations, then care should be taken to ensure that the
maximum junction temperature is not exceeded. Proper thermal derating should always be used (please refer to
the Thermal Dissipation section). If the junction temperature exceeds the thermal shutdown point than VTT will tristate until the part returns below the hysteretic trip-point.
8
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COMPONENT SELECTIONS
INPUT CAPACITOR
The LP2996-N does not require a capacitor for input stability, but it is recommended for improved performance
during large load transients to prevent the input rail from dropping. The input capacitor should be located as
close as possible to the PVIN pin. Several recommendations exist dependent on the application required. A
typical value recommended for AL electrolytic capacitors is 50 µF. Ceramic capacitors can also be used, a value
in the range of 10 µF with X5R or better would be an ideal choice. The input capacitance can be reduced if the
LP2996-N is placed close to the bulk capacitance from the output of the 2.5V DC-DC converter. If the two supply
rails (AVIN and PVIN) are separated then the 47uF capacitor should be placed as close to possible to the PVIN
rail. An additional 0.1uF ceramic capacitor can be placed on the AVIN rail to prevent excessive noise from
coupling into the device.
OUTPUT CAPACITOR
The LP2996-N has been designed to be insensitive of output capacitor size or ESR (Equivalent Series
Resistance). This allows the flexibility to use any capacitor desired. The choice for output capacitor will be
determined solely on the application and the requirements for load transient response of VTT. As a general
recommendation the output capacitor should be sized above 100 µF with a low ESR for SSTL applications with
DDR-SDRAM. The value of ESR should be determined by the maximum current spikes expected and the extent
at which the output voltage is allowed to droop. Several capacitor options are available on the market and a few
of these are highlighted below:
AL - It should be noted that many aluminum electrolytics only specify impedance at a frequency of 120 Hz, which
indicates they have poor high frequency performance. Only aluminum electrolytics that have an impedance
specified at a higher frequency (between 20 kHz and 100 kHz) should be used for the LP2996-N. To improve the
ESR several AL electrolytics can be combined in parallel for an overall reduction. An important note to be aware
of is the extent at which the ESR will change over temperature. Aluminum electrolytic capacitors can have their
ESR rapidly increase at cold temperatures.
Ceramic - Ceramic capacitors typically have a low capacitance, in the range of 10 to 100 µF range, but they have
excellent AC performance for bypassing noise because of very low ESR (typically less than 10 mΩ). However,
some dielectric types do not have good capacitance characteristics as a function of voltage and temperature.
Because of the typically low value of capacitance it is recommended to use ceramic capacitors in parallel with
another capacitor such as an aluminum electrolytic. A dielectric of X5R or better is recommended for all ceramic
capacitors.
Hybrid - Several hybrid capacitors such as OS-CON and SP are available from several manufacturers. These
offer a large capacitance while maintaining a low ESR. These are the best solution when size and performance
are critical, although their cost is typically higher than any other capacitor.
Thermal Dissipation
Since the LP2996-N is a linear regulator any current flow from VTT will result in internal power dissipation
generating heat. To prevent damaging the part from exceeding the maximum allowable junction temperature,
care should be taken to derate the part dependent on the maximum expected ambient temperature and power
dissipation. The maximum allowable internal temperature rise (TRmax) can be calculated given the maximum
ambient temperature (TAmax) of the application and the maximum allowable junction temperature (TJmax).
TRmax = TJmax − TAmax
(1)
From this equation, the maximum power dissipation (PDmax) of the part can be calculated:
PDmax = TRmax / θJA
(2)
The θJA of the LP2996-N will be dependent on several variables: the package used; the thickness of copper; the
number of vias and the airflow. For instance, the θJA of the SOIC-8 is 163°C/W with the package mounted to a
standard 8x4 2-layer board with 1oz. copper, no airflow, and 0.5W dissipation at room temperature. This value
can be reduced to 151.2°C/W by changing to a 3x4 board with 2 oz. copper that is the JEDEC standard.
Figure 21 shows how the θJA varies with airflow for the two boards mentioned.
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180
170
160
150
SOP Board
TJA
140
130
120
110
JEDEC Board
100
90
80
0
200
400
600
800
1000
AIRFLOW (Linear Feet per Minute)
Figure 21. θJA vs Airflow (SOIC-8)
Additional improvements can be made by the judicious use of vias to connect the part and dissipate heat to an
internal ground plane. Using larger traces and more copper on the top side of the board can also help. With
careful layout it is possible to reduce the θJA further than the nominal values shown in Figure 21
Layout is also extremely critical to maximize the output current with the WQFN package. By simply placing vias
under the DAP the θJA can be lowered significantly. Figure 22 shows the WQFN thermal data when placed on a
4-layer JEDEC board with copper thickness of 0.5/1/1/0.5 oz. The number of vias, with a pitch of 1.27 mm, has
been increased to the maximum of 4 where a θJA of 50.41°C/W can be obtained. Via wall thickness for this
calculation is 0.036 mm for 1oz. Copper.
100
90
TJA (qC/W)
80
70
60
50
40
0
1
2
3
4
NUMBER OF VIAS
Figure 22. WQFN-16 θJA vs # of Vias (4 Layer JEDEC Board))
Additional improvements in lowering the θJA can also be achieved with a constant airflow across the package.
Maintaining the same conditions as above and utilizing the 2x2 via array, Figure 23 shows how the θJA varies
with airflow.
10
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51
50
qJA (oC/W)
49
48
47
46
45
0
100
200
300
400
500
600
AIRFLOW (Linear Feet Per Minute)
Figure 23. θJA vs Airflow Speed (JEDEC Board with 4 Vias)
Optimizing the θJA and placing the LP2996-N in a section of a board exposed to lower ambient temperature
allows the part to operate with higher power dissipation. The internal power dissipation can be calculated by
summing the three main sources of loss: output current at VTT, either sinking or sourcing, and quiescent current
at AVIN and VDDQ. During the active state (when shutdown is not held low) the total internal power dissipation
can be calculated from the following equations:
PD = PAVIN + PVDDQ + PVTT
where
(3)
PAVIN = IAVIN * VAVIN
PVDDQ = VVDDQ * IVDDQ = VVDDQ2 x RVDDQ
(4)
(5)
To calculate the maximum power dissipation at VTT both conditions at VTT need to be examined, sinking and
sourcing current. Although only one equation will add into the total, VTT cannot source and sink current
simultaneously.
PVTT = VVTT x ILOAD (Sinking) or
PVTT = ( VPVIN - VVTT) x ILOAD (Sourcing
(6)
(7)
The power dissipation of the LP2996-N can also be calculated during the shutdown state. During this condition
the output VTT will tri-state, therefore that term in the power equation will disappear as it cannot sink or source
any current (leakage is negligible). The only losses during shutdown will be the reduced quiescent current at
AVIN and the constant impedance that is seen at the VDDQ pin.
PD = PAVIN + PVDDQ
PAVIN = IAVIN x VAVIN
PVDDQ = VVDDQ * IVDDQ = VVDDQ2 x RVDDQ
(8)
(9)
(10)
Typical Application Circuits
Several different application circuits have been shown in Figure 24 through Figure 33 to illustrate some of the
options that are possible in configuring the LP2996-N. Graphs of the individual circuit performance can be found
in the Typical Performance Characteristics section in the beginning of the datasheet. These curves illustrate how
the maximum output current is affected by changes in AVIN and PVIN.
SSTL-2 APPLICATIONS
For the majority of applications that implement the SSTL-2 termination scheme it is recommended to connect all
the input rails to the 2.5V rail. This provides an optimal trade-off between power dissipation and component count
and selection. An example of this circuit can be seen in Figure 24.
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11
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LP2996
VREF = 1.25V
VREF
SD
SD
+
CREF
VDDQ = 2.5V
VDDQ
VDD = 2.5V
AVIN
VSENSE
PVIN
VTT
+
VTT = 1.25V
+
GND
CIN
COUT
Figure 24. Recommended SSTL-2 Implementation
If power dissipation or efficiency is a major concern then the LP2996-N has the ability to operate on split power
rails. The output stage (PVIN) can be operated on a lower rail such as 1.8V and the analog circuitry (AVIN) can
be connected to a higher rail such as 2.5V, 3.3V or 5V. This allows the internal power dissipation to be lowered
when sourcing current from VTT. The disadvantage of this circuit is that the maximum continuous current is
reduced because of the lower rail voltage, although it is adequate for all motherboard SSTL-2 applications.
Increasing the output capacitance can also help if periods of large load transients will be encountered.
LP2996
VREF = 1.25V
VREF
SD
SD
+
CREF
VDDQ = 2.5V
VDDQ
AVIN = 2.2V to 5.5V
AVIN
VSENSE
PVIN
VTT
PVIN = 1.8V
+
VTT = 1.25V
+
GND
CIN
COUT
Figure 25. Lower Power Dissipation SSTL-2 Implementation
The third option for SSTL-2 applications in the situation that a 1.8V rail is not available and it is not desirable to
use 2.5V, is to connect the LP2996-N power rail to 3.3V. In this situation AVIN will be limited to operation on the
3.3V or 5V rail as PVIN can never exceed AVIN. This configuration has the ability to provide the maximum
continuous output current at the downside of higher thermal dissipation. Care should be taken to prevent the
LP2996-N from experiencing large current levels which cause the junction temperature to exceed the maximum.
Because of this risk it is not recommended to supply the output stage with a voltage higher than a nominal 3.3V
rail.
LP2996
VREF = 1.25V
VREF
SD
SD
+
VDDQ = 2.5V
VDDQ
AVIN = 3.3V or 5V
AVIN
CREF
VSENSE
VTT
PVIN
PVIN = 3.3V
+
CIN
GND
VTT = 1.25V
+
COUT
Figure 26. SSTL-2 Implementation with higher voltage rails
12
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LP2996-N
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SNOSA40J – NOVEMBER 2002 – REVISED MARCH 2013
DDR-II APPLICATIONS
With the separate VDDQ pin and an internal resistor divider it is possible to use the LP2996-N in applications
utilizing DDR-II memory. Figure 25 and Figure 26 show several implementations of recommended circuits with
output curves displayed in the Typical Performance Characteristics. Figure 25 shows the recommended circuit
configuration for DDR-II applications. The output stage is connected to the 1.8V rail and the AVIN pin can be
connected to either a 3.3V or 5V rail. For new designs, the LP2997 or LP2998 is recommended for DDR-II
applications.
LP2996
VREF = 0.9V
VREF
SD
SD
+
VDDQ = 1.8V
VDDQ
AVIN = 2.2V to 5.5V
AVIN
CREF
VSENSE
VTT
PVIN
PVIN = 1.8V
+
CIN
VTT = 0.9V
+
GND
COUT
Figure 27. Recommended DDR-II Termination
If it is not desirable to use the 1.8V rail it is possible to connect the output stage to a 3.3V rail. Care should be
taken to not exceed the maximum junction temperature as the thermal dissipation increases with lower VTT
output voltages. For this reason it is not recommended to power PVIN off a rail higher than the nominal 3.3V.
The advantage of this configuration is that it has the ability to source and sink a higher maximum continuous
current.
LP2996
+
CREF
VDDQ = 1.8V
VDDQ
AVIN = 3.3V or 5.5V
AVIN
VSENSE
PVIN
VTT
PVIN = 3.3V
+
CIN
VREF= 0.9V
VREF
SD
SD
GND
VTT = 0.9V
+
COUT
Figure 28. DDR-II Termination with higher voltage rails
LEVEL SHIFTING
If standards other than SSTL-2 are required, such as SSTL-3, it may be necessary to use a different scaling
factor than 0.5 times VDDQ for regulating the output voltage. Several options are available to scale the output to
any voltage required. One method is to level shift the output by using feedback resistors from VTT to the VSENSE
pin. This has been illustrated in Figure 29 and Figure 30. Figure 29 shows how to use two resistors to level shift
VTT above the internal reference voltage of VDDQ/2. To calculate the exact voltage at VTT the following equation
can be used.
VTT = VDDQ/2 ( 1 + R1/R2)
(11)
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LP2996-N
SNOSA40J – NOVEMBER 2002 – REVISED MARCH 2013
www.ti.com
LP2996
VDDQ
VDDQ
VDD
AVIN
VTT
VTT
R1
PVIN
+
VSENSE
COUT
+
GND
CIN
R2
Figure 29. Increasing VTT by Level Shifting
Conversely, the R2 resistor can be placed between VSENSE and VDDQ to shift the VTT output lower than the
internal reference voltage of VDDQ/2. The equations relating VTT and the resistors can be seen below:
VTT = VDDQ/2 (1 - R1/R2)
(12)
LP2996
VDDQ
VDDQ
VDD
AVIN
R2
VSENSE
R1
VTT
PVIN
VTT
+
+
COUT
GND
CIN
Figure 30. Decreasing VTT by Level Shifting
HSTL APPLICATIONS
The LP2996-N can be easily adapted for HSTL applications by connecting VDDQ to the 1.5V rail. This will
produce a VTT and VREF voltage of approximately 0.75V for the termination resistors. AVIN and PVIN should be
connected to a 2.5V rail for optimal performance.
LP2996
VDDQ = 1.5V
VDDQ
VDD = 2.5V
AVIN
+
CREF
VSENSE
VTT
PVIN
+
CIN
VREF = 0.75V
VREF
SD
SD
GND
VTT = 0.75V
+
COUT
Figure 31. HSTL Application
QDR APPLICATIONS
Quad data rate (QDR) applications utilize multiple channels for improved memory performance. However, this
increase in bus lines has the effect of increasing the current levels required for termination. The recommended
approach in terminating multiple channels is to use a dedicated LP2996-N for each channel. This simplifies
layout and reduces the internal power dissipation for each regulator. Separate VREF signals can be used for each
DIMM bank from the corresponding regulator with the chipset reference provided by a local resistor divider or
one of the LP2996-N signals. Because VREF and VTT are expected to track and the part to part variations are
minor, there should be little difference between the reference signals of each LP2996-N.
14
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LP2996-N
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SNOSA40J – NOVEMBER 2002 – REVISED MARCH 2013
OUTPUT CAPACITOR SELECTION
For applications utilizing the LP2996-N to terminate SSTL-2 I/O signals the typical application circuit shown in
Figure 30 can be implemented.
LP2996
VREF = 1.25V
VREF
SD
SD
+
VDDQ = 2.5V
VDDQ
VDD = 2.5V
AVIN
0.01PF
VSENSE
VTT
PVIN
+
VTT = 1.25V
+
GND
PF
220PF
Figure 32. Typical SSTL-2 Application Circuit
This circuit permits termination in a minimum amount of board space and component count. Capacitor selection
can be varied depending on the number of lines terminated and the maximum load transient. However, with
motherboards and other applications where VTT is distributed across a long plane it is advisable to use multiple
bulk capacitors and addition to high frequency decoupling. Figure 31 shown below depicts an example circuit
where 2 bulk output capacitors could be situated at both ends of the VTT plane for optimal placement. Large
aluminum electrolytic capacitors are used for their low ESR and low cost.
LP2996
SD
VREF = 1.25V
VREF
SD
+
VDDQ = 2.5V
VDDQ
VDD = 2.5V
AVIN
0.01PF
VSENSE
PVIN
+
47PF
VTT
GND
VTT = 1.25V
+
+
330PF
330PF
Figure 33. Typical SSTL-2 Application Circuit for Motherboards
In most PC applications an extensive amount of decoupling is required because of the long interconnects
encountered with the DDR-SDRAM DIMMs mounted on modules. As a result bulk aluminum electrolytic
capacitors in the range of 1000uF are typically used.
PCB Layout Considerations
1. The input capacitor for the power rail should be placed as close as possible to the PVIN pin.
2. VSENSE should be connected to the VTT termination bus at the point where regulation is required. For
motherboard applications an ideal location would be at the center of the termination bus.
3. VDDQ can be connected remotely to the VDDQ rail input at either the DIMM or the Chipset. This provides the
most accurate point for creating the reference voltage.
4. For improved thermal performance excessive top side copper should be used to dissipate heat from the
package. Numerous vias from the ground connection to the internal ground plane will help. Additionally these
can be located underneath the package if manufacturing standards permit.
5. Care should be taken when routing the VSENSE trace to avoid noise pickup from switching I/O signals. A
0.1uF ceramic capacitor located close to the SENSE can also be used to filter any unwanted high frequency
signal. This can be an issue especially if long SENSE traces are used.
6. VREF should be bypassed with a 0.01 µF or 0.1 µF ceramic capacitor for improved performance. This
capacitor should be located as close as possible to the VREF pin.
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15
LP2996-N
SNOSA40J – NOVEMBER 2002 – REVISED MARCH 2013
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REVISION HISTORY
Changes from Revision I (March 2013) to Revision J
•
16
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 15
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PACKAGE OPTION ADDENDUM
www.ti.com
12-Jun-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LP2996LQ/NOPB
ACTIVE
WQFN
NHP
16
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
0 to 125
L00006B
LP2996LQX/NOPB
ACTIVE
WQFN
NHP
16
4500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
0 to 125
L00006B
LP2996M
NRND
SOIC
D
8
95
TBD
Call TI
Call TI
0 to 125
2996M
LP2996M/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
0 to 125
2996M
NRND
SO PowerPAD
DDA
8
95
TBD
Call TI
Call TI
0 to 125
LP2996
ACTIVE SO PowerPAD
DDA
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
0 to 125
LP2996
SO PowerPAD
DDA
8
2500
TBD
Call TI
Call TI
0 to 125
LP2996
ACTIVE SO PowerPAD
DDA
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
0 to 125
LP2996
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
0 to 125
2996M
LP2996MR
LP2996MR/NOPB
LP2996MRX
LP2996MRX/NOPB
LP2996MX/NOPB
NRND
ACTIVE
SOIC
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
12-Jun-2014
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LP2996LQ/NOPB
WQFN
NHP
16
1000
178.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
LP2996LQX/NOPB
WQFN
NHP
16
4500
330.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
LP2996MRX
SO
Power
PAD
DDA
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LP2996MRX/NOPB
SO
Power
PAD
DDA
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LP2996MX/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LP2996LQ/NOPB
WQFN
NHP
16
1000
213.0
191.0
55.0
LP2996LQX/NOPB
WQFN
NHP
16
4500
367.0
367.0
35.0
LP2996MRX
SO PowerPAD
DDA
8
2500
367.0
367.0
35.0
LP2996MRX/NOPB
SO PowerPAD
DDA
8
2500
367.0
367.0
35.0
LP2996MX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DDA0008A
PowerPAD TM SOIC - 1.7 mm max height
SCALE 2.400
PLASTIC SMALL OUTLINE
C
6.2
TYP
5.8
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
6X 1.27
8
1
2X
3.81
5.0
4.8
NOTE 3
4
5
B
8X
4.0
3.8
NOTE 4
0.51
0.31
0.25
1.7 MAX
C A B
0.25
TYP
0.10
SEE DETAIL A
5
4
EXPOSED
THERMAL PAD
0.25
GAGE PLANE
2.34
2.24
8
1
0 -8
0.15
0.00
1.27
0.40
DETAIL A
2.34
2.24
TYPICAL
4218825/A 05/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012.
www.ti.com
EXAMPLE BOARD LAYOUT
DDA0008A
PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.95)
NOTE 9
SOLDER MASK
DEFINED PAD
(2.34)
SOLDER MASK
OPENING
8X (1.55)
SEE DETAILS
1
8
8X (0.6)
SYMM
(1.3)
TYP
(2.34)
SOLDER MASK
OPENING
(4.9)
NOTE 9
6X (1.27)
5
4
(R0.05) TYP
METAL COVERED
BY SOLDER MASK
SYMM
( 0.2) TYP
VIA
(1.3) TYP
(5.4)
LAND PATTERN EXAMPLE
SCALE:10X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218825/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DDA0008A
PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.34)
BASED ON
0.125 THICK
STENCIL
8X (1.55)
(R0.05) TYP
1
8
8X (0.6)
(2.34)
BASED ON
0.125 THICK
STENCIL
SYMM
6X (1.27)
5
4
METAL COVERED
BY SOLDER MASK
SYMM
(5.4)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.125
0.150
0.175
2.62 X 2.62
2.34 X 2.34 (SHOWN)
2.14 X 2.14
1.98 X 1.98
4218825/A 05/2016
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
NHP0016A
LQA16A (REV A)
www.ti.com
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non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
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