ICS840001I-25 FEMTOCLOCK™ LVCMOS/LVTTL CLOCK GENERATOR ICS840001I-25 FEMTOCLOCK™ LVCMOS/LVTTL CLOCK GENERATOR GENERAL DESCRIPTION FEATURES The ICS840001I-25 is a General Purpose Clock ICS Generator and a member of the HiPerClocksTM famHiPerClockS™ ily of high performance devices from IDT. The ICS840001I-25 can accept frequency from a 22.4MHz to 170MHz and generate a 22.4MHz to 170MHz output. The ICS840001I-25 has excellent phase jitter performance, from 637kHz – 10MHz integration range. The ICS840001I-25 is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space. • One LVCMOS/LVTTL output, 15Ω output impedence • Output frequency range: 22.4MHz – 170MHz • VCO range: 560MHz to 680MHz • RMS phase jitter @ 125MHz (637kHz - 10MHz): 0.36ps (typical) • Full 3.3V or 2.5V operating supply • -40°C to 85°C ambient operating temperature • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages COMMONLY USED FREQUENCY TABLE Inputs SEL2 0 SEL1 0 SEL0 0 M Divider 25 0 0 0 1 10 1 0 4 Output Frequency (MHz) N Divider 25 REF_IN (MHz) 25 Q 25 25 62.5 25 25 156.25 25 0 1 1 5 25 125 25 1 0 0 10 10 62.5 62.5 1 0 1 5 5 125 125 1 1 0 4 4 156.25 156.25 1 1 1 10 25 62.5 25 (default) BLOCK DIAGRAM PIN ASSIGNMENT N REF_IN Pullup Phase Detector VCO 560-680MHz ÷4 ÷5 ÷10 ÷25 Q 8 7 6 5 Q VDDO GND SEL_2 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View 3 IDT™ / ICS™ LVCMOS CLOCK GENERATOR 1 2 3 4 ICS840001I-25 M ÷4, ÷5, ÷10, ÷25 SEL_[0:2] Pullup VDD REF_IN SEL_0 SEL_1 1 ICS840001BGI-25 REV. A MARCH 31, 2009 ICS840001I-25 FEMTOCLOCK™ LVCMOS/LVTTL CLOCK GENERATOR TABLE 1. PIN DESCRIPTIONS Number Name 1 VDD Power Type Description 2 REF_IN Input Pullup 3, 4, 5 SEL_0, SEL_1, SEL_2 Input Pullup 6 GND Power 7 VDDO Power Positive supply pin. Reference input frequency. LVCMOS/LVTTL interface levels. M and N configuration select pins. LVCMOS/LVTTL interface levels. Power supply ground. Output supply pin. Single-ended clock output. LVCMOS/LVTTL interface levels. 8 Q Output 15Ω output impedance. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance CPD Power Dissipation Capacitance 5 pF RPULLUP Input Pullup Resistor 51 kΩ ROUT Output Impedance 15 Ω IDT™ / ICS™ LVCMOS CLOCK GENERATOR Test Conditions VDD, VDDO = 3.465V VDD, VDDO = 2.625V 2 Minimum Typical Maximum Units 4 pF 6 pF ICS840001BGI-25 REV. A MARCH 31, 2009 ICS840001I-25 FEMTOCLOCK™ LVCMOS/LVTTL CLOCK GENERATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, θJA 129.5°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Positive Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 83 mA IDDO Output Supply Current 2 mA No Load TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO =2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Positive Supply Voltage 2.375 2.5 2.625 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current IDDO Output Supply Current 80 mA 2 mA Maximum Units No Load TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDO = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current VOH Output High Voltage; NOTE 1 REF_IN, SEL_[0:2] REF_IN, SEL_[0:2] Minimum Typical VDD = 3.465V 2 VDD + 0.3 V VDD = 2.625V 1.7 VDD + 0.3 V VDD = 3.465V -0.3 0.8 V VDD = 2.625V -0.3 0.7 V 5 µA VDD = VIN = 3.465V or 2.625V VDD = 3.465V or 2.625V, VIN = 0V -150 µA VDDO = 3.465V 2.6 V VDDO = 2.625V 1.8 V Output Low Voltage; NOTE 1 VDDO = 3.465V or 2.625V VOL NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information Section, "Output Load Test Circuit" diagrams. IDT™ / ICS™ LVCMOS CLOCK GENERATOR 3 0.6 V ICS840001BGI-25 REV. A MARCH 31, 2009 ICS840001I-25 FEMTOCLOCK™ LVCMOS/LVTTL CLOCK GENERATOR TABLE 4A. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter fOUT Output Frequency tjit(Ø) tR / tF RMS Phase Jitter (Random); NOTE 1 Output Rise/Fall Time Test Conditions Minimum Typical 22.4 125MHz, Integration Range: 637kHz - 10MHz 156.25MHz, Integration Range: 637kHz - 10MHz 20% to 80% odc Output Duty Cycle NOTE 1: Please refer to the Phase Noise Plot. Maximum Units 170 MHz 0.37 ps 0.38 ps 150 650 ps 47 53 % Maximum Units 170 MHz TABLE 4B. AC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter fOUT Output Frequency tjit(Ø) t R / tF RMS Phase Jitter (Random); NOTE 1 Output Rise/Fall Time Test Conditions Typical 22.4 125MHz, Integration Range: 637kHz - 10MHz 156.25MHz, Integration Range: 637kHz - 10MHz 20% to 80% odc Output Duty Cycle NOTE 1: Please refer to the Phase Noise Plot. IDT™ / ICS™ LVCMOS CLOCK GENERATOR Minimum 4 0.36 ps 0.35 ps 150 650 ps 47 53 % ICS840001BGI-25 REV. A MARCH 31, 2009 ICS840001I-25 FEMTOCLOCK™ LVCMOS/LVTTL CLOCK GENERATOR TYPICAL PHASE NOISE AT 125MHZ @ 3.3V 125MHz ➤ RMS Phase Jitter (Random) 637kHz to 10MHz = 0.37ps (typical) NOISE POWER dBc Hz Filter Raw Phase Noise Data ➤ ➤ Phase Noise Result by adding a Filter to raw data OFFSET FREQUENCY (HZ) TYPICAL PHASE NOISE AT 156.25MHZ @ 3.3V 156.25MHz NOISE POWER dBc Hz ➤ RMS Phase Jitter (Random) 637kHz to 10MHz = 0.38ps (typical) Filter Raw Phase Noise Data ➤ ➤ Phase Noise Result by adding a Filter to raw data OFFSET FREQUENCY (HZ) IDT™ / ICS™ LVCMOS CLOCK GENERATOR 5 ICS840001BGI-25 REV. A MARCH 31, 2009 ICS840001I-25 FEMTOCLOCK™ LVCMOS/LVTTL CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION 1.65V ± 5% 1.25V ± 5% SCOPE VDD, VDDO SCOPE VDD, VDDO Qx Qx LVCMOS LVCMOS GND GND -1.65V ± 5% -1.25V ± 5% 3.3V OUTPUT LOAD AC TEST CIRCUIT 2.5V OUTPUT LOAD AC TEST CIRCUIT Noise Power Phase Noise Plot 80% Phase Noise Mask Offset Frequency 20% 20% Q f1 80% tR tF f2 RMS Jitter = Area Under the Masked Phase Noise Plot RMS PHASE JITTER OUTPUT RISE/FALL TIME V DDO 2 Q t PW t odc = PERIOD t PW x 100% t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD IDT™ / ICS™ LVCMOS CLOCK GENERATOR 6 ICS840001BGI-25 REV. A MARCH 31, 2009 ICS840001I-25 FEMTOCLOCK™ LVCMOS/LVTTL CLOCK GENERATOR APPLICATION INFORMATION RECOMMENDATIONS FOR UNUSED INPUT PINS INPUTS: LVCMOS CONTROL PINS: All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. IDT™ / ICS™ LVCMOS CLOCK GENERATOR 7 ICS840001BGI-25 REV. A MARCH 31, 2009 ICS840001I-25 FEMTOCLOCK™ LVCMOS/LVTTL CLOCK GENERATOR POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS840001I-25. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS840001I-25 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. Core and Output Power Dissipation • Power (core, output) = VDD_MAX * (IDD + IDDO) = 3.465V * (83mA + 2mA) = 294.5mW LVCMOS Output Power Dissipation • Output Impedance ROUT Power Dissipation due to Loading 50Ω to VDDO/2 Output Current IOUT = VDDO_MAX / [2 * (50Ω + ROUT)] = 3.465V / [2 * (50Ω + 15Ω)] = 26.6mA • Power Dissipation on the ROUT per LVCMOS output Power (ROUT) = ROUT * (IOUT)2 = 15Ω * (26.6mA)2 = 10.6mW per output • Dynamic Power Dissipation at 156.25MHz Power (156.25MHz) = CPD * Frequency * (VDDO)2 = 6pF * 156.25MHz * (3.465V)2 = 11.26mW per output Total Power Dissipation • Total Power = Power (core, output) + Power Dissipation (ROUT) + Dyamic Power Dissipation (156.25MHz) = 294.5mW + 10.6mW + 11.26mW = 316.4mW IDT™ / ICS™ LVCMOS CLOCK GENERATOR 8 ICS840001BGI-25 REV. A MARCH 31, 2009 ICS840001I-25 FEMTOCLOCK™ LVCMOS/LVTTL CLOCK GENERATOR 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 1meter per second and a multi-layer board, the appropriate value is 125.5°C/W per Table 5. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.316W * 125.5°C/W = 124.7°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (multi-layer). TABLE 5. THERMAL RESISTANCE θJA FOR 8-LEAD TSSOP, FORCED CONVECTION θJA by Velocity (Meters Per Second) Multi-Layer PCB, JEDEC Standard Test Boards IDT™ / ICS™ LVCMOS CLOCK GENERATOR 9 0 1 2.5 129.5°C/W 125.5°C/W 123.5°C/W ICS840001BGI-25 REV. A MARCH 31, 2009 ICS840001I-25 FEMTOCLOCK™ LVCMOS/LVTTL CLOCK GENERATOR RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP θJA by Velocity (Meters Per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 129.5°C/W 125.5°C/W 123.5°C/W TRANSISTOR COUNT The transistor count for ICS840001I-25 is: 2588 PACKAGE OUTLINE AND PACKAGE DIMENSIONS PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP TABLE 7. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N Maximum 8 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 2.90 E E1 3.10 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 IDT™ / ICS™ LVCMOS CLOCK GENERATOR 10 ICS840001BGI-25 REV. A MARCH 31, 2009 ICS840001I-25 FEMTOCLOCK™ LVCMOS/LVTTL CLOCK GENERATOR TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 840001BGI-25 1BI25 8 lead TSSOP tube -40°C to 85°C 840001BGI-25T 1BI25 8 lead TSSOP 2500 tape & reel -40°C to 85°C 840001BGI-25LF BI25L 8 lead "Lead Free" TSSOP tube -40°C to 85°C 840001BGI-25LFT BI25L 8 lead "Lead Free" TSSOP 2500 tape & reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT™ / ICS™ LVCMOS CLOCK GENERATOR 11 ICS840001BGI-25 REV. A MARCH 31, 2009 ICS840001I-25 FEMTOCLOCK™ LVCMOS/LVTTL CLOCK GENERATOR Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support Corporate Headquarters 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT [email protected] +480-763-2056 Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA) © 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA