SCLS169E − DECEMBER 1982 − REVISED APRIL 2004
Operating Voltage Range of 4.5 V to 5.5 V
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 40-µA Max ICC
Typical tpd = 17 ns
±4-mA Output Drive at 5 V
Low Input Current of 1 µA Max
Inputs Are TTL-Voltage Compatible
SN54HCT74 . . . J OR W PACKAGE
SN74HCT74 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
1CLR
1D
1CLK
1PRE
1Q
1Q
GND
description/ordering information
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
2CLR
2D
2CLK
2PRE
2Q
2Q
1D
1CLR
NC
VCC
2CLR
SN54HCT74 . . . FK PACKAGE
(TOP VIEW)
1CLK
NC
1PRE
NC
1Q
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
1Q
GND
NC
The ’HCT74 devices contain two independent
D-type positive-edge-triggered flip-flops. A low
level at the preset (PRE) or clear (CLR) inputs sets
or resets the outputs, regardless of the levels of
the other inputs. When PRE and CLR are inactive
(high), data at the data (D) input meeting the setup
time requirements are transferred to the outputs
on the positive-going edge of the clock (CLK)
pulse. Clock triggering occurs at a voltage level
and is not directly related to the rise time of CLK.
Following the hold-time interval, data at the
D input may be changed without affecting the
levels at the outputs.
1
2D
NC
2CLK
NC
2PRE
2Q
2Q
D
D
D
D
D
D
D
NC − No internal connection
ORDERING INFORMATION
PACKAGE†
TA
PDIP − N
SN74HCT74N
Tube of 50
SN74HCT74D
Reel of 2500
SN74HCT74DR
Reel of 250
SN74HCT74DT
SOP − NS
Reel of 2000
SN74HCT74NSR
HCT74
SSOP − DB
Reel of 2000
SN74HCT74DBR
HT74
Tube of 90
SN74HCT74PW
Reel of 2000
SN74HCT74PWR
TSSOP − PW
−55°C
−55
C to 125
125°C
C
TOP-SIDE
MARKING
Tube of 25
SOIC − D
−40°C
−40
C to 85
85°C
C
ORDERABLE
PART NUMBER
SN74HCT74N
HCT74
HT74
Reel of 250
SN74HCT74PWT
CDIP − J
Tube of 25
SNJ54HCT74J
SNJ54HCT74J
CFP − W
Tube of 150
SNJ54HCT74W
SNJ54HCT74W
LCCC − FK
Tube of 55
SNJ54HCT74FK
SNJ54HCT74FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2004, Texas Instruments Incorporated
!"#$ $%$ $&'"%$ !''#$ % & (!)*%$ %#+ '! $&'" (#&%$ (#' # #'" & #,% $'!"#$ %$%' -%''%$.+
'!$ ('#$/ # $ $##%'*. $*!# #$/ & %**
(%'%"##'+
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SCLS169E − DECEMBER 1982 − REVISED APRIL 2004
FUNCTION TABLE
OUTPUT
INPUTS
PRE
CLR
CLK
D
Q
Q
L
H
X
X
H
L
H
L
X
X
H
H†
L
L
X
X
L
H†
H
H
°
H
H
L
H
H
°
L
L
H
H
H
L
X
Q0
Q0
† This configuration is nonstable; that is, it does not
persist when PRE or CLR returns to its inactive
(high) level.
logic diagram (positive logic)
PRE
CLK
C
C
Q
TG
C
C
C
C
C
D
TG
TG
TG
Q
C
C
C
CLR
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCLS169E − DECEMBER 1982 − REVISED APRIL 2004
recommended operating conditions (see Note 3)
SN54HCT74
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
0
VO
∆t/∆v
Output voltage
0
High-level input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
SN74HCT74
2
2
Input transition rise/fall time
V
V
0.8
VCC
VCC
UNIT
0
0
500
0.8
V
VCC
VCC
V
500
ns
V
TA
Operating free-air temperature
−55
125
−40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
VOH
VI = VIH or VIL
IOH = −20 µA
IOH = −4 mA
4.5 V
VOL
VI = VIH or VIL
IOL = 20 µA
IOL = 4 mA
4.5 V
II
ICC
VI = VCC or 0
VI = VCC or 0,
∆ICC†
MIN
MIN
MAX
SN74HCT74
MIN
4.4
4.499
4.4
4.4
4.3
3.7
3.84
5.5 V
4.5 V
to 5.5 V
MAX
UNIT
V
0.001
0.1
0.1
0.1
0.17
0.26
0.4
0.33
±0.1
±100
±1000
±1000
nA
4
80
40
µA
1.4
2.4
3
2.9
mA
3
10
10
10
pF
5.5 V
Ci
SN54HCT74
3.98
5.5 V
IO = 0
One input at 0.5 V or 2.4 V,
Other inputs at 0 or VCC
TA = 25°C
TYP
MAX
V
† This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
fclock
Clock frequency
PRE or CLR low
tw
Pulse duration
CLK high or low
Data
tsu
Setup time before CLK↑
PRE or CLR inactive
th
Hold time, data after CLK↑
VCC
TA = 25°C
MIN
MAX
SN54HCT74
4.5 V
27
18
22
5.5 V
30
20
24
MIN
MAX
SN74HCT74
MIN
4.5 V
16
24
20
5.5 V
14
21
18
4.5 V
18
27
23
5.5 V
16
24
21
4.5 V
12
18
15
5.5 V
11
16
14
4.5 V
0
0
0
5.5 V
0
0
0
4.5 V
0
0
0
5.5 V
0
0
0
MAX
UNIT
MHz
ns
ns
ns
$&'"%$ $#'$ ('! $ # &'"%0# '
#/$ (%# & #0#*("#$+ %'%#' %% %$ #'
(#&%$ %'# #/$ /%*+ #,% $'!"#$ '##'0# # '/ %$/# ' $$!# ## ('! -! $#+
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SCLS169E − DECEMBER 1982 − REVISED APRIL 2004
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
PRE or CLR
Q or Q
tpd
CLK
Q or Q
tt
Q or Q
VCC
MIN
TA = 25°C
TYP
MAX
SN54HCT74
MIN
MAX
SN74HCT74
MIN
4.5 V
27
40
18
22
5.5 V
30
46
20
24
MAX
UNIT
MHz
4.5 V
21
35
53
44
5.5 V
17
31
48
40
4.5 V
20
28
42
35
5.5 V
18
25
38
31
4.5 V
8
15
22
19
5.5 V
7
14
20
17
ns
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance per flip-flop
No load
TYP
35
UNIT
pF
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
Test
Point
3V
High-Level
Pulse
1.3 V
0V
CL = 50 pF
(see Note A)
tw
1.3 V
1.3 V
0V
3V
1.3 V
3V
Low-Level
Pulse
LOAD CIRCUIT
Input
1.3 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.3 V
0V
tPLH
In-Phase
Output
1.3 V
10%
tPHL
90%
90%
tr
Out-ofPhase
Output
tPHL
90%
VOH Reference
1.3 V
Input
10% V
OL
tf
tPLH
1.3 V
10%
tf
1.3 V
10%
90%
VOH
Data
Input 1.3 V
0.3 V
3V
1.3 V
0V
tsu
2.7 V
VOL
tr
tr
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES
th
2.7 V
3V
1.3 V
0.3 V 0 V
tf
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. For clock inputs, fmax is measured when the input duty cycle is 50%.
D. The outputs are measured one at a time, with one input transition per measurement.
E. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
$&'"%$ $#'$ ('! $ # &'"%0# '
#/$ (%# & #0#*("#$+ %'%#' %% %$ #'
(#&%$ %'# #/$ /%*+ #,% $'!"#$ '##'0# # '/ %$/# ' $$!# ## ('! -! $#+
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
24-Apr-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
JM38510/65352B2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
JM38510/
65352B2A
JM38510/65352BCA
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
65352BCA
JM38510/65352BDA
ACTIVE
CFP
W
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
65352BDA
M38510/65352B2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
JM38510/
65352B2A
M38510/65352BCA
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
65352BCA
M38510/65352BDA
ACTIVE
CFP
W
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
65352BDA
SN74HCT74D
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT74
SN74HCT74DBR
ACTIVE
SSOP
DB
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT74
SN74HCT74DE4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT74
SN74HCT74DG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT74
SN74HCT74DR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT74
SN74HCT74DRE4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT74
SN74HCT74DRG4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT74
SN74HCT74DT
ACTIVE
SOIC
D
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT74
SN74HCT74N
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
SN74HCT74N
SN74HCT74NE4
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
SN74HCT74N
SN74HCT74NSR
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT74
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
24-Apr-2015
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74HCT74NSRE4
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HCT74
SN74HCT74PW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT74
SN74HCT74PWG4
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT74
SN74HCT74PWLE
OBSOLETE
TSSOP
PW
14
TBD
Call TI
Call TI
-40 to 85
SN74HCT74PWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT74
SN74HCT74PWRE4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT74
SN74HCT74PWT
ACTIVE
TSSOP
PW
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HT74
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Apr-2015
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54HCT74, SN74HCT74 :
• Catalog: SN74HCT74
• Military: SN54HCT74
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Military - QML certified for Military and Defense Applications
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74HCT74DBR
SSOP
DB
14
2000
330.0
16.4
8.2
6.6
2.5
12.0
16.0
Q1
SN74HCT74DR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
SN74HCT74DT
SOIC
D
14
250
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
SN74HCT74NSR
SO
NS
14
2000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
SN74HCT74PWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74HCT74PWT
TSSOP
PW
14
250
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74HCT74DBR
SSOP
DB
14
2000
367.0
367.0
38.0
SN74HCT74DR
SOIC
D
14
2500
367.0
367.0
38.0
SN74HCT74DT
SOIC
D
14
250
367.0
367.0
38.0
SN74HCT74NSR
SO
NS
14
2000
367.0
367.0
38.0
SN74HCT74PWR
TSSOP
PW
14
2000
367.0
367.0
35.0
SN74HCT74PWT
TSSOP
PW
14
250
367.0
367.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
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