IM REL IN MITSUBISHI MICROCOMPUTERS Y AR M37736EHBXXXGP M37736EHBGS ge. ion. icat o chan t ecif l sp ubject a in f s are ot a is n limits This ric ice: aramet t o N ep Som P PROM VERSION OF M37736MHBXXXGP DESCRIPTION The M37736EHBXXXGP is a single-chip microcomputer using the 7700 Family core. This single-chip microcomputer has a CPU and a bus interface unit. The CPU is a 16-bit parallel processor that can be an 8-bit parallel processor, and the bus interface unit enhances the memory access efficiency to execute instructions fast. This microcomputer also includes a 32 kHz oscillation circuit, in addition to the PROM, RAM, multiple-function timers, serial I/O, A-D converter, and others. In the M37736EHBXXXGP, as the multiplex method of the external bus, either of 2 types can be selected. The M37736EHBXXXGP has the same function as the M37736MHBXXXGP except that the built-in ROM is PROM. (Refer to the basic function blocks description.) For program development, the M37736EHBGS with erasable ROM that is housed in a windowed ceramic LCC is also provided. FEATURES ●Number of basic instructions .................................................. 103 ●Memory size PROM ............................................. 124 Kbytes RAM ................................................ 3968 bytes ●Instruction execution time The fastest instruction at 25 MHz frequency ...................... 160 ns ●Single power supply ...................................................... 5 V ± 10% ●Low power dissipation (at 25 MHz frequency) ............................................47.5 mW (Typ.) ●Interrupts ............................................................ 19 types, 7 levels ●Multiple-function 16-bit timer ................................................. 5 + 3 ●Serial I/O (UART or clock synchronous) ..................................... 3 ●10-bit A-D converter ............................................ 8-channel inputs ●12-bit watchdog timer ●Programmable input/output, output (ports P0, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10)..........................84 ●Clock generating circuit ........................................ 2 circuits built-in APPLICATION Control devices for general commercial equipment such as office automation, office equipment, and others. Control devices for general industrial equipment such as communication equipment, and others. Note. Do not use the windowed EPROM version for mass production, because it is a tool for program development (for evaluation). 80 ↔ P87/TXD1 79 ↔ P90/CTS2 78 ↔ P91/CLK2 77 ↔ P92/RXD2 76 → P93/TXD2 75 → P94 74 → P95 73 → P96 72 → P97 71 ↔ P00/A0/CS0 70 ↔ P01/A1/CS1 69 ↔ P02/A2/CS2 68 ↔ P03/A3/CS3 67 ↔ P04/A4/CS4 66 ↔ P05/A5/RSMP 65 ↔ P06/A6/A16 64 ↔ P07/A7/A17 63 ↔ P10/A8/D8 62 ↔ P11/A9/D9 61 ↔ P12/A10/D10 60 ↔ P13/A11/D11 59 ↔ P14/A12/D12 58 ↔ P15/A13/D13 57 ↔ P16/A14/D14 56 ↔ P17/A15/D15 55 ↔ P20/A16/A0/D0 54 ↔ P21/A17/A1/D1 53 ↔ P22/A18/A2/D2 52 ↔ P23/A19/A3/D3 51 ↔ P24/A20/A4/D4 PIN CONFIGURATION (TOP VIEW) M37736EHBXXXGP P67/TB2IN/f SUB ↔ 1 P66/TB1IN ↔ 2 P65/TB0IN ↔ 3 P64/INT2 ↔ 4 P63/INT1 ↔ 5 P62/INT0 ↔ 6 P61/TA4IN ↔ 7 P60/TA4OUT ↔ 8 P57/TA3IN ↔ 9 P56/TA3OUT ↔ 10 P55/TA2IN ↔ 11 P54/TA2OUT ↔ 12 P53/TA1IN ↔ 13 P52/TA1OUT ↔ 14 P51/TA0IN ↔ 15 P50/TA0OUT ↔ 16 P107/KI3 ↔ 17 P106/KI2 ↔ 18 P105/KI1 ↔ 19 P104/KI0 ↔ 20 P103 ↔ 21 P102 ↔ 22 P101 ↔ 23 P100 ↔ 24 P47 ↔ 25 P46 ↔ 26 P45 ↔ 27 P44 ↔ 28 P43 ↔ 29 P42/f1 ↔ 30 P86/RXD1 ↔ 81 P85/CLK1 ↔ 82 P84/CTS1/RTS1 ↔ 83 P83/TXD0 ↔ 84 P82/RXD0/CLKS0 ↔ 85 P81/CLK0 ↔ 86 P80/CTS0/RTS0/CLKS1 ↔ 87 88 VCC AVCC 89 VREF → 90 91 AVSS 92 VSS P77/AN7/XCIN ↔ 93 P76/AN6/XCOUT ↔ 94 P75/AN5/ADTRG ↔ 95 P74/AN4 ↔ 96 P73/AN3 ↔ 97 P72/AN2 ↔ 98 P71/AN1 ↔ 99 P70/AN0 ↔ 100 50 ↔ P25/A21/A5/D5 49 ↔ P26/A22/A6/D6 48 ↔ P27/A23/A7/D7 47 ↔ P30/R/W/WEL 46 ↔ P31/BHE/WEH 45 ↔ P32/ALE 44 ↔ P33/HLDA 43 → EVL0 42 → EVL1 VCC 41 40 VSS 39 → E/RDE 38 → XOUT 37 ← XIN 36 ← RESET 35 ← BSEL 34 ← CNVSS 33 ← BYTE 32 ↔ P40/HOLD 31 ↔ P41/RDY Outline 100P6S-A 1 M37736EHBXXXGP M37736EHBGS Stack Pointer S(16) XCIN XCOUT Accumulator B(16) Accumulator A(16) Arithmetic Logic Unit(16) PROM 124 Kbytes Clock Generating Circuit Index Register X(16) RAM 3968 bytes Index Register Y(16) Input/Output port P0 Input/Output port P3 Input/Output port P4 Input/Output port P5 Timer TB1(16) Timer TB2(16) Timer TB0(16) Timer TA0(16) XCOUT XCIN Direct Page Register DPR(16) Timer TA1(16) Processor Status Register PS(11) Timer TA4(16) Input Buffer Register IB(16) Timer TA2(16) VCC Data Bank Register DT((8) Timer TA3(16) Watchdog Timer Program Bank Register PG(8) Input/Output port P1 Input/Output port P6 Input/Output port P7 Input/Output port P8 A-D Converter(10) UART0(9) UART2(9) CNVSS UART1(9) Data Address Register DA(24) Input/Output port P2 P0(8) P1(8) P2(8) P3(4) P4(8) P5(8) AVCC Address Bus (0V) AVSS P6(8) Instruction Queue Buffer Q2(8) Incrementer(24) (0V) VSS Bus method Reset input selection input RESET BSEL Enable output E Clock output XOUT P7(8) Instruction Queue Buffer Q1(8) Program Counter PC(16) Clock input XIN P8(8) Instruction Register(8) Data Bus(Odd) Incrementer/Decrementer(24) M37736EHBXXXGP BLOCK DIAGRAM Data Bus(Even) Instruction Queue Buffer Q0(8) Program Address Register PA(24) 2 Data Buffer DBL(8) P9(8) P10(8) Data Buffer DBH(8) Output port P9 Input/Output port P10 Reference External data bus width selection input voltage input BYTE VREF PROM VERSION OF M37736MHBXXXGP P IN e. n. atio chang cific spe bject to l a fin re su a ot a is n limits his e: T ametric ic t No e par Som IM REL MITSUBISHI MICROCOMPUTERS Y AR IM REL INA RY . . tion hange c ifica pec ject to s l fina sub ot a its are is n m This etric li : e m ic Not e para Som P MITSUBISHI MICROCOMPUTERS M37736EHBXXXGP M67736EHBGS PROM VERSION OF M37736MHBXXXGP FUNCTIONS OF M37736EHBXXXGP Parameter Number of basic instructions Instruction execution time Memory size Input/Output ports Output port Multi-function timers PROM RAM P0 – P2, P4 – P8, P10 P3 P9 TA0, TA1, TA2, TA3, TA4 TB0, TB1, TB2 Serial I/O A-D converter Watchdog timer Interrupts Clock generating circuit Supply voltage Power dissipation Input/Output characteristic Input/Output voltage Output current Memory expansion Operating temperature range Device structure Package M37736EHBXXXGP M37736EHBGS Functions 103 160 ns (the fastest instruction at external clock 25 MHz frequency) 124 Kbytes 3968 bytes 8-bit ✕ 9 4-bit ✕ 1 8-bit ✕ 1 16-bit ✕ 5 16-bit ✕ 3 (UART or clock synchronous serial I/O) ✕ 3 10-bit ✕ 1 (8 channels) 12-bit ✕ 1 3 external types, 16 internal types Each interrupt can be set to the priority level (0 – 7.) 2 circuits built-in (externally connected to a ceramic resonator or a quartz-crystal oscillator) 5 V ± 10% 47.5 mW (at external clock 25 MHz frequency) 5V 5 mA External bus mode A; maximum 16 Mbytes, External bus mode B; maximum 1 Mbytes –20 to 85 °C CMOS high-performance silicon gate process 100-pin plastic molded QFP (100P6S-A) 100-pin ceramic LCC (with a window) (100D0) 3 IM REL IN MITSUBISHI MICROCOMPUTERS Y AR M37736EHBXXXGP M37736EHBGS e. n. atio chang cific spe bject to l a fin re su a ot a is n limits his e: T ametric ic t No e par Som P PROM VERSION OF M37736MHBXXXGP PIN DESCRIPTION Pin Vcc, Vss CNVss Name Input/Output Power source Apply 5 V ± 10% to Vcc and 0 V to Vss. CNVss input Input RESET Reset input Input XIN Clock input Input XOUT Clock output Output E Enable output Output BYTE External data bus width selection input Bus method select input Input _____ _ BSEL AVcc, AVss VREF P00 – P07 Analog power source input Reference voltage input I/O port P0 Input Input I/O P10 – P17 I/O port P1 I/O P20 – P27 I/O port P2 I/O P30 – P33 I/O port P3 I/O P40 – P47 I/O port P4 I/O P50 – P57 I/O port P5 I/O P60 – P67 I/O port P6 I/O P70 – P77 I/O port P7 I/O P80 – P87 I/O port P8 I/O P90 – P97 Output port P9 Output P100 – P107 I/O port P10 I/O EVL0, EVL1 4 –– Output Functions This pin controls the processor mode. Connect to Vss for the single-chip mode and the memory expansion mode, and to Vcc for the microprocessor mode. When “L” level is applied to this pin, the microcomputer enters the reset state. These are pins of main-clock generating circuit. Connect a ceramic resonator or a quartzcrystal oscillator between XIN and XOUT. When an external clock is used, the clock source should be connected to the XIN pin, and the XOUT pin should be left open. This pin functions as the enable signal output pin which indicates the access status in the internal bus. In the external bus mode B and the memory expansion mode or the microprocessor mode, ___ this pin output signal RDE. In the memory expansion mode or the microprocessor mode, this pin determines whether the external data bus has an 8-bit width or a 16-bit width. The data bus has a 16-bit width when “L” signal is input and an 8-bit width when “H” signal is input. In the memory expansion mode or the microprocessor mode, this pin determines the external bus mode. The bus mode becomes the external bus mode A when “H” signal is input, and the external bus mode B when “L” signal is input. Power source input pin for the A-D converter. Externally connect AVcc to Vcc and AVss to Vss. This is reference voltage input pin for the A-D converter. In the single-chip mode, port P0 becomes an 8-bit I/O port. An I/O direction register is available so that each pin can be programmed for input or output. These ports are in the input mode when reset. In the memory expansion mode or the microprocessor mode, these pins output ____ address (A0 – A7) ___ ___ at the external bus mode A, and these pins output signals CS0 – CS4 and RSMP, and addresses (A16, A17) at the external bus mode B. In the single-chip mode, these pins have the same functions as port P0. When the BYTE pin is set to “L” in the memory expansion mode or the microprocessor mode and external data bus has a 16-bit width, high-order data (D8 – D15) is input/output or an address (A8 – A15) is output. When the BYTE pin is “H” and an external data bus has an 8-bit width, only address (A8 – A15) is output. In the single-chip mode, these pins have the same functions as port P0. In the memory expansion mode or the microprocessor mode, low-order data (D0 – D7) is input/output or an address is output. When using the external bus mode A, the address is A16 – A23. When using the external bus mode B, the address is A0 – A7. In the single-chip mode, these pins have the same function as port P0. In the memory expansion ____ __ ___ mode or the microprocessor , BHE, ALE, and HLDA signals are output at the external ___ ___ mode, R/W ____ bus mode A, and WEL, WEH, ALE, and HLDA signals are output at the external bus mode B. In the single-chip mode, these pins have the same functions as____ port P0. In the memory expansion ___ mode or the microprocessor mode, P40, P41 and P42 become HOLD and RDY input pins, and a clock φ1 output pin, respectively. Functions of the other pins are the same as in the single-chip mode. However, in the memory expansion mode, P42 can be selected as an I/O port. In addition to having the same functions as port P0 in the single-chip mode, these pins also function as I/O pins for timers A0 to A3. In addition to having the same functions as port P0 in the single-chip mode, ___ these ___ pins also function as I/O pins for timer A4, input pins for external interrupt input (INT0 – INT2) and input pins for timers B0 to B2. P67 also functions as sub-clock φSUB output pin. In addition to having the same functions as port P0 in the single-chip mode, these pins function as input pins for A-D converter. Additionally, P76 and P77 have the function as the output pin (XCOUT) and the input pin (XCIN) of the sub-clock (32 kHz) oscillation circuit, respectively. When P76 and P77 are used as the XCOUT and XCIN pins, connect a resonator or an oscillator between the both. In addition to having the same functions as port P0 in the single-chip mode, these pins also function as I/O pins for UART 0 and UART 1. Port P9 is an 8-bit I/O port. These ports are floating when reset. When writting to the port latch, these ports become the output mode. P90 – P93 also function as I/O port for UART 2. In addition to having the same functions as port P0__ in the __single-chip mode, P104 – P107 also function as input pins for key input interrupt input (KI0 – KI3). These pins should be left open. IM REL INA MITSUBISHI MICROCOMPUTERS RY M37736EHBXXXGP M67736EHBGS . . tion hange c ifica pec ject to s l fina sub ot a its are is n m This etric li : e m ic Not e para Som P PROM VERSION OF M37736MHBXXXGP BASIC FUNCTION BLOCKS The M37736EHBXXXGP has the same function as the M37736MHB XXXGP except that the built-in ROM is PROM. Refer to the section on the M37736MHBXXXGP. PIN DESCRIPTION (EPROM MODE) Pin VCC, VSS CNVSS BYTE _____ RESET XIN XOUT _ E AVCC, AVSS VREF P00 – P07 P10 – P17 P20 – P27 P30 P31 – P33 P40 – P47 P50 – P57 Name Power supply VPP input VPP input Reset input Clock input Clock output Enable output Analog supply input Reference voltage input Address input (A0 – A7) Address input (A8 – A15) Data I/O (D0 – D7) Address input (A16) Input port P3 Input port P4 Control signal input Input/Output Input Input Input Input Output Output Input Input Input I/O Input Input Input Input Functions Supply 5V±10% to VCC and 0V to VSS. Connect to VPP when programming or verifing. Connect to VPP when programming or verifing. Connect to VSS. Connect a ceramic resonator between XIN and XOUT. Keep open. Connect AVCC to VCC and AVSS to VSS. Connect to VSS. Port P0 functions as the lower 8 bits address input (A0 – A7). Port P1 functions as the higher 8 bits address input (A8 – A15). Port P2 functions as the 8 bits data input/output (D0 – D7). P30 functions as the most significant bit address input (A16). Connect to VSS. Connect to VSS. _____ ___ ___ Input Input P80 – P87 Input port P6 Input port P7 Input port P8 P50, P51, and P52 function as PGM, OE, and CE input pins respectively. Connect P53, P54, P55, and P56 to VCC. Connect P57 to VSS. Connect to VSS. Connect to VSS. Input Connect to VSS. P90 – P97 Input port P9 Input Connect to VSS. P100 – P107 Input port P10 _____ Input Connect to VSS. P60 – P67 P70 – P77 BSEL EVL0, EVL1 _____ Input Output Connect to VCC. Keep open. 5 IM REL IN MITSUBISHI MICROCOMPUTERS Y AR M37736EHBXXXGP M37736EHBGS e. n. atio chang cific spe bject to l a fin re su a ot a is n limits his e: T ametric ic t No e par Som P PROM VERSION OF M37736MHBXXXGP EPROM MODE The M37736EHBXXXGP features an EPROM mode in addition to _____ its normal modes. When the RESET signal level is “L”, the chip automatically enters the EPROM mode. Table 1 list the correspondence between pins and Figure 1 shows the pin connections in the EPROM mode. The EPROM mode is the 1M mode for the EPROM that is equivalent to the M5M27C101K. When in the EPROM mode, ports P0, P1, P2, P30, P50, P51, P52, CNV SS, and BYTE are used for the EPROM (equivalent to the M5M27C101K). When in this mode, the built-in PROM can be programmed or read from using these pins in the same way as with the M5M27C101K. This chip does not have Device Identifier Mode, so that set the corresponding program algorithm. The program area should specify address 0100016 – 1FFFF16. Connect the clock which is either ceramic resonator or external clock to XIN pin and XOUT pin. Table 1 Pin function in EPROM mode VCC VPP VSS Address input Data I/O ___ CE ___ OE _____ M37736EHBXXXGP VCC M5M27C101K VCC CNVSS, BYTE VSS VPP VSS A0 – A16 D0 – D7 Ports P0, P1, P30 Port P2 P52 P51 ___ CE ___ OE _____ P50 PGM 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 ↔ P87 ↔ P90 ↔ P91 ↔ P92 → P93 → P94 → P95 → P96 → P97 ↔ P00 ↔ P01 ↔ P02 ↔ P03 ↔ P04 ↔ P05 ↔ P06 ↔ P07 ↔ P10 ↔ P11 ↔ P12 ↔ P13 ↔ P14 ↔ P15 ↔ P16 ↔ P17 ↔ P20 ↔ P21 ↔ P22 ↔ P23 ↔ P24 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 D0 D1 D2 D3 D4 PGM 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 D5 D6 D7 A16 VSS ∗ VPP CE OE PGM P67 ↔ 1 P66 ↔ 2 P65 ↔ 3 P64 ↔ 4 P63 ↔ 5 P62 ↔ 6 P61 ↔ 7 P60 ↔ 8 P57 ↔ 9 P56 ↔ 10 P55 ↔ 11 P54 ↔ 12 P53 ↔ 13 P52 ↔ 14 P51 ↔ 15 P50 ↔ 16 P107 ↔ 17 P106 ↔ 18 P105 ↔ 19 P104 ↔ 20 P103 ↔ 21 P102 ↔ 22 P101 ↔ 23 P100 ↔ 24 P47 ↔ 25 P46 ↔ 26 P45 ↔ 25 P44 ↔ 28 P43 ↔ 29 P42 ↔ 30 M37736EHBGP ↔ P25 ↔ P26 ↔ P27 ↔ P30 ↔ P31 ↔ P32 ↔ P33 → EVL0 → EVL1 VCC VSS →E → XOUT ← XIN ← RESET ← BSEL CNVSS ← BYTE ↔ P40 ↔ P41 VCC P86 ↔ 81 P85 ↔ 82 P84 ↔ 83 P83 ↔ 84 P82 ↔ 85 P81 ↔ 86 P80 ↔ 87 88 VCC 89 AVCC VREF → 90 91 AVSS 92 VSS P77 ↔ 93 P76 ↔ 94 P75 ↔ 95 P74 ↔ 96 P73 ↔ 97 P72 ↔ 98 P71 ↔ 99 P70 ↔ 100 ∗ : Connect to ceramic oscillation circuit. Outline 100P6S-A Fig. 1 Pin connection in EPROM mode 6 : It is used in the EPROM mode. MI ELI NA MITSUBISHI MICROCOMPUTERS RY M37736EHBXXXGP M67736EHBGS . . tion nge ifica to cha t pec al s subjec in f ot a its are is n m This etric li m ice: Not e para m So PR PROM VERSION OF M37736MHBXXXGP FUNCTION IN EPROM MODE 1M mode (equivalent to the M5M27C101K) Reading ___ ___ To read the EPROM, set the CE and OE pins to a “L” level. Input the address of the data (A0 – A16) to be read, and the data will be output to the I/O pins D0 – D7. The data I/O pins will be floating when either __ __ the CE or OE pins are in the “H” state. Programming Programming must be performed in 8 bits by a byte program. To ___ ___ program to the EPROM, set the CE pin to a “L” level and the OE pin to a “H” level. The CPU will enter the programming mode when 12.5 V is applied to the VPP pin. The address to be programmed to is selected with pins A0 –_____ A16, and the data to be programmed is input to pins D0 – D7. Set the PGM pin to a “L” level to being programming. Programming operation To program the M37733EHBXXXFP, first set VCC = 6 V, VPP = 12.5 V, and set the address to 0100016. Apply a 0.2 ms programming pulse, check that the data can be read, and if it cannot be read OK, repeat the procedure, applying a 0.2 ms programming pulse and checking that the data can be read until it can be read OK. Record the accumulated number of pulse applied (X) before the data can be read OK, and then write the data again, applying a further once this number of pulses (0.2 ✕ X ms). When this series of programming operations is complete, increment the address, and continue to repeat the procedure above until the last address has been reached. Finally, when all addresses have been programmed, read with VCC = VPP = 5 V (or VCC = VPP = 5.5 V). Table 2. I/O signal in each mode Pin Erasing To erase data on this chip, use an ultraviolet light source with a 2537 Angstrom wave length. The minimum radiation power necessary for erasing is 15 J/cm2. ___ ___ _____ CE OE PGM VPP VCC Data I/O VIL VIL VIH X X 5V 5V 5V 5V Output Floating VIL VIL VIH X VIH X 5V 5V VIL 12.5 V 6 V Floating Input Programming Verify VIL VIL VIH 12.5 V 6 V Output Program Disable VIH VIH VIH 12.5 V 6 V Floating Mode Read-out Output Disable Programming Note 1 : An X indicates either VIL or VIH. Programming operation (equivalent to the M5M27C101K) AC ELECTRICAL CHARACTERISTICS (Ta = 25 ± 5 °C, VCC = 6 V ± 0.25 V, VPP = 12.5 ± 0.3 V, unless otherwise noted) Symbol Parameter Test conditions Min. 2 tAS Address setup time tOES tDS OE setup time Data setup time tAH tDH Address hold time Data hold time 0 tDFP Output enable to output float delay VCC setup time VPP setup time _____ PGM pulse width _____ PGM over program pulse width ___ CE setup time __ Data valid from OE 0 tVCS tVPS tPW tOPW tCES tOE ___ Limits Typ. Max. µs µs µs µs 2 2 2 130 2 2 0.19 0.19 Unit 0.2 0.21 5.25 2 150 µs ns µs µs ms ms µs ns 7 IM REL IN MITSUBISHI MICROCOMPUTERS Y AR M37736EHBXXXGP M37736EHBGS e. n. atio chang cific spe bject to l a fin re su a ot a is n limits his e: T ametric ic t No e par Som P PROM VERSION OF M37736MHBXXXGP AC waveforms PROGRAM VERIFY VIH ADDRESS VIL tAH tAS VIH/VOH DATA DATA OUTPUT VALID DATA SET VIL/VOL tDS tDH tDFP VPP VPP VCC VCC +1 VCC VCC tVPS tVCS VIH CE VIL tCES VIH PGM tOES VIL tOE tPW VIH tOPW OE VIL Test conditions for A.C. characteristics Input voltage : VIL = 0.45 V, VIH = 2.4 V Input rise and fall times (10 % – 90 %) : ≤ 20 ns Reference voltage at timing measurement : Input, Output “L” = 0.8 V, “H” = 2 V Programming algorithm flow chart START ADDR=FIRST LOCATION VCC=6.0 V VPP=12.5 V X=0 PROGRAM ONE PULSE OF 0.2 ms X=X+1 YES X=25? NO FAIL VERIFY BYTE FAIL VERIFY BYTE PASS PROGRAM PULSE OF 0.2X ms DURATION DEVICE FAILED PASS NO INCREMENT ADDR LAST ADDR? YES VCC=VPP=*5.0 V VERIFY ALL BYTE FAIL DEVICE FAILED PASS DEVICE PASSED 8 *4.5 V ≤ VCC = VPP ≤ 5.5 V IM REL INA MITSUBISHI MICROCOMPUTERS RY M37736EHBXXXGP M37736EHBGS e. n. atio ang cific t to ch c spe inal e subje f a ar ot is n mits This etric li m ice: Not e para Som P PROM VERSION OF M37736MHBXXXGP SAFETY INSTRUCTIONS ADDRESSING MODES (1) Sunlight and fluorescent lamp contain light that can erase written information. When using in read mode, be sure to cover the transparent glass portion with a seal or other materials (ceramic package product). (2) Mitsubishi Electric corp. provides the seal for covering the transparent glass. Take care that the seal does not touch the read pins (ceramic package product). (3) Clean the transparent glass before erasing. Fingers’ fat and paste disturb the passage of ultraviolet rays and may affect badly the erasure capability (ceramic package product). (4) A high voltage is used for programming. Take care that overvoltage is not applied. Take care especially at power on. (5) The programmable M37736EHBGP that is shipped in blank is also provided. For the M37736EHBGP, Mitsubishi Electric corp. does not perform PROM programming test and screening following the assembly processes. To improve reliability after programming, performing programming and test according to the flow below before use is recommended. The M37736EHBXXXGP has 28 powerful addressing modes. Refer to the “7700 Family Software Manual” for the details. MACHINE INSTRUCTION LIST The M37736EHBXXXGP has 103 machine instructions. Refer to the “7700 Family Software Manual” for the details. DATA REQUIRED FOR PROM ORDERING Please send the following data for writing to PROM. (1) M37736EHBXXXGP writing to PROM order confirmation form (2) 100P6S mark specification form (3) ROM data (EPROM 3 sets) Programming with PROM programmer Screening (Caution) (Leave at 150 °C for 40 hours) Verify test with PROM programmer Function check in target device Caution : Never expose to 150 °C exceeding 100 hours. 9 IM REL IN MITSUBISHI MICROCOMPUTERS Y AR M37736EHBXXXGP M37736EHBGS e. n. atio chang cific spe bject to l a fin re su a ot a is n limits his e: T ametric ic t No e par Som P PROM VERSION OF M37736MHBXXXGP ABSOLUTE MAXIMUM RATINGS Symbol Vcc AVcc VI VI VO Pd Topr Tstg Parameter Conditions Power source voltage Analog power_____ source voltage Input voltage RESET, CNVss, BYTE Input voltage P00 – P07, P10 – P17, P20 – P27, P30 – P33, P40 – P47, P50 – P57, P60 – P67, P70 – P77, P80 – P87, P90 – P92, P100 – P107, VREF, XIN, BSEL Output voltage P00 – P07, P10 – P17, P20 – P27, P30 – P33, P40 – P47, P50 – P57, 7, P60 – P67, P70 – P77, P80 – P8_ P90 – P97, P100 – P107, XOUT, E Power dissipation Ta = 25 °C Operating temperature Storage temperature Ratings –0.3 to +7 –0.3 to +7 –0.3 to +12(Note) Unit V V V –0.3 to Vcc + 0.3 V –0.3 to Vcc + 0.3 V 300 –20 to +85 –40 to +150 mW °C °C Note. When the EPROM is programmed, input voltage of pins CNVss and BYTE is 13 V respectively. RECOMMENDED OPERATING CONDITIONS (Vcc = 5 V ± 10%, Ta = –20 to +85 °C, unless otherwise noted) Symbol Vcc AVcc Vss AVss VIH VIH VIH VIL VIL VIL IOH(peak) IOH(avg) IOL(peak) IOL(peak) IOL(avg) IOL(avg) f(XIN) f(XCIN) Parameter f(XIN) : Operating f(XIN) : Stopped, f(XCIN) = 32.768 kHz Analog power source voltage Power source voltage Analog power source voltage , P60 – P67, High-level input voltage P00 – P07, P30 – P33, P40 – P47, P50 – P57_____ P70 – P77, P80 – P87, P90 – P92, P100 – P107, XIN, RESET, CNVss, BYTE, BSEL, XCIN (Note 3) High-level input voltage P10 – P17, P20 – P27 (in single-chip mode) High-level input voltage P10 – P17, P20 – P27 (in memory expansion mode and microprocessor mode) P60 – P67, Low-level input voltage P00 – P07, P30 – P33, P40 – P47, P50 – P57, _____ P70 – P77, P80 – P87, P90 – P92, P100 – P107, XIN, RESET, CNVss, BYTE, BSEL, XCIN (Note 3) Low-level input voltage P10 – P17, P20 – P27 (in single-chip mode) Low-level input voltage P10 – P17, P20 – P27 (in memory expansion mode and microprocessor mode) High-level peak output current P00 – P07, P10 – P17, P20 – P27, P30 – P33, P40 – P47, P50 – P57, P60 – P67, P70 – P77, P80 – P87, P90 – P97, P100 – P107 High-level average output current P00 – P07, P10 – P17, P20 – P27, P30 – P33, P40 – P47, P50 – P57, P60 – P67, P70 – P77, P80 – P87, P90 – P97, P100 – P107 Low-level peak output current P00 – P07, P10 – P17, P20 – P27, P30 – P33, P40 – P43, P54 – P57, P60 – P67, P70 – P77, P80 – P87, P90 – P97, P104 – P107 Low-level peak output current P44 – P47, P100 – P103 Low-level average output current P00 – P07, P10 – P17, P20 – P27, P30 – P33, P40 – P43, P54 – P57, P60 – P67, P70 – P77, P80 – P87, P90 – P97, P104 – P107 Low-level average output current P44 – P47, P100 – P103 Main-clock oscillation frequency (Note 4) Sub-clock oscillation frequency Power source voltage Min. 4.5 2.7 Max. 5.5 5.5 Vcc 0 0 Unit V V V V 0.8 Vcc Vcc V 0.8 Vcc Vcc V 0.5 Vcc Vcc V 0 0.2Vcc V 0 0.2Vcc V 0 0.16Vcc V –10 mA –5 mA 10 mA 20 mA 5 mA 15 25 50 mA MHz kHz Notes 1. Average output current is the average value of a 100 ms interval. 2. The sum of IOL(peak) for ports P0, P1, P2, P3, P8, and P9 must be 80 mA or less, the sum of IOH(peak) for ports P0, P1, P2, P3, P8, and P9 must be 80 mA or less, the sum of IOL(peak) for ports P4, P5, P6, P7, and P10 must be 100 mA or less, and the sum of IOH(peak) for ports P4, P5, P6, P7, and P10 must be 80 mA or less. 3. Limits VIH and VIL for XCIN are applied when the sub clock external input selection bit = “1”. 4. The maximum value of f(XIN) = 12.5 MHz when the main clock division selection bit = “1”. 10 Limits Typ. 5.0 32.768 IM REL INA MITSUBISHI MICROCOMPUTERS RY M37736EHBXXXGP M67736EHBGS . . tion hange c ifica pec ject to s l fina sub ot a its are is n m This etric li : e m ic Not e para Som P PROM VERSION OF M37736MHBXXXGP ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz, unless otherwise noted) Symbol VOH VOH VOH VOH VOL VOL VOL VOL VOL VT+ – VT– VT+ – VT– VT+ – VT– VT+ – VT– IIH IIL IIL VRAM Parameter Test conditions High-level output voltage P00 – P07, P10 – P17, P20 – P27, P33, P40 – P47, P50 – P57, IOH = –10 mA P60 – P67, P70 – P77, P80 – P87, P90 – P97, P100 – P107 High-level output voltage P00 – P07, P10 – P17, P20 – P27, IOH = –400 µA P33 IOH = –10 mA High-level output voltage P30 – P32 ICH = –400 µA _ IOH = –10 mA High-level output voltage E IOH = –400 µA Low-level output voltage P00 – P07, P10 – P17, P20 – P27, P33, P40 – P43, P50 – P57, IOL = 10 mA P60 – P67, P70 – P75, P80 – P87, P90 – P97, P104 – P107 Low-level output voltage P44 – P47, P100 – P103 IOL = 20 mA Low-level output voltage P00 – P07, P10 – P17, P20 – P27, IOL = 2 mA P33 IOL = 10 mA Low-level output voltage P30 – P32 IOL = 2 mA _ IOL = 10 mA Low-level output voltage E IOL = 2 mA ____ ___ Hysteresis HOLD , _______ RDY, __________ TA0IN –________ TA4IN , TB0________ IN – TB2IN, _______ ________ INT0 – INT2, ADTRG, CTS0, CTS1, CTS2, CLK0, _____ _____ CLK1, CLK2, KI0 – KI3 _____ Hysteresis RESET Hysteresis XIN Hysteresis XCIN (When external clock is input) High-level input current P00 – P07, P10 – P17, P20 – P27, P30 – P33, VI = 5 V P40 – P47, P50 – P57, P60 – P67, P70 – P7 7, _____ P80 – P87, P90 – P92, P100 – P107, XIN, RESET, CNVss, BYTE, BSEL Low-level input current P00 – P07, P10 – P17, P20 – P27, P30 – P33, VI = 0 V P40 – P47, P50 – P57, P60, P61, P65 – P67, – P77, P80 – P87, P90 – P92, P100 – P103, P70 _____ XIN, RESET, CNVss, BYTE, BSEL VI = 0 V, Low-level input current P104 – P107, P62 – P64 RAM hold voltage Min. Limits Typ. Unit 3 V 4.7 V 3.1 4.8 3.4 4.8 V V 2 V 2 V 0.45 V 1.9 0.43 1.6 0.4 V V 0.4 1 V 0.2 0.1 0.1 0.5 0.4 0.4 V V V without a pull-up transistor VI = 0 V, with a pull-up transistor When clock is stopped. Max. –0.25 2 –0.5 5 µA –5 µA –5 µA –1.0 mA V 11 IM REL IN MITSUBISHI MICROCOMPUTERS Y AR M37736EHBXXXGP M37736EHBGS e. n. atio chang cific spe bject to l a fin re su a ot a is n limits his e: T ametric ic t No e par Som P PROM VERSION OF M37736MHBXXXGP ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol Parameter Limits Typ. Max. 9.5 19 mA 1.3 2.6 mA VCC = 5V, f(XIN) = 25 MHz (square waveform), f(XCIN) = 32.768 kHz, when a WIT instruction is executed (Note 2) 10 20 µA VCC = 5 V, f(XIN) : Stopped, f(XCIN) : 32.768 kHz, in operating (Note 3) 50 100 µA Test conditions Min. VCC = 5 V, f(XIN) = 25 MHz (square waveform), f(f2) = 12.5 MHz, f(XCIN) = 32.768 kHz, in operating (Note 1) VCC = 5 V, f(XIN) = 25 MHz (square waveform), (f(f2) = 1.5625 MHz), f(XCIN) = Stopped, in operating (Note 1) Power source current ICC Notes 1. 2. 3. 4. In single-chip mode, output pins are open, and other pins are VSS. Unit VCC = 5 V, f(XIN) : Stopped, 5 10 µA f(XCIN) : 32.768 kHz, when a WIT instruction is executed (Note 4) Ta = 25 °C, 1 µA when clock is stopped Ta = 85 °C, 20 µA when clock is stopped This applies when the main clock external input selection bit = “1”, the main clock division selection bit = “0”, and the signal output stop bit = “1”. This applies when the main clock external input selection bit = “1” and the system clock stop bit at wait state = “1”. This applies when CPU and the clock timer are operating with the sub clock (32.768 kHz) selected as the system clock. This applies when the XCOUT drivability selection bit = “0” and the system clock stop bit at wait state = “1”. A–D CONVERTER CHARACTERISTICS (VCC = AVCC = 5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz (Note), unless otherwise noted) Symbol Parameter Test conditions Resolution VREF = VCC Absolute accuracy VREF = VCC RLADDER Ladder resistance VREF = VCC tCONV Conversion time VREF Reference voltage Analog input voltage VIA Note. This applies when the main clock division selection bit = “0” and f(f2) = 12.5 MHz. Min. — — 12 10 9.44 2 0 Limits Typ. Max. 10 ±3 25 VCC VREF Unit Bits LSB kΩ µs V V IM REL INA MITSUBISHI MICROCOMPUTERS RY M37736EHBXXXGP M67736EHBGS . . tion hange c ifica pec ject to s l fina sub ot a its are is n m This etric li : e m ic Not e para Som P PROM VERSION OF M37736MHBXXXGP TIMING REQUIREMENTS (VCC = 5 V ± 10%, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz, unless otherwise noted (Note)) Notes 1. This applies when the main clock division selection bit = “0” and f(f2) = 12.5 MHz. 2. Input signal’s rise/fall time must be 100 ns or less, unless otherwise noted. External clock input Symbol Parameter Limits Unit Max. tc External clock input cycle time (Note 3) ns tw(H) External clock input high-level pulse width (Note 4) ns tw(L) External clock input low-level pulse width (Note 4) ns tr External clock rise time 8 ns External clock fall time 8 ns tf Notes 3. When the main clock division selection bit = “1”, the minimum value of tc = 80 ns. 4. When the main clock division selection bit = “1”, values of tw(H) / tc and tw(L) / tc must be set to values from 0.45 through 0.55. Min. 40 15 15 Single-chip mode Symbol tsu(P0D–E) tsu(P1D–E) tsu(P2D-E) tsu(P3D–E) tsu(P4D–E) tsu(P5D–E) tsu(P6D–E) tsu(P7D–E) tsu(P8D–E) tsu(P10D–E) th(E–P0D) th(E–P1D) th(E–P2D) th(E–P3D) th(E–P4D) th(E–P5D) th(E–P6D) th(E–P7D) th(E–P8D) th(E–P10D) Parameter Port P0 input setup time Port P1 input setup time Port P2 input setup time Port P3 input setup time Port P4 input setup time Port P5 input setup time Port P6 input setup time Port P7 input setup time Port P8 input setup time Port P10 input setup time Port P0 input hold time Port P1 input hold time Port P2 input hold time Port P3 input hold time Port P4 input hold time Port P5 input hold time Port P6 input hold time Port P7 input hold time Port P8 input hold time Port P10 input hold time Limits Min. 60 60 60 60 60 60 60 60 60 60 0 0 0 0 0 0 0 0 0 0 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Memory expansion mode and microprocessor mode Symbol tsu(D–E) tsu(D–RDE) tsu(RDY–φ1) tsu(HOLD–φ1) th(E–D) th(RDE–D) th(φ1–RDY) th(φ1–HOLD) Parameter Data input setup time (external bus mode A) Data input setup time (external bus mode B) RDY input setup time ____ HOLD input setup time Data input hold time (external bus mode A) Data input hold time (external bus mode B) ___ RDY input hold time ____ HOLD input hold time ___ Limits Min. 32 32 55 55 0 0 0 0 Max. Unit ns ns ns ns ns ns ns ns 13 IM REL IN MITSUBISHI MICROCOMPUTERS Y AR M37736EHBXXXGP M37736EHBGS e. n. atio chang cific spe bject to l a fin re su a ot a is n limits his e: T ametric ic t No e par Som P Timer A input (Count input in event counter mode) Symbol tc(TA) tw(TAH) tw(TAL) PROM VERSION OF M37736MHBXXXGP parameter TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width Limits Min. 80 40 40 Max. Unit ns ns ns Timer A input (Gating input in timer mode) Symbol tc(TA) tw(TAH) tw(TAL) parameter TAiIN input cycle time (Note) TAiIN input high-level pulse width (Note) TAiIN input low-level pulse width (Note) Limits Min. 320 160 160 Max. Unit ns ns ns Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS”. Timer A input (External trigger input in one-shot pulse mode) Symbol t c(TA) tw(TAH) tw(TAL) parameter TAiIN input cycle time (Note) TAiIN input high-level pulse width TAiIN input low-level pulse width Limits Min. 320 80 80 Max. Unit ns ns ns Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS”. Timer A input (External trigger input in pulse width modulation mode) Symbol tw(TAH) tw(TAL) parameter TAiIN input high-level pulse width TAiIN input low-level pulse width Limits Min. 80 80 Max. Unit ns ns Timer A input (Up-down input in event counter mode) Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP–TIN) th(TIN–UP) parameter TAiOUT input cycle time TAiOUT input high-level pulse width TAiOUT input low-level pulse width TAiOUT input setup time TAiOUT input hold time Limits Min. 2000 1000 1000 400 400 Max. Unit ns ns ns ns ns Timer A input (Two-phase pulse input in event counter mode) Symbol t c(TA) TAj input cycle time tsu(TAjIN–TAjOUT) TAjIN input setup time tsu(TAjOUT–TAjIN) TAjOUT input setup time 14 parameter Limits Min. 800 200 200 Max. Unit ns ns ns IM REL INA MITSUBISHI MICROCOMPUTERS RY M37736EHBXXXGP M67736EHBGS . . tion hange c ifica pec ject to s l fina sub ot a its are is n m This etric li : e m ic Not e para Som P PROM VERSION OF M37736MHBXXXGP Timer B input (Count input in event counter mode) Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Limits Parameter Min. 80 40 40 160 80 80 TBiIN input cycle time (one edge count) TBiIN input high-level pulse width (one edge count) TBiIN input low-level pulse width (one edge count) TBiIN input cycle time (both edges count) TBiIN input high-level pulse width (both edges count) TBiIN input low-level pulse width (both edges count) Max. Unit ns ns ns ns ns ns Timer B input (Pulse period measurement mode) Symbol tc(TB) tw(TBH) tw(TBL) Limits Parameter Min. 320 160 160 TBiIN input cycle time (Note) TBiIN input high-level pulse width (Note) TBiIN input low-level pulse width (Note) Max. Unit ns ns ns Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS”. Timer B input (Pulse width measurement mode) Symbol tc(TB) tw(TBH) tw(TBL) Limits Parameter Min. 320 160 160 TBiIN input cycle time (Note) TBiIN input high-level pulse width (Note) TBiIN input low-level pulse width (Note) Max. Unit ns ns ns Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS”. A-D trigger input Symbol Limits Parameter Min. 1000 125 __________ tc(AD) tw(ADL) AD TRG input cycle time (minimum allowable trigger) __________ ADTRG input low-level pulse width Max. Unit ns ns Serial I/O Symbol tc(CK) tw(CKH) tw(CKL) td(C–Q) th(C–Q) tsu(D–C) th(C–D) Limits Parameter Min. 200 100 100 CLKi input cycle time CLKi input high-level pulse width CLKi input low-level pulse width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time Max. 80 0 30 90 ______ Unit ns ns ns ns ns ns ns ____ External interrupt INTi input, key input interrupt KIi input Symbol Parameter _______ tw(INH) tw(INL) tw(KIL) INT i input high-level pulse width ______ INTi input low-level pulse width ____ KIi input low-level pulse width Limits Min. 250 250 250 Max. Unit ns ns ns 15 IM REL IN MITSUBISHI MICROCOMPUTERS Y AR M37736EHBXXXGP M37736EHBGS e. n. atio chang cific spe bject to l a fin re su a ot a is n limits his e: T ametric ic t No e par Som P PROM VERSION OF M37736MHBXXXGP DATA FORMULAS Timer A input (Gating input in timer mode) Symbol Parameter tc(TA) TAiIN input cycle time tw(TAH) TAiIN input high-level pulse width tw(TAL) TAiIN input low-level pulse width Limits Min. 8 ✕ 109 2 · f(f2) 4 ✕ 109 2 · f(f2) 4 ✕ 109 2 · f(f2) Max. Unit ns ns ns Timer A input (External trigger input in one-shot pulse mode) Symbol tc(TA) Parameter TAiIN input cycle time Limits Min. 8 ✕ 109 2 · f(f2) Max. Unit ns Timer B input (In pulse period measurement mode or pulse width measurement mode) Symbol Parameter tc(TB) TBiIN input cycle time tw(TBH) TBiIN input high-level pulse width tw(TBL) TBiIN input low-level pulse width Limits Min. 8 ✕ 109 2 · f(f2) 4 ✕ 109 2 · f(f2) 4 ✕ 109 2 · f(f2) Note. f(f2) represents the clock f2 frequency. For the relation to the main clock and sub clock, refer to Table 10 in data sheet “ M37736MHBXXXGP ”. 16 Max. Unit ns ns ns MI I L E NA MITSUBISHI MICROCOMPUTERS RY M37736EHBXXXGP M67736EHBGS . . tion nge ifica to cha t pec al s subjec in f are ot a is n limits This ric ice: aramet t o N ep Som PR PROM VERSION OF M37736MHBXXXGP SWITCHING CHARACTERISTICS (VCC = 5 V ± 10%, VSS = 0 V, Ta = –20 to 85°C, f(XIN) = 25 MHz (Note), unless otherwise noted) Symbol Parameter Test conditions td(E–P0Q) Port P0 data output delay time td(E–P1Q) Port P1 data output delay time td(E–P2Q) Port P2 data output delay time td(E–P3Q) Port P3 data output delay time td(E–P4Q) Port P4 data output delay time Fig. 2 td(E–P5Q) Port P5 data output delay time td(E–P6Q) Port P6 data output delay time td(E–P7Q) Port P7 data output delay time td(E–P8Q) Port P8 data output delay time td(E–P9Q) Port P9 data output delay time Port P10 data output delay time td(E–P10Q) Note. This applies when the main clock division selection bit = “0” and f(f2) = 12.5 MHz. Limits Min. Max. 80 80 80 80 80 80 80 80 80 80 80 Unit ns ns ns ns ns ns ns ns ns ns ns P0 P1 P2 P3 50 pF P4 P5 P6 P7 P8 P9 P10 φ1 E Fig. 2 Measuring circuit for ports P0 – P10 and φ1 17 IM REL IN MITSUBISHI MICROCOMPUTERS Y AR M37736EHBXXXGP M37736EHBGS e. n. atio chang cific spe bject to l a fin re su a ot a is n limits his e: T ametric ic t No e par Som P PROM VERSION OF M37736MHBXXXGP [External bus mode A] Memory expansion mode and microprocessor mode (VCC = 5 V ± 10%, VSS = 0 V, Ta = 25 °C, f(XIN) = 25 MHz (Note 1), unless otherwise noted) Symbol td(An–E) td(A–E) Parameter Address output delay time Address output delay time th(E–An) Address hold time tw(ALE) ALE pulse width tsu(A–ALE) th(ALE–A) Address output setup time Address hold time td(ALE–E) ALE output delay time td(E–DQ) th(E–DQ) Data output delay time Data hold delay time tw(EL) tpxz(E–DZ) tpzx(E–DZ) td(BHE–E) td(R/W–E) th(E–BHE) th(E–R/W) td(E–φ1) td(φ1–HLDA) _ E pulse width Test (Note 2) Wait mode conditions No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 Fig. 2 BHE output delay time _ R/ W output delay time ___ No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 BHE hold time _ R/ W hold time φ1 output delay time ____ HLDA output delay time Unit 12 ns 87 ns 12 ns 75 ns 18 ns 22 ns 57 ns 5 ns 45 ns 9 ns 15 ns 4 ns 18 50 ns ns ns ns 130 ns 10 20 ns ns 12 ns 87 ns 12 ns 87 18 18 0 ns ns ns ns ns 5 Notes 1. This applies when the main clock division selection bit = “0” and f(f2) = 12.5 MHz. 2. No wait : Wait bit = “1”. Wait 1 : The external memory area is accessed with wait bit = “0” and wait selection bit = “1”. Wait 0 : The external memory area is accessed with wait bit = “0” and wait selection bit = “0”. 18 Max. 45 Floating start delay time Floating release delay time ___ Limits Min. 18 50 IM REL INA MITSUBISHI MICROCOMPUTERS RY M37736EHBXXXGP M67736EHBGS . . tion hange c ifica pec ject to s l fina sub ot a its are is n m This etric li : e m ic Not e para Som P PROM VERSION OF M37736MHBXXXGP [External bus mode A] Memory expansion mode and microprocessor mode Bus timing data formulas (VCC = 5 V ± 10%, VSS = 0 V, Ta = –20 to 85 °C, Symbol td(An–E) Parameter Address output delay time f(XIN) = 25 MHz (Max., Note), unless otherwise noted) Wait mode No wait Wait 1 Wait 0 td(A–E) Address output delay time No wait Wait 1 Wait 0 th(E–An) Address hold time tw(ALE) ALE pulse width No wait Wait 1 Wait 0 tsu(A–ALE) Address output setup time No wait Wait 1 Wait 0 th(ALE–A) Address hold time No wait Wait 1 Wait 0 td(ALE–E) td(E–DQ) th(E–DQ) ALE output delay time Wait 0 No wait 1 ✕ 109 2 · f(f2) 2 ✕ 109 2 · f(f2) 4 ✕ 109 2 · f(f2) E pulse width tpxz(E–DZ) Floating start delay time tpzx(E–DZ) Floating release delay time ___ BHE output delay time _ R/W output delay time No wait Wait 1 No wait Wait 1 Wait 0 ___ th(E–BHE) BHE hold time _ th(E–R/W) R/W hold time td(E–φ1) φ1 output delay time ns ns ns ns ns ns ns ns – 25 ns ns – 30 ns 1 ✕ 109 2 · f(f2) 1 ✕ 109 2 · f(f2) 3 ✕ 109 2 · f(f2) 1 ✕ 109 2 · f(f2) 3 ✕ 109 2 · f(f2) 1 ✕ 109 2 · f(f2) 1 ✕ 109 2 · f(f2) ns – 22 ns – 30 ns – 30 ns 5 Wait 0 td(R/W–E) ns 45 Wait 1 Wait 0 Unit ns 4 1 ✕ 109 2 · f(f2) Data hold time _ Max. 9 1 ✕ 109 2 · f(f2) Data output delay time tw(EL) td(BHE–E) No wait Wait 1 Limits Min. 1 ✕ 109 – 28 2 · f(f2) 3 ✕ 109 – 33 2 · f(f2) 9 1 ✕ 10 – 28 2 · f(f2) 9 3 ✕ 10 – 45 2 · f(f2) 9 1 ✕ 10 – 22 2 · f(f2) 9 1 ✕ 10 – 18 2 · f(f2) 9 2 ✕ 10 – 23 2 · f(f2) 9 1 ✕ 10 – 35 2 · f(f2) 2 ✕ 109 – 35 2 · f(f2) ns – 20 ns – 28 ns – 33 ns – 28 ns – 33 ns – 22 ns – 22 ns 0 18 ns Notes 1. This applies when the main-clock division selection bit = “0”. 2. f(f2) represents the clock f2 frequency. For the relation to the main clock and sub clock, refer to Table 10 in data sheet “ M37736MHBXXXGP ”. 19 IM REL IN MITSUBISHI MICROCOMPUTERS Y AR M37736EHBXXXGP M37736EHBGS e. n. atio chang cific spe bject to l a fin re su a ot a is n limits his e: T ametric ic t No e par Som P PROM VERSION OF M37736MHBXXXGP [External bus mode B] Memory expansion mode and microprocessor mode (VCC = 5 V ± 10%, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz (Note 1), unless otherwise noted) Symbol Parameter td(CS–WE) td(CS–RDE) Chip-select output delay time th(WE–CS) th(RDE–CS) Chip-select hold time td(An–WE) td(An–RDE) Address output delay time td(A–WE) td(A–RDE) Address output delay time th(WE–An) th(RDE–An) Address hold time tw(ALE) ALE pulse width tsu(A–ALE) th(ALE–A) Address output setup time Address hold time td(ALE–WE) td(ALE–RDE) ALE output delay time td(WE–DQ) th(WE–DQ) Data output delay time Data hold delay time ___ ___ tw(WE) WEL/WEH pulse width tpxz(RDE–DZ) tpzx(RDE–DZ) Floating start delay time Floating release delay time tw(RDE) td(RSMP–WE) td(RSMP–RDE) th(φ1–RSMP) td(WE–φ1) td(RDE–φ1) td(φ1–HLDA) Test (Note 2) Wait mode conditions No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 Fig.2 Max. No wait Wait 1 Wait 0 Unit 12 ns 87 ns 4 ns 12 ns 87 ns 12 ns 75 ns 18 ns 22 ns 57 ns 5 ns 45 ns 9 ns 15 ns 4 ns 18 50 ns ns ns ns 130 ns 10 45 20 48 ns ns ns 128 ns 10 ns RSMP hold time 0 ns φ1 output delay time 0 ___ RDE pulse width 5 No wait Wait 1 Wait 0 ____ RSMP output delay time ____ 18 ns 50 ns ____ HLDA output delay time Notes 1. This applies when the main clock division selection bit = “0” and f(f2) = 12.5 MHz. 2. No wait : Wait bit = “1”. Wait 1 : The external memory area is accessed with wait bit = “0” and wait selection bit = “1”. Wait 0 : The external memory area is accessed with wait bit = “0” and wait selection bit = “0”. 20 Limits Min. IM REL INA MITSUBISHI MICROCOMPUTERS RY M37736EHBXXXGP M67736EHBGS . . tion hange c ifica pec ject to s l fina sub ot a its are is n m This etric li : e m ic Not e para Som P PROM VERSION OF M37736MHBXXXGP [External bus mode B] Memory expansion mode and microprocessor mode Bus timing data formulas (VCC = 5 V ± 10%, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz (Max., Note1), unless otherwise noted) Symbol Parameter td(CS–WE) td(CS–RDE) Chip-select output delay time th(WE–CS) th(RDE–CS) Chip-select hold time Wait mode No wait Wait 1 Wait 0 td(An–WE) td(An–RDE) Address output delay time td(A–WE) td(A–RDE) Address output delay time th(WE–An) th(RDE–An) Address hold time tw(ALE) ALE pulse width No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 Address output setup time No wait Wait 1 No wait Wait 1 Wait 0 th(ALE–A) Address hold time No wait Wait 1 ALE output delay time td(WE–DQ) Data output delay time th(WE–DQ) Data hold time tw(WE) WEL/WEH pulse width ___ ___ tpxz(RDE–DZ) tpzx(RDE–DZ) td(RSMP–WE) td(RSMP–RDE) th(φ1–RSMP) td(WE–φ1) td(RDE–φ1) No wait Wait 1 ____ RSMP output delay time ____ RSMP hold time φ1 output delay time ns ns – 28 ns – 33 ns – 28 ns – 45 ns – 22 ns – 18 ns – 23 ns – 35 ns – 35 ns ns 9 1 ✕ 10 2 · f(f2) – 25 ns ns 4 Wait 0 1 ✕ 10 2 · f(f2) No wait 1 ✕ 109 2 · f(f2) 2 ✕ 109 2 · f(f2) 4 ✕ 109 2 · f(f2) 9 – 30 ns 45 Wait 1 Wait 0 No wait Wait 1 Wait 0 1 ✕ 109 2 · f(f2) 2 ✕ 109 2 · f(f2) 4 ✕ 109 2 · f(f2) 1 ✕ 109 2 · f(f2) 0 ns – 22 ns – 30 ns – 30 ns 5 Floating release delay time RDE pulse width ns 9 Floating start delay time ___ tw(RDE) 1 ✕ 10 2 · f(f2) 3 ✕ 109 2 · f(f2) 1 ✕ 109 2 · f(f2) 3 ✕ 109 2 · f(f2) 1 ✕ 109 2 · f(f2) 1 ✕ 109 2 · f(f2) 2 ✕ 109 2 · f(f2) 1 ✕ 109 2 · f(f2) 2 ✕ 109 2 · f(f2) Unit 9 Wait 0 td(ALE–WE) td(ALE–RDE) Max. 4 Wait 0 tsu(A–ALE) Limits Min. 1 ✕ 109 – 28 2 · f(f2) 3 ✕ 109 – 33 2 · f(f2) ns – 20 ns – 32 ns – 32 ns – 30 ns 0 ns 18 ns Notes 1. This applies when the main-clock division selection bit = “0”. 2. f(f2) represents the clock f2 frequency. For the relation to the main clock and sub clock, refer to Table 10 in data sheet “ M37736MHBXXXGP ”. 21 IM REL IN MITSUBISHI MICROCOMPUTERS Y AR M37736EHBXXXGP M37736EHBGS e. n. atio chang cific spe bject to l a fin re su a ot a is n limits his e: T ametric ic t No e par Som P PROM VERSION OF M37736MHBXXXGP TIMING DIAGRAM tr tf tc tw(H) Single-chip mode XIN E td(E–PiQ) Port Pi output (i = 0 – 10) tsu(PiD–E) th(E–PiD) Port Pi input (i = 0 – 8, 10) td(E–P1Q) Port P1 output tsu(P1D–E) th(E–P1D) Port P1 input td(E–P2Q) Port P2 output tsu(P2D–E) th(E–P2D) Port P2 input td(E–P3Q) Port P3 output tsu(P3D–E) th(E–P3D) Port P3 input td(E–P4Q) Port P4 output tsu(P4D–E) th(E–P4D) Port P4 input td(E–P5Q) Port P5 output tsu(P5D–E) th(E–P5D) Port P5 input td(E–P6Q) Port P6 output tsu(P6D–E) th(E–P6D) Port P6 input td(E–P7Q) Port P7 output tsu(P7D–E) th(E–P7D) Port P7 input td(E–P8Q) Port P8 output tsu(P8D–E) Port P8 input 22 th(E–P8D) tw(L) IM REL INA MITSUBISHI MICROCOMPUTERS RY M37736EHBXXXGP M67736EHBGS . . tion hange c ifica pec ject to s l fina sub ot a its are is n m This etric li : e m ic Not e para Som P PROM VERSION OF M37736MHBXXXGP tc(TA) tw(TAH) TAiIN input tw(TAL) tc(UP) tw(UPH) TAiOUT input tw(UPL) In event count mode TAiOUT input (Up-down input) TAiIN input (when count by falling) TAiIN input (when count by rising) th(TIN–UP) tsu(UP–TIN) In event counter mode (When two-phase pulse input is selected) tc(TA) TAjIN input tsu(TAjIN–TAjOUT) tsu(TAjIN–TAjOUT) tsu(TAjOUT–TAjIN) TAjOUT input tsu(TAjOUT–TAjIN) tc(TB) tw(TBH) TBiIN input tw(TBL) 23 IM REL IN MITSUBISHI MICROCOMPUTERS Y AR M37736EHBXXXGP M37736EHBGS e. n. atio chang cific spe bject to l a fin re su a ot a is n limits his e: T ametric ic t No e par Som P PROM VERSION OF M37736MHBXXXGP tc(AD) tw(ADL) ADTRG input tc(CK) tw(CKH) CLKi tw(CKL) th(C–Q) TxDi td(C–Q) tSU(D–C) RxDi tw(INL) INTi input Kli input 24 tw(INH) tw(KNL) th(C–D) MI I L E NA MITSUBISHI MICROCOMPUTERS RY M37736EHBXXXGP M67736EHBGS . . tion nge ifica to cha t pec al s subjec in f are ot a is n limits This ric ice: aramet t o N ep Som PR PROM VERSION OF M37736MHBXXXGP Memory expansion mode and microprocessor mode (When wait bit = “1”) φ1 E or RDE, WEL, WEH RDY input tsu(RDY– φ 1) th(φ1–RDY) ( When wait bit = “0”) φ1 E or RDE, WEL, WEH RDY input tsu(RDY– φ 1) th(φ 1–RDY) (When wait bit = “1” or “0” in common) φ1 tsu(HOLD– φ 1) th( φ 1–HOLD) HOLD input td(φ 1–HLDA) td(φ1–HLDA) HLDA output Test conditions • VCC = 5 V ± 10% • Input timing voltage : V IL = 1.0 V, VIH = 4.0 V • Output timing voltage : V OL = 0.8 V, VOH = 2.0 V 25 IM REL INA MITSUBISHI MICROCOMPUTERS RY M37736EHBXXXGP M37736EHBGS . . tion nge ifica to cha t pec al s subjec in f ot a its are is n m This etric li m ice: Not e para m So P PROM VERSION OF M37736MHBXXXGP [External bus mode A] Memory expansion mode and microprocessor mode (No wait : When wait bit = “1”) tw(L) tw(H) tf tr tc XIN φ1 td(E-φ1) td(E-φ1) tw(EL) E td(An-E) An th(E-An) Address tw(ALE) Address Address td(ALE-E) ALE th(ALE-A) th(E-DQ) tsu(A-ALE) Am/Dm Address Data tpxz(E-DZ) tpzx(E-DZ) Address Address th(E-D) td(E-DQ) td(A-E) tsu(D-E) DmIN Data td(BHE-E) th(E-BHE) BHE td(R/W-E) R/W Test conditions • VCC = 5 V ± 10% • Output timing voltage : VOL = 0.8 V, VOH = 2.0 V • Data input DmIN : VIL = 0.8 V, VIH = 2.5 V 26 th(E-R/W) IM REL INA MITSUBISHI MICROCOMPUTERS RY M37736EHBXXXGP M67736EHBGS . . tion hange c ifica pec ject to s l fina sub ot a its are is n m This etric li : e m ic Not e para Som P PROM VERSION OF M37736MHBXXXGP [External bus mode A] Memory expansion mode and microprocessor mode (Wait 1 : The external area is accessed when wait bit = “0” and wait selection = “1”.) tw(L) tw(H) tf tr tc XIN φ1 td(E–φ1) td(E–φ1) tw(EL) E td(An–E) th(E–An) Address An tw(ALE) Address td(ALE–E) ALE th(ALE–A) tsu(A–ALE) Am/Dm th(E–DQ) Address td(A–E) Data tpzx(E–DZ) tpxz(E–DZ) Address Address td(E–DQ) th(E–D) tsu(D–E) DmIN Data td(BHE–E) th(E–BHE) td(R/W–E) th(E–R/W) BHE R/W Test conditions • Vcc = 5 V ± 10% • Output timing voltage : V OL = 0.8 V, V OH = 2.0 V • Data input Dm IN : VIL = 0.8 V, VIH = 2.5 V 27 IM REL IN MITSUBISHI MICROCOMPUTERS Y AR M37736EHBXXXGP M37736EHBGS e. n. atio chang cific spe bject to l a fin re su a ot a is n limits his e: T ametric ic t No e par Som P PROM VERSION OF M37736MHBXXXGP [External bus mode A] Memory expansion mode and microprocessor mode (Wait 0 : The external memory area is accessed when wait bit = “0” and wait selection bit = “0”.) tw(L) tw(H) tf tr tc XIN φ1 td(E–φ1) td(E–φ1) tw(EL) E td(An–E) th(E–An) Address An tw(ALE) td(ALE–E) tsu(A–ALE) th(ALE–A) Address Address ALE th(E–DQ) Am/Dm Address Data tpzx(E–DZ) tpxz(E–DZ) Address Address td(E–DQ) td(A–E) tsu(D–E) Data DmIN td(BHE–E) th(E–BHE) BHE td(R/W–E) R/W Test conditions • Vcc = 5 V ± 10% • Output timing voltage : V OL = 0.8 V, V OH = 2.0 V • Data input Dm IN : VIL = 0.8 V, VIH = 2.5 V 28 th(E–R/W) th(E–D) MI I L E NA MITSUBISHI MICROCOMPUTERS RY M37736EHBXXXGP M67736EHBGS . . tion nge ifica to cha t pec al s subjec in f are ot a is n limits This ric ice: aramet t o N ep Som PR PROM VERSION OF M37736MHBXXXGP [External bus mode B] Memory expansion mode and microprocessor mode (No wait : When wait bit = “1”) tw(L) tw(H) tf tr tc XIN φ1 td(WE– φ1) td(WE– φ1) td(RDE– φ1 ) td(RDE– φ1) CS0 – CS4 t d(CS–WE) td(CS–RDE) th(WE –CS) An th(RDE– CS) Address Address td(An–WE) tw(ALE) Address td(An–RDE ) td(ALE –WE) th(RDE –An) th(WE–An) ALE td(ALE –RDE) th(ALE –A) tsu(A–ALE) th(WE–DQ) Am/Dm Address Data td(WE–DQ) tpxz(RDE –DZ) tpzx(RDE –DZ) Address Address td(A–RDE) t d(A–WE) tw(WE) th(RDE–D) WEL, WEH t su(D–RDE) DmIN Data tw(RDE) RDE th(φ1–RSMP) td(RSMP –WE) td(RSMP –RDE) RSMP Test conditions • Vcc = 5 V ± 10% • Output timing voltage : V OL = 0.8 V, V OH = 2.0 V • Data input Dm IN : VIL = 0.8 V, VIH = 2.5 V 29 IM REL IN MITSUBISHI MICROCOMPUTERS Y AR M37736EHBXXXGP M37736EHBGS e. n. atio chang cific spe bject to l a fin re su a ot a is n limits his e: T ametric ic t No e par Som P PROM VERSION OF M37736MHBXXXGP [External bus mode B] Memory expansion mode and microprocessor mode (Wait 1 : The external area is accessed when wait bit = “0” and wait selection bit = “1”.) tw(L) tw(H) tf tr tc XIN φ1 td(WE–φ1) td(WE–φ1) td(RDE–φ1) td(RDE-φ1) CS0 – CS4 th(WE–CS) th(RDE–CS) td(CS–RDE) td(CS–WE) An Address td(An–WE) tw(ALE) Address th(RDE–An) td(An–RDE) th(WE-An) td(ALE–WE) ALE th(ALE–A) tsu(A–ALE) Am/Dm td(ALE–RDE) tpxz(RDE–DZ) th(WE–DQ) Address td(A–WE) Data td(WE–DQ) Address tpzx(RDE–DZ) Address td(A–RDE) tw(WE) th(RDE–D) WEL, WEH tsu(D–RDE) DmIN Data tw(RDE) RDE th(φ 1–RSMP) RSMP td(RSMP–WE) Test conditions • Vcc = 5 V ± 10% • Output timing voltage : V OL = 0.8 V, V OH = 2.0 V • Data input Dm IN : VIL = 0.8 V, VIH = 2.5 V 30 td(RSMP–RDE) IM REL IN MITSUBISHI MICROCOMPUTERS Y AR M37736EHBXXXGP M67736EHBGS e. n. atio chang cific spe bject to l a fin re su a ot a is n limits his e: T ametric ic t No e par Som P PROM VERSION OF M37736MHBXXXGP [External bus mode B] Memory expansion mode and microprocessor mode (Wait 0 : The external memory area is accessed when wait bit = “0” and wait selection bit = “0”.) tw(L) tw(H) tf tr tc XIN φ1 td(WE– φ 1) td(RDE– φ1) td(RDE– φ 1) td(WE– φ 1) CS0 – CS4 td(CS–WE) th(WE–CS) td(CS–RDE) th(RDE–CS) Address An Address td(An–WE) tw(ALE) Address td(An–RDE) td(ALE–WE) th(RDE–An) th(WE–An) ALE td(ALE–RDE) tsu(A–ALE) Am/Dm Address th(ALE–A) Data th(WE–DQ) tpxz(RDE–DZ) tpzx(RDE–DZ) Address Address td(WE–DQ) td(A–WE) td(A–RDE) tw(WE) WEL, WEH tsu(D–RDE) th(RDE–D) Data DmIN tw(RDE) RDE td(RSMP–WE) th(φ1–RSMP) td(RSMP–RDE) RSMP Test conditions • Vcc = 5 V ± 10% • Output timing voltage : VOL = 0.8 V, VOH = 2.0 V • Data input DmIN : VIL = 0.8 V, VIH = 2.5 V 31 IM REL IN Y AR e. n. atio chang cific spe bject to l a fin re su a ot a is n limits his e: T ametric ic t No e par Som P MITSUBISHI MICROCOMPUTERS M37736EHBXXXGP M37736EHBGS PROM VERSION OF M37736MHBXXXGP PACKAGE OUTLINE Keep safety first in your circuit designs! ¡ Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials ¡ These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. ¡ Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. ¡ All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. 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Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. ¡ The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. ¡ If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. ¡ Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. © 1997 MITSUBISHI ELECTRIC CORP. H-LF488-A KI-9703 Printed in Japan (ROD) 2 New 32 publication, effective Mar. 1997. Specifications subject to change without notice. REVISION DESCRIPTION LIST Rev. No. M37736EHBXXXGP, M37736EHBGS Datasheet Rev. date Revision Description 1.00 First Edition 970611 2.00 The following are revised: 980731 Page Previous Version Revised Version P9 Right column Line 2 The M37736EHBXXXGP has 28 powerful addressing modes. Refer to the MITSUBISHI SEMICONDUCTORS DATA BOOK SINGLECHIP 16-BIT MICROCOMPUTERS for the details of each addressing mode. The M37736EHBXXXGP has 28 powerful addressing modes. Refer to the “7700 Family Software Manual” for the details. MACHINE INSTRUCTION LIST The M37736EHBXXXGP has 103 machine instructions. Refer to the MITSUBISHI SEMICONDUCTORS DATA BOOK SINGLECHIP 16-BIT MICROCOMPUTERS for details. Line 10 MACHINE INSTRUCTION LIST The M37736EHBXXXGP has 103 machine instructions. Refer to the “7700 Family Software Manual” for the details. (2) 100P6S mark specification form (2) 80P6N mark specification form (1)