Fault Protection and Detection, 10 Ω RON, Dual SPDT Switch ADG5436F Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM Overvoltage protection up to −55 V and +55 V Power-off protection up to −55 V and +55 V Overvoltage detection on source pins Interrupt flags indicate fault status Low on resistance: 10 Ω (typical) On-resistance flatness of 0.5 Ω (maximum) 6 kV human body model (HBM) ESD rating Latch-up immune under any circumstance Known state without digital inputs present VSS to VDD analog signal range ±5 V to ±22 V dual supply operation 8 V to 44 V single-supply operation Fully specified at ±15 V, ±20 V, +12 V, and +36 V ADG5436F S1A S2A D1 D2 S1B S2B IN1 IN2 EN SF FF DR NOTES 1. SWITCHES SHOWN FOR A LOGIC 1 INPUT. 12882-001 FAULT DETECTION + SWITCH DRIVER Figure 1. APPLICATIONS Analog input/output modules Process control/distributed control systems Data acquisition Instrumentation Avionics Automatic test equipment Communication systems Relay replacement GENERAL DESCRIPTION The ADG5436F is an analog multiplexer, containing two independently selectable single-pole, double-throw (SPDT) switches. An EN input is used to disable all the switches. For use in multiplexer applications, both switches exhibit break-beforemake switching action. resistance of the ADG5436F, combined with the on-resistance flatness over a significant portion of the signal range, makes it an ideal solution for data acquisition and gain switching applications where excellent linearity and low distortion are critical. Each channel conducts equally well in both directions when on, and each switch has an input signal range that extends to the supplies. The digital inputs are compatible with 3 V logic inputs over the full operating supply range. Note that, throughout this data sheet, the dual function pin names are referenced only by the relevant function where applicable. See the Pin Configurations and Function Descriptions section for full pin names and function descriptions. When no power supplies are present, the switch remains in the off condition, and the channel inputs are high impedance. Under normal operating conditions, if the analog input signal level on any Sxx pin exceeds VDD or VSS by a threshold voltage, VT, the channel turns off and that Sxx pin becomes high impedance. If the channel is on, the drain pin reacts according to the drain response (DR) input pin. If the DR pin is left floating or pulled high, the drain remains high impedance and floats. If the DR pin is pulled low, the drain pulls to the exceeded rail. Input signal levels of up to +55 V or −55 V relative to ground are blocked, in both the powered and unpowered conditions. The low on PRODUCT HIGHLIGHTS Rev. B 1. 2. 3. 4. 5. 6. Source pins are protected against voltages greater than the supply rails, up to −55 V and +55 V. Source pins are protected against voltages between −55 V and +55 V in an unpowered state. Overvoltage detection with digital output indicates the operating state of the switches. Trench isolation guards against latch-up. Optimized for low on resistance and on-resistance flatness. The ADG5436F operates from a dual supply of ±5 V up to ±22 V, or a single power supply of 8 V up to 44 V. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. 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Technical Support www.analog.com ADG5436F Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Test Circuits..................................................................................... 20 Applications ....................................................................................... 1 Terminology .................................................................................... 24 Functional Block Diagram .............................................................. 1 Theory of Operation ...................................................................... 26 General Description ......................................................................... 1 Switch Architecture .................................................................... 26 Product Highlights ........................................................................... 1 Fault Protection .......................................................................... 27 Revision History ............................................................................... 2 Applications Information .............................................................. 28 Specifications..................................................................................... 3 Power Supply Rails ..................................................................... 28 ±15 V Dual Supply ....................................................................... 3 Power Supply Sequencing Protection ...................................... 28 ±20 V Dual Supply ....................................................................... 5 Signal Range ................................................................................ 28 12 V Single Supply ........................................................................ 7 Low Impedance Channel Protection ....................................... 28 36 V Single Supply ........................................................................ 9 Power Supply Recommendations............................................. 28 Continuous Current per Channel, Sxx or Dx ......................... 11 High Voltage Surge Suppression .............................................. 28 Absolute Maximum Ratings .......................................................... 12 Intelligent Fault Detection ........................................................ 29 ESD Caution ................................................................................ 12 Large Voltage, High Frequency Signals ................................... 29 Pin Configurations and Function Descriptions ......................... 13 Outline Dimensions ....................................................................... 30 Truth Tables for Switches .......................................................... 14 Ordering Guide .......................................................................... 30 Typical Performance Characteristics ........................................... 15 REVISION HISTORY 1/16—Rev. A to Rev. B Changes to Table 1 ............................................................................ 3 Changes to Table 2 ............................................................................ 5 Changes to Table 3 ............................................................................ 7 Changes to Table 4 ............................................................................ 9 Changes to ESD Performance Section ......................................... 26 5/15—Rev. 0 to Rev. A Added 16-Lead LFCSP Package........................................ Universal Changes to Table 1 ............................................................................ 3 Changes to Table 2 ............................................................................ 5 Changes to Table 3 ............................................................................ 7 Changes to Table 4 ............................................................................ 9 Changes to Table 5 .......................................................................... 11 Changes to Table 6 .......................................................................... 12 Added Figure 3; Renumbered Sequentially ................................ 13 Changes to Table 7 .......................................................................... 13 Added Figure 53.............................................................................. 30 Updated Outline Dimensions ....................................................... 30 Changes to Ordering Guide .......................................................... 30 1/15—Revision 0: Initial Version Rev. B | Page 2 of 30 Data Sheet ADG5436F SPECIFICATIONS ±15 V DUAL SUPPLY VDD = 15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, CDECOUPLING = 0.1 µF, unless otherwise noted. Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, ∆RON On-Resistance Flatness, RFLAT(ON) Threshold Voltage, VT LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID (On), IS (On) +25°C −40°C to +85°C VDD to VSS 10 11.2 9.5 10.7 0.15 14 16.5 13.5 16 0.65 0.15 0.6 0.6 0.8 0.95 0.7 0.8 0.9 0.1 0.4 0.7 1.1 1.1 0.5 0.5 ±0.1 ±1.5 ±0.1 ±1.5 ±0.5 ±1.5 ±5.0 ±7.0 ±5.0 FAULT Source Leakage Current, IS With Overvoltage Power Supplies Grounded or Floating Drain Leakage Current, ID With Overvoltage Power Supplies Grounded Power Supplies Floating DIGITAL INPUTS/OUTPUTS Input Voltage High, VINH Input Voltage Low, VINL Input Current, IINL or IINH −40°C to +125°C ±21 ±25 Ω max Ω typ Ω max Ω typ Ω max Ω typ Ω max V typ nA typ nA max nA typ nA max nA typ nA max ±72 µA typ ±49 µA typ ±2.0 nA typ ±8.0 ±10 ±15 ±30 ±10 ±50 ±10 ±49 nA max nA typ ±100 ±10 nA max µA typ 2.0 0.8 V min V max µA typ µA max pF typ V min V max ±0.7 6.0 2.0 0.8 V Ω typ Ω max Ω typ Ω max Ω typ ±21 ±1.2 Digital Input Capacitance, CIN Output Voltage High, VOH Output Voltage Low, VOL Unit Rev. B | Page 3 of 30 Test Conditions/Comments VDD = 13.5 V, VSS = −13.5 V, see Figure 30 Voltage on the Sxx pins (VS) = ±10 V, IS = −10 mA VS = ±9 V, IS = −10 mA VS = ±10 V, IS = −10 mA VS = ±9 V, IS = −10 mA VS = ±10 V, IS = −10 mA VS = ±9 V, IS = −10 mA See Figure 26 VDD = 16.5 V, VSS = −16.5 V VS = ±10 V, voltage on the Dx pin (VD) = ∓10 V, see Figure 31 VS = ±10 V, VD = ∓10 V, see Figure 31 VS = VD = ±10 V, see Figure 32 VDD = 16.5 V, VSS = −16.5 V, GND = 0 V, VS = ±55 V, see Figure 35 VDD = 0 V or floating, VSS = 0 V or floating, GND = 0 V, EN = 0 V or floating, INx = 0 V or floating, VS = ±55 V, see Figure 36 DR = floating or >2 V VDD = 16.5 V, VSS = −16.5 V, GND = 0 V, VS = ±55 V, see Figure 35 VDD = 0 V, VSS = 0 V, GND = 0 V, INx = 0 V or floating, VS = ±55 V, EN = 0 V, see Figure 36 VDD = floating, VSS = floating, GND = 0 V, VS = ±55 V, EN = 0 V, see Figure 36 VIN = VGND or VDD ADG5436F Parameter DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION tON (EN) tOFF (EN) Break-Before-Make Time Delay, tD Overvoltage Response Time, tRESPONSE Overvoltage Recovery Time, tRECOVERY Interrupt Flag Response Time, tDIGRESP Interrupt Flag Recovery Time, tDIGREC Charge Injection, QINJ Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion Plus Noise, THD + N −3 dB Bandwidth Insertion Loss Source Capacitance (CS), Off Drain Capacitance (CD), Off CD (On), CS (On) POWER REQUIREMENTS Normal Mode IDD IGND ISS Fault Mode IDD IGND ISS Data Sheet +25°C −40°C to +85°C −40°C to +125°C 555 570 530 550 215 220 Unit Test Conditions/Comments ns typ ns max ns typ ns max ns typ ns max ns typ RL = 300 Ω, CL = 35 pF VS = 10 V, see Figure 46 RL = 300 Ω, CL = 35 pF VS = 10 V, see Figure 45 RL = 300 Ω, CL = 35 pF VS = 10 V, see Figure 45 RL = 300 Ω, CL = 35 pF 190 ns min ns typ VS = 10 V, see Figure 44 RL = 1 kΩ, CL = 2 pF, see Figure 39 750 ns max ns typ RL = 1 kΩ, CL = 2 pF, see Figure 40 1200 115 ns max ns typ CL = 12 pF, see Figure 41 85 µs typ CL = 12 pF, see Figure 42 600 −724 −71 −73 0.001 ns typ pC typ dB typ dB typ % typ CL = 12 pF, RPULLUP = 1 kΩ, see Figure 43 VS = 0 V, RS = 0 Ω, CL = 1 nF, see Figure 47 RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 33 RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 34 RL = 10 kΩ, VS = 15 V p-p, f = 20 Hz to 20 kHz, see Figure 38 169 −0.8 12 24 37 MHz typ dB typ pF typ pF typ pF typ RL = 50 Ω, CL = 5 pF, see Figure 37 RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 37 VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VDD = 16.5 V, VSS = −16.5 V, GND = 0 V, digital inputs = 0 V, 5 V, or VDD 400 540 435 515 165 210 320 510 680 820 725 1100 85 1150 60 0.9 1.2 0.4 0.55 0.5 0.65 0.6 0.7 mA typ mA max mA typ mA max mA typ mA max VS = ±55 V 1.2 1.6 0.8 1.0 0.5 1.0 VDD/VSS 1 1.3 1.8 1.1 1.8 ±5 ±22 mA typ mA max mA typ mA max mA typ mA max V min V max Guaranteed by design. Not subject to production test. Rev. B | Page 4 of 30 Digital inputs = 5 V VS = ±55 V, VD = 0 V GND = 0 V GND = 0 V Data Sheet ADG5436F ±20 V DUAL SUPPLY VDD = 20 V ± 10%, VSS = −20 V ± 10%, GND = 0 V, CDECOUPLING = 0.1 µF, unless otherwise noted. Table 2. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, ∆RON On-Resistance Flatness, RFLAT(ON) Threshold Voltage, VT LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID (On), IS (On) +25°C −40°C to +85°C VDD to VSS 10 11.5 9.5 11 0.15 0.65 0.15 0.6 1.0 1.4 0.1 0.4 0.7 ±0.1 ±1.5 ±0.1 ±1.5 ±0.5 ±1.5 14.5 16.5 14 16.5 0.8 0.95 0.7 0.8 1.5 1.5 0.5 0.5 ±7.0 ±25 ±5.0 ±21 nA typ nA max nA typ nA max nA typ nA max ±84 µA typ ±49 µA typ ±5.0 nA typ ±1.0 ±10 ±1.0 Power Supplies Grounded Power Supplies Floating ±30 ±10 ±50 ±10 ±1.0 µA max nA typ ±100 ±10 nA max µA typ 2.0 0.8 V min V max µA typ µA max pF typ V min V max 0.7 1.2 Digital Input Capacitance, CIN Output Voltage High, VOH Output Voltage Low, VOL V Ω typ Ω max Ω typ Ω max Ω typ Ω max Ω typ Ω max Ω typ Ω max Ω typ Ω max V typ ±21 Power Supplies Grounded or Floating DIGITAL INPUTS Input Voltage High, VINH Input Voltage Low, VINL Input Current, IINL or IINH Unit ±5.0 FAULT Source Leakage Current, IS With Overvoltage Drain Leakage Current, ID With Overvoltage −40°C to +125°C 6.0 2.0 0.8 Rev. B | Page 5 of 30 Test Conditions/Comments VDD = 18 V, VSS = −18 V, see Figure 30 VS = ±15 V, IS = −10 mA VS = ±13.5 V, IS = −10 mA VS = ±15 V, IS = −10 mA VS = ±13.5 V, IS = −10 mA VS = ±15 V, IS = −10 mA VS = ±13.5 V, IS = −10 mA See Figure 26 VDD = 22 V, VSS = −22 V VS = ±15 V, VD = ±15 V, see Figure 31 VS = ±15 V, VD = ±15 V, see Figure 31 VS = VD = ±15 V, see Figure 32 VDD = +22 V, VSS = −22 V, GND = 0 V, VS = ±55 V, see Figure 35 VDD = 0 V or floating, VSS = 0 V or floating, GND = 0 V, EN = 0 V or floating, INx = 0 V or floating, VS = ±55 V, see Figure 36 DR = floating or >2 V VDD = +22 V, VSS = −22 V, GND = 0 V, INx = 0 V or floating, VS = ±55 V, see Figure 35 VDD = 0 V, VSS = 0 V, GND = 0 V, VS = ±55 V, EN = 0 V, see Figure 36 VDD = floating, VSS = floating, GND = 0 V, VS = ±55 V, EN = 0 V, see Figure 36 VIN = VGND or VDD ADG5436F Parameter DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION tON (EN) tOFF (EN) Break-Before-Make Time Delay, tD Data Sheet +25°C 405 540 430 535 170 205 330 −40°C to +85°C −40°C to +125°C 555 570 560 585 210 215 205 Overvoltage Response Time, tRESPONSE Test Conditions/Comments ns typ ns max ns typ ns max ns typ ns max ns typ ns min ns typ ns max ns typ ns max ns typ µs typ ns typ pC typ RL = 300 Ω, CL = 35 pF VS = 10 V, see Figure 46 RL = 300 Ω, CL = 35 pF VS = 10 V, see Figure 45 RL = 300 Ω, CL = 35 pF VS = 10 V, see Figure 45 RL = 300 Ω, CL = 35 pF VS = 10 V, see Figure 44 RL = 1 kΩ, CL = 2 pF, see Figure 39 Charge Injection, QINJ 430 560 930 1300 85 60 600 −737 Off Isolation −72 dB typ Channel-to-Channel Crosstalk −73 dB typ Total Harmonic Distortion Plus Noise, THD + N 0.001 % typ −3 dB Bandwidth Insertion Loss 171 −0.8 MHz typ dB typ 11 23 36 pF typ pF typ pF typ Overvoltage Recovery Time, tRECOVERY Interrupt Flag Response Time, tDIGRESP Interrupt Flag Recovery Time, tDIGREC CS (Off ) CD (Off ) CD (On), CS (On) POWER REQUIREMENTS Normal Mode IDD IGND ISS Fault Mode IDD IGND ISS VDD/VSS 1 Unit 0.9 1.2 0.4 0.55 0.5 0.65 605 630 1500 1700 115 85 1.3 0.6 0.7 RL = 1 kΩ, CL = 2 pF, see Figure 40 CL = 12 pF, see Figure 41 CL = 12 pF, see Figure 42 CL = 12 pF, RPULLUP = 1 kΩ, see Figure 43 VS = 0 V, RS = 0 Ω, CL = 1 nF, see Figure 47 RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 33 RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 34 RL = 10 kΩ, VS = 20 V p-p, f = 20 Hz to 20 kHz, see Figure 38 RL = 50 Ω, CL = 5 pF, see Figure 37 RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 37 VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VDD = 22 V, VSS = −22 V, digital inputs = 0 V, 5 V, or VDD mA typ mA max mA typ mA max mA typ mA max VS = ±55 V 1.2 1.6 0.8 1.0 0.5 1.0 1.8 1.1 1.8 ±5 ±22 Guaranteed by design. Not subject to production test. Rev. B | Page 6 of 30 mA typ mA max mA typ mA max mA typ mA max V min V max Digital inputs = 5 V VS = ±55 V, VD = 0 V GND = 0 V GND = 0 V Data Sheet ADG5436F 12 V SINGLE SUPPLY VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, CDECOUPLING = 0.1 µF, unless otherwise noted. Table 3. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, ∆RON On-Resistance Flatness, RFLAT(ON) Threshold Voltage, VT LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID (On), IS (On) +25°C −40°C to +85°C 0 V to VDD 22 24.5 10 11.2 0.2 0.65 0.2 0.65 12.5 14.5 0.6 0.9 0.7 ±0.1 ±1.5 ±0.1 ±1.5 ±0.5 ±1.5 31 37 14 16.5 0.8 0.95 0.8 0.95 19 23 1.1 1.3 ±7.0 ±25 ±5.0 ±21 nA typ nA max nA typ nA max nA typ nA max ±65 µA typ ±49 µA typ ±2.0 nA typ ±8.0 ±10 ±15 Power Supplies Grounded Power Supplies Floating ±30 ±10 ±50 ±10 ±49 nA max nA typ ±100 ±10 nA max µA typ 2.0 0.8 V min V max µA typ µA max pF typ V min V max 0.7 1.2 Digital Input Capacitance, CIN Output Voltage High, VOH Output Voltage Low, VOL V Ω typ Ω max Ω typ Ω max Ω typ Ω max Ω typ Ω max Ω typ Ω max Ω typ Ω max V typ ±21 Power Supplies Grounded or Floating DIGITAL INPUTS Input Voltage High, VINH Input Voltage Low, VINL Input Current, IINL or IINH Unit ±5.0 FAULT Source Leakage Current, IS With Overvoltage Drain Leakage Current, ID With Overvoltage −40°C to +125°C 6.0 2.0 0.8 Rev. B | Page 7 of 30 Test Conditions/Comments VDD = 10.8 V, VSS = 0 V, see Figure 30 VS = 0 V to 10 V, IS = −10 mA VS = 3.5 V to 8.5 V, IS = −10 mA VS = 0 V to 10 V, IS = −10 mA VS = 3.5 V to 8.5 V, IS = −10 mA VS = 0 V to 10 V, IS = −10 mA VS = 3.5 V to 8.5 V, IS = −10 mA See Figure 26 VDD = 13.2 V, VSS = 0 V VS = 1 V/10 V, VD = 10 V/1 V, see Figure 31 VS = 1 V/10 V, VD = 10 V/1 V, see Figure 31 VS = VD = 1 V/10 V, see Figure 32 VDD = 13.2 V, VSS = 0 V, GND = 0 V, VS = ±55 V, see Figure 35 VDD = 0 V or floating, VSS = 0 V or floating, GND = 0 V, EN = 0 V or floating, VS = ±55 V, see Figure 36 DR = floating or >2 V VDD = 13.2 V, VSS = 0 V, GND = 0 V, INx = 0 V or floating, VS = ±55 V, see Figure 35 VDD = 0 V, VSS = 0 V, GND = 0 V, VS = ±55 V, EN = 0 V, see Figure 36 VDD = floating, VSS = floating, GND = 0 V, VS = ±55 V, EN = 0 V, see Figure 36 VIN = VGND or VDD ADG5436F Parameter DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION tON (EN) tOFF (EN) Break-Before-Make Time Delay, tD Data Sheet +25°C 400 545 435 515 185 230 300 −40°C to +85°C −40°C to +125°C 560 570 530 550 240 250 180 Overvoltage Response Time, tRESPONSE Overvoltage Recovery Time, tRECOVERY Interrupt Flag Response Time, tDIGRESP Interrupt Flag Recovery Time, tDIGREC Charge Injection, QINJ Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion Plus Noise, THD + N −3 dB Bandwidth Insertion Loss CS (Off ) CD (Off ) CD (On), CS (On) POWER REQUIREMENTS Normal Mode IDD IGND ISS Fault Mode IDD IGND ISS VDD 1 590 770 680 850 85 60 600 −341 −68 −70 0.007 830 870 910 1000 115 85 152 −0.8 14 30 41 0.9 1.2 0.4 0.55 0.5 0.65 Unit Test Conditions/Comments ns typ ns max ns typ ns max ns typ ns max ns typ ns min ns typ ns max ns typ ns max ns typ µs typ ns typ pC typ dB typ dB typ % typ RL = 300 Ω, CL = 35 pF VS = 10 V, see Figure 46 RL = 300 Ω, CL = 35 pF VS = 8 V, see Figure 45 RL = 300 Ω, CL = 35 pF VS = 8 V, see Figure 45 RL = 300 Ω, CL = 35 pF VS = 8 V, see Figure 44 RL = 1 kΩ, CL = 2 pF, see Figure 39 MHz typ dB typ pF typ pF typ pF typ 1.3 0.6 0.7 RL = 1 kΩ, CL = 2 pF, see Figure 40 CL = 12 pF, see Figure 41 CL = 12 pF, see Figure 42 CL = 12 pF, RPULLUP = 1 kΩ, see Figure 43 VS = 6 V, RS = 0 Ω, CL = 1 nF, see Figure 47 RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 33 RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 34 RL = 10 kΩ, VS = 6 V p-p, f = 20 Hz to 20 kHz, see Figure 38 RL = 50 Ω, CL = 5 pF, see Figure 37 RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 37 VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz VDD = 13.2 V, VSS = 0 V, digital inputs = 0 V, 5 V, or VDD mA typ mA max mA typ mA max mA typ mA max VS = ±55 V 1.2 1.6 0.8 1.0 0.5 1.0 1.8 1.1 1.8 8 44 Guaranteed by design. Not subject to production test. Rev. B | Page 8 of 30 mA typ mA max mA typ mA max mA typ mA max V min V max Digital inputs = 5 V VS = ±55 V, VD = 0 V GND = 0 V GND = 0 V Data Sheet ADG5436F 36 V SINGLE SUPPLY VDD = 36 V ± 10%, VSS = 0 V, GND = 0 V, CDECOUPLING = 0.1 µF, unless otherwise noted. Table 4. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, ∆RON On-Resistance Flatness, RFLAT(ON) Threshold Voltage, VT LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID (On), IS (On) +25°C −40°C to +85°C 0 V to VDD 22 24.5 10 11 0.15 0.65 0.15 0.6 12.5 14.5 0.1 0.4 0.7 ±0.1 ±1.5 ±0.1 ±1.5 ±0.5 ±1.5 31 37 14 16.5 0.8 0.95 0.7 0.8 19 23 0.5 0.5 ±7.0 ±25 ±5.0 ±21 nA typ nA max nA typ nA max nA typ nA max ±60 µA typ ±49 µA typ ±2.0 nA typ ±8.0 ±10 ±15 Power Supplies Grounded Power Supplies Floating ±30 ±10 ±50 ±10 ±49 nA max nA typ ±100 ±10 nA max µA typ 2.0 0.8 V min V max µA typ µA max pF typ V min V max 0.7 1.2 Digital Input Capacitance, CIN Output Voltage High, VOH Output Voltage Low, VOL V Ω typ Ω max Ω typ Ω max Ω typ Ω max Ω typ Ω max Ω typ Ω max Ω typ Ω max V typ ±21 Power Supplies Grounded or Floating DIGITAL INPUTS Input Voltage High, VINH Input Voltage Low, VINL Input Current, IINL or IINH Unit ±5.0 FAULT Source Leakage Current, IS With Overvoltage Drain Leakage Current, ID With Overvoltage −40°C to +125°C 6.0 2.0 0.8 Rev. B | Page 9 of 30 Test Conditions/Comments VDD = 32.4 V, VSS = 0 V, see Figure 30 VS = 0 V to 30 V, IS = −10 mA VS = 4.5 V to 28 V, IS = −10 mA VS = 0 V to 30 V, IS = −10 mA VS = 4.5 V to 28 V, IS = −10 mA VS = 0 V to 30 V, IS = −10 mA VS = 4.5 V to 28 V, IS = −10 mA See Figure 26 VDD =39.6 V, VSS = 0 V VS = 1 V/30 V, VD = 30 V/1 V, see Figure 31 VS = 1 V/30 V, VD = 30 V/1 V, see Figure 31 VS = VD = 1 V/30 V, see Figure 32 VDD = 39.6 V, VSS = 0 V, GND = 0 V, INx = 0 V or floating, VS = +55 V, −40 V, see Figure 35 VDD = 0 V or floating, VSS = 0 V or floating, GND = 0 V, INx = 0 V or floating, VS = +55 V, −40 V, see Figure 36 DR = floating or >2 V VDD = 39.6 V, VSS = 0 V, GND = 0 V, VS = +55 V, −40 V, see Figure 35 VDD = 0 V, VSS = 0 V, GND = 0 V, VS = +55 V, −40 V, EN = 0 V, see Figure 36 VDD = floating, VSS = floating, GND = 0 V, VS = +55 V, −40 V, EN = 0 V, see Figure 36 VIN = VGND or VDD ADG5436F Parameter DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION tON (EN) tOFF (EN) Break-Before-Make Time Delay, tD Data Sheet +25°C 400 540 440 520 160 190 330 −40°C to +85°C −40°C to +125°C 555 570 540 560 195 200 210 Overvoltage Response Time, tRESPONSE Test Conditions/Comments ns typ ns max ns typ ns max ns typ ns max ns typ ns min ns typ ns max ns typ ns max ns typ µs typ ns typ pC typ RL = 300 Ω, CL = 35 pF VS = 10 V, see Figure 46 RL = 300 Ω, CL = 35 pF VS = 18 V, see Figure 45 RL = 300 Ω, CL = 35 pF VS = 18 V, see Figure 45 RL = 300 Ω, CL = 35 pF VS = 18 V, see Figure 44 RL = 1 kΩ, CL = 2 pF, see Figure 39 Charge Injection, QINJ 260 340 1500 2100 85 60 600 −627 Off Isolation −71 dB typ Channel-to-Channel Crosstalk −73 dB typ Total Harmonic Distortion Plus Noise, THD + N 0.001 % typ −3 dB Bandwidth Insertion Loss 173 −0.8 MHz typ dB typ 11 23 36 pF typ pF typ pF typ Overvoltage Recovery Time, tRECOVERY Interrupt Flag Response Time, tDIGRESP Interrupt Flag Recovery Time, tDIGREC CS (Off ) CD (Off ) CD (On), CS (On) POWER REQUIREMENTS Normal Mode IDD IGND ISS Fault Mode IDD IGND ISS VDD 1 Unit 0.9 1.2 0.4 0.55 0.5 0.65 360 385 2400 2700 115 85 1.3 0.6 0.7 RL = 1 kΩ, CL = 2 pF, see Figure 40 CL = 12 pF, see Figure 41 CL = 12 pF, see Figure 42 CL = 12 pF, RPULLUP = 1 kΩ, see Figure 43 VS = 18 V, RS = 0 Ω, CL = 1 nF, see Figure 47 RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 33 RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 34 RL = 10 kΩ, VS = 18 V p-p, f = 20 Hz to 20 kHz, see Figure 38 RL = 50 Ω, CL = 5 pF, see Figure 37 RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 37 VS = 18 V, f = 1 MHz VS = 18 V, f = 1 MHz VS = 18 V, f = 1 MHz VDD = 39.6 V, VSS = 0 V, digital inputs = 0 V, 5 V, or VDD mA typ mA max mA typ mA max mA typ mA max VS = +55 V, −40 V 1.2 1.6 0.8 1.0 0.5 1.0 1.8 1.1 1.8 8 44 Guaranteed by design. Not subject to production test. Rev. B | Page 10 of 30 mA typ mA max mA typ mA max mA typ mA max V min V max Digital inputs = 5 V VS = ±55 V, VD = 0 V GND = 0 V GND = 0 V Data Sheet ADG5436F CONTINUOUS CURRENT PER CHANNEL, Sxx OR Dx Table 5. Parameter 16-Lead TSSOP θJA = 112.6°C/W 16-Lead LFCSP θJA = 30.4°C/W 25°C 85°C 125°C Unit Test Conditions/Comments 113 88 77 61 50 42 mA max mA max VS = VSS + 4.5 V to VDD − 4.5 V VS = VSS to VDD 207 161 125 103 68 61 mA max mA max VS = VSS + 4.5 V to VDD − 4.5 V VS = VSS to VDD Rev. B | Page 11 of 30 ADG5436F Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 6. Parameter VDD to VSS VDD to GND VSS to GND Sxx to GND Sxx to VDD or VSS VS to VD Dx Pin1 to GND Digital Inputs to GND Peak Current, Sxx or Dx Pins Continuous Current, Sxx or Dx Digital Output Dx Pin, Overvoltage State, DR = GND, Load Current Operating Temperature Range Storage Temperature Range Junction Temperature Thermal Impedance, θJA 16-Lead TSSOP (4-Layer Board) 16-Lead LFCSP (4-Layer Board) Reflow Soldering Peak Temperature, Pb-Free ESD Rating, HBM: ESDA/JEDEC JS-001-2011 Input/Output (I/O) Port to Supplies I/O Port to I/O Port All Other Pins Rating 48 V −0.3 V to +48 V −48 V to +0.3 V −55 V to +55 V 80 V 80 V VSS − 0.7 V to VDD + 0.7 V or 30 mA, whichever occurs first GND − 0.7 V to 48 V or 30 mA, whichever occurs first 288 mA (pulsed at 1 ms, 10% duty cycle maximum) Data2 + 15% GND − 0.7 V to 6 V or 30 mA, whichever occurs first 1 mA Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Only one absolute maximum rating can be applied at any one time. ESD CAUTION −40°C to +125°C −65°C to +150°C 150°C 112.6°C/W 30.4°C/W As per JEDEC J-STD-020 6 kV 6 kV 6 kV Overvoltages at the Dx pin are clamped by internal diodes. Limit current to the maximum ratings given. 2 See Table 5. 1 Rev. B | Page 12 of 30 Data Sheet ADG5436F 15 FF D1 3 14 EN S1B 4 ADG5436F VSS 3 5 6 11 NIC 7 10 S2A DR 8 NOTES 1. NIC = NO INTERNAL CONNECTION. 13 FF D2 NOTES 1. NIC = NO INTERNAL CONNECTION. 2. THE EXPOSED PAD IS INTERNALLY CONNECTED. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED THAT THE PAD BE CONNECTED TO THE LOWEST SUPPLY VOLTAGE, VSS. IN2/F2 12882-002 9 D2 10 S2B 9 DR 5 VSS TOP VIEW (Not to Scale) GND 4 TOP VIEW 13 VDD (Not to Scale) 12 S2B GND ADG5436F 11 VDD 12882-103 2 12 EN NIC 7 S1A D1 1 S1B 2 S2A 8 16 SF 14 SF 16 S1A 1 IN2/F2 6 IN1/F1 15 IN1/F1 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 2. TSSOP Pin Configuration Figure 3. LFCSP Pin Configuration Table 7. Pin Function Descriptions Pin No. TSSOP LFCSP 1 15 Mnemonic IN1/F1 2 3 4 5 6 7 8 16 1 2 3 4 7 5 S1A D1 S1B VSS GND NIC DR 9 6 IN2/F2 10 11 12 13 14 8 9 10 11 12 S2A D2 S2B VDD EN 15 13 FF 16 14 SF EP Exposed Pad Description Logic Control Input 1 (IN1). See Table 8. Decoder Pin (F1). This pin is used together with the specific fault pin (SF) to indicate which input is in a fault condition. See Table 9. Overvoltage Protected Source Terminal 1A. This pin can be an input or output. Drain Terminal 1. This pin can be an input or output. Overvoltage Protected Source Terminal 1B. This pin can be an input or output. Most Negative Power Supply Potential. Ground (0 V) Reference. No Internal Connection. Drain Response Digital Input. Tying this pin to GND enables the drain to pull to VDD or VSS during an overvoltage fault condition. The default condition of the drain is open-circuit when the pin is left floating or if it is tied to VDD. Logic Control Input 2 (IN2). See Table 8. Decoder Pin (F2). This pin is used together with the specific fault pin (SF) to indicate which input is in a fault condition. See Table 9. Overvoltage Protected Source Terminal 2A. This pin can be an input or output. Drain Terminal 2. This pin can be an input or output. Overvoltage Protected Source Terminal 2B. This pin can be an input or output. Most Positive Power Supply Potential. Active High Digital Input. When this pin is low, the device is disabled and all switches are off. When this pin is high, the INx logic inputs determine the on switches. Fault Flag Digital Output. This pin has a high output when the device is in normal operation or a low output when a fault condition occurs on any of the Sxx inputs. The FF pin has a weak internal pull-up that allows the signals to be combined into a single interrupt for larger modules that contain multiple devices. Specific Fault Digital Output. This pin has a high output when the device is in normal operation, or a low output when a fault condition is detected on a specific pin, depending on the state of F1 and F2 per Table 9. The exposed pad is connected internally. For increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the lowest supply voltage, VSS. Rev. B | Page 13 of 30 ADG5436F Data Sheet TRUTH TABLES FOR SWITCHES Table 8. Truth Table INx 0 1 SxA Off On SxB On Off Table 9. Fault Diagnostic Output Truth Table Switch in Fault None S1A S1B S2A S2B S1A, S1B S1A, S2A S1A, S2B S1B, S2A S1B, S2B S2A, S2B S1A, S1B, S2A S1A, S1B, S2B S1A, S2A, S2B S1B, S2A, S2B S1A, S1B, S2A, S2B 1 1 State of Specific Fault Pin (SF) with Decoder Pins (F2, F1) F2 = 0, F1 = 0 F2 = 0, F1 = 1 F2 = 1, F1 = 0 F2 = 1, F1 = 1 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1 0 1 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 1 0 1 0 1 0 0 1 1 1 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 Note that more than one pin can be in fault at any one time. See the Applications Information section for more details. Rev. B | Page 14 of 30 State of Fault Flag (FF) 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Data Sheet ADG5436F TYPICAL PERFORMANCE CHARACTERISTICS 30 VDD = +13.5V VSS = –13.5V 10 VDD = +15V VSS = –15V 5 25 20 +125°C 15 +85°C 10 +25°C –40°C 0 –25 –20 –15 –10 –5 0 5 10 15 20 25 VS, VD (V) 12882-003 5 0 –15 –9 –6 –3 0 3 6 9 40 VDD = +20V VSS = –20V 35 15 VDD = 12V VSS = 0V 30 ON RESISTANCE (Ω) ON RESISTANCE (Ω) VDD = 10.8V VSS = 0V 10 VDD = 13.2V VSS = 0V 5 25 20 +125°C 15 +85°C 10 +25°C 0 2 4 6 8 10 12 14 VS, VD (V) 12882-004 5 0 –40°C 0 –20 –15 –10 –5 0 5 10 40 VDD = 12V VSS = 0V 35 ON RESISTANCE (Ω) 30 VDD = 32.4V VSS = 0V 10 VDD = 39.6V VSS = 0V 5 25 20 +125°C 15 +85°C 10 +25°C –40°C 5 0 0 5 10 15 20 25 30 35 VS, VD (V) 40 12882-005 ON RESISTANCE (Ω) VDD = 36V VSS = 0V 15 20 Figure 8. RON as a Function of VS and VD for Different Temperatures, ±20 V Dual Supply TA = 25°C 20 15 VS, VD (V) Figure 5. RON as a Function of VS and VD, 12 V Single Supply 25 15 Figure 7. RON as a Function of VS and VD for Different Temperatures, ±15 V Dual Supply TA = 25°C 20 12 VS, VD (V) Figure 4. RON as a Function of VS and VD, Various Dual Supplies 25 –12 12882-006 15 VDD = +16.5V VSS = –16.5V 12882-007 ON RESISTANCE (Ω) VDD = +18V VSS = –18V VDD = +15V VSS = –15V 35 VDD = +20V VSS = –20V 20 40 TA = 25°C Figure 6. RON as a Function of VS and VD, 36 V Single Supply 0 0 2 4 6 VS, VD (V) 8 10 12 12882-008 VDD = +22V VSS = –22V ON RESISTANCE (Ω) 25 Figure 9. RON as a Function of VS and VD for Different Temperatures, 12 V Single Supply Rev. B | Page 15 of 30 ADG5436F Data Sheet 40 2 VDD = 36V VSS = 0V 35 LEAKAGE CURRENT (nA) 25 20 +125°C 15 +85°C 10 +25°C –4 16 20 24 28 32 36 0 –2 –3 –4 ID (OFF) +– ID (OFF) –+ IS, ID (ON) – – IS (OFF) +IS (OFF) –+ IS, ID (ON)++ –5 –6 –7 20 40 60 80 100 120 TEMPERATURE (°C) VDD = +15V VSS = –15V –5 –10 –15 VS = –30V VS = –55V VS = +30V VS = +55V 0 5 OVERVOLTAGE LEAKAGE CURRENT (nA) 0 VDD = +20V VSS = –20V VS = VD = +15V, –15V –4 IS (OFF) +IS (OFF) –+ IS, ID (ON)++ ID (OFF) +– ID (OFF) –+ IS, ID (ON) – – 20 40 60 80 100 120 TEMPERATURE (°C) Figure 12. Leakage Current vs. Temperature, ±20 V Dual Supply 20 40 60 80 100 120 VDD = +20V VSS = –20V 0 –5 –10 –15 VS = –30V VS = –55V VS = +30V VS = +55V –20 –25 12882-011 –8 0 120 Figure 14. Overvoltage Leakage Current vs. Temperature, ±15 V Dual Supply 2 –6 100 TEMPERATURE (°C) Figure 11. Leakage Current vs. Temperature, ±15 V Dual Supply –2 80 0 –20 12882-010 0 60 Figure 13. Leakage Current vs. Temperature, 12 V Single Supply OVERVOLTAGE LEAKAGE CURRENT (nA) VDD = +15V VSS = –15V VS = VD = +10V, –10V 40 TEMPERATURE (°C) 5 –1 20 12882-012 12 0 LEAKAGE CURRENT (nA) ID (OFF) +– ID (OFF) –+ IS, ID (ON) – – 12882-014 8 1 LEAKAGE CURRENT (nA) IS (OFF) +IS (OFF) –+ IS, ID (ON)++ 12882-009 4 Figure 10. RON as a Function of VS and VD for Different Temperatures, 36 V Single Supply –10 –2 –6 0 VS, VD (V) –8 VDD = +12V VSS = 0V VS = VD = +1V, –10V –40°C 5 0 0 0 20 40 60 80 TEMPERATURE (°C) 100 120 12882-015 ON RESISTANCE (Ω) 30 Figure 15. Overvoltage Leakage Current vs. Temperature, ±20 V Dual Supply Rev. B | Page 16 of 30 Data Sheet ADG5436F 0 –2 –4 –6 –8 –10 –12 VS = –30V VS = –55V VS = +30V VS = +55V –14 0 20 40 60 80 100 120 TEMPERATURE (°C) –40 –60 –80 –100 –120 10k CHARGE INJECTION (pC) –6 –8 VS = –38V VS = –40V VS = +38V VS = +55V –12 0 20 400 300 200 100 VDD = 12V, VSS = 0V VDD = 36V, VSS = 0V –100 40 60 80 100 120 Figure 17. Overvoltage Leakage Current vs. Temperature, 36 V Single Supply –200 0 5 10 15 20 VS (V) 25 30 35 40 Figure 20. Charge Injection vs. Source Pin Voltage (VS), Single Supply 900 TA = 25°C VDD = 15V 800 TA = 25°C CHARGE INJECTION (pC) 700 –40 –60 –80 –100 600 500 400 300 200 VDD = +15V, VSS = –15V VDD = +20V, VSS = –20V 100 0 –100 100k 1M 100M 10M FREQUENCY (Hz) 1G 10G 12882-018 –120 10k 500 0 TEMPERATURE (°C) OFF ISOLATION (dB) 10G 12882-020 –10 –20 1G 600 –4 0 100M TA = 25°C 700 12882-017 OVERVOLTAGE LEAKAGE CURRENT (nA) 800 –2 –14 10M Figure 19. Channel-to-Channel Crosstalk vs. Frequency VDD = 36V VSS = 0V 0 1M FREQUENCY (Hz) Figure 16. Overvoltage Leakage Current vs. Temperature, 12 V Single Supply 2 100k –200 –20 –15 –10 –5 0 VS (V) Figure 18. Off Isolation vs. Frequency 5 10 15 20 12882-021 –16 TA = 25°C VDD = +15V VSS = –15V –20 12882-019 0 CHANNEL-TO-CHANNEL CROSSTALK (dB) VDD = 12V VSS = 0V 12882-016 OVERVOLTAGE LEAKAGE CURRENT (nA) 2 Figure 21. Charge Injection vs. Source Pin Voltage (VS), Dual Supply Rev. B | Page 17 of 30 ADG5436F 0 Data Sheet 490 TA = 25°C VDD = +15V VSS = –15V WITH DECOUPLING CAPACITORS –100 –200 480 tTRANSITION (ns) –400 –500 –600 –700 460 450 440 –800 100M 10M 1M 1G FREQUENCY (Hz) 420 –40 –20 = +12V, VSS = +36V, VSS = +15V, VSS = +20V, VSS 10 15 20 FREQUENCY (kHz) 0.5 –40 –20 0 20 40 60 80 120 TEMPERATURE (°C) Figure 26. Threshold Voltage (VT) vs. Temperature T SOURCE –1.5 VDD –2.0 –2.5 –3.0 –3.5 2 –4.0 DRAIN –4.5 –5.0 10k 100k 1M 10M FREQUENCY (Hz) 100M 12882-024 BANDWIDTH (dB) –1.0 100 0.6 TA = 25°C VDD = +15V VSS = –15V –0.5 120 0.7 Figure 23. THD + N vs. Frequency 0 100 0.8 12882-023 0.005 5 80 0.9 = 0V, VS = 6V p-p = 0V, VS = 18V p-p = –15V, VS = 15V p-p = –20V, VS = 20V p-p 0.010 0 60 CH1 5.00V CH3 5.00V CH2 5.00V M400ns A CH2 T –10.00ns 10.1V Figure 27. Drain Output Response to Positive Overvoltage (DR Pin = Floating or High) Figure 24. Bandwidth vs. Frequency Rev. B | Page 18 of 30 12882-027 THD + N (%) 0.015 VDD VDD VDD VDD 40 Figure 25. tTRANSITION vs. Temperature THRESHOLD VOLTAGE, VT (V) LOAD = 10kΩ TA = 25°C 20 TEMPERATURE (°C) Figure 22. ACPSRR vs. Frequency 0.020 0 12882-026 100k 12882-022 –100 10k 12882-025 430 –900 0 = +12V, VSS = 0V = +36V, VSS = 0V = +15V, VSS = –15V = +20V, VSS = –20V 470 –300 ACPSRR (dB) VDD VDD VDD VDD Data Sheet ADG5436F 24 TA = 25°C VDD = +10V VSS = –10V SIGNAL VOLTAGE (V p-p) 20 DRAIN 1 VSS 16 12 DISTORTIONLESS OPERATING REGION 8 4 CH2 5.00V M400ns A CH2 T –10.00ns –14.7V 0 12882-028 CH1 5.00V CH3 5.00V 1 10 FREQUENCY (MHz) Figure 28. Drain Output Response to Negative Overvoltage (DR Pin = Floating or High) Figure 29. Large Signal Voltage Tracking vs. Frequency Rev. B | Page 19 of 30 100 12882-029 SOURCE ADG5436F Data Sheet TEST CIRCUITS VDD VSS VDD VSS 0.1µF 0.1µF NETWORK ANALYZER SxA Figure 30. On Resistance SxB A Dx ID (OFF) A IS VD SxA SxB A Dx ID (ON) IS IS (OFF) VSS VDD ID Dx A RL 10kΩ Figure 36. Switch Unpowered Leakage 0.1µF 0.1µF VDD VSS VDD VSS 0.1µF NETWORK ANALYZER VSS Sxx INx Sxx VS 12882-032 VD Figure 32. Channel On Leakage VDD RL 10kΩ VDD = VSS = GND = 0V A A VS A Figure 35. Switch Overvoltage Leakage Figure 31. Off Leakage NC ID Dx |VS| > |VDD| OR |VSS| 12882-031 VS 0.1µF Sxx A 50Ω VS VIN RL 50Ω GND Sxx INx OFF ISOLATION = 20 log 50Ω VS VOUT Dx VIN RL 50Ω GND VOUT VS 12882-033 Dx NETWORK ANALYZER INSERTION LOSS = 20 log VOUT WITH SWITCH VOUT WITHOUT SWITCH Figure 37. Bandwidth Figure 33. Off Isolation Rev. B | Page 20 of 30 VOUT 12882-037 SxA Figure 34. Channel-to-Channel Crosstalk 12882-035 A VOUT VS CHANNEL-TO-CHANNEL CROSSTALK = 20 log 12882-034 IDS RON = V/IDS IS (OFF) VS GND 12882-036 VS VOUT SxB Dx 12882-030 Sxx Dx RL 50Ω V RL 50Ω Data Sheet ADG5436F 0.1µF VDD VSS VDD VSS 0.1µF AUDIO PRECISION RS Sxx INx VS V p-p Dx VIN VOUT RL 10kΩ 12882-038 GND Figure 38. THD + N 0.1µF VDD VSS VDD VSS 0.1µF VDD + 0.5V SOURCE VOLTAGE (VS) SxA SxB RL 1kΩ CL* 2pF VD 0V tRESPONSE INx 2.4V VDD × 0.9V OUTPUT (VD) GND 12882-039 VS Dx 0V *INCLUDES TRACK CAPACITANCE Figure 39. Overvoltage Response Time, tRESPONSE 0.1µF VDD VSS 0.1µF VDD + 0.5V VDD SOURCE VOLTAGE (VS) VSS SxA VS Dx SxB RL 1kΩ CL* 2pF VD 0V tRECOVERY INx 2.4V GND *INCLUDES TRACK CAPACITANCE Figure 40. Overvoltage Recovery Time, tRECOVERY Rev. B | Page 21 of 30 12882-040 OUTPUT (VD) VDD × 1 0V ADG5436F Data Sheet 0.1µF VDD + 0.5V SOURCE VOLTAGE (VS) VDD VSS VDD VSS 0.1µF S1A VS 0V ADG5436F tDIGRESP S1B FF CL* 12pF D1 OUTPUT (VFF) GND 0V 12882-041 0.1VOUT *INCLUDES TRACK CAPACITANCE Figure 41. Interrupt Flag Response Time, tDIGRESP 0.1µF VDD + 0.5V VDD VSS VDD VSS 0.1µF S1A SOURCE VOLTAGE (VS) VS ADG5436F 0V S1B tDIGREC FF CL* 12pF D1 0.9VOUT OUTPUT (VFF) 0V 12882-042 GND *INCLUDES TRACK CAPACITANCE Figure 42. Interrupt Flag Recovery Time, tDIGREC 0.1µF VDD + 0.5V SOURCE VOLTAGE (VS) VDD VSS VDD VSS S1A tDIGREC ADG5436F S1B 0V D1 RPULLUP 1kΩ OUTPUT FF 5V 3V 5V GND CL* 12pF *INCLUDES TRACK CAPACITANCE Figure 43. Interrupt Flag Recovery Time, tDIGREC, with a 1 kΩ Pull-Up Resistor Rev. B | Page 22 of 30 12882-043 VS 0V OUTPUT (VFF) 0.1µF Data Sheet ADG5436F 0.1µF VDD VSS VDD VSS SxB VS 0.1µF VIN Dx SxA VOUT RL 300Ω INx VOUT CL 35pF 80% tD tD 12882-044 GND VIN Figure 44. Break-Before-Make Time Delay, tD 0.1µF 3V VIN 50% 50% VDD VSS VDD VSS INx 0.1µF SxB VS SxA 0V tOFF (EN) tON (EN) 0.9VOUT VIN VOUT Dx EN VOUT 50Ω 300Ω Figure 45. Enable Delay, tON (EN), tOFF (EN) VDD VSS VDD VSS SxB VS 0.1µF Dx SxA VOUT RL 300Ω INx CL 35pF VIN 50% 90% VOUT GND VIN 50% 10% tON tOFF 12882-046 0.1µF Figure 46. Address to Output Switching Times, tTRANSITION VS VDD VSS VDD VSS SxB Dx SxA INx VIN 0.1µF GND NC VOUT CL 1nF VIN VOUT ΔVOUT Figure 47. Charge Injection, QINJ Rev. B | Page 23 of 30 QINJ = CL × ΔVOUT 12882-047 0.1µF 35pF 12882-045 GND 0.1VOUT ADG5436F Data Sheet TERMINOLOGY tOFF tOFF represents the delay between applying the digital control input and the output switching off (see Figure 45). IDD IDD represents the positive supply current. ISS ISS represents the negative supply current. VD, VS VD and VS represent the analog voltage on the Dx pins and the Sxx pins, respectively. RON RON represents the ohmic resistance between the Dx pins and the Sxx pins. ∆RON ∆RON represents the difference between the RON of any two channels. RFLAT(ON) RFLAT(ON) is the flatness defined as the difference between the maximum and minimum value of on resistance measured over the specified analog signal range. IS (Off) IS (Off) is the source leakage current with the switch off. ID (Off) ID (Off) is the drain leakage current with the switch off. ID (On), IS (On) ID (On) and IS (On) represent the channel leakage currents with the switch on. VINL VINL is the maximum input voltage for Logic 0. tDIGRESP tDIGRESP is the time required for the FF pin to go low (0.3 V), measured with respect to the voltage on the source pin exceeding the supply voltage by 0.5 V. tDIGREC tDIGREC is the time required for the FF pin to return high, measured with respect to the voltage on the Sxx pin falling below the supply voltage plus 0.5 V. tRESPONSE tRESPONSE represents the delay between the source voltage exceeding the supply voltage by 0.5 V and the drain voltage falling to 90% of the supply voltage. tRECOVERY tRECOVERY represents the delay between an overvoltage on the Sxx pin falling below the supply voltage plus 0.5 V and the drain voltage rising from 0 V to 10% of the supply voltage. Off Isolation Off isolation is a measure of unwanted signal coupling through an off switch. Charge Injection Charge injection is a measure of the glitch impulse transferred from the digital input to the analog output during switching. VINH VINH is the minimum input voltage for Logic 1. IINL, IINH IINL and IINH represent the low and high input currents of the digital inputs. CD (Off) CD (Off) represents the off switch drain capacitance, which is measured with reference to ground. CS (Off) CS (Off) represents the off switch source capacitance, which is measured with reference to ground. CD (On), CS (On) CD (On) and CS (On) represent on switch capacitances, which are measured with reference to ground. CIN CIN is the digital input capacitance. tD tD represents the off time measured between the 90% point of both switches when switching from one address state to another. Channel-to-Channel Crosstalk Channel-to-channel crosstalk is a measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. −3 dB Bandwidth −3 dB bandwidth is the frequency at which the output is attenuated by 3 dB. On Response On response is the frequency response of the on switch. Insertion Loss Insertion loss is the loss due to the on resistance of the switch. Total Harmonic Distortion Plus Noise (THD + N) THD + N is the ratio of the harmonic amplitude plus noise of the signal to the fundamental. tON tON represents the delay between applying the digital control input and the output switching on (see Figure 45). Rev. B | Page 24 of 30 Data Sheet ADG5436F AC Power Supply Rejection Ratio (ACPSRR) ACPSRR is the ratio of the amplitude of the signal on the output to the amplitude of the modulation. ACPSRR is a measure of the ability of the device to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p. VT VT is the voltage threshold at which the overvoltage protection circuitry engages (see Figure 26). Rev. B | Page 25 of 30 ADG5436F Data Sheet THEORY OF OPERATION SWITCH ARCHITECTURE Each channel of the ADG5436F consists of a parallel pair of NDMOS and PDMOS transistors. This construction provides excellent performance across the signal range. The ADG5436F channels operate as standard switches when input signals with a voltage between VSS and VDD are applied. For example, the on resistance is 10 Ω typically and the appropriate control pin, INx, controls the opening or closing of the switch. Additional internal circuitry enables the switch to detect overvoltage inputs by comparing the voltage on the source pin with VDD and VSS. A signal is considered overvoltage if it exceeds the supply voltages by the voltage threshold, VT. The threshold voltage is typically 0.7 V, but can range from 0.8 V at −40°C down to 0.6 V at +125°C. See Figure 26 to see the change in VT with operating temperature. The maximum voltage that can be applied to any source input is −55 V or +55 V. When the device is powered using a single supply of greater than 25 V, the maximum undervoltage signal level reduces down from −55 V. For example, the undervoltage signal reduces to −40 V at VDD = 40 V to remain within the 80 V maximum rating. The construction of the process allows the channel to withstand 80 V across the switch when it is opened. These overvoltage limits apply whether the power supplies are present or not. VDD DR SWITCH DRIVER ESD DIODE VSS LOGIC BLOCK 12882-048 FAULT DETECTOR ESD Performance The ADG5436F has an ESD (HBM) rating of 6 kV. The drain pins (Dx) have ESD protection diodes to the supply rails, and the voltage at these pins must not exceed the supply voltage. The source pins (Sxx) have specialized ESD protection that allows the signal voltage to reach ±55 V with a ±22 V dual supply, and from −40 V to +55 V with a +40 V single supply. See Figure 48 for the switch channel overview. Exceeding ±55 V on any source input may damage the ESD protection circuitry on the device. Trench Isolation In the ADG5436F, an insulating oxide layer (trench) is placed between the NDMOS and the PDMOS transistors of each switch. Parasitic junctions, which occur between the transistors in junction isolated switches, are eliminated, and the result is a switch that is latch-up immune under all circumstances. This device passes a JESD78D latch-up test of ±500 mA for 1 sec, the strictest test in the specification. ESD DIODE Dx Sxx When an overvoltage event occurs, the channels undisturbed by the overvoltage input continue to operate normally without additional crosstalk. Figure 48. Switch Channel and Control Function When an overvoltage condition is detected on a source pin (Sxx), the switch automatically opens and the source pin (Sxx) becomes high impedance and ensures that no current flows through the switch. If the DR pin is driven low, the drain pin, Dx, is pulled to the supply that was exceeded. For example, if the source voltage exceeds VDD, the drain output pulls to VDD. The same is true for VSS. If the DR pin is allowed to float or is driven high, the Dx pin also becomes open circuit. The voltage on the Dx pin follows the voltage on the source pin, Sxx, until the switch turns off completely and the drain voltage discharges through the load. The maximum voltage on the drain is limited by the internal ESD diodes and the rate at which the output voltage discharges is dependent on the load at the pin. NDMOS PDMOS P-WELL N-WELL TRENCH BURIED OXIDE LAYER HANDLE WAFER Figure 49. Trench Isolation Rev. B | Page 26 of 30 12882-049 ESD PROTECTION During overvoltage conditions, the leakage current into and out of the source pins (Sxx) is limited to tens of microamperes. If the DR pin is allowed to float or is driven high, only nanoamperes of leakage are seen on the drain pin (Dx). If the DR pin is driven low, the drain pin (Dx) is pulled to the rail. The device that pulls the drain pin to the rail has an impedance of approximately 40 kΩ; therefore, the Dx pin current is limited to about 1 mA during a shorted load condition. This internal impedance also determines the minimum external load resistance required to ensure that the drain pin is pulled to the desired voltage level during a fault. Data Sheet ADG5436F +22V FAULT PROTECTION When the voltages at the source inputs exceed VDD or VSS by VT, the switch turns off, or, if the device is unpowered, the switch remains off. The switch input remains high impedance regardless of the digital input state or the load resistance, and the output acts as a virtual open circuit. Signal levels up to +55 V and −55 V are blocked in both the powered and unpowered conditions as long as the 80 V limitation between the source and supply pins is met. VDD VSS S2A +22V D1 D2 –55V S1B S2B +55V 5V F1 F2 EN DR SF FF 3V 0V 12882-050 FAULT DETECTION + SWITCH DRIVER VDD to VSS ≥ 8 V. The input signal is between VSS − VT and VDD + VT. The digital logic control input, INx, is turned on. Figure 50. ADG5436F Under Example Overvoltage Conditions When the switch is turned on, the signal levels up to the supply rails are passed. The switch responds to an analog input that exceeds VDD or VSS by a threshold voltage, VT, by turning off. The absolute input voltage limits are −55 V and +55 V, while maintaining an 80 V limit between the source pin and the supply rails. The switch remains off until the voltage at the source pin returns to between VDD and VSS. The fault response time (tRESPONSE) when powered by a ±15 V dual supply is typically 510 ns, and the fault recovery time (tRECOVERY) is 820 ns. These vary with supply voltages and output load conditions. Power-Off Protection When no power supplies are present, the switch remains in the off condition, and the switch inputs are high impedance. This state ensures that no current flows and prevents damage to the switch or downstream circuitry. The switch output is a virtual open circuit. The switch remains off regardless of whether the VDD and VSS supplies are 0 V or floating. A GND reference must always be present to ensure proper operation. Signal levels of up to ±55 V are blocked in the unpowered condition. Digital Input Protection The ADG5436F can tolerate unpowered digital input signals present on the device. When the device is unpowered, the switch is guaranteed to be in the off state, regardless of the state of the digital logic signals. Exceeding ±55 V on any source input may damage the ESD protection circuitry on the device. The maximum stress across the switch channel is 80 V. Therefore, the user must pay close attention to this limit when using the device with a 40 V single supply. In this case, the maximum undervoltage condition is −40 V to maintain the 80 V across the switch channel. The digital inputs are protected against positive faults up to 44 V. The digital inputs do not offer protection against negative overvoltages. ESD protection diodes connected to GND are present on the digital inputs. For undervoltage and overvoltage conditions, consider the case where the device is set up as shown in Figure 50. • • • GND +22V S1A The following three conditions must be satisfied for the switch to be in the on condition: • • –22V ADG5436F Power-On Protection • • • 0V VDD/VSS = ±22 V. S1A and S2A = 22 V, and are both on. Therefore, D1 and D2 = 22 V. S1B has a −55 V fault and S2B has a +55 V fault. The voltage between S1B and D1 = 22 V − (−55 V) = +77 V. The voltage between S2B and D2= 22 V− 55 V = -33 V. These calculations are all within device specifications: a 55 V maximum fault on source inputs and a maximum of 80 V across the off switch channel. FF is low due to the fault conditions. The specific switches in fault can be deduced by cycling through F2 and F1 and noting the state of SF. In this example, SF is low (asserted) when F2 = 0 and F1 = 1; it is also low when F2 = 1 and F1 = 0. This signifies a fault on S1B and S2B. See Table 9 for details on how to decode SF by F2 and F1. Overvoltage Interrupt Flag The voltages on the source inputs of the ADG5436F are continuously monitored, and the state of the switches is indicated by an active low digital output pin, FF. The voltage on the FF pin indicates if any of the source input pins are experiencing a fault condition. The output of the FF pin is a nominal 3 V when all source pins are within normal operating range. If any source pin voltage exceeds the supply voltage by VT, the FF output reduces to below 0.8 V. Use the specific fault digital output pin, SF, to decode which inputs are experiencing a fault condition. The SF pin reduces to below 0.8 V when a fault condition is detected on a specific pin, depending on the state of F1 and F2 (see Table 9). The specific fault feature also works with the switches disabled (EN pin low), which allows the user to cycle through and check the fault conditions without connecting the fault to the drain output. Rev. B | Page 27 of 30 ADG5436F Data Sheet APPLICATIONS INFORMATION The overvoltage protected family of switches and multiplexers provide a robust solution for instrumentation, industrial, aerospace, and other harsh environments where overvoltage signals can be present and the system must remain operational both during and after the overvoltage has occurred. POWER SUPPLY RAILS To guarantee correct operation of the device, 0.1 µF decoupling capacitors are required. The ADG5436F can operate with bipolar supplies between ±5 V and ±22 V. The supplies on VDD and VSS do not need to be symmetrical, but the VDD to VSS range must not exceed 44 V. The ADG5436F can also operate with single supplies between 8 V and 44 V, with VSS connected to GND. The ADG5436F is fully specified at the ±15 V, ±20 V, 12 V, and +36 V supply ranges. LOW IMPEDANCE CHANNEL PROTECTION The ADG5436F can be used as a protective element in signal chains that are sensitive to both channel impedance and overvoltage signals. Traditionally, series resistors limit the current during an overvoltage condition to protect susceptible components. These series resistors affect the performance of the signal chain and reduce the signal chain precision. A compromise must be reached on the value of the series resistance that is high enough to sufficiently protect sensitive components, but low enough that the precision performance of the signal chain is not sacrificed. The ADG5436F enables the designer to remove these resistors and retain precision performance without compromising the protection of the circuit. POWER SUPPLY SEQUENCING PROTECTION POWER SUPPLY RECOMMENDATIONS The switch channel remains open when the device is unpowered and signals from −55 V to +55 V can be applied without damaging the device. The switch channel closes only when the supplies are connected, a suitable digital control signal is placed on the INx pins, and the signal is within the normal operating range. Placing the ADG5436F between external connectors and sensitive components offers protection in systems where a signal is presented to the source pins before the supply voltages are available. Analog Devices, Inc., has a wide range of power management products to meet the requirements of most high performance signal chains. +16V SIGNAL RANGE The ADG5436F has overvoltage detection circuitry on the inputs that compares the voltage levels at the source terminals with VDD and VSS. To protect downstream circuitry from overvoltage conditions, supply the ADG5436F with voltages that match the intended signal range. The low on-resistance switch allows signals to the supply rails to be passed with very little distortion. A signal that exceeds the supply rail by the threshold voltage is then blocked. This signal block offers protection to both the device and any downstream circuitry. 12V INPUT DUAL SWITCHING REGULATOR ADP7118 +15V ADP7182 –15V LDO –16 V LDO 12882-051 An example of a bipolar power solution is shown in Figure 51. The ADP7118 and ADP7182 can be used to generate clean positive and negative rails from the dual switching regulator output. These rails can be used to power the ADG5436F, amplifier, and/or precision converter in a typical signal chain. Figure 51. Bipolar Power Solution Table 10. Recommended Power Management Devices Product ADP7118 ADP7142 ADP7182 Description 20 V, 200 mA, low noise, CMOS LDO 40 V, 200 mA, low noise, CMOS LDO −28 V, −200 mA, low noise, linear regulator HIGH VOLTAGE SURGE SUPPRESSION The ADG5436F is not intended for use in very high voltage applications. The maximum operating voltage of the transistor is 80 V. In applications where the inputs are likely to be subject to overvoltage conditions exceeding the breakdown voltage, use transient voltage suppressors (TVSs) or similar devices. Rev. B | Page 28 of 30 Data Sheet ADG5436F INTELLIGENT FAULT DETECTION The recovery time, tDIGREC, can be decreased from a typical 60 µs to 600 ns by using a 1 kΩ pull-up resistor. The ADG5436F digital output pin, FF, can interface with a microprocessor or control system and can be used as an interrupt flag. This feature provides real-time diagnostic information on the state of the device and the system to which it connects. The control system can use the digital interrupt, FF, to start a variety of actions, as follows: • • • Initiating an investigation into the source of an overvoltage fault. Shutting down critical systems in response to the overvoltage condition. Using data recorders to mark data during these events as unreliable or out of specification. For systems sensitive during a start-up sequence, the active low operation of the flag allows the system to ensure that the ADG5436F is powered on and that all input voltages are within the normal operating range before initiating operation. The specific fault digital output, SF decodes which inputs are experiencing a fault condition. The SF pin reduces to below 0.8 V when a fault condition is detected on a specific pin, depending on the state of F1 and F2 (see Table 9). The specific fault feature also works with the switches disabled (EN pin low), which allows the user to cycle through and check the fault conditions without connecting the fault to the drain output. LARGE VOLTAGE, HIGH FREQUENCY SIGNALS Figure 29 shows the voltage range and frequencies that the ADG5436F can reliably convey. For signals extending across the full signal range from VSS to VDD, keep the frequency below 3 MHz. If the required frequency is greater than 3 MHz, decrease the signal range appropriately to ensure signal integrity. The FF pin is a weak pull-up, which allows the signals to combine into a single interrupt for larger modules that contain multiple devices. Rev. B | Page 29 of 30 ADG5436F Data Sheet OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.65 BSC 0.30 0.19 COPLANARITY 0.10 0.20 0.09 0.75 0.60 0.45 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 52. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters PIN 1 INDICATOR 4.10 4.00 SQ 3.90 0.35 0.30 0.25 0.65 BSC 16 13 PIN 1 INDICATOR 12 1 EXPOSED PAD 4 2.70 2.60 SQ 2.50 9 0.80 0.75 0.70 0.45 0.40 0.35 8 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WGGC. 08-16-2010-C TOP VIEW 5 Figure 53. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm × 4 mm Body, Very Very Thin Quad (CP-16-17) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADG5436FBRUZ ADG5436FBRUZ-RL7 ADG5436FBCPZ-RL7 1 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] Z = RoHS Compliant Part. ©2015–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12882-0-1/16(B) Rev. B | Page 30 of 30 Package Option RU-16 RU-16 CP-16-17