EVALUATION KIT AVAILABLE MAX11108 Tiny, 2.1mm x 1.6mm, 3Msps, Low-Power, Serial 12-Bit ADC General Description Benefits and Features The MAX11108 features a single-ended analog input connected to the ADC core. The device also includes a separate supply input for data interface and a dedicated input for reference voltage. ●● Low Power Consumption Extends Battery Life • 6.6mW at 3Msps • Very Low Power Consumption at 2.5μA/ksps • 1.3μA Power-Down Current • 2.2V to 3.6V Supply Voltage The MAX11108 is a tiny (2.1mm x 1.6mm), 12-bit, compact, high-speed, low-power, successive approximation analog-to-digital converter (ADC). This high-performance ADC includes a high-dynamic range sample-and-hold and a high-speed serial interface. This ADC accepts a full-scale input from 0V to the power supply or to the reference voltage. ●● Compact ADC Saves Space • Single-Ended Analog Input 12-Bit Resolution ADC • 3Msps Conversion Rate with No Pipeline Delay • 73dB SNR • 10-Pin, Ultra-TQFN (μDFN), 2.1mm x 1.6mm Package The MAX11108 "communicates" from 1.5V to VDD and operates from a 2.2V to 3.6V supply. The device consumes only 6.6mW at 3Msps and includes full powerdown mode and fast wake-up for optimal power management and a high-speed 3-wire serial interface. The 3-wire serial interface directly connects to SPI/QSPI™/ MICROWIRE® devices without external logic. ●● Variable I/O Voltage Range of 1.5V to 3.6V Eases Interface to Microcontrollers Excellent dynamic performance, low voltage, low power, ease of use, and extremely small package size make this converter ideal for portable battery-powered data-acquisition applications, and for other applications that demand low-power consumption and minimal space. Functional Diagram The MAX11108 is available in an ultra-TQFN (2.1mm x 1.6mm) package, and operates over the -40°C to +125°C temperature range. ●● SPI-/QSPI-/MICROWIRE-Compatible Serial Interface Directly Connects to 1.5V, 1.8V, 2.5V, or 3V Digital System VOVDD CS SCLK CONTROL LOGIC VDD MAX11108 Applications ●● ●● ●● ●● ●● ●● Instrument Data Acquisition Mobile Portable Data Logging Medical Instrumentation Battery-Operated Systems Communication Systems AIN QSPI is a trademark of Motorola, Inc. MICROWIRE is a registered trademark of National Semiconductor Corp. µMAX is a registered trademark of Maxim Integrated Products, Inc. 19-6227; Rev 3; 3/15 OUTPUT BUFFER SAR CDAC VREF AGND DOUT MAX11108 Tiny, 2.1mm x 1.6mm, 3Msps, Low-Power, Serial 12-Bit ADC Absolute Maximum Ratings VDD to AGND...........................................................-0.3V to +4V REF, OVDD, AIN to AGND.......................... -0.3V to the lower of .............................................................. (VDD + 0.3V) and +4V CS, SCLK, DOUT TO AGND...................... -0.3V to the lower of (VOVDD + 0.3V) and +4V Input/Output Current (all pins).............................................50mA Continuous Power Dissipation (TA = +70°C) Ultra TQFN (derate 9mW/°C above +70°C).................722mW Operating Temperature Range......................... .-40°C to +125°C Junction Temperature.......................................................+150°C Storage Temperature Range............................. -65°C to +150°C Lead Temperature (soldering, 10s).................................. +300°C Soldering Temperature (reflow)........................................+260°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Package Thermal Characteristics (Note 1) Ultra TQFN Junction-to-Ambient Thermal Resistance (θJA)..........110.8°C/W Junction-to-Case Thermal Resistance (θJC).............62.1°C/W Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. Electrical Characteristics (VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD. fSCLK = 48MHz, 50% duty cycle, 3Msps. CDOUT = 10pF, TA = -40°C to +125°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY Resolution 12 Integral Nonlinearity INL Differential Nonlinearity DNL Offset Error OE Gain Error GE Total Unadjusted Error TUE Bits No missing codes Excluding offset and reference errors ±1 LSB ±1 LSB ±0.3 ±3 LSB ±1 ±3 LSB ±1.5 LSB DYNAMIC PERFORMANCE (fAIN = 1MHz) Signal-to-Noise and Distortion Signal-to-Noise Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Intermodulation Distortion SINAD 70 72 dB SNR 70.5 72 dB THD -85 SFDR IMD 76 f1 = 1.0003MHz, f2 = 0.99955MHz -75 dB 85 dB -84 dB Full-Power Bandwidth -3dB point 40 MHz Full-Linear Bandwidth SINAD > 68dB 2.5 MHz 45 MHz Small-Signal Bandwidth www.maximintegrated.com Maxim Integrated │ 2 MAX11108 Tiny, 2.1mm x 1.6mm, 3Msps, Low-Power, Serial 12-Bit ADC Electrical Characteristics (continued) (VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD. fSCLK = 48MHz, 50% duty cycle, 3Msps. CDOUT = 10pF, TA = -40°C to +125°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 3 Msps CONVERSION RATE Throughput 0.03 Conversion Time 260 Acquisition Time tACQ Aperture Delay 52 From CS falling edge ns 4 Aperture Jitter Serial-Clock Frequency ns ns 15 fCLK 0.48 Input Voltage Range VAIN 0 Input Leakage Current IILA ps 48 MHz ANALOG INPUT (AIN) Input Capacitance CAIN 0.002 Track 20 Hold 5 VREF V ±1 µA pF EXTERNAL REFERENCE INPUT (REF) Reference Input-Voltage Range Reference Input Leakage Current Reference Input Capacitance DIGITAL INPUTS (SCLK, CS) VREF IILR VIH Digital Input Low Voltage VIL Digital Input Leakage Current Digital Input Capacitance Conversion stopped 0.005 CREF Digital Input High Voltage Digital Input Hysteresis 1 V ±1 µA 5 pF 0.75 × VOVDD V 0.25 × VOVDD 0.15 × VOVDD VHYST IIL VDD + 0.05 Inputs at GND or VDD 0.001 CIN V V ±1 2 µA pF DIGITAL OUTPUT (DOUT) Output High Voltage VOH ISOURCE = 1mA Output Low Voltage VOL ISINK = 5µA High-Impedance Leakage Current IOL High-Impedance Output Capacitance www.maximintegrated.com COUT 0.85 × VOVDD V 4 0.15 × VOVDD V ±1.0 µA pF Maxim Integrated │ 3 MAX11108 Tiny, 2.1mm x 1.6mm, 3Msps, Low-Power, Serial 12-Bit ADC Electrical Characteristics (continued) (VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD. fSCLK = 48MHz, 50% duty cycle, 3Msps. CDOUT = 10pF, TA = -40°C to +125°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER SUPPLY Positive Supply Voltage Digital I/O Supply Voltage Positive Supply Current (Full-Power Mode) Positive Supply Current (FullPower Mode), No Clock VDD 2.2 3.6 V VOVDD 1.5 VDD V IVDD VAIN = VGND 3.3 IOVDD VAIN = VGND 0.33 IVDD Power-Down Current IPD Line Rejection 1.98 Leakage only 1.3 VDD = 2.2V to 3.6V, VREF = 2.2V 0.7 mA mA 10 µA LSB/V TIMING CHARACTERISTICS (Note 2) Quiet Time tQ (Note 3) 4 ns CS Pulse Width t1 (Note 3) 10 ns CS Fall to SCLK Setup t2 (Note 3) 5 ns CS Falling Until DOUT HighImpedance Disabled t3 (Note 3) 1 ns Data Access Time After SCLK Falling Edge t4 SCLK Pulse Width Low t5 Percentage of clock period (Note 3) 40 60 % SCLK Pulse Width High t6 Percentage of clock period (Note 3) 40 60 % Data Hold Time From SCLK Falling Edge t7 Figure 3 (Note 3) 5 SCLK Falling Until DOUT HighImpedance t8 Figure 4 (Note 3) 2.5 Power-Up Time Figure 2, VOVDD = 2.2V to 3.6V 15 Figure 2, VOVDD = 1.5V to 2.2V 16.5 Conversion cycle (Note 3) ns ns 14 ns 1 Cycle Note 2: All timing specifications given are with a 10pF capacitor. Note 3: Guaranteed by design in characterization; not production tested. www.maximintegrated.com Maxim Integrated │ 4 MAX11108 Tiny, 2.1mm x 1.6mm, 3Msps, Low-Power, Serial 12-Bit ADC SAMPLE SAMPLE t6 CS t1 t5 t2 SCLK DOUT 16 1 2 0 HIGH IMPEDANCE 3 D11 4 D10 5 D9 6 D8 7 D7 8 D6 9 10 D5 D4 11 D3 12 D2 13 D1 14 D0 15 0 16 0 HIGH IMPEDANCE (MSB) t3 t4 t7 1 t8 tQUIET tCONVERT tACQ 1/fSAMPLE Figure 1. Interface Signals for Maximum Throughput t7 t4 SCLK SCLK VIH DOUT OLD DATA NEW DATA VIL Figure 2. Setup Time After SCLK Falling Edge VIH DOUT OLD DATA NEW DATA VIL Figure 3. Hold Time After SCLK Falling Edge t8 SCLK DOUT HIGH IMPEDANCE Figure 4. SCLK Falling Edge DOUT Three-State www.maximintegrated.com Maxim Integrated │ 5 MAX11108 Tiny, 2.1mm x 1.6mm, 3Msps, Low-Power, Serial 12-Bit ADC Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) -0.5 0 -0.5 MAX11108 toc03 0.5 DNL (LSB) 0 fS = 3.0Msps OFFSET ERROR vs. TEMPERATURE 2.0 1.5 OFFSET ERROR (LSB) fS = 3.0Msps 0.5 INL (LSB) 1.0 MAX11108 toc01 1.0 DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE MAX11108 toc02 INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE 1.0 0.5 0 -0.5 -1.0 -1.5 1000 2000 3000 -1.0 4000 1000 0 DIGITAL OUTPUT CODE MAX11108 toc04 0.8 0.6 0.2 TEMPERATURE (°C) 35,000 HISTOGRAM FOR 30,000 CONVERSIONS 30,000 20,000 0 15,000 -0.2 -0.4 10,000 -0.6 5000 -0.8 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 2047 2046 SNR AND SINAD vs. ANALOG INPUT FREQUENCY fS = 3Msps SNR 2050 -80 73 72 fS = 3Msps -70 THD (dB) SNR AND SINAD (dB) 74 2049 THD vs. ANALOG INPUT FREQUENCY -60 MAX11108 toc06 75 2048 DIGITAL CODE OUTPUT TEMPERATURE (°C) SINAD -90 -100 71 70 -40 -25 -10 5 20 35 50 65 80 95 110 125 25,000 0.4 -1.0 -2.0 4000 CODE COUNT GAIN ERROR (LSB) 3000 DIGITAL OUTPUT CODE GAIN ERROR vs. TEMPERATURE 1.0 2000 MAX11108 toc05 0 MAX11108 toc07 -1.0 -110 0 300 600 900 fIN (kHz) www.maximintegrated.com 1200 1500 -120 0 300 600 900 1200 1500 fIN (kHz) Maxim Integrated │ 6 MAX11108 Tiny, 2.1mm x 1.6mm, 3Msps, Low-Power, Serial 12-Bit ADC Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) fS = 3Msps 120 THD (dB) 100 -85 90 -90 80 -95 300 600 900 1200 0 20 40 60 80 fIN (kHz) RIN (Ω) 1MHz SINE-WAVE INPUT (16,834-POINT FFT PLOT) REFERENCE CURRENT vs. SAMPLING RATE fS = 3.0Msps fIN = 1.0183MHz -20 -100 1500 200 100 MAX11108 toc11 0 MAX11108 toc10 150 -40 -60 IREF (µA) SFDR (dB) -80 0 AMPLITUDE (dB) fS = 3.0Msps fIN = 1.0183MHz -75 110 70 THD vs. INPUT RESISTANCE -70 MAX11108 toc09 SFDR vs. ANALOG INPUT FREQUENCY MAX11108 toc08 130 AHD3 = -122.7dB 100 AHD2 = -109.5dB -80 50 -100 0 250 500 750 1000 1250 0 1500 500 0 1000 ANALOG SUPPLY CURRENT vs. TEMPERATURE VDD = 3.6V 2.9 2.6 VDD = 3.0V 2.3 2.0 73.0 SNR (dB) IVDD (mA) 3.2 73.5 MAX11108 toc12 3.5 1500 2000 2500 3000 fS (ksps) FREQUENCY (kHz) SNR vs. REFERENCE VOLTAGE MAX11108 toc13 -120 fS = 3Msps fIN = 1.0183MHz 72.5 72.0 71.5 VDD = 2.2V -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) www.maximintegrated.com 71.0 2.2 2.4 2.6 2.8 3.0 VREF (V) 3.2 3.4 3.6 Maxim Integrated │ 7 MAX11108 Tiny, 2.1mm x 1.6mm, 3Msps, Low-Power, Serial 12-Bit ADC Pin Configuration TOP VIEW AGND SCLK DOUT OVDD CS 9 8 7 6 MAX11108 10 + 5 1 2 3 4 AIN AGND REF VDD AGND ULTRA TQFN (2.1mm x 1.6mm) Pin Description PIN 1 NAME AIN FUNCTION Analog Single-Ended Input 2, 5, 10 AGND 3 REF Reference Input Pin 4 VDD Positive Supply Voltage 6 CS Chip Select (Active Low). Initiates acquisition on the falling edge. 7 OVDD Digital I/O Supply Voltage (CS, DOUT, SCLK). 8 DOUT Serial Data Output. DOUT changes state on SCLK’s falling edge. See Figures 1 to 4 for details. 9 SCLK Serial Clock Input. SCLK drives the conversion process and clocks data out. See Figures 1 to 4 for details. www.maximintegrated.com Ground. This pin must connect to a solid ground plane. Maxim Integrated │ 8 MAX11108 Tiny, 2.1mm x 1.6mm, 3Msps, Low-Power, Serial 12-Bit ADC Typical Operating Circuit VDD VOVDD +3V +3V REF REFERENCE INPUT +3V ANALOG INPUT MAX11108 SCLK SCK DOUT MISO CS AIN CPU SS AGND Detailed Description The MAX11108 is a tiny, fast, 12-bit, low-power, singlesupply ADC. This device “communicates” from 1.5V to VDD, operates from a 2.2V to 3.6V supply, and consumes only 9mW (VDD = 3V)/6.6mW (VDD = 2.2V) at 3Msps. This 3Msps device is capable of sampling at full rate when driven by a 48MHz clock. The conversion result appears at DOUT, MSB first, with a leading zero followed by the 12-bit result. A 12-bit result is followed by two trailing zeros (see Figure 1). The device features a dedicated reference input (REF). The input signal range for AIN is defined as 0V to VREF with respect to AGND. This ADC includes a power-down feature allowing minimized power consumption at 2.5µA/ksps for lower throughput rates. The wake-up and power-down feature is controlled by using the SPI interface as described in the Operating Modes section. Serial Interface This device features a 3-wire serial interface that directly connects to SPI/QSPI/MICROWIRE devices without external logic. Figure 1 shows the interface signals for a single conversion frame to achieve maximum throughput. The falling edge of CS defines the sampling instant. Once CS transitions low, the external clock signal (SCLK) controls the conversion. www.maximintegrated.com The SAR core successively extracts binary-weighted bits in every clock cycle. The MSB appears on the data bus during the 2nd clock cycle with a delay outlined in the timing specifications. All extracted data bits appear successively on the data bus with the LSB appearing during the 13th clock cycle for 12-bit operation. The serial data stream of conversion bits is preceded by a leading “zero” and succeeded by trailing “zeros.” The data output (DOUT) goes into high-impedance state during the 16th clock cycle. To sustain the maximum sample rate, the device has to be resampled immediately after the 16th clock cycle. For lower sample rates, the CS falling edge can be delayed leaving DOUT in a high-impedance condition. Pull CS high after the 10th SCLK falling edge (see the Operating Modes section). Analog Input The ADC produces a digital output that corresponds to the analog input voltage within the specified operating range of 0 to VREF. Figure 5 shows an equivalent circuit for the analog input AIN. Internal protection diodes D1/D2 confine the analog input voltage within the power rails (VDD, AGND). The analog input voltage can swing from (AGND - 0.3V) to (VDD + 0.3V) without damaging the device. The electric load presented to the external stage driving the analog input varies depending on which mode the ADC is in: track mode vs. conversion mode. In track mode, the internal sampling capacitor CS (16pF) has Maxim Integrated │ 9 MAX11108 Tiny, 2.1mm x 1.6mm, 3Msps, Low-Power, Serial 12-Bit ADC Operating Modes to be charged through the resistor R (50Ω) to the input voltage. For faithful sampling of the input, the capacitor voltage on CS has to settle to the required accuracy during the track time. The IC offers two modes of operation: normal mode and power-down mode. The logic state of the CS signal during a conversion activates these modes. The power-down mode can be used to optimize power dissipation with respect to sample rate. The source impedance of the external driving stage in conjunction with the sampling switch resistance affects the settling performance. The THD vs. Input Resistance graph in the Typical Operating Characteristics shows THD sensitivity as a function of the signal source impedance. Keep the source impedance at a minimum for highdynamic performance applications. Use a high-performance op amp such as the MAX4430 to drive the analog input, thereby decoupling the signal source and the ADC. Normal Mode In normal mode, the device is powered up at all times, thereby achieving its maximum throughput rates. Figure 6 shows the timing diagram in normal mode. The falling edge of CS samples the analog input signal, starts a conversion, and frames the serial data transfer. To remain in normal mode, keep CS low until the falling edge of the 10th SCLK cycle. Pulling CS high after the 10th SCLK falling edge keeps the part in normal mode. However, pulling CS high before the 10th SCLK falling edge terminates the conversion, DOUT goes into highimpedance mode, and the device enters power-down mode. See Figure 7. While the ADC is in conversion mode, the sampling switch is open presenting a pin capacitance, CP (CP = 5pF), to the driving stage. See the Applications Information section for information on choosing an appropriate buffer for the ADC. ADC Transfer Function The output format is straight binary. The code transitions midway between successive integer LSB values such as 0.5 LSB, 1.5 LSB, etc. The LSB size is VREF/2n where n = 12. The ideal transfer characteristic is shown in Figure 9. VDD Power-Down Mode In power-down mode, all bias circuitry is shut down drawing typically only 1.3µA of leakage current. To save power, put the device in power-down mode between conversions. Using the power-down mode between conversions is ideal for saving power when sampling the analog input infrequently. Entering Power-Down Mode SWITCH CLOSED IN TRACK MODE SWITCH OPEN IN CONVERSION MODE D1 To enter power-down mode, drive CS high between the 2nd and 10th falling edges of SCLK (see Figure 7). By pulling CS high, the current conversion terminates and DOUT enters high impedance. CS R AIN CP D2 Figure 5. Analog Input Circuit KEEP CS LOW UNTIL AFTER THE 10TH SCLK FALLING EDGE PULL CS HIGH AFTER THE 10TH SCLK FALLING EDGE CS SCLK DOUT 1 2 HIGH IMPEDANCE 3 4 5 6 7 8 VALID DATA 9 10 11 12 13 14 15 16 HIGH IMPEDANCE Figure 6. Normal Mode www.maximintegrated.com Maxim Integrated │ 10 MAX11108 Tiny, 2.1mm x 1.6mm, 3Msps, Low-Power, Serial 12-Bit ADC PULL CS HIGH AFTER THE 2ND AND BEFORE THE 10TH SCLK FALLING EDGE CS SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DOUT HIGH IMPEDANCE INVALID DATA INVALID DATA OR HIGH IMPEDANCE HIGH IMPEDANCE Figure 7. Entering Power-Down Mode CS 1 SCLK 2 3 4 DOUT 5 6 7 8 9 10 11 12 13 14 15 INVALID DATA (DUMMY CONVERSION) HIGH IMPEDANCE 16 N 1 HIGH IMPEDANCE 2 3 4 5 6 7 8 9 10 11 12 13 VALID DATA 14 15 16 HIGH IMPEDANCE Figure 8. Exiting Power-Down Mode Exiting Power-Down Mode OUTPUT CODE To exit power-down mode, implement one dummy conversion by driving CS low for at least 10 clock cycles (see Figure 8). The data on DOUT is invalid during this dummy conversion. The first conversion following the dummy cycle contains a valid conversion result. FS - 1.5 x LSB 111...111 111...110 111...101 The power-up time equals the duration of the dummy cycle, and is dependent on the clock frequency. The power-up time for 3Msps operation (48MHz SCLK) is 333ns. Supply Current vs. Sampling Rate 000...010 000...001 000...000 0 1 2 3 0.5 x LSB Figure 9. ADC Transfer Function www.maximintegrated.com 2n-2 2n-1 2n ANALOG INPUT (LSB) FULL SCALE (FS): AIN = VREF n = RESOLUTION For applications requiring lower throughput rates, the user can reduce the clock frequency (fSCLK) to lower the sample rate. Figure 10 shows the typical supply current (IVDD) as a function of sample rate (fS). The part operates in normal mode and is never powered down. The user can also power down the ADC between conversions by using the power-down mode. Figure 11 shows that as the sample rate is reduced, the device remains in the power-down state longer and the average supply current (IVDD) drops accordingly. Maxim Integrated │ 11 MAX11108 Tiny, 2.1mm x 1.6mm, 3Msps, Low-Power, Serial 12-Bit ADC 14-Cycle Conversion Mode The ICs can operate with 14 cycles per conversion. Figure 12 shows the corresponding timing diagram. Observe that DOUT does not go into high-impedance mode. Also, observe that tACQ needs to be sufficiently long to guarantee proper settling of the analog input voltage. See the Electrical Characteristics table for tACQ requirements and the Analog Input section for a description of the analog inputs. Applications Information Layout, Grounding, and Bypassing For best performance, use PCBs with a solid ground plane. Ensure that digital and analog signal lines are separated from each other. Do not run analog and digital (especially clock) lines parallel to one another or digital lines underneath the ADC package. Noise in the VDD power supply, OVDD, and REF affects the ADC’s performance. Bypass the VDD, OVDD, and REF to ground with 0.1µF and 10µF bypass capacitors. Minimize capacitor lead and trace lengths for best supply-noise rejection. Choosing an Input Amplifier It is important to match the settling time of the input amplifier to the acquisition time of the ADC. The conversion results are accurate when the ADC samples the input signal for an interval longer than the input signal’s worst-case settling time. By definition, settling time is the interval between the application of an input voltage VDD = 3V fSCLK = VARIABLE 16 CYCLES/CONVERSION For devices using an external reference, the choice of the reference determines the output accuracy of the ADC. An ideal voltage reference provides a perfect initial accuracy and maintains the reference voltage independent of changes in load current, temperature, and time. Considerations in selecting a reference include initial voltage accuracy, temperature drift, current source, sink capability, quiescent current, and noise. Figure 13 shows a typical application circuit using the MAX6126 to provide the reference voltage. The MAX6033 and MAX6043 are also excellent choices. 3.0 VDD = 3V fSCLK = 48MHz 2.5 2.0 3 2 1.5 1.0 1 0 Choosing a Reference IVDD (mA) IVDD (mA) 4 Figure 13 shows a typical application circuit. The MAX4430, offering a settling time of 37ns at 16 bits, is an excellent choice for this application. See the THD vs. Input Resistance graph in the Typical Operating Characteristics. MAX11102 fig11 5 step and the point at which the output signal reaches and stays within a given error band centered on the resulting steady-state amplifier output level. The ADC input sampling capacitor charges during the sampling cycle, referred to as the acquisition period. During this acquisition period, the settling time is affected by the input resistance and the input sampling capacitance. This error can be estimated by looking at the settling of an RC time constant using the input capacitance and the source impedance over the acquisition time period. 0.5 0 500 1000 1500 2000 2500 3000 fS (ksps) Figure 10. Supply Current vs. Sample Rate (Normal Operating Mode, 3Msps Devices) www.maximintegrated.com 0 0 200 400 600 800 1000 fS (ksps) Figure 11. Supply Current vs. Sample Rate (Device Powered Down Between Conversions, 3Msps Devices) Maxim Integrated │ 12 MAX11108 Tiny, 2.1mm x 1.6mm, 3Msps, Low-Power, Serial 12-Bit ADC SAMPLE SAMPLE CS SCLK 2 1 DOUT 3 D11 0 4 D10 5 D9 6 D8 7 8 D7 9 D6 D5 10 D4 11 D3 12 D2 13 14 D1 D0 (MSB) 1 0 0 tACQ 1/fSAMPLE tCONVERT Figure 12. 14-Clock Cycle Operation +5V 10µF 0.1µF 3V 100pF COG 3V VDD 500Ω VSOURCE 500Ω VDC 0.1µF 10µF MAX4430 3 -5V 2 0.1µF 10Ω 1 10µF 0.1µF AGND 5 4 OVDD AIN 470pF COG CAPACITOR MAX11108 10µF SCLK SCK DOUT MISO CS SS CPU REF 0.1µF 10µF EP 3V +5V 7 6 0.1µF 4 3 OUTF IN 2 1µF OUTS MAX6126 GNDS GND NR 0.1µF 1 0.1µF Figure 13. Typical Application Circuit www.maximintegrated.com Maxim Integrated │ 13 MAX11108 Definitions Integral Nonlinearity Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. For these devices, the straight line is a line drawn between the end points of the transfer function after offset and gain errors are nulled. Differential Nonlinearity Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of ±1 LSB or less guarantees no missing codes and a monotonic transfer function. Offset Error The deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, that is, AGND + 0.5 LSB. Gain Error The deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal after adjusting for the offset error, that is, VREF - 1.5 LSB. Aperture Jitter Aperture jitter (tAJ) is the sample-to-sample variation in the time between the samples. Aperture Delay Aperture delay (tAD) is the time between the falling edge of sampling clock and the instant when an actual sample is taken. Signal-to-Noise Ratio (SNR) SNR is a dynamic figure of merit that indicates the converter’s noise performance. For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits): SNR (dB) (MAX) = (6.02 x N + 1.76) (dB) In reality, there are other noise sources such as thermal noise, reference noise, and clock jitter that also degrade SNR. SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, 2nd to 5th harmonic, and the DC offset. www.maximintegrated.com Tiny, 2.1mm x 1.6mm, 3Msps, Low-Power, Serial 12-Bit ADC Signal-to-Noise Ratio and Distortion (SINAD) SINAD is a dynamic figure of merit that indicates the converter’s noise and distortion performance. SINAD is computed by taking the ratio of the RMS signal to the RMS noise plus distortion. RMS noise plus distortion includes all spectral components to the Nyquist frequency excluding the fundamental and the DC offset: SIGNAL RMS SINAD(dB) = 20 × log (NOISE + DISTORTION) RMS Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RMS sum of the first four harmonics of the input signal to the fundamental itself. This is expressed as: V 22 + V32 + V 42 + V52 THD = 20 × log V1 where V1 is the fundamental amplitude and V2–V5 are the amplitudes of the 2nd- through 5th-order harmonics. Spurious-Free Dynamic Range (SFDR) SFDR is a dynamic figure of merit that indicates the lowest usable input signal amplitude. SFDR is the ratio of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset. SFDR is specified in decibels with respect to the carrier (dBc). Full-Power Bandwidth Full-power bandwidth is the frequency at which the input signal amplitude attenuates by 3dB for a full-scale input. Full-Linear Bandwidth Full-linear bandwidth is the frequency at which the signalto-noise ratio and distortion (SINAD) is equal to a specified value. Intermodulation Distortion Any device with nonlinearities creates distortion products when two sine waves at two different frequencies (f1 and f2) are applied into the device. Intermodulation distortion (IMD) is the total power of the IM2 to IM5 intermodulation products to the Nyquist frequency relative to the total input power of the two input tones, f1 and f2. The individual input tone levels are at -6dBFS. Maxim Integrated │ 14 MAX11108 Tiny, 2.1mm x 1.6mm, 3Msps, Low-Power, Serial 12-Bit ADC Ordering Information PART PIN-PACKAGE BITS SPEED (Msps) NO. OF CHANNELS TOP MARK 1 +ABC MAX11108AVB+T 10 Ultra TQFN 12 3 Note: This device is specified over the -40°C to +125°C operating temperature range. +Denotes a lead(Pb)-free/RoHS-compliant package. T = Tape and reel. Chip Information PROCESS: BiCMOS www.maximintegrated.com Package Information For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 10 Ultra TQFN V101A2CN+1 21-0610 90-0386 Maxim Integrated │ 15 MAX11108 Tiny, 2.1mm x 1.6mm, 3Msps, Low-Power, Serial 12-Bit ADC Revision History REVISION NUMBER REVISION DATE 0 9/12 Initial release 1 4/13 Updated data sheet 2 12/14 Revised Benefits and Features section 1 3 3/15 Removed automotive reference from data sheet 1 DESCRIPTION PAGES CHANGED — 1–4, 8–15 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com. Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2015 Maxim Integrated Products, Inc. │ 16