ON NLVHC1G04DFT2G Single inverter Datasheet

MC74HC1G04
Single Inverter
The MC74HC1G04 is a high speed CMOS inverter fabricated with
silicon gate CMOS technology.
The internal circuit is composed of multiple stages, including
a buffer output which provides high noise immunity and stable output.
The MC74HC1G04 output drive current is 1/2 compared to
MC74HC series.
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High Speed: tPD = 7 ns (Typ) at VCC = 5 V
Low Power Dissipation: ICC = 1 mA (Max) at TA = 25_C
High Noise Immunity
Balanced Propagation Delays (tpLH = tpHL)
Symmetrical Output Impedance (IOH = IOL = 2 mA)
Chip Complexity: FET = 105
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
SC−88A
(SC70−5/SOT−353)
DF SUFFIX
CASE 419A
TSOP−5
DT SUFFIX
CASE 483
MARKING DIAGRAMS
5
5
H5 MG
G
5
1
NC
H5 MG
G
1
VCC
1
SC−88A
IN A
2
GND
3
H5
M
G
TSOP−5
= Specific Device Code
= Date Code
= Pb−Free Package
OUT Y
4
(Note: Microdot may be in either location)
Figure 1. Pinout (Top View)
PIN ASSIGNMENT
1
IN A
OUT Y
1
NC
2
IN A
3
GND
4
OUT Y
5
VCC
Figure 2. Logic Symbol
FUNCTION TABLE
Input A
Output Y
L
H
H
L
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
September, 2014 − Rev. 10
1
Publication Order Number:
MC74HC1G04/D
MC74HC1G04
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage
−0.5 to +7.0
V
VIN
DC Input Voltage
−0.5 to VCC + 0.5
V
DC Output Voltage
−0.5 to VCC + 0.5
V
VOUT
IIK
DC Input Diode Current
±20
mA
IOK
DC Output Diode Current
±20
mA
IOUT
DC Output Sink Current
±12.5
mA
ICC
DC Supply Current per Supply Pin
±25
mA
−65 to +150
_C
260
_C
TSTG
Storage Temperature Range
TL
Lead Temperature, 1 mm from Case for 10 Seconds
TJ
Junction Temperature Under Bias
qJA
Thermal Resistance
PD
Power Dissipation in Still Air at 85_C
MSL
Moisture Sensitivity
FR
Flammability Rating
VESD
Latchup Performance
_C
350
230
_C/W
SC70−5/SC−88A
TSOP−5
150
200
mW
Level 1
Oxygen Index: 28 to 34
ESD Withstand Voltage
ILATCHUP
+150
SC70−5/SC−88A (Note 1)
TSOP−5
UL 94 V−0 @ 0.125 in
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
Above VCC and Below GND at 125_C (Note 5)
> 2000
> 200
N/A
V
±500
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2 ounce copper trace with no air flow.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Min
Max
Unit
VCC
DC Supply Voltage
2.0
6.0
V
VIN
DC Input Voltage
0.0
VCC
V
DC Output Voltage
0.0
VCC
V
Operating Temperature Range
−55
+125
_C
0
0
0
0
1000
600
500
400
ns
VOUT
TA
tr , tf
Parameter
Input Rise and Fall Time
VCC = 2.0 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 6.0 V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
90
419,300
47.9
100
178,700
20.4
110
79,600
9.4
120
37,000
4.2
130
17,800
2.0
140
8,900
1.0
TJ = 80_C
117.8
TJ = 90_C
1,032,200
TJ = 100_C
80
TJ = 110_C
Time, Years
TJ = 120_C
Time, Hours
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
TJ = 130_C
Junction
Temperature °C
NORMALIZED FAILURE RATE
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
1
1
10
100
1000
TIME, YEARS
Figure 3. Failure Rate vs. Time Junction Temperature
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2
MC74HC1G04
DC ELECTRICAL CHARACTERISTICS
VCC
Symbol
Parameter
Test Conditions
(V)
Min
1.5
2.1
3.15
4.20
VIH
Minimum High−Level
Input Voltage
2.0
3.0
4.5
6.0
VIL
Maximum Low−Level
Input Voltage
2.0
3.0
4.5
6.0
VOH
Minimum High−Level
Output Voltage
VIN = VIH or VIL
VIN = VIH or VIL
IOH = −20 mA
VIN = VIH or VIL
IOH = −2 mA
IOH = −2.6 mA
VOL
Maximum Low−Level
Output Voltage
VIN = VIH or VIL
VIN = VIH or VIL
IOL = 20 mA
TA v 85_C
TA = 25_C
Typ
Max
Min
*55_C v TA v 125_C
Max
Min
1.5
2.1
3.15
4.20
0.5
0.9
1.35
1.80
Max
1.5
2.1
3.15
4.20
0.5
0.9
1.35
1.80
V
0.5
0.9
1.35
1.80
2.0
3.0
4.5
6.0
1.9
2.9
4.4
5.9
2.0
3.0
4.5
6.0
1.9
2.9
4.4
5.9
1.9
2.9
4.4
5.9
4.5
6.0
4.18
5.68
4.31
5.80
4.13
5.63
4.08
5.58
Unit
V
V
2.0
3.0
4.5
6.0
0.0
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
VIN = VIH or VIL
IOL = 2 mA
IOL = 2.6 mA
4.5
6.0
0.17
0.18
0.26
0.26
0.33
0.33
0.40
0.40
V
IIN
Maximum Input
Leakage Current
VIN = 6.0 V or GND
6.0
±0.1
±1.0
±1.0
mA
ICC
Maximum Quiescent
Supply Current
VIN = VCC or GND
6.0
1.0
10
40
mA
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 6.0 ns)
TA v 85_C
TA = 25_C
Symbol
Parameter
tPLH,
tPHL
Maximum
Propagation Delay,
Input A or B to Y
tTLH,
tTHL
Output Transition
Time
CIN
Maximum Input
Capacitance
Test Conditions
Min
Typ
Max
Min
*55_C v TA v 125_C
Max
Min
Max
Unit
ns
VCC = 5.0 V
CL = 15 pF
3.5
15
20
25
VCC = 2.0 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 6.0 V
CL = 50 pF
18
10
7
6
100
27
20
17
125
35
25
21
155
90
35
26
VCC = 5.0 V
CL = 15 pF
3
10
15
20
VCC = 2.0 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 6.0 V
CL = 50 pF
25
16
11
9
125
35
25
21
155
45
31
26
200
60
38
32
5
10
10
10
ns
pF
Typical @ 25_C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Note 6)
10
pF
6. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no−load dynamic
power consumption; PD = CPD VCC2 fin + ICC VCC.
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3
MC74HC1G04
tr
tf
90%
50%
10%
INPUT A
CL*
GND
tPHL
OUTPUT Y
OUTPUT
INPUT
VCC
tPLH
90%
50%
10%
tTHL
*Includes all probe and jig capacitance.
A 1−MHz square input wave is recommended for
propagation delay tests.
tTLH
Figure 4. Switching Waveforms
Figure 5. Test Circuit
DEVICE ORDERING INFORMATION
Device Nomenclature
Device Order
Number
Logic
Circuit
Indicator
Temp
Range
Identifier
Technology
Device
Function
Package
Suffix
Tape
and
Reel
Suffix
MC74HC1G04DFT1G
MC
74
HC1G
08
DF
NLVHC1G04DFT1G*
NLV
74
HC1G
08
MC74HC1G04DFT2G
MC
74
HC1G
NLVHC1G04DFT2G*
NLV
74
MC74HC1G04DTT1G
MC
74
Package
Type
Tape and
Reel Size†
T1
SC−88A
(SC70−5/SOT−353)
(Pb−Free)
178 mm (7 in)
3000 Unit
DF
T1
SC−88A
(SC70−5/SOT−353)
(Pb−Free)
178 mm (7 in)
3000 Unit
08
DF
T2
SC−88A
(SC70−5/SOT−353)
(Pb−Free)
178 mm (7 in)
3000 Unit
HC1G
08
DF
T2
SC−88A
(SC70−5/SOT−353)
(Pb−Free)
178 mm (7 in)
3000 Unit
HC1G
08
DT
T1
TSOP−5
(Pb−Free)
178 mm (7 in)
3000 Unit
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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4
MC74HC1G04
PACKAGE DIMENSIONS
SC−88A (SC−70−5/SOT−353)
CASE 419A−02
ISSUE L
A
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
G
5
4
−B−
S
1
2
DIM
A
B
C
D
G
H
J
K
N
S
3
0.2 (0.008)
D 5 PL
B
M
M
N
INCHES
MIN
MAX
0.071
0.087
0.045
0.053
0.031
0.043
0.004
0.012
0.026 BSC
--0.004
0.004
0.010
0.004
0.012
0.008 REF
0.079
0.087
J
C
K
H
SOLDER FOOTPRINT*
0.50
0.0197
0.65
0.025
0.65
0.025
0.40
0.0157
1.9
0.0748
SCALE 20:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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5
MILLIMETERS
MIN
MAX
1.80
2.20
1.15
1.35
0.80
1.10
0.10
0.30
0.65 BSC
--0.10
0.10
0.25
0.10
0.30
0.20 REF
2.00
2.20
MC74HC1G04
PACKAGE DIMENSIONS
TSOP−5
CASE 483−02
ISSUE K
NOTE 5
2X
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.15 PER SIDE. DIMENSION A.
5. OPTIONAL CONSTRUCTION: AN ADDITIONAL
TRIMMED LEAD IS ALLOWED IN THIS LOCATION.
TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2
FROM BODY.
D 5X
0.20 C A B
0.10 T
M
2X
0.20 T
B
5
1
4
2
S
3
K
B
DETAIL Z
G
A
A
TOP VIEW
DIM
A
B
C
D
G
H
J
K
M
S
DETAIL Z
J
C
0.05
H
SIDE VIEW
C
SEATING
PLANE
END VIEW
MILLIMETERS
MIN
MAX
3.00 BSC
1.50 BSC
0.90
1.10
0.25
0.50
0.95 BSC
0.01
0.10
0.10
0.26
0.20
0.60
0_
10 _
2.50
3.00
SOLDERING FOOTPRINT*
0.95
0.037
1.9
0.074
2.4
0.094
1.0
0.039
0.7
0.028
SCALE 10:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
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For additional information, please contact your local
Sales Representative
MC74HC1G04/D
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