TI DAC8043U/2K5G4 Cmos 12-bit serial input multiplying digital-to-analog converter Datasheet

®
DAC
DAC8043
804
3
CMOS 12-Bit Serial Input Multiplying
DIGITAL-TO-ANALOG CONVERTER
FEATURES
APPLICATIONS
● 12-BIT ACCURACY IN 8-PIN SOIC
● AUTOMATIC CALIBRATION
● FAST 3-WIRE SERIAL INTERFACE
● MOTION CONTROL
● LOW INL AND DNL: ±1/2 LSB max
● MICROPROCESSOR CONTROL SYSTEMS
● GAIN ACCURACY TO ±1LSB max
● PROGRAMMABLE AMPLIFIER/
ATTENUATORS
● DIGITALLY CONTROLLED FILTERS
● LOW GAIN TEMPCO: 5ppm/°C max
● OPERATES WITH +5V SUPPLY
● TTL/CMOS COMPATIBLE
● ESD PROTECTED
DESCRIPTION
The DAC8043 is a 12-bit current output multiplying
digital-to-analog converter (DAC) that is packaged in a
space-saving, surface-mount 8-pin SOIC. Its 3-wire serial interface saves additional circuit board space which
results in low power dissipation. When used with microprocessors having a serial port, the DAC8043 minimizes
the digital noise feedthrough from its input to output.
The serial port can be used as a dedicated analog bus and
kept inactive while the DAC8043 is in use. Serial interfacing reduces the complexity of opto or transformer
isolation applications.
The DAC8043 contains a 12-bit serial-in, parallel-out
shift register, a 12-bit DAC register, a 12-bit CMOS
DAC, and control logic. Serial input (SRI) data is clocked
into the input register on the rising edge of the clock
(CLK) pulse. When the new data word had been clocked
in, it is loaded into the DAC register by taking the LD
input low. Data in the DAC register is converted to an
output current by the D/A converter.
RFB
VREF
1
12-Bit
D/A
Converter
2
3
RFB
IOUT
12
5
LD
12-Bit
DAC Register
8
VDD
12
4
7
CLK
6
SRI
GND
12-Bit Input
Shift Register
The DAC8043 operates from a single +5V power supply
which makes the DAC8043 an ideal low power, small
size, high performance solution for several applications.
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
®
©
SBAS028
1993 Burr-Brown Corporation
PDS-1197B
1
Printed in U.S.A. March, 1998
DAC8043
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
At VDD = +5V; VREF = +10V; IOUT = GND = 0V; TA = Full Temperature Range specified under Absolute Maximum Ratings, unless otherwise noted.
DAC8043U
PARAMETER
SYMBOL
STATIC PERFORMANCE
Resolution
Nonlinearity(1)
Differential Nonlinearity(2)
Gain Error(3)
Gain Tempco(5)
Power Supply Rejection Ratio
Output Leakage Current(4)
N
INL
DNL
FSE
IZSE
Input Resistance
RIN
AC PERFORMANCE
Output Current Settling Time(5, 6)
Digital-to-Analog Glitch
Energy(5, 10)
MIN
ANALOG OUTPUTS
Output Capacitance(5)
MAX
±0.0006
11
±1
±1
±2
±2
±5
±0.002
±5
±100
0.03
0.60
15
∆VDD = ±5%
T A = +25°C
TA = Full Temp Range
T A = +25°C
TA = Full Temp Range
7
tS
0.25
2
0.7
VIH
VIL
IIL
CIN
TYP
MAX
UNITS
±0.0006
11
±1/2
±1/2
±1
±2
±5
±0.002
±5
±25
0.03
0.15
15
Bits
LSB
LSB
LSB
LSB
ppm/°C
%/%
nA
nA
LSB
LSB
kΩ
1
20
0.25
2
1
20
µs
nVs
1
0.7
1
mVp-p
–85
17
dB
17
nV/√Hz
VIN = 0V to +5V
VIN = 0V
0.8
±1
8
0.8
±1
8
V
V
µA
pF
Digital Inputs = VIH
Digital Inputs = VIL
110
80
110
80
pF
pF
TIMING CHARACTERISTICS(5, 14)
Data Setup Time
Data Hold Time
Clock Pulse Width High
Clock Pulse Width Low
Load Pulse Width
LSB Clock into Input Register
to Load DAC Register Time
tDS
tDH
tCH
tCL
tLD
TA
TA
TA
TA
TA
tASB
TA = Full Temperature Range
POWER SUPPLY
Supply Voltage
Supply Current
VDD
IDD
=
=
=
=
=
7
–85
2.4
COUT
MIN
12
T A = +25°C
TA = Full Temp Range
T A = +25°C
VREF = 0V
Q
IOUT = Load = 100Ω
CEXT = 13pF
DAC Register Loaded Alternately with all 0s and all 1s
Feedthrough Error(5, 11)
FT
VREF = 20Vp-p at f = 10kHz
(VREF to IOUT)
Digital Input = 0000 0000 0000
T A = +25°C
Total Harmonic Distortion(5)
THD
VREF = 6VRMS at 1kHz
DAC Register Loaded with all 1s
Output Noise Voltage Density(5, 13)
eN
10Hz to 100kHz
Between RFB and IOUT
DIGITAL INPUTS
Digital Input High
Digital Input Low
Input Leakage Current(9)
Input Capacitance(5, 11)
DAC8043UC
TYP
12
TCFSE
PSRR
ILKG
Zero Scale Error(7, 12)
(8)
CONDITIONS
Full
Full
Full
Full
Full
Temperature
Temperature
Temperature
Temperature
Temperature
Range
Range
Range
Range
Range
2.4
40
80
90
120
120
40
80
90
120
120
ns
ns
ns
ns
ns
0
0
ns
4.75
Digital Inputs = VIH or VIL
Digital Inputs = 0V or VDD
5
5.25
500
100
4.75
5
5.25
500
100
V
µA
µA
NOTES: (1) ±1/2 LSB = ±0.012% of Full Scale. (2) All grades are monotonic to 12-bits over temperature. (3) Using internal feedback resistor. (4) Applies to IOUT; All
digital inputs = 0V. (5) Guaranteed by design and not tested. (6) IOUT Load = 100Ω, CEXT = 13pF, digital input = 0V to VDD or VDD to 0V. Extrapolated to 1/2 LSB:
tS = propagation delay (tPD) + 9τ where τ = measured time constant of the final RC decay. (7) VREF = +10V, all digital inputs = 0V. (8) Absolute temperature coefficient
is less than ±50ppm/°C. (9) Digital inputs are CMOS gates: IIN is typically 1nA at +25°C. (10) VREF = 0V, all digital inputs = 0V to VDD or VDD to 0V. (11) All digital
inputs = 0V. (12) Calculated from worst case RREF: IZSE (in LSBs) = (RREF X ILKG X 4096)/VREF. (13) Calculations from en = √4K TRB where: K = Boltzmann constant,
J/°K, R = resistance, Ω. T = Resistor temperature, °K, B = bandwidth, Hz. (14) Tested at VIN = 0V or VDD.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
DAC8043
2
WAFER TEST LIMITS
At VDD = +5V; VREF = +10V; IOUT = GND = 0V; TA = +25°C.
PARAMETER
CONDITIONS
LIMIT
DAC8043
UNITS
Using Internal Feedback Resistor
∆VDD = ±5%
Digital Inputs = VIL
12
±1
±1
±2
±0.002
±5
Bits min
LSB max
LSB max
LSB max
%/% max
nA max
SYMBOL
STATIC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Gain Error
Power Supply Rejection Ratio
Output Leakage Current (IOUT)
N
INL
DNL
GFSE
PSRR
ILKG
REFERENCE INPUT
Input Resistance
RIN
7/15
kΩ min/max
DIGITAL INPUTS
Digital Input HIGH
Digital Input LOW
Input Leakage Current
VIH
VIL
IIL
VIN = 0V to VDD
2.4
0.8
±1
V min
V max
µA max
POWER SUPPLY
Supply Current
IDD
Digital Inputs = VIH or VIL
Digital Inputs = 0V to VDD
500
100
µA max
µA max
NOTE: Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not
guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
VDD to GND .................................................................................. 0V, +7V
VREF to GND ...................................................................................... ±25V
VRFB to GND ...................................................................................... ±25V
Digital Input Voltage Range ................................................. –0.3V to VDD
Output Voltage (Pin 3) ......................................................... –0.3 V to VDD
Operating Temperature Range
AD ........................................................................................ 0°C to +70°C
U, UC ............................................................................... –40°C to +85°C
Junction Temperature .................................................................... +150°C
Storage Temperature .................................................... –65°C to + 150°C
Lead Temperature (soldering, 10s) .............................................. +300° C
θJA .......................................................................................................................... +100°C/W
θJC ........................................................................................... +42°C/W
Top View
CAUTION: 1. Do not apply voltages higher than VDD or less than GND
potential on any terminal except VREF (Pin 1) and RFB (Pin 2). 2. The digital
control inputs are ESD protected: however, permanent damage may occur on
unprotected units from high-energy electrostatic fields. Keep units in conductive foam at all times until ready to use. 3. Use proper anti-static handling
procedures. 4. Absolute Maximum Ratings apply to both packaged devices.
Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device.
PRODUCT
DAC8043U
DAC8043UC
INL
PACKAGE
PACKAGE
DRAWING
NUMBER (1)
1LSB
1/2LSB
–40°C to +85°C
–40°C to +85°C
8-pin SOIC
8-pin SOIC
182
182
VREF
1
8
VDD
RFB
2
7
CLK
IOUT
3
6
SRI
GND
4
5
LD
ELECTROSTATIC
DISCHARGE SENSITIVITY
Any integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
PACKAGE/ORDERING INFORMATION
TEMPERATURE
RANGE
8-Pin SOIC
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet
published specifications.
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
Digital Inputs: All digital inputs of the DAC8043 incorporate on-chip ESD protection circuitry. This protection is
designed and has been tested to withstand five 2500V
positive and negative discharges (100pF in series with 1500Ω)
applied to each digital input.
Analog Pins: Each analog pin has been tested to BurrBrown’s analog ESD test consisting of five 1000V positive
and negative discharges (100pF in series with 1500Ω) applied to each pin. VREF and RFB show some sensitivity.
3
DAC8043
®
WRITE CYCLE TIMING DIAGRAM
Bit 1
MSB(1)
SRI
Bit 11
2
11
1
tCH
tCL
Load Serial Data
Into Input Register
tASB
tLD
LD
Load Input Register's
Data Into DAC Register
NOTE: (1) Data loaded MSB first.
®
DAC8043
Bit 12
LSB
tDH
tDS
CLK INPUT
Bit 2
4
TYPICAL PERFORMANCE CURVES
At VDD = +5V; VREF = +10V; IOUT = GND = 0V; TA = Full Temperature Range specified under Absolute Maximum Ratings, unless otherwise noted.
LINEARITY ERROR vs REFERENCE VOLTAGE
GAIN vs FREQUENCY
0
0.5
Digital Input
= 1111 1111 1111
–20
0.25
Gain (dB)
INL (LSB)
–40
0
Digital Input
= 0000 0000 0000
–60
–80
–0.25
VDD = +5V
VREF = 100mV
TA = +25°C
–100
–0.5
–120
2
4
6
8
1k
10
100k
1M
Frequency (Hz)
SUPPLY CURRENT vs LOGIC INPUT VOLTAGE
TOTAL HARMONIC DISTORTION vs FREQUENCY
(Multiplying Mode)
10M
0
1.6
VDD = +5V
VDD = +5V
1.4
VIN = 6Vrms
–20
TA = +25°C
1.2
–40
1.0
THD (dB)
IDD (mA)
10k
VREF (V)
0.8
0.6
–60
–80
0.4
–100
0.2
0
–120
0
1
2
3
10
4
100
10000
DNL ERROR vs REFERENCE VOLTAGE
LINEARITY ERROR vs DIGITAL CODE
1
0.5
TA = +25°C
0.75
VREF = +10V
0.25
0.5
DNL (LSB)
Linearity Error (LSB)
1000
Frequency (Hz)
VIN (V)
0.25
0
–0.25
0
–0.25
–0.5
–0.75
–0.5
–1
0
1024
2048
3072
2
4096
Digital Input Code (Decimal)
4
6
8
10
VREF (V)
®
5
DAC8043
DISCUSSION OF
SPECIFICATIONS
tains a constant current in each leg of the ladder regardless of
the input code. The input resistance at VREF is therefore
constant and can be driven by either a voltage or current, AC
or DC, positive or negative polarity, and have a voltage range
up to ±20V.
RELATIVE ACCURACY
This term, also known as end point linearity or integral
linearity, describes the transfer function of analog output to
digital input code. Relative accuracy describes the deviation
from a straight line, after zero and full scale errors have been
adjusted to zero.
A CMOS switch transistor, included in series with the ladder
terminating resistor and in series with the feedback resistor,
RFB, compensates for the temperature drift of the ON resistance of the ladder switches.
Figure 2 shows an equivalent circuit for the DAC. COUT is the
output capacitance due to the N-channel switches and varies
from about 80pF to 110pF with digital input code. The current
source ILKG is the combination of surface and junction leakages to the substrate. ILKG approximately doubles every 10°C.
RO is the equivalent output resistance of the D/A and it varies
with input code.
DIFFERENTIAL NONLINEARITY
Differential nonlinearity is the deviation from an ideal 1LSB
change in the output when the input code changes by 1LSB.
A differential nonlinearity specification of 1LSB maximum
guarantees monotonicity.
GAIN ERROR
Gain error is the difference between the full-scale DAC
output and the ideal value. The ideal full scale output value
for the DAC8043 is –(4095/4096)VREF . Gain error may be
adjusted to zero using external trims as shown in Figure 4.
R
R
OUTPUT LEAKAGE CURRENT
The current which appears at IOUT with the DAC loaded with
all zeros.
All digital inputs of the DAC8043 incorporate on-chip ESD
protection circuitry. This protection is designed to withstand
2.5kV (using the Human Body Model, 100pF and 1500Ω).
However, industry standard ESD protection methods should
be used when handling or storing these components. When
not in use, devices should be stored in conductive foam or
rails. The foam or rails should be discharged to the destination socket potential before devices are removed.
POWER SUPPLY CONNECTIONS
The DAC8043 is designed to operate on VDD = +5V ±5%.
For optimum performance and noise rejection, power supply
decoupling capacitors CD should be added as shown in the
application circuits. These capacitors (1µF tantalum recommended) should be located close to the D/A. Output op amp
analog common (+ input) should be connected as near to the
GND pins of the DAC8043 as possible.
CIRCUIT DESCRIPTION
Figure 1 shows a simplified schematic of a DAC8043. The
current from the VREF pin is switched between IOUT and GND
by 12 single-pole double-throw CMOS switches. This mainR
2R
2R
2R
2R
WIRING PRECAUTIONS
To minimize AC feedthrough when designing a PC board,
care should be taken to minimize capacitive coupling between the VREF lines and the IOUT lines. Coupling from any
of the digital control or data lines might degrade the glitch
performance. Solder the DAC8043 directly into the PC board
without a socket. Sockets add parasitic capacitance (which
can degrade AC performance).
R RFB
IOUT
GND
Bit 1
(MSB)
Bit 2
Bit 3
Bit 12
(LSB)
FIGURE 1. Simplified Circuit Diagram for the DAC.
®
DAC8043
COUT
ESD PROTECTION
DIGITAL-TO-ANALOG GLITCH ENERGY
The integrated area of the glitch pulse measured in nanovoltseconds. The key contributor to digital-to-analog glitch is
charge injected by digital logic switching transients.
2R
IOUT
INSTALLATION
OUTPUT CURRENT SETTLING TIME
The time required for the output current to settle to within
+0.01% of final value for a full scale step.
R
RO
ILKG
FIGURE 2. Equivalent Circuit for the DAC.
FEEDTHROUGH ERROR
The AC output error due to capacitive coupling from VREF to
IOUT with the DAC loaded with all zeros.
R
DIN VREF
x
4096
R
GND
OUTPUT CAPACITANCE
The parasitic capacitance measured from IOUT to GND.
VREF
RFB
VREF
6
AMPLIFIER OFFSET VOLTAGE
The output amplifier used with the DAC8043 should have
low input offset voltage to preserve the transfer function
linearity. The voltage output of the amplifier has an error
component which is the offset voltage of the op amp multiplied by the “noise gain” of the circuit. This “noise gain” is
equal to (RF / RO + 1) where RO is the output impedance of the
D/A IOUT terminal and RF is the feedback network impedance. The nonlinearity occurs due to the output impedance
varying with code. If the 0 code case is excluded (where
RO = infinity), the RO will vary from R to 3R providing a
“noise gain” variation between 4/3 and 2. In addition, the
variation of RO is nonlinear with code, and the largest steps
in RO occur at major code transitions where the worst
differential nonlinearity is also likely to be experienced. The
nonlinearity seen at the amplifier output is
2VOS – 4VOS /3 = 2VOS/3.
versus digital input code are listed in Table I. The operational
amplifiers used in this circuit can be single amplifiers such as
the OPA602, or a dual amplifier such as the OPA2107. C1
provides phase compensation to minimize settling time and
overshoot when using a high speed operational amplifier.
If an application requires the D/A to have zero gain error, the
circuit shown in Figure 4 may be used. Resistor R2 induces
a positive gain error greater than worst-case initial negative
gain error. Trim resistor R1 provides a variable negative gain
error and have sufficient trim range to correct for the worstcase initial positive gain error plus the error produced by R2.
BIPOLAR CONFIGURATION
Figure 5 shows the DAC8043 in a typical bipolar (fourquadrant) multiplying configuration. The analog output values versus digital input code are listed in Table II.
The operational amplifiers used in this circuit can be single
amplifiers such as the OPA602 or a dual amplifier such as
the OPA2107. C1 provides phase compensation to minimize
settling time and overshoot when using a high speed operational amplifier. The bipolar offset resistors R1–R2 should
be ratio-matched to 0.01% to ensure the specified gain error
performance.
Thus, to maintain good nonlinearity the op amp offset should
be much less than 1/2LSB.
UNIPOLAR CONFIGURATION
Figure 3 shows DAC8043 in a typical unipolar (two-quadrant) multiplying configuration. The analog output values
DATA INPUT
DATA INPUT
ANALOG OUTPUT
MSB ↓
↓ LSB
1111 1111 1111
1000 0000 0000
0000 0000 0001
0000 0000 0000
–VREF (4095/4096)
–VREF (2048/4096) = –1/2VREF
–VREF (1/4096)
0 Volts
TABLE I. Unipolar Output Code.
VDD
+5V
+
IOUT
GND
C1
10pF
VIN
R1
100Ω
+
CD
1µF
RFB
DAC
+VREF (2047/2048)
+VREF (1/2048)
0 Volts
–VREF (1/2048)
–VREF (2048/2048)
TABLE II. Bipolar Output Code.
VDD VREF
+5V
CD
1µF
ANALOG OUTPUT
MSB ↓
↓ LSB
1111 1111 1111
1000 0000 0001
1000 0000 0000
0111 1111 1111
0000 0000 0000
V REF
RFB
–
A1
+
IOUT
DAC
VOUT
R2
C1 10pF
47Ω
–
A1
+
GND
VOUT
DAC8043
DAC8043
A1 OPA602 or 1/2 OPA2107.
A1 OPA602 or 1/2 OPA2107.
FIGURE 3. Unipolar Configuration.
FIGURE 4. Unipolar Configuration with Gain Trim.
R1
20k Ω
+5V
VDD VREF
R2
20k Ω
–
CD +
1µF
A2
R3
10k Ω
VOUT
+
RFB
C1
10pF
IOUT
DAC
–
A1
GND
+
A1–A2, OPA602 or 1/2 OPA2107.
DAC8043
FIGURE 5. Bipolar Configuration.
®
7
DAC8043
PACKAGE OPTION ADDENDUM
www.ti.com
16-Feb-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
DAC8043U
ACTIVE
SOIC
D
8
DAC8043U/2K5
ACTIVE
SOIC
D
DAC8043U/2K5G4
ACTIVE
SOIC
DAC8043UC
ACTIVE
DAC8043UC/2K5
75
Lead/Ball Finish
MSL Peak Temp (3)
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
SOIC
D
8
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
DAC8043UC/2K5G4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
DAC8043UCG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
DAC8043UG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
75
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DAC8043U/2K5
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
DAC8043UC/2K5
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DAC8043U/2K5
SOIC
D
8
2500
346.0
346.0
29.0
DAC8043UC/2K5
SOIC
D
8
2500
346.0
346.0
29.0
Pack Materials-Page 2
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