ON NIV1161MTTAG Esd protection Datasheet

NIV1161, NIS1161
ESD Protection with
Automotive Short-toBattery Blocking
Low Capacitance ESD Protection with
short−to−battery blocking for Automotive
High Speed Data Lines
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MARKING
DIAGRAM
The NIS/NIV1161 is designed to protect high speed data lines from
ESD as well as short to vehicle battery situations. The ultra−low
capacitance and low ESD clamping voltage make this device an ideal
solution for protecting voltage sensitive high speed data lines while
the low RDS(on) FET limits distortion on the signal lines. The
flow−through style package allows for easy PCB layout and matched
trace lengths necessary to maintain consistent impedance between
high speed differential lines such as USB and LVDS protocols.
WDFN6
CASE 511CB
V6
M
Features
•
= Specific Device Code
= Date Code
PIN CONFIGURATION
AND SCHEMATICS
• Low Capacitance (0.65 pF Typical, I/O to GND)
• Protection for the Following Standards:
•
•
V6 M
1
1
IEC 61000−4−2 (Level 4) & ISO 10605
Integrated MOSFETs for Short−to−Battery Blocking
NIV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q101
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
6
6
2
5
4
3
4
(Top View)
Pin 2 − 5 V
Typical Applications
•
•
•
•
Automotive High Speed Signal Pairs
USB 2.0/3.0
LVDS
APIX 2/3
Pin 1
D+ HOST
Pin 6
D+
Pin 3
D− HOST
Pin 4
D−
ABSOLUTE MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Pin 5 − GND
Pin 2 − 5 V
Rating
Symbol
Value
Unit
Operating Junction Temperature Range
TJ(max)
−55 to +150
°C
Storage Temperature Range
TSTG
−55 to +150
°C
Drain−to−Source Voltage
VDSS
30
V
Gate−to−Source Voltage
VGS
±10
V
Device
Package
Shipping†
Lead Temperature Soldering
TSLD
260
°C
NIV1161MTTAG
ESD
ESD
±8
±15
kV
kV
WDFN−6
(Pb−Free)
3000 / Tape & Reel
IEC 61000−4−2 Contact (ESD)
IEC 61000−4−2 Air (ESD)
NIS1161MTTAG
WDFN−6
(Pb−Free)
3000 / Tape & Reel
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
© Semiconductor Components Industries, LLC, 2016
March, 2016 − Rev. 1
1
ORDERING INFORMATION
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Publication Order Number:
NIV1161/D
NIV1161, NIS1161
ELECTRICAL CHARACTERISTICS (TA = 25_C unless otherwise specified)
Parameter
Reverse Working Voltage
Breakdown Voltage
Symbol
VRWM
VBR
Conditions
Min
I/O Pin to GND
IT = 1 mA, I/O Pin to GND
Typ
Max
Unit
5
16
V
16.5
V
1.0
mA
26
V
Reverse Leakage Current
IR
VRWM = 5 V, I/O Pin to GND
Clamping Voltage
VC
IPP = 1 A, I/O Pin to GND (8/20 ms pulse)
Clamping Voltage (Note 1)
VC
IEC61000−4−2, ±8 KV Contact
Clamping Voltage TLP (Note 2)
See Figures 5 & 6
VC
IPP = 8 A
IPP = 16 A
IPP = −8 A
IPP = −16 A
34
55
−5.2
−10
V
V
V
V
D CJ
VR = 0 V, f = 1 MHz between I/O 1 to GND
and I/O 2 to GND
1.0
%
CJ
VR = 0 V, f = 1 MHz between I/O Pins and
GND (Pin 4 to GND, Pin 6 to GND)
0.65
pF
Junction Capacitance Match
Junction Capacitance
Drain−to−Source Breakdown Voltage
VBR(DSS)
VGS = 0 V, ID = 100 mA
Drain−to−Source Breakdown Voltage
Temperature Coefficient
VBR(DSS)/
TJ
Reference to 25_C, ID = 100 mA
See Figures 1 & 2
30
V
27
mV/_C
Zero Gate Voltage Drain Current
IDSS
VGS = 0 V, VDS = 30 V
1.0
mA
Gate−to−Source Leakage Current
IGSS
VDS = 0 V, VGS = ±5 V
±1.0
mA
VGS(TH)
VDS = VGS, ID = 100 mA
1.5
V
Gate Threshold Voltage (Note 3)
Gate Threshold Voltage Temperature
Coefficient
Drain−to−Source On Resistance
Forward Transconductance
VGS(TH)/TJ
RDS(on)
0.1
1.0
Reference to 25_C, ID = 100 mA
−2.5
VGS = 4.5 V, ID = 125 mA
1.4
7.0
VGS = 2.5 V, ID = 125 mA
2.3
7.5
mV/_C
W
gFS
VDS = 3.0 V, ID = 125 mA
80
mS
Switching Turn−On Delay Time (Note 4)
td(ON)
9
nS
Switching Turn−On Rise Time (Note 4)
tr
VGS = 4.5 V, VDS = 24 V
ID = 125 mA, RG = 10 VW
41
nS
Switching Turn−Off Delay Time (Note 4)
td(OFF)
96
nS
tf
72
nS
Switching Turn−Off Fall Time (Note 4)
Drain−to−Source Forward Diode Voltage
VSD
VGS = 0 V, Is = 125 mA
3 dB Bandwidth
fBW
RL = 50 W
0.79
5
0.9
V
GHz
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. For test procedure see Figures 3 and 4 and application note AND8307/D.
2. ANSI/ESD STM5.5.1 * Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z0 = 50W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns.
3. Pulse test: pulse width ≤ 300 mS, duty cycle ≤ 2%
4. Switching characteristics are independent of operating junction temperatures.
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2
NIV1161, NIS1161
Figure 1. IEC61000−4−2 +8kV Contact ESD
Clamping Voltage
Figure 2. IEC61000−4−2 −8kV Contact ESD
Clamping Voltage
IEC61000−4−2 Waveform
IEC61000−4−2 Spec.
Ipeak
Level
Test Voltage (kV)
First Peak
Current
(A)
Current at
30 ns (A)
Current at
60 ns (A)
1
2
7.5
4
2
2
4
15
8
4
3
6
22.5
12
6
4
8
30
16
8
100%
90%
I @ 30 ns
I @ 60 ns
10%
tP = 0.7 ns to 1 ns
Figure 3. IEC61000−4−2 Spec
ESD Gun
Oscilloscope
TVS
50 W
Cable
50 W
Figure 4. Diagram of ESD Clamping Voltage Test Setup
The following is taken from Application Note
AND8307/D − Characterization of ESD Clamping
Performance.
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping
voltage at the device level. ON Semiconductor has
developed a way to examine the entire voltage waveform
across the ESD protection diode over the time domain of
an ESD pulse in the form of an oscilloscope screenshot,
which can be found on the datasheets for all ESD protection
diodes. For more information on how ON Semiconductor
creates these screenshots and how to interpret them please
refer to AND8307/D.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
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3
NIV1161, NIS1161
16
8
14
8
4
6
4
2
2
6
-12
-10
4
-8
-6
2
-4
Equivalent VIEC [kV]
10
TLP Current [A]
TLP Current [A]
6
Equivalent V IEC [kV]
-14
12
0
8
-16
-2
0
10
20
30
40
Vc [V]
50
60
70
0
0
0
Figure 5. Positive TLP I−V Curve
NOTE:
10
20
30
40
50
Vc [V]
60
70
0
Figure 6. Negative TLP I−V Curve
TLP parameter: Z0 = 50 W, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns. VIEC is the equivalent voltage
stress level calculated at the secondary peak of the IEC 61000−4−2 waveform at t = 30 ns with 2 A/kV. See TLP description
below for more information.
Transmission Line Pulse (TLP) Measurement
L
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 7. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 8 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels. For more
information on TLP measurements and how to interpret
them please refer to AND9007/D.
S Attenuator
÷
50 W Coax
Cable
10 MW
IM
50 W Coax
Cable
VM
DUT
VC
Oscilloscope
Figure 7. Simplified Schematic of a Typical TLP
System
Figure 8. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
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4
NIV1161, NIS1161
TYPICAL MOSFET PERFORMANCE CURVES
4.5 V
ID, DRAIN CURRENT (A)
4.0 V
1.0
0.9
3.5 V
0.8
0.7
3.0 V
2.8 V
2.6 V
2.4 V
2.2 V
2.0 V
1.8 V
0.6
0.5
0.4
0.3
0.2
0.1
0
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
5.0 V
VGS = 10 V
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VDS = 5 V
TJ = 25°C
TJ = 150°C
0.7
0.6
TJ = −55°C
0.5
0.4
0.3
0.2
5.0
0
1.0
2.0
2.5
3.0
3.5
Figure 9. On−Region Characteristics
Figure 10. Transfer Characteristics
TJ = 25°C
ID = 125 mA
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
2.0
3.0
2.5
3.5
4.0
4.5
4.0 4.5
10
TJ = −55°C
TJ = 125°C
9.0
8.0
VGS = 2.5 V
VGS = 4.5 V
TJ = 25°C
7.0
6.0
5.0
TJ = 125°C
4.0
3.0
TJ = 25°C
2.0
1.0
0
TJ = −55°C
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
VGS, GATE VOLTAGE (V)
ID, DRAIN CURRENT (A)
Figure 12. On−Resistance vs. Drain Current
and Gate Voltage
Figure 11. On−Resistance vs. Gate−to−Source
Voltage
1000
ID = 125 mA
VGS = 4.5 V
IDSS, LEAKAGE (nA)
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
−50
1.5
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
9.0
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
0.5
VGS, GATE−TO−SOURCE VOLTAGE (V)
10
1.5
1.2
1.1
1.0
0.9
0.8
0.1
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
ID, DRAIN CURRENT (A)
1.2
1.1
TJ = 150°C
100
TJ = 125°C
10
TJ = 85°C
1
0.1
−25
0
25
50
75
100
125
150
0
5
10
15
20
25
30
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 13. On−Resistance Variation with
Temperature
Figure 14. Drain−to−Source Leakage Current
vs. Voltage
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5
NIV1161, NIS1161
APPLICATION INFORMATION
• Make sure to use differential design methodology and
Today’s connected cars are using multiple high speed
signal pair interfaces for various applications such as
infotainment, connectivity and ADAS. The electrical
hazards likely to be encountered in these automotive high
speed signal interfaces include damaging ESD and
transient events which occur during manufacturing and
assembly, by vehicle occupants or other electrical circuits
in the vehicle. The major documents discussing ESD and
transient events as far as road vehicles are concerned are
ISO 10605 (Road vehicles − Test methods for electrical
disturbances from electrostatic discharge) which describes
ESD test methods and ISO 7637 (Road vehicles − Electrical
disturbances from conduction and coupling) for effects
caused by other electronics in the vehicle. IS0 10605 is
based on IEC 61000−4−2 Industry Standard, which
specifies the various levels of ESD signal characteristics,
but also includes additional vehicle−specific requirements.
Further, OEM specific test requirements are usually also
imposed. In addition, these high speed signal pairs require
protection from short−to−battery (which goes up to
16 VDC) and short−to−ground faults.
A suitable protection solution must satisfy well known
constraints, such as low capacitive loading of the signal
lines to minimize signal attenuation, and also respond
quickly to surges and transients with low clamping voltage.
In addition, small package sizes help to minimize demand
for board−space while providing the ability to route the
trace signals with minimal bending to maintain signal
integrity.
impedance matching of all high speed signal traces.
♦ Use curved traces when possible to avoid unwanted
reflections.
♦ Keep the trace lengths equal between the positive
and negative lines of the differential data lanes to
avoid common mode noise generation and
impedance mismatch.
♦ Place grounds between high speed pairs and keep
as much distance between pairs as possible to
reduce crosstalk.
Modes of Operation
There are two distinct modes of operation of the
NIV1161: normal (steady state) and short−to−battery
event. The below describes each of these in more detail.
Normal Operation (Steady State)
In normal operation, the MOSFETs operate in linear
mode, with all source and drain voltages nearly equal,
passing the signal levels effectively from the USB
transceiver. To ensure successful link communication, the
applied gate voltage must be greater than the maximum
signal level from the data line plus the maximum threshold
voltage of the MOSFET device. Due to the NIV1161’s low
of 1.5 V, both 3.3 and 5 V gate drives are suitable to provide
headroom for most communication protocols. The net
effect of the 1 kW pull−up resistor on the MOSFET gate to
the source effectively level−shifts the common mode
voltage on the individual data lines up to the gate voltage.
This action is cancelled out when an appropriate NIV1161
is used on the opposite side of the data line to level−shift the
common−mode voltage back down to levels appropriate
for the reader. If a NIV1161 is not used on the opposite side
of the data line, the pull−up resistor may either not be
populated or populated with high value resistor (15 kW+);
differential data signal integrity is maintained.
Short−to−Battery (STB) Event
While the NIV1161 and data channel are off, one pair of
MOSFET body diodes passively protects the USB
transceiver ’s ports. While the data channel is on during an
event, the NIV1161 actively uses the internal MOSFETs to
clamp in a manner akin to level−shifting as the MOSFET
operates in the saturation region. The source node will
increase to a threshold voltage minus a working below the
gate voltage thus allowing current to flow into the data port
impedance until the gate−source voltage comes to rest just
above the threshold voltage. In this way, the NIV1161
protects the data port by limiting the termination current as
well as voltage clamping the data port itself.
PCB Layout Guidelines
It is optional to route both pins 4 & 6 to their respective
belly pads with a top metal trace as both pins are internally
connected respectively. Also, steps must be taken for
proper placement and signal trace routing of the ESD
protection device in order to ensure the maximum ESD
survivability and signal integrity for the application. Such
steps are listed below.
• Place the ESD protection device as close as possible to
the I/O connector to reduce the ESD path to ground
and improve the protection performance.
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6
NIV1161, NIS1161
PACKAGE DIMENSIONS
WDFN6 2x2, 0.65P
CASE 511CB
ISSUE O
D
PIN ONE
REFERENCE
0.10 C
0.10 C
ÉÉÉ
ÉÉ
ÇÇÇ
ÇÇÇ ÉÉ
ÉÉÉ
ÇÇÇÇÇ
EXPOSED Cu
A B
ÍÍ
ÍÍ
ÍÍ
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND 0.25
mm FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
MOLD CMPD
DETAIL B
E
ALTERNATE TERMINAL
CONSTRUCTIONS
L
DIM
A
A1
A3
b
b2
D
D2
E
E2
e
F
G
L
L1
L2
L
TOP VIEW
L1
DETAIL A
A3
DETAIL B
0.10 C
ALTERNATE
CONSTRUCTIONS
A
6X
0.08 C
A1
NOTE 4
C
SIDE VIEW
2X
DETAIL A
e
F
SEATING
PLANE
RECOMMENDED
MOUNTING FOOTPRINT
0.10 C A B
2X
1
D2
1.72
3
2X
0.65
PITCH
E2
0.48
L2
6
PACKAGE
OUTLINE
0.10 C A B
L
G
MILLIMETERS
MIN
MAX
0.70
0.80
0.00
0.05
0.20 REF
0.25
0.35
0.35
0.45
2.00 BSC
0.55
0.65
2.00 BSC
0.55
0.65
0.65 BSC
0.52 BSC
0.20 BSC
0.20
0.30
--0.15
0.55
0.65
0.80
4
b2
5X
BOTTOM VIEW
2.30
5X
b
0.10
M
C A
0.05
M
C
0.44
B
2X
0.67
0.54
5X
1
0.35
2X
0.67
DIMENSIONS: MILLIMETERS
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
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representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product
or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in
SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must
be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products
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NIV1161/D
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