ESMT M52D128324A-2E Lvcmos compatible with multiplexed address Datasheet

ESMT
M52D128324A (2E)
Mobile SDRAM
1M x 32Bit x 4Banks
Mobile Synchronous DRAM
FEATURES
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GENERAL DESCRIPTION
The M52D128324A is 134,217,728 bits synchronous high
data rate Dynamic RAM organized as 4 x 1,048,576 words
by 32 bits, fabricated with high performance CMOS
technology. Synchronous design allows precise cycle
control with the use of system clock I/O transactions are
possible on every clock cycle. Range of operating
frequencies, programmable burst length and programmable
latencies allow the same device to be useful for a variety of
high bandwidth, high performance memory system
applications.
1.8V power supply
LVCMOS compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
CAS Latency (2 & 3 )
Burst Length (1, 2, 4, 8 & full page)
Burst Type (Sequential & Interleave)
EMRS cycle with address key programs.
All inputs are sampled at the positive going edge of the
system clock
Burst Read Single-bit Write operation
Special Function Support
PASR (Partial Array Self Refresh )
TCSR (Temperature Compensated Self Refresh)
DS (Driver Strength)
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle)
ORDERING INFORMATION
Max
Freq.
Product ID
Package
Comments
M52D128324A -5BG2E
200MHz 90 Ball BGA
Pb-free
M52D128324A -6BG2E
166MHz 90 Ball BGA
Pb-free
M52D128324A -7BG2E
143MHz 90 Ball BGA
Pb-free
BALL CONFIGURATION (TOP VIEW)
(BGA90, 8mmX13mmX1.0mm Body, 0.8mm Ball Pitch)
1
2
3
4
5
6
7
8
9
A
DQ26 DQ24 VSS
VDD DQ23 DQ21
B
DQ28 VDDQ VSSQ
VDDQ VSSQ DQ19
C VSSQ DQ27 DQ25
DQ22 DQ20 VDDQ
D VSSQ DQ29 DQ30
DQ17 DQ18 VDDQ
E VDDQ DQ31
NC
NC
DQ16 VSSQ
F
A3
A2
DQM2 VDD
VSS DQM3
G
A4
A5
A6
A10
A0
A1
H
A7
A8
NC
NC
BA1
A11
J
CLK
CKE
A9
BA0
CS
RAS
NC
NC
CAS
WE
DQM0
VSS
VDD
DQ7 VSSQ
M VSSQ DQ10 DQ9
DQ6
DQ5 VDDQ
N VSSQ DQ12 DQ14
DQ1
DQ3 VDDQ
K DQM1
L VDDQ DQ8
P
DQ11 VDDQ VSSQ
R
DQ13 DQ15 VSS
Elite Semiconductor Memory Technology Inc.
VDDQ VSSQ DQ4
VDD
DQ0
DQ2
Publication Date : Aug. 2012
Revision : 1.0
1/31
ESMT
M52D128324A (2E)
FUNCTIONAL BLOCK DIAGRAM
Clock
CKE
Generator
Bank D
Bank C
Bank B
Row
Address
Buffer
&
Refresh
Counter
Address
Mode
Register
Row Decoder
CLK
Bank A
WE
Column Decoder
Data Control Circuit
Input & Output
Buffer
CAS
DQM0~3
Latch Circuit
RAS
Control Logic
CS
Command Decoder
Sense Amplifier
Column
Address
Buffer
&
Refresh
Counter
DQ
PIN FUNCTION DESCRIPTION
Pin
Name
Input Function
CLK
System Clock
CS
Chip Select
CKE
Clock Enable
A0 ~ A11
Address
BA0, BA1
Bank Select Address
RAS
Row Address Strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS
Column Address Strobe
WE
Write Enable
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
DQM0~3
Data Input / Output Mask
DQ0~31
VDD/VSS
Data Input / Output
Power Supply / Ground
Data Output Power /
Ground
No Connection
VDDQ/VSSQ
NC
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM.
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row / column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA11, column address : CA0 ~ CA7
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
Latches data in starting from CAS , WE active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved
noise immunity.
This pin is recommended to be left No Connection on the device.
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2012
Revision : 1.0
2/31
ESMT
M52D128324A (2E)
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Voltage on any pin relative to VSS
VIN,VOUT
-1.0 ~ 2.6
V
Voltage on VDD supply relative to VSS
VDD,VDDQ
-1.0 ~ 2.6
TA
0 ~ +70
V
℃
Operation ambient temperature
TSTG
-55 ~ + 150
℃
Power dissipation
PD
0.7
W
Short circuit current
IOS
50
mA
Storage temperature
Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V)
Parameter
Symbol
Min
Typ
Max
Unit
Note
VDD,VDDQ
1.7
1.8
1.95
V
1
Input logic high voltage
VIH
0.8 x VDDQ
1.8
VDDQ+0.3
V
2
Input logic low voltage
VIL
-0.3
0
0.3
V
3
Output logic high voltage
VOH
VDDQ - 0.2
-
-
V
IOH =-0.1mA
Output logic low voltage
VOL
-
-
0.2
V
IOL = 0.1mA
IIL
-2
-
2
uA
4
Supply voltage
Input leakage current
Note: 1. Under all conditions. VDDQ must be less than or equal to VDD.
2. VIH (max) = 2.2V AC. The overshoot voltage duration is ≤ 3ns.
3. VIL (min) = -1.0V AC. The undershoot voltage duration is ≤ 3ns.
4. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs.
CAPACITANCE (VDD = 1.8V, TA = 25℃, f = 1MHz)
Pin
Symbol
Min
Max
Unit
CLOCK
CCLK
2.0
4.0
pF
RAS , CAS , WE , CS , CKE, DQM0~3
CIN
2.0
4.0
pF
ADDRESS
CADD
2.0
4.0
pF
DQ0 ~DQ31
COUT
3.5
6.0
pF
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2012
Revision : 1.0
3/31
ESMT
M52D128324A (2E)
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted)
Parameter
Operating Current
(One Bank Active)
Precharge Standby
Current in power-down
mode
Precharge Standby
Current in non
power-down mode
Symbol
Version
Test Condition
-5
-6
-7
55
50
45
Unit Note
ICC1
Burst Length = 1
tRC ≥ tRC (min), tCC ≥ tCC (min), IOL= 0mA
ICC2P
CKE ≤ VIL(max), tCC =15ns
900
uA
ICC2PS
CKE ≤ VIL(max), CLK ≤ VIL(max), tCC = ∞
900
uA
10
mA
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
10
mA
CKE ≤ VIL(max), tCC =15ns
3
CKE ≤ VIL(max), CLK ≤ VIL(max), tCC = ∞
1
CKE ≥ VIH(min), CS ≥ VIH(min), tCC=15ns
Input signals are changed one time during 2clks
All other pins ≥ VDD-0.2V or ≤ 0.2V
20
mA
CKE ≥ VIH (min), CLK ≤ VIL(max), tCC= ∞
Input signals are stable
7
mA
ICC2N
ICC2NS
ICC3P
Active Standby Current
in power-down mode
ICC3PS
Active Standby Current ICC3N
in non power-down
mode
(One Bank Active)
ICC3NS
CKE ≥ VIH(min), CS ≥ VIH(min), tCC =15ns
Input signals are changed one time during 30ns
mA
1
mA
Operating Current
(Burst Mode)
ICC4
IOL= 0mA, Page Burst
All Bank Activated, tCCD = tCCD (min)
100
90
80
mA
1
Refresh Current
ICC5
tRFC ≥ tRFC(min)
70
65
60
mA
2
Self Refresh Current
Deep Power Down
Current
ICC6
ICC7
CKE ≤ 0.2V
TCSR range
45
85
Full array
950
1000
1/2 array
900
950
1/4 array
850
900
1/8 array
800
850
CKE ≤ 0.2V
10
°C
uA
uA
Note: 1. Measured with outputs open. Addresses are changed only one time during tCC(min).
2. Refresh period is 64ms. Addresses are changed only one time during tCC(min).
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2012
Revision : 1.0
4/31
ESMT
M52D128324A (2E)
AC OPERATING TEST CONDITIONS (VDD= 1.7V~1.95V)
Parameter
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
Unit
0.9 x VDDQ / 0.2
0.5 x VDDQ
tr / tf = 1 / 1
0.5 x VDDQ
See Fig.2
V
V
ns
V
1.8V
Vtt =0.5x VDDQ
13.9K
50
Output
VOH(DC) = VDDQ-0.2V, IOH = -0.1mA
VOL(DC) = 0.2V, IOL = 0.1mA
10.6K
Output
Z0=50
20 pF
20 pF
(Fig.2) AC Output Load Circuit
(Fig.1) DC Output Load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Version
Symbol
-5
-6
-7
Unit
Note
Row active to row active delay
tRRD(min)
10
12
14
ns
1
RAS to CAS delay
tRCD(min)
15
18
21
ns
1
Row precharge time
tRP(min)
tRAS(min)
tRAS(max)
15
40
18
42
100
21
42
ns
ns
us
1
1
-
@ Operating
tRC(min)
55
60
63
ns
1
@ Auto refresh
tRFC(min)
55
60
63
Row active time
Row cycle time
Last data in to new col. Address delay
Last data in to row precharge
Last data in to burst stop
Col. Address to col. Address delay
Mode Register command to Active or
Refresh command
Refresh period (4,096 rows)
Number of valid output data
Note:
1.
2.
3.
4.
5.
6.
ns
1,6
tCDL(min)
tRDL(min)
tBDL(min)
tCCD(min)
1
2
1
1
CLK
CLK
CLK
CLK
2
2
2
3
tMRD(min)
2
CLK
-
tREF(max)
CAS Latency=3
CAS Latency=2
64
2
1
ms
5
ea
4
The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
Minimum delay is required to complete write.
All parts allow every cycle column address change.
In case of row precharge interrupt, auto precharge and read burst stop.
The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks.
A maximum of eight consecutive AUTO REFRESH commands (with tRFCmin) can be posted to any given SDRAM, and
the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is
8x15.6 μ s.)
A new command may be given tRFC after self refresh exit.
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2012
Revision : 1.0
5/31
ESMT
M52D128324A (2E)
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter
CLK cycle time
CLK to valid
output delay
CAS Latency =3
CAS Latency =2
CAS Latency =3
CAS Latency =2
Symbol
tCC
-6
-5
Min
5
10
tSAC
Max
1000
Min
6
10
-7
Max
1000
Min
7
10
Max
1000
4.5
5
6
8
8
9
Unit
Note
ns
1
ns
1
Output data hold time
tOH
2
2
2.5
ns
2
CLK high pulse width
tCH
2
2
2.5
ns
3
CLK low pulse width
tCL
2
2
2.5
ns
3
Input setup time
tSS
1.5
1.5
2
ns
3
Input hold time
tSH
1
1
1.5
ns
3
CLK to output in Low-Z
tSLZ
1
1
1
ns
2
ns
-
CLK to output in
Hi-Z
CAS Latency =3
CAS Latency =2
tSHZ
4.5
5
6
8
8
9
*All AC parameters are measured from half to half.
Note: 1.Parameters depend on programmed CAS latency.
2.If clock rising time is longer than 1ns,(tr/2-0.5)ns should be added to the parameter.
3.Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr+ tf)/2-1]ns should be added to the
parameter.
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2012
Revision : 1.0
6/31
ESMT
M52D128324A (2E)
MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with MRS
Address
BA0~BA1
A11
A10/AP
A9
Function
0
RFU
RFU
W.B.L
Test Mode
A8
A7
A6
TM
CAS Latency
A5
A4
A3
CAS Latency
BT
Burst Type
A2
A1
A0
Burst Length
Burst Length
A8
A7
Type
A6
A5
A4
Latency
A3
Type
A2
A1
A0
BT = 0
BT = 1
0
0
Mode Register Set
0
0
0
Reserved
0
Sequential
0
0
0
1
1
0
1
Reserved
0
0
1
Reserved
1
Interleave
0
0
1
2
2
1
0
Reserved
0
1
0
2
0
1
0
4
4
1
1
Reserved
0
1
1
3
0
1
1
8
8
1
0
0
Reserved
1
0
0
Reserved Reserved
Write Burst Length
A9
Length
1
0
1
Reserved
1
0
1
Reserved Reserved
0
Burst
1
1
0
Reserved
1
1
0
Reserved Reserved
1
Single Bit
1
1
1
Reserved
1
1
1
Full Page Reserved
Full Page Length: 256
Note:
1. RFU (Reserved for future use) should stay “0” during MRS cycle.
2. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.
3. The full column burst (256 bit) is available only at sequential mode of burst type.
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2012
Revision : 1.0
7/31
ESMT
M52D128324A (2E)
Extended Mode Register
BA1 BA0
1
0
A11 ~ A8
0*
A7
A6 A5
DS
A4 A3
TCSR
A2
A1
A0
PASR
Address bus
Extended Mode Register Set
A2-0
000
001
010
PASR
011
100
101
110
111
Self Refresh Coverage
Full array
1/2 array (BA 1=0)
1/4 array
(BA0=BA1=0)
Reserved
Reserved
1/8 Array
(BA1 = BA0 = Row Addr MSB** =0)
Reserved
Reserved
Internal TCSR
DS
A7-5
000
001
010
011
100
101
110
111
Drive Strength
Full Strength
1/2 Strength
1/4 Strength
1/8 Strength
3/4 Strength
Reserved
Reserved
Reserved
Note: * BA0, A11~A8 should stay “0” during EMRS cycle.
** MSB: most significant bit.
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2012
Revision : 1.0
8/31
ESMT
M52D128324A (2E)
Burst Length and Sequence
(Burst of Two)
Starting Address
(column address A0 binary)
0
1
Sequential Addressing
Sequence (decimal)
0,1
1,0
Interleave Addressing
Sequence (decimal)
0,1
1,0
Sequential Addressing
Sequence (decimal)
0,1,2,3
1,2,3,0
2,3,0,1
3,0,1,2
Interleave Addressing
Sequence (decimal)
0,1,2,3
1,0,3,2
2,3,0,1
3,2,1,0
(Burst of Four)
Starting Address
(column address A1-A0, binary)
00
01
10
11
(Burst of Eight)
Starting Address
(column address A2-A0, binary)
000
001
010
0 11
100
101
11 0
111
Sequential Addressing
Sequence (decimal)
0,1,2,3,4,5,6,7
1,2,3,4,5,6,7,0
2,3,4,5,6,7,0,1
3,4,5,6,7,0,1,2
4,5,6,7,0,1,2,3
5,6,7,0,1,2,3,4
6,7,0,1,2,3,4,5
7,0,1,2,3,4,5,6
Interleave Addressing
Sequence (decimal)
0,1,2,3,4,5,6,7
1,0,3,2,5,4,7,6
2,3,0,1,6,7,4,5
3,2,1,0,7,6,5,4
4,5,6,7,0,1,2,3
5,4,7,6,1,0,3,2
6,7,4,5,2,3,0,1
7,6,5,4,3,2,1,0
Full page burst is an extension of the above tables of Sequential Addressing, with the length being 256 for 4Mx32 device.
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2012
Revision : 1.0
9/31
ESMT
M52D128324A (2E)
SIMPLIFIED TRUTH TABLE
COMMAND
CKEn-1 CKEn CS
Mode Register Set
Extended Mode Register
Set
Auto Refresh
Register
Entry
Refresh
Self Refresh
Exit
Bank Active & Row Addr.
Read &
Column Address
Auto Precharge Disable
Write & Column
Address
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Enable
Burst Stop
Precharge
Bank Selection
All Banks
Clock Suspend or
Active Power Down Mode
DQM BA0,1 A10/AP
A11
A9~A0
Note
L
L
L
L
X
OP CODE
1,2
H
X
L
L
L
L
X
OP CODE
1,2
L
L
L
H
X
X
3
H
X
L
H
X
H
H
X
H
X
3
3
X
V
H
L
H
X
V
H
H
L
L
H
H
X
L
H
L
H
X
L
X
H
X
L
H
L
L
X
H
X
L
H
H
L
X
X
H
L
Exit
L
H
Entry
H
L
Exit
L
H
Entry
Exit
H
H
H
H
L
Precharge Power Down Mode
Deep Power Down Mode
WE
X
Entry
No Operation Command
CAS
H
H
DQM
RAS
X
L
H
L
L
H
L
H
L
X
H
L
H
L
X
H
X
X
H
X
H
X
X
H
H
X
X
H
X
X
H
X
H
X
H
X
X
H
X
H
H
L
L
X
X
H
H
X
X
H
L
X
X
Row Address
L
H
L
V
V
X
X
3
H
X
L
H
Column
4
Address
(A0~A7) 4,5
Column
4
Address
(A0~A7) 4,5
X
6
4
4
X
X
X
X
X
V
X
X
X
X
X
X
7
(V= Valid, X= Don’t Care, H= Logic High, L = Logic Low)
Note:
1. OP Code: Operation Code
A0~A10/AP, A11, BA0~BA1: Program keys (@MRS). BA1 = 0 for MRS and BA1 = 1 for EMRS
2. MRS/EMRS can be issued only at all banks precharge state.
A new command can be issued after 2 clock cycles of MRS/EMRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
4.
5.
6.
7.
The automatical precharge without row precharge command is meant by “Auto”.
Auto / self refresh can be issued only at all banks idle state.
BA0~BA1: Bank select addresses.
If both BA1 and BA0 are “Low” at read, write, row active and precharge, bank A is selected.
If both BA1 is “Low” and BA0 is “High” at read, write, row active and precharge, bank B is selected.
If both BA1 is “High” and BA0 is “Low” at read, write, row active and precharge, bank C is selected.
If both BA1 and BA0 are “High” at read, write, row active and precharge, bank D is selected
If A10/AP is “High” at row precharge, BA1 and BA0 is ignored and all banks are selected.
During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read / write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
Burst stop command is valid at every burst length.
DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0), but
makes Hi-Z state the data-out of 2 CLK cycles after (Read DQM latency is 2).
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2012
Revision : 1.0
10/31
ESMT
M52D128324A (2E)
Single Bit Read-Write-Read Cycle (Same Page) @ CAS Latency=3, Burst Length=1
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2012
Revision : 1.0
11/31
ESMT
M52D128324A (2E)
Note: 1. All inputs expect CKE & DQM can be don’t care when CS is high at the CLK high going edge.
2. Bank active @ read/write are controlled by BA0~BA1.
BA1
BA0
Active & Read/Write
0
0
Bank A
0
1
Bank B
1
0
Bank C
1
1
Bank D
3. Enable and disable auto precharge function are controlled by A10/AP in read/write command
A10/AP
0
1
BA1
BA0
Operating
0
0
Disable auto precharge, leave A bank active at end of burst.
0
1
Disable auto precharge, leave B bank active at end of burst.
1
0
Disable auto precharge, leave C bank active at end of burst.
1
1
Disable auto precharge, leave D bank active at end of burst.
0
0
Enable auto precharge, precharge bank A at end of burst.
0
1
Enable auto precharge, precharge bank B at end of burst.
1
0
Enable auto precharge, precharge bank C at end of burst.
1
1
Enable auto precharge, precharge bank D at end of burst.
4. A10/AP and BA0~BA1 control bank precharge when precharge is asserted.
A10/AP
BA1
BA0
Precharge
0
0
0
Bank A
0
0
1
Bank B
0
1
0
Bank C
0
1
1
Bank D
1
X
X
All Banks
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2012
Revision : 1.0
12/31
ESMT
M52D128324A (2E)
Power Up Sequence
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CLOCK
CKE
High level is necessary
CS
tRFC
tRP
tRFC
tMRD
tMRD
RAS
CAS
ADDR
Key
Key
RA
BA1
BS
BA0
BS
A10 /AP
RA
DQ
High-Z
WE
DQM
High level is necessary
Precharge
Auto Refresh
Auto Refresh
Mode Register Set
(All Banks)
Row Active
Extended Mode
Register Set
: Don't care
Power-Up and Initialization Sequence
The following sequence is required for POWER UP and Initialization.
1. Apply power and attempt to maintain CKE at a low state (all other inputs may be undefined.)
Apply VDD before or at the same time as VDDQ
Apply VDDQ
2. Start clock and maintain stable condition for a minimum.
3. The minimum of 200us after stable power and clock (CLK), apply NOP & take CKE high.
4. Issue precharge commands for all banks of the device.
5. Issue 2 or more auto-refresh commands.
6. Issue mode register set command to initialize the mode register.
7. Issue extended mode register set command to set PASR and DS.
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2012
Revision : 1.0
13/31
ESMT
M52D128324A (2E)
Read & Write Cycle at Same Bank @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
*Note1
t RC
CS
tRCD
RAS
*Note2
CAS
ADDR
Ra
Rb
Ca
Cb
BA1
BA0
A10/AP
`
Rb
Ra
tOH
Qa0
CL=2
Qa1
t S AC
DQ
Qa2
Qa3
tOH
CL=3
Qa0
Qa1
Db0
tS H Z
Qa2
Db2
Db3
tRDL
Db0
Qa3
t S AC
Db1
*Note3
tS H Z
*Note3
Db1
Db2
Db3
tRDL
WE
DQM
Row Active
(A- Ban k)
Read
(A- Ban k)
Precharge
Row Active
W rite
Precharge
(A-Ban k)
(A- Bank)
(A- Bank)
(A-Bank)
: Don't care
Note: 1.Minimum row cycle times is required to complete internal DRAM operation.
2.Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row
precharge. Last valid output will be Hi-Z(tSHZ) after the clock.
3.Output will be Hi-Z after the end of burst.(1,2,4,8 bit burst)
Burst can’t end in Full Page Mode.
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2012
Revision : 1.0
14/31
ESMT
M52D128324A (2E)
Page Read & Write Cycle at Same Bank @ Burst Length=4
Note: 1.To write data before burst read ends, DQM should be asserted three cycles prior to write command to avoid bus
contention.
2.Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written.
3.DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst.
Input data after Row precharge cycle will be masked internally.
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2012
Revision : 1.0
15/31
ESMT
M52D128324A (2E)
Page Read Cycle at Different Bank @ Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
HIGH
*Note1
CS
RAS
*Note2
CAS
ADDR
RAa
RBb
RAa
RBb
CAa
RCc
CBb
RDd
CCc
CDd
BA1
BA0
A10 /AP
CL= 2
RCc
QAa0
RDd
Q A a 1 Q A a 2 Q B b 0 Q B b 1 Q B b 2 Q C c 0 Q C c 1 Q C c 2 QD d 0 QD d 1 Q D d 2
DQ
CL= 3
Q A a 0 Q A a 1 Q A a 2 Q B b 0 Q B b 1 Q B b 2 Q C c 0 Q C c 1 Q C c 2 QD d 0 Q D d 1 QD d 2
WE
DQM
Row Act ive
( A-B ank )
Read
(B -Bank )
Read
(A -Bank )
Row Active
( B-B ank )
Row Act ive
(C -B an k)
Read
( C- Bank )
Row Act ive
( D- Bank )
Pre charg e
(A- Ban k)
Read
( D- Bank )
Pre charg e
(D -B an k)
Pre charg e
(C -B an k)
Pre charg e
(B- Ban k)
:Don't Care
Note: 1. CS can be don’t cared when RAS , CAS and WE are high at the clock high going edge.
2.To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2012
Revision : 1.0
16/31
ESMT
M52D128324A (2E)
Page Write Cycle at Different Bank @ Burst Length = 4
Note: 1.To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.
2.To interrupt burst write by Row precharge, both the write and the precharge banks must be the same.
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2012
Revision : 1.0
17/31
ESMT
M52D128324A (2E)
Read & Write Cycle at Different Bank @ Burst Length = 4
Note: 1.tCDL should be met to complete write.
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2012
Revision : 1.0
18/31
ESMT
M52D128324A (2E)
Read & Write Cycle with Auto Precharge @ Burst Length =4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
CAS
ADDR
Ra
Rb
Ra
Rb
Ca
Cb
BA0
BA1
A10 /AP
QAa0 QAa1 QAa2 QAa3
CL =2
DD b0 Ddb1 DD b2 DD d3
DQ
CL =3
QAa0 QAa1 QAa2 QAa3
DD b0 Ddb1 DD b2 DD d3
WE
DQM
Row Active
( A - Bank )
Read with
Auto Precharge
( A - Bank )
Auto Pr echar ge
Star t Poin t
W rite with
Auto Pr echar ge
( D- B an k )
Auto Pr echar ge
Star t Poin t
(D- Ban k )
Row Active
( D - Bank )
:D on' t Ca re
Note: 1.tCDL should be controlled to meet minimum tRAS before internal precharge start
(In the case of Burst Length=1 & 2)
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2012
Revision : 1.0
19/31
ESMT
M52D128324A (2E)
Clock Suspension & DQM Operation Cycle @ CAS Latency=2, Burst Length=4
Note:
1. DQM is needed to prevent bus contention.
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2012
Revision : 1.0
20/31
ESMT
M52D128324A (2E)
Read Interrupted by Precharge Command & Read Burst Stop Cycle @ Burst Length =Full page
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
CAS
ADDR
RAa
CAa
CAb
*Note1
*Note 1
BA1
BA0
A10 /AP
RAa
*Note2
CL=2
1
1
QAa0 QAa1 QAa2 QAa3 QAa4
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
DQ
CL= 3
2
2
QAa0 QAa1 QAa2 QAa3 QAa4
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
WE
DQM
Row Active
( A- B an k )
Read
(A- Ban k)
Burst Stop
Read
(A- Ban k)
Precharge
( A- Ban k )
:Don't Care
Note: 1.Burst can’t end in full page mode, so auto precharge can’t issue.
2.About the valid DQs after burst stop, it is same as the case of RAS interrupt.
Both cases are illustrated above timing diagram. See the label 1, 2 on them.
But at burst write, burst stop and RAS interrupt should be compared carefully.
Refer the timing diagram of “Full page write burst stop cycle”.
3.Burst stop is valid at every burst length.
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2012
Revision : 1.0
21/31
ESMT
M52D128324A (2E)
Write Interrupted by Precharge Command & Write Burst stop Cycle @ Burst Length =Full page
Note:
1. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined
by AC parameter of tRDL.
DQM at write interrupted by precharge command is needed to prevent invalid write.
DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst.
Input data after Row precharge cycle will be masked internally.
2. Burst stop is valid at every burst length.
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2012
Revision : 1.0
22/31
ESMT
M52D128324A (2E)
Burst Read Single bit Write Cycle @ Burst Length=2
CLOCK
*Note1
HIGH
CKE
CS
RAS
*Note2
CAS
RAa
ADDR
CAa
RBb
CAb
CBc
RAc
CAd
BA
A10 /AP
RAa
RAc
RBb
CL=2
DAa0
CL= 3
DAa0
QAb0 QAb1
QAd0 QAd1
DBc0
DQ
QAb0 QAb1
QAd0 QAd1
DBc0
WE
DQM
Row Active
( A- B an k )
Row Active
(B-Bank)
W rite
(A- Ban k)
Read with
Auto Precharge
(A-Bank)
Read
( A- B an k )
Row Act ive
( A- B an k )
Precharge
( A- B an k )
W rite with
Auto Pr echarge
( B- Bank )
:Don't Care
Note: 1. BRSW modes is enabled by setting A9 “High” at MRS (Mode Register Set).
At the BRSW Mode, the burst length at write is fixed to “1” regardless of programmed burst length.
2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated.
Auto precharge is executed at the next cycle of burst-end, so in the case of BRSW write command, the precharge
command will be issued after two clock cycles.
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2012
Revision : 1.0
23/31
ESMT
M52D128324A (2E)
Active/Precharge Power Down Mode @ CAS Latency=2, Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
*Note2
tSS
tSS
*Note1
tSS
CKE
*Note3
CS
RAS
CAS
ADDR
Ra
Ca
BA1
BA0
A10 /AP
Ra
tSHZ
DQ
Q a0
Qa1
Qa2
WE
DQM
Pr ech ar ge
Pow er - D own
Entry
Row Active
Pr ech arge
Power - Down
Exi t
Active
Power - dow n
Entry
Read
Precharge
Active
Power - down
Exi t
: Don't care
Note: 1. All banks should be in idle state prior to entering precharge power down mode.
2. CKE should be set high at least 1CLK+tss prior to Row active command.
3. Can not violate minimum refresh specification. (64ms)
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2012
Revision : 1.0
24/31
ESMT
M52D128324A (2E)
Deep Power Down Mode Entry & Exit Cycle
Note:
DEFINITION OF DEEP POWER MODE FOR Mobile SDRAM:
Deep Power Down Mode is an operating mode to achieve maximum power reduction by cutting the power of the whole memory
of the device. Once the device enters in Deep Power Down Mode, data will not be retained. Full initialization is required when
the device exits from Deep Power Down Mode.
TO ENTER DEEP POWER DOWN MODE
1) The deep power down mode is entered by having CS and WE held low with RAS and CAS high at the rising edge of
the clock. While CKE is low.
2) Clock must be stable before exited deep power down mode.
3) Device must be in the all banks idle state prior to entering Deep Power Down mode.
TO EXIT DEEP POWER DOWN MODE
4) The deep power down mode is exited by asserting CKE high.
5) 200μs wait time is required to exit from Deep Power Down.
6) Upon exiting deep power down an all bank precharge command must be issued followed by two auto refresh commands
and a load mode register sequence.
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2012
Revision : 1.0
25/31
ESMT
M52D128324A (2E)
Self Refresh Entry & Exit Cycle
Note: TO ENTER SELF REFRESH MODE
1. CS , RAS & CAS with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE.
3. The device remains in self refresh mode as long as CKE stays “Low”.
cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System clock restart and be stable before returning CKE high.
5. CS Starts from high.
6. Minimum tRFC is required after CKE going high to complete self refresh exit.
7. 4K cycles of burst auto refresh is required immediately before self refresh entry and immediately after self refresh exit.
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2012
Revision : 1.0
26/31
ESMT
M52D128324A (2E)
Mode Register Set Cycle
0
1
2
3
Auto Refresh Cycle
4
5
6
0
1
2
3
4
5
6
7
8
9
10
CLOCK
HIGH
CKE
HIGH
CS
*Note2
tRFC
RAS
*Note1
CAS
*Note3
ADDR
Key
Ra
BA0
BS
BA1
BS
DQ
Hi-Z
Hi-Z
WE
DQM
MRS
New Comm and
Auto Refresh
New Command
:Don't Care
* All banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
MODE REGISTER SET CYCLE
*Note: 1. CS , RAS , CAS & WE activation at the same clock cycle with address key will set internal mode register.
2.Minimum 2 clock cycles should be met before new RAS activation.
3.Please refer to Mode Register Set table.
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2012
Revision : 1.0
27/31
ESMT
M52D128324A (2E)
Extended Mode Register Set Cycle
0
1
2
3
4
5
6
CLOCK
HIGH
CKE
CS
*Note2
RAS
*Note1
CAS
*Note3
ADDR
Key
Ra
BA0
BS
BA1
BS
DQ
Hi-Z
WE
DQM
EMRS
New Command
:Don't Care
*All banks precharge should be completed before Extended Mode Register Set cycle.
EXTENDED MODE REGISTER SET CYCLE
*Note: 1. CS , RAS , CAS & WE activation at the same clock cycle with address key will set internal mode register.
2.Minimum 2 clock cycles should be met before new RAS activation.
3.Please refer to Mode Register Set table.
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2012
Revision : 1.0
28/31
ESMT
PACKING
90-BALL
M52D128324A (2E)
DIMENSIONS
SDRAM ( 8x13 mm )
Symbol
A
A1
A2
øb
D
E
D1
E1
e
Dimension in mm
Min
Norm
Max
______
______
1.00
0.30
0.35
0.40
______
______
0.586
0.40
0.45
0.50
7.90
8.00
8.10
12.90
13.00
13.10
______
______
6.40
______
______
11.20
______
______
0.80
Dimension in inch
Min
Norm
Max
______
______
0.039
0.012
0.014
0.016
______
______
0.023
0.016
0.018
0.020
0.311
0.315
0.319
0.508
0.512
0.516
______
______
0.252
______
______
0.441
______
______
0.031
Controlling dimension : Millimeter.
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2012
Revision : 1.0
29/31
ESMT
M52D128324A (2E)
Revision History
Revision
Date
0.1
2010.01.26
Original
0.2
2010.05.11
Add package description into ball configuration
2012.08.24
1. Delete "Preliminary"
2. Add speed grade -6 and delete speed grade -10
3. Correct the specification of tRC and tRFC for speed
grade -5
4. Add the specification of tMRD
5. Correct EMRS and Power Up Sequence
6. Correct A(max) of packing dimension
7. Correct typo and figures
8. Modify the specification of ICC1, ICC2P,ICC2PS,ICC4,ICC6 for
speed grade -5/-7
1.0
Elite Semiconductor Memory Technology Inc.
Description
Publication Date : Aug. 2012
Revision : 1.0
30/31
ESMT
M52D128324A (2E)
Important Notice
All rights reserved.
No part of this document may be reproduced or duplicated in any form or by
any means without the prior permission of ESMT.
The contents contained in this document are believed to be accurate at the
time of publication. ESMT assumes no responsibility for any error in this
document, and reserves the right to change the products or specification in
this document without notice.
The information contained herein is presented only as a guide or examples
for the application of our products. No responsibility is assumed by ESMT for
any infringement of patents, copyrights, or other intellectual property rights of
third parties which may result from its use. No license, either express ,
implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of ESMT or others.
Any semiconductor devices may have inherently a certain rate of failure. To
minimize risks associated with customer's application, adequate design and
operating safeguards against injury, damage, or loss from such failure,
should be provided by the customer when making application designs.
ESMT's products are not authorized for use in critical applications such as,
but not limited to, life support devices or system, where failure or abnormal
operation may directly affect human lives or cause physical injury or property
damage. If products described here are to be used for such kinds of
application, purchaser must do its own quality assurance testing appropriate
to such applications.
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2012
Revision : 1.0
31/31