ON NTMFS08N004C N-channel shielded gate powertrench mosfet Datasheet

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NTMFS08N004C
N-Channel Shielded Gate PowerTrench® MOSFET
80 V, 126 A, 4.0 mΩ
Features
General Description
„ Shielded Gate MOSFET Technology
This N-Channel MV MOSFET is produced using ON
Semiconductor’s advanced PowerTrench® process that
incorporates Shielded Gate technology. This process has been
optimized to minimise on-state resistance and yet maintain
superior switching performance with best in class soft body
diode.
„ Max rDS(on) = 4.0 mΩ at VGS = 10 V, ID = 44 A
„ Max rDS(on) = 10.4 mΩ at VGS = 6 V, ID = 22 A
„ 50% Lower Qrr than Other MOSFET Suppliers
„ Lowers Switching Noise/EMI
Applications
„ MSL1 Robust Package Design
„ 100% UIL Tested
„ Primary DC-DC MOSFET
„ RoHS Compliant
„ Synchronous Rectifier in DC-DC and AC-DC
„ Motor Drive
„ Solar
D
G
S
S
D
D
Pin 1
S
Top
D
D
5
4
G
D
6
3
S
D
7
2
S
D
8
1
S
Bottom
Power 56
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted.
Symbol
VDS
Drain to Source Voltage
Parameter
VGS
Gate to Source Voltage
Drain Current -Continuous
ID
TC = 25 °C
-Continuous
TC = 100 °C
-Continuous
TA = 25 °C
-Pulsed
EAS
PD
TJ, TSTG
Single Pulse Avalanche Energy
Power Dissipation
TC = 25 °C
Power Dissipation
TA = 25 °C
Ratings
80
Units
V
±20
V
(Note 5)
126
(Note 5)
80
(Note 1a)
18
(Note 4)
637
(Note 3)
486
125
(Note 1a)
Operating and Storage Junction Temperature Range
2.5
-55 to +150
A
mJ
W
°C
Thermal Characteristics
RθJC
Thermal Resistance, Junction to Case
RθJA
Thermal Resistance, Junction to Ambient
1.0
(Note 1a)
50
°C/W
Package Marking and Ordering Information
Device Marking
NTMFS08N004C
Device
NTMFS08N004C
Package
Power 56
Semiconductor Components Industries, LLC, 2017
March, 2017, Rev. 1.0
Reel Size
13 ’’
Tape Width
12 mm
Quantity
3000 units
Publication Order Number:
NTMFS08N004C/D
1
NTMFS08N004C N-Channel Shielded Gate PowerTrench® MOSFET
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Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Units
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
ID = 250 μA, VGS = 0 V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
ID = 250 μA, referenced to 25 °C
IDSS
Zero Gate Voltage Drain Current
VDS = 64 V, VGS = 0 V
1
μA
IGSS
Gate to Source Leakage Current
VGS = ±20 V, VDS = 0 V
±100
nA
4.0
V
80
V
40
mV/°C
On Characteristics
VGS(th)
Gate to Source Threshold Voltage
VGS = VDS, ID = 250 μA
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID = 250 μA, referenced to 25 °C
VGS = 10 V, ID = 44 A
3.4
4.0
rDS(on)
Static Drain to Source On Resistance
VGS = 6 V, ID = 22 A
5.2
10.4
VGS = 10 V, ID = 44 A, TJ = 125 °C
5.8
6.5
VDS = 5 V, ID = 44 A
98
gFS
Forward Transconductance
2.0
3.1
-8.3
mV/°C
mΩ
S
Dynamic Characteristics
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
Rg
Gate Resistance
VDS = 40 V, VGS = 0 V,
f = 1 MHz
0.1
3035
4250
940
1315
pF
pF
27
40
pF
1.1
2.3
Ω
17
30
ns
6
12
ns
25
40
ns
4
10
ns
39
55
nC
25
34
Switching Characteristics
td(on)
Turn-On Delay Time
tr
Rise Time
td(off)
Turn-Off Delay Time
tf
Fall Time
VDD = 40 V, ID = 44 A,
VGS = 10 V, RGEN = 6 Ω
Qg
Total Gate Charge
VGS = 0 V to 10 V
Qg
Total Gate Charge
VGS = 0 V to 6 V
Qgs
Gate to Source Charge
Qgd
Gate to Drain “Miller” Charge
Qoss
Output Charge
VDD = 40 V, VGS = 0 V
55
nC
Qsync
Total Gate Charge Sync.
VDS = 0 V, ID = 44 A
35
nC
VDD = 40 V,
ID = 44 A
nC
13
nC
7
nC
Drain-Source Diode Characteristics
VSD
Source to Drain Diode Forward Voltage
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
VGS = 0 V, IS = 2.1 A
(Note 2)
0.7
1.2
VGS = 0 V, IS = 44 A
(Note 2)
0.8
1.3
IF = 22 A, di/dt = 300 A/μs
IF = 22 A, di/dt = 1000 A/μs
V
26
41
ns
48
76
nC
19
31
ns
108
174
nC
Notes:
1. RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθCA is determined by the user's board design.
50 °C/W when mounted on a
1 in2 pad of 2 oz copper
125 °C/W when mounted on a
minimum pad of 2 oz copper.
SS
SF
DS
DF
G
SS
SF
DS
DF
G
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.
3. EAS of 486 mJ is based on starting TJ = 25 °C; N-ch: L = 3 mH, IAS = 18 A, VDD = 80 V, VGS =10 V. 100% test at L = 0.1 mH, IAS = 57 A.
4. Pulsed Id please refer to Fig 11 SOA graph for more details.
5. Computed continuous current limited to Max Junction Temperature only, actual continuous current will be limited by thermal & electro-mechanical application board design.
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2
NTMFS08N004C N-Channel Shielded Gate PowerTrench® MOSFET
Electrical Characteristics TJ = 25 °C unless otherwise noted.
VGS = 10 V
250
VGS = 8 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
200
150
VGS = 6 V
100
VGS = 5.5 V
50
0
VGS = 5 V
0
1
2
3
4
5
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
ID, DRAIN CURRENT (A)
300
VGS = 5 V
4
VGS = 5.5 V
3
VGS = 6 V
2
VGS = 8 V
1
0
5
0
50
VDS, DRAIN TO SOURCE VOLTAGE (V)
200
250
300
25
ID = 44 A
VGS = 10 V
1.8
rDS(on), DRAIN TO
1.6
1.4
1.2
1.0
0.8
0.6
-75
-50
SOURCE ON-RESISTANCE (mΩ)
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
150
Figure 2. Normalized On-Resistance
vs. Drain Current and Gate Voltage
2.0
300
IS, REVERSE DRAIN CURRENT (A)
180
TJ = 150 oC
TJ = 25 oC
60
TJ = -55 oC
3
4
5
6
7
8
ID = 44 A
15
10
TJ = 125 oC
5
TJ = 25 oC
4
5
6
7
8
9
10
Figure 4. On-Resistance vs. Gate to
Source Voltage
VDS = 5 V
120
20
VGS, GATE TO SOURCE VOLTAGE (V)
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
240
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
0
-25
0
25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (oC)
Figure 3. Normalized On Resistance
vs. Junction Temperature
ID, DRAIN CURRENT (A)
100
ID, DRAIN CURRENT (A)
Figure 1. On Region Characteristics
0
VGS = 10 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
300
100
VGS = 0 V
10
TJ = 150 oC
1
TJ = 25 oC
0.1
0.01
TJ = -55 oC
0.001
0.0
9
0.2
0.4
0.6
0.8
1.0
VGS, GATE TO SOURCE VOLTAGE (V)
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics
Figure 6. Source to Drain Diode
Forward Voltage vs. Source Current
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3
1.2
NTMFS08N004C N-Channel Shielded Gate PowerTrench® MOSFET
Typical Characteristics TJ = 25 °C unless otherwise noted.
10000
Ciss
ID = 44 A
VDD = 30 V
8
CAPACITANCE (pF)
VGS, GATE TO SOURCE VOLTAGE (V)
10
VDD = 40 V
6
VDD = 50 V
4
1000
2
0
Coss
100
Crss
10
f = 1 MHz
VGS = 0 V
0
8
16
24
32
1
0.1
40
1
10
80
VDS, DRAIN TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics
Figure 8. Capacitance vs. Drain
to Source Voltage
150
100
ID, DRAIN CURRENT (A)
IAS, AVALANCHE CURRENT (A)
o
TJ = 25 oC
10
TJ = 100 oC
TJ = 125 oC
RθJC = 1.0 C/W
125
100
VGS = 10 V
75
50
VGS = 6 V
25
1
0.001
0.01
0.1
1
10
100
0
25
1000
50
P(PK), PEAK TRANSIENT POWER (W)
ID, DRAIN CURRENT (A)
150
100000
10 μs
100
THIS AREA IS
LIMITED BY rDS(on)
100 μs
SINGLE PULSE
TJ = MAX RATED
1 ms
RθJC = 1.0 oC/W
0.1
0.1
125
Figure 10. Maximum Continuous Drain
Current vs Case Temperature
1000
1
100
TC, CASE TEMPERATURE ( C)
Figure 9. Unclamped Inductive
Switching Capability
10
75
o
tAV, TIME IN AVALANCHE (ms)
TC = 25 oC
1
CURVE BENT TO
MEASURED DATA
10
TC = 25 oC
10000
10 ms
100 ms/DC
100
SINGLE PULSE
RθJC = 1.0 oC/W
1000
500
100
10
-5
10
-4
10
-3
10
-2
10
-1
10
t, PULSE WIDTH (sec)
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 11. Forward Bias Safe
Operating Area
Figure 12. Single Pulse Maximum
Power Dissipation
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4
1
NTMFS08N004C N-Channel Shielded Gate PowerTrench® MOSFET
Typical Characteristics TJ = 25 °C unless otherwise noted.
r(t), NORMALIZED EFFECTIVE TRANSIENT
THERMAL RESISTANCE
2
1
0.1
DUTY CYCLE-DESCENDING ORDER
D = 0.5
0.2
0.1
0.05
0.02
0.01
PDM
t1
t2
0.01
0.001
-5
10
NOTES:
SINGLE PULSE
-4
10
ZθJC(t) = r(t) x RθJC
RθJC = 1.0 oC/W
Peak TJ = PDM x ZθJC(t) + TC
Duty Cycle, D = t1 / t2
-3
-2
10
10
Figure 13. Junction-to-Case Transient Thermal Response Curve
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5
-1
10
t, RECTANGULAR PULSE DURATION (sec)
1
NTMFS08N004C N-Channel Shielded Gate PowerTrench® MOSFET
Typical Characteristics TJ = 25 °C unless otherwise noted.
PQFN8 5X6, 1.27P
CASE 483AE
ISSUE A
5.10
PKG
CL
8
5.10
3.91
A
SEE
DETAIL B
B
5
1.27
8
7
6
5
0.77
4.52
PKG CL
5.85
5.65
6.15
3.75
6.61
KEEP OUT
AREA
1.27
1
4
1
TOP VIEW
2
3
4
0.61
1.27
3.81
OPTIONAL DRAFT
ANGLE MAY APPEAR
ON FOUR SIDES
OF THE PACKAGE
SEE
DETAIL C
5.00
4.80
LAND PATTERN
RECOMMENDATION
0.35
0.15
0.10 C
0.05
0.00
SIDE VIEW
8X
0.08 C
5.20
4.80
1.10
0.90
3.81
0.35
0.15
DETAIL C
SCALE: 2:1
1.27
0.51 (8X)
0.31
(0.34)
0.10
1
2
3
C A B
4
0.76
0.51
(0.52)
6.25
5.90
3.48+0.30
-0.10
(0.50)
(0.30)
(2X)
8
0.20+0.10
-0.15 (8X)
7
6
3.96
3.61
BOTTOM VIEW
0.30
0.05
5
C
SEATING
PLANE
DETAIL B
SCALE: 2:1
NOTES: UNLESS OTHERWISE SPECIFIED
A. PACKAGE STANDARD REFERENCE: JEDEC MO-240,
ISSUE A, VAR. AA,.
B. DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH.
MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM.
C. ALL DIMENSIONS ARE IN MILLIMETERS.
D. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-2009.
E. IT IS RECOMMENDED TO HAVE NO TRACES OR
VIAS WITHIN THE KEEP OUT AREA.
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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