TI1 OPA2316SIDGS 10-mhz, low-power, low-noise, rrio, 1.8-v cmos operational amplifier Datasheet

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OPA316, OPA2316, OPA2316S, OPA4316
SBOS703E – APRIL 2014 – REVISED JUNE 2016
OPAx316 10-MHz, Low-Power, Low-Noise, RRIO, 1.8-V CMOS Operational Amplifier
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
The OPA316 family of single, dual, and quad
operational amplifiers represents a new generation of
general-purpose, low-power operational amplifiers.
Featuring rail-to-rail input and output swings, low
quiescent current (400 μA/ch typical) combined with a
wide bandwidth of 10 MHz and very-low noise
(11 nV/√Hz at 1 kHz) makes this family attractive for
a variety of applications that require a good balance
between cost and performance. The low input bias
current supports those operational amplifiers to be
used in applications with MΩ source impedances.
1
Unity-Gain Bandwidth: 10 MHz
Low IQ: 400 µA/ch
Wide Supply Range: 1.8 V to 5.5 V
Low Noise: 11 nV/√Hz at 1 kHz
Low Input Bias Current: ±5 pA
Offset Voltage: ±0.5 mV
Unity-Gain Stable
Internal RFI-EMI Filter
Shutdown Version: OPA2316S
Extended Temperature Range: –40°C to +125°C
2 Applications
•
•
•
•
•
•
Battery-Powered Instruments:
– Consumer, Industrial, Medical
– Notebooks, Portable Media Players
Sensor Signal Conditioning
Automotive Applications
Barcode Scanners
Active Filters
Audio
The robust design of the OPA316 devices provide
ease-of-use to the circuit designer—a unity-gain
stable, integrated RFI-EMI rejection filter, no phase
reversal in overdrive condition, and high electrostatic
discharge (ESD) protection (4-kV HBM).
These devices are optimized for low-voltage
operation as low as 1.8 V (±0.9 V) and up to 5.5 V
(±2.75 V). This latest addition of low-voltage CMOS
operational amplifiers, in conjunction with the
OPAx313 and OPAx314 provide a family of
bandwidth, noise, and power options to meet the
needs of a wide variety of applications.
Device Information(1)
PART NUMBER
OPA316
OPA2316
PACKAGE
BODY SIZE (NOM)
SC-70 (5)
1.25 mm × 2.00 mm
SOT-23 (5)
1.60 mm × 2.90 mm
DFN (8)
3.00 mm × 3.00 mm
MSOP, VSSOP (8)
3.00 mm × 3.00 mm
SOIC (8)
3.91 mm × 4.90 mm
MSOP, VSSOP (10) 3.00 mm × 3.00 mm
OPA2316S
OPA4316
X2QFN (10)
1.50 mm × 2.00 mm
TSSOP (14)
4.40 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
SPACE
Single-Pole, Low-Pass Filter
Low Supply Current (400 µA/ch) for 10-MHz Bandwidth
RF
VOUT
VIN
C1
1
f-3 dB =
2pR1C1
120
270
100
225
80
180
60
135
Phase
40
90
20
45
VS
= “2.75 V
V
S = “2.75 V
0
(
RF
VOUT
= 1+
RG
VIN
((
1
1 + sR1C1
(
Phase (º)
R1
Gain (dB)
RG
0
Gain
VS
= “0.9
“0.9 VV
V
S =
±20
1
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
-45
100M
C006
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA316, OPA2316, OPA2316S, OPA4316
SBOS703E – APRIL 2014 – REVISED JUNE 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
7
1
1
1
2
3
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information: OPA316 .................................. 5
Thermal Information: OPA2316 ................................ 6
Thermal Information: OPA2316S.............................. 6
Thermal Information: OPA4316 ................................ 7
Electrical Characteristics........................................... 8
Typical Characteristics ............................................ 10
Detailed Description ............................................ 16
7.1 Overview ................................................................. 16
7.2 Functional Block Diagram ....................................... 16
7.3 Feature Description................................................. 16
7.4 Device Functional Modes........................................ 19
8
Application and Implementation ........................ 20
8.1 Application Information............................................ 20
8.2 Typical Application .................................................. 21
9 Power Supply Recommendations...................... 24
10 Layout................................................................... 25
10.1 Layout Guidelines ................................................. 25
10.2 Layout Example .................................................... 25
11 Device and Documentation Support ................. 26
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
26
26
12 Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (December 2014) to Revision E
•
Page
Added new "RUG" package ................................................................................................................................................... 1
Changes from Revision C (October 2014) to Revision D
Page
•
Added Shutdown section to Electrical Characteristics table ................................................................................................. 9
•
Added Related Documentation section ............................................................................................................................... 26
Changes from Revision B (August 2014) to Revision C
Page
•
Updated devices and packages in Device Information table ................................................................................................ 1
•
Added thermal information for OPA2316S and OPA4316 ..................................................................................................... 6
Changes from Revision A (April 2014) to Revision B
Page
•
Added OPA2316 to the Device Information table................................................................................................................... 1
•
Added thermal information for OPA2316 .............................................................................................................................. 6
•
Added channel separation to Electrical Characteristics ........................................................................................................ 8
•
Added GBP instead of UGB in the Electrical Characteristics ................................................................................................ 8
•
Added Channel Separation vs Frequency plot..................................................................................................................... 15
Changes from Original (April 2014) to Revision A
•
2
Page
Changed status from preview to production .......................................................................................................................... 1
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Product Folder Links: OPA316 OPA2316 OPA2316S OPA4316
OPA316, OPA2316, OPA2316S, OPA4316
www.ti.com
SBOS703E – APRIL 2014 – REVISED JUNE 2016
5 Pin Configuration and Functions
DCK Package
SC70-5
(Top View)
+IN
1
V-
2
-IN
3
DGS Package
MSOP-10
(Top View)
V+
5
OUT A
1
–IN A
2
10 V+
9
OUT B
8
–IN B
A
OUT
4
+IN A
3
B
DBV Package
SOT23-5
(Top View)
OUT
1
V-
2
+IN
3
5
V+
4
-IN
V–
4
7
+IN B
SHDN A
5
6
SHDN B
RUG Package
QFN-10
(Top View)
+IN A
10
DRG Package
DFN-8
(Top View)
OUT A
1
-IN A
2
+IN A
3
V-
4
Exposed
Thermal
Die Pad
on
Underside(2)
V±
1
9
±IN A
SHDN A
2
8
OUT A
SHDN B
3
7
V+
+IN B
4
6
OUT B
(1)
8
V+
7
OUT B
6
-IN B
5
+IN B
5
Pitch: 0.5 mm.
±IN B
Connect thermal pad to V–. Pad size: 2.00 mm × 1.20 mm.
PW Package
TSSOP-14
(Top View)
D, DGK Packages
SO-8, MSOP-8
(Top View)
OUT A
1
8
V+
OUT A
1
A
D
14
OUT D
13
-IN D
-IN A
2
7
OUT B
-IN A
2
+IN A
3
6
-IN B
+IN A
3
12
+IN D
V-
4
5
+IN B
V+
4
11
V-
+IN B
5
10
+IN C
-IN B
6
9
-IN C
OUT B
7
8
OUT C
Copyright © 2014–2016, Texas Instruments Incorporated
B
C
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OPA316, OPA2316, OPA2316S, OPA4316
SBOS703E – APRIL 2014 – REVISED JUNE 2016
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Pin Functions
PIN
NAME
OPA316
OPA2316
OPA2316S
OPA4316
DESCRIPTION
DBV
DCK
D, DGK, DRG
DGS
RUG
PW
+IN
3
1
—
—
—
—
Noninverting input
+IN A
—
—
3
3
10
3
Noninverting input
+IN B
—
—
5
7
4
5
Noninverting input
+IN C
—
—
—
—
—
10
Noninverting input
+IN D
—
—
—
—
—
12
Noninverting input
–IN
4
3
—
—
—
—
Inverting input
–IN A
—
—
2
2
9
2
Inverting input
–IN B
—
—
6
8
5
6
Inverting input
–IN C
—
—
—
—
—
9
Inverting input
–IN D
—
—
—
—
—
13
Inverting input
OUT
1
4
—
—
—
—
Output
OUT A
—
—
1
1
8
1
Output
OUT B
—
—
7
9
6
7
Output
OUT C
—
—
—
—
—
8
Output
OUT D
—
—
—
—
—
14
Output
SHDN A
—
—
—
5
2
—
Shutdown (logic low), enable (logic high)
SHDN B
—
—
—
6
3
—
Shutdown (logic low), enable (logic high)
V+
5
5
8
10
7
4
Positive supply
V–
2
2
4
4
1
11
Negative supply or ground (for single-supply
operation)
4
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Product Folder Links: OPA316 OPA2316 OPA2316S OPA4316
OPA316, OPA2316, OPA2316S, OPA4316
www.ti.com
SBOS703E – APRIL 2014 – REVISED JUNE 2016
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted) (1)
MIN
MAX
UNIT
7
V
(V+) + 0.5
V
Supply voltage
Signal input pins
Common-mode
Voltage (2)
(V–) – 0.5
Differential
Current (2)
Operating temperature
TJ
Junction temperature
Tstg
Storage temperature
(3)
mA
Continuous
TA
(2)
V
10
–10
Output short-circuit (3)
(1)
(V+) – (V–) + 0.2
–55
–65
150
°C
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input pins are diode-clamped to the power-supply rails. Current limit input signals that can swing more than 0.5 V beyond the supply
rails to 10 mA or less.
Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
over operating free-air temperature range (unless otherwise noted)
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VS
MAX
UNIT
Supply voltage
1.8
5.5
V
Specified temperature
–40
125
°C
6.4 Thermal Information: OPA316
OPA316
THERMAL METRIC (1)
SOT23 (DBV)
SC70 (DCK)
5 PINS
5 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance (2)
221.7
263.3
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance (3)
144.7
75.5
°C/W
RθJB
Junction-to-board thermal resistance (4)
49.7
51
°C/W
ψJT
Junction-to-top characterization parameter (5)
26.1
1
°C/W
ψJB
Junction-to-board characterization parameter (6)
49
50.3
°C/W
(1)
(2)
(3)
(4)
(5)
(6)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
Copyright © 2014–2016, Texas Instruments Incorporated
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SBOS703E – APRIL 2014 – REVISED JUNE 2016
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Thermal Information: OPA316 (continued)
OPA316
THERMAL METRIC (1)
RθJC(bot)
(7)
SOT23 (DBV)
SC70 (DCK)
5 PINS
5 PINS
N/A
N/A
Junction-to-case(bottom) thermal resistance (7)
UNIT
°C/W
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
6.5 Thermal Information: OPA2316
OPA2316
THERMAL METRIC (1)
SO (D)
MSOP (DGK)
DFN (DRG)
8 PINS
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance (2)
127.2
186.6
56.3
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance (3)
71.6
78.8
72.2
°C/W
RθJB
Junction-to-board thermal resistance (4)
68.2
107.9
31
°C/W
ψJT
Junction-to-top characterization parameter (5)
22
15.5
2.3
°C/W
ψJB
Junction-to-board characterization parameter (6)
67.6
106.3
21.2
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance (7)
N/A
N/A
10.9
°C/W
(1)
(2)
(3)
(4)
(5)
(6)
(7)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
6.6 Thermal Information: OPA2316S
OPA2316S
THERMAL METRIC (1)
MSOP (DGS)
RUG (QFN)
10 PINS
10 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance (2)
189.6
158
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance (3)
73.9
52
°C/W
RθJB
Junction-to-board thermal resistance (4)
110.7
88
°C/W
ψJT
Junction-to-top characterization parameter (5)
13.4
1
°C/W
ψJB
Junction-to-board characterization parameter (6)
109.1
87
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance (7)
N/A
N/A
°C/W
(1)
(2)
(3)
(4)
(5)
(6)
(7)
6
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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SBOS703E – APRIL 2014 – REVISED JUNE 2016
6.7 Thermal Information: OPA4316
OPA4316
THERMAL METRIC (1)
TSSOP (PW)
UNIT
14 PINS
Junction-to-ambient thermal resistance (2)
RθJA
(3)
117.2
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
46.2
°C/W
RθJB
Junction-to-board thermal resistance (4)
58.9
°C/W
ψJT
Junction-to-top characterization parameter (5)
4.9
°C/W
ψJB
Junction-to-board characterization parameter (6)
58.3
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance (7)
N/A
°C/W
(1)
(2)
(3)
(4)
(5)
(6)
(7)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Copyright © 2014–2016, Texas Instruments Incorporated
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6.8 Electrical Characteristics
VS (total supply voltage) = (V+) – (V–) = 1.8 V to 5.5 V.
At TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
±0.5
±2.5
mV
OFFSET VOLTAGE
VOS
Input offset voltage
dVOS/dT
Drift
PSRR
vs power supply
VS = 5 V
VS = 5 V, TA = –40°C to +125°C
VS = 5 V, TA = –40°C to +125°C
VS = 1.8 V – 5.5 V, VCM = (V–)
±3.5
mV
±2
±10
μV/°C
±30
±150
µV/V
±250
µV/V
VS = 1.8 V – 5.5 V, VCM = (V–), TA = –40°C to +125°C
Channel separation, dc
At dc
10
µV/V
INPUT VOLTAGE RANGE
VCM
Common-mode voltage
CMRR
Common-mode rejection ratio
VS = 1.8 V to 2.5 V
(V–) – 0.2
(V+)
V
VS = 2.5 V to 5.5 V
(V–) – 0.2
(V+) + 0.2
V
VS = 1.8 V, (V–) – 0.2 V < VCM < (V+) – 1.4 V,
TA= –40°C to +125°C
70
86
dB
VS = 5.5 V, (V–) – 0.2 V < VCM < (V+) – 1.4 V,
TA= –40°C to +125°C
76
90
dB
VS = 1.8 V, VCM = –0.2 V to 1.8 V,
TA= –40°C to +125°C
57
72
dB
VS = 5.5 V, VCM = –0.2 V to 5.7 V,
TA= –40°C to +125°C
65
80
dB
INPUT BIAS CURRENT
IB
±5
Input bias current
IOS
TA= –40°C to +125°C
±2
Input offset current
TA= –40°C to +125°C
±15
pA
±15
nA
±15
pA
±8
nA
NOISE
En
Input voltage noise (peak-to-peak)
VS = 5 V, f = 0.1 Hz to 10 Hz
3
μVPP
en
Input voltage noise density
VS = 5 V, f = 1 kHz
11
nV/√Hz
in
Input current noise density
f = 1 kHz
1.3
fA/√Hz
INPUT IMPEDANCE
ZID
Differential
2 || 2
1016Ω || pF
ZIC
Common-mode
2 || 4
1011Ω || pF
OPEN-LOOP GAIN
AOL
VS = 1.8 V, (V–) + 0.04 V < VO < (V+) – 0.04 V,
RL = 10 kΩ
94
100
dB
VS = 5.5 V, (V–) + 0.05 V < VO < (V+) – 0.05 V,
RL = 10 kΩ
104
110
dB
90
96
dB
VS = 5.5 V, (V–) + 0.15 V < VO < (V+) – 0.15 V,
RL = 2 kΩ
100
106
dB
VS = 5.5 V, (V–) + 0.05 V < VO < (V+) – 0.05 V,
RL = 10 kΩ, TA= –40°C to +125°C
86
dB
VS = 5.5 V, (V–) + 0.15 V < VO < (V+) – 0.15 V,
RL = 2 kΩ, TA= –40°C to +125°C
84
dB
VS = 1.8 V, (V–) + 0.1 V < VO < (V+) – 0.1 V,
RL = 2 kΩ
Open-loop voltage gain
FREQUENCY RESPONSE
GBP
Gain bandwidth product
VS = 5 V, G = +1
10
MHz
φm
Phase margin
VS = 5 V, G = +1
60
Degrees
SR
Slew rate
VS = 5 V, G = +1
6
V/μs
To 0.1%, VS = 5 V, 2-V step , G = +1, CL = 100 pF
1
μs
1.66
μs
0.3
μs
tS
Settling time
tOR
Overload recovery time
THD + N
Total harmonic distortion + noise (1) VS = 5 V, VO = 0.5 VRMS, G = +1, f = 1 kHz
(1)
8
To 0.01%, VS = 5 V, 2-V step , G = +1, CL = 100 pF
VS = 5 V, VIN × gain = VS
0.0008%
Third-order filter; bandwidth = 80 kHz at –3 dB.
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Electrical Characteristics (continued)
VS (total supply voltage) = (V+) – (V–) = 1.8 V to 5.5 V.
At TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
VO
Voltage output swing from supply
rails
VS = 1.8 V, RL = 10 kΩ, TA= –40°C to 125°C
15
mV
VS = 5.5 V, RL = 10 kΩ, TA= –40°C to 125°C
30
mV
VS = 1.8 V, RL = 2 kΩ, TA= –40°C to 125°C
60
mV
VS = 5.5 V, RL = 2 kΩ, TA= –40°C to 125°C
120
mV
ISC
Short-circuit current
VS = 5 V
±50
mA
ZO
Open-loop output impedance
VS = 5 V, f = 10 MHz
250
Ω
POWER SUPPLY
VS
Specified voltage
IQ
Quiescent current per amplifier
VS = 5 V, IO = 0 mA, TA= –40°C to +125°C
1.8
400
Power-on time
VS = 0 V to 5.5 V
200
All amplifiers disabled, SHDN = VS–
0.01
5.5
V
500
µA
µs
SHUTDOWN (VS = 1.8 V to 5.5 V) (2)
IQSD
Quiescent current, per device
VIH
High voltage (enabled)
Amplifier enabled
VIL
Low voltage (disabled)
Amplifier disabled
tON
tOFF
Amplifier enable time
One amplifier disabled (OPA2316S)
(3)
Amplifier disable time
(3)
345
µA
µA
(V+) – 0.5
V
(V–) + 0.2
V
Full shutdown, G = 1, VOUT = 0.9 × VS / 2 (4)
13
µs
Partial shutdown, G = 1, VOUT = 0.9 × VS / 2 (4)
10
µs
G = 1, VOUT = 0.1 × VS / 2
SHDN pin input bias current (per
pin)
1
5
µs
VIH = 5 V
3.5
pA
VIL = 0 V
2.5
pA
TEMPERATURE
Specified temperature
–40
125
°C
TA
Operating temperature
–55
150
°C
Tstg
Storage temperature
–65
150
°C
(2)
(3)
(4)
Ensured by design and characterization; not production tested.
Enable time (tON) and disable time (tOFF) are defined as the time interval between the 50% point of the signal applied to the SHDN pin
and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.
Full shutdown refers to the dual OPA2316S having both channels A and B disabled (SHDN_A = SHDN_B = VS–). For partial shutdown,
only one SHDN pin is exercised; in partial mode, the internal biasing and oscillator remain operational and the enable time is shorter.
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6.9 Typical Characteristics
At TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.
40
Percentage of Amplifiers (%)
Percentage of Amplifiers (%)
25
20
15
10
5
35
30
25
20
15
10
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.5
0
-2.0
5
Offset Voltage (mV)
Offset Voltage Drift (µV/ƒC)
C013
C013
Distribution taken from 12551 amplifiers
TA = –40°C to +125°C, Distribution taken from 70 amplifiers
Figure 2. Offset Voltage Drift Distribution
2500
2000
2000
1500
1500
1000
1000
500
500
VOS ( V)
VOS ( V)
Figure 1. Offset Voltage Production Distribution
2500
0
±500
0
±500
±1000
±1000
±1500
±1500
±2000
±2000
±2500
±2500
±75
±50
0
±25
25
50
75
100
125
150
Temperature (ƒC)
0
±1
1
2
3
C001
V+ = 2.75 V, V– = –2.75 V, 9 typical units shown
Figure 4. Offset Voltage vs Common-Mode Voltage
2000
VS = ±2.75 V
VS = ±0.9 V
Gain (dB)
500
0
±500
±1000
120
270
100
225
80
180
60
135
Phase
40
90
20
±1500
45
VS
= “2.75 V
V
S = “2.75 V
0
±2000
Phase (º)
VOS ( V)
±2
VCM (V)
Figure 3. Offset Voltage vs Temperature
0
Gain
VS
= “0.9
“0.9 VV
V
S =
±2500
±20
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
VSUPPLY (V)
V+ = 0.9 V to 2.75 V, V– = –0.9 V to –2.75 V,
9 typical units shown
Figure 5. Offset Voltage vs Power Supply
10
Transition
±3
2500
1000
NChannel
PChannel
C001
9 typical units shown
1500
VCM = 2.95 V
VCM = -2.95 V
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2.8
C001
1
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
-45
100M
C006
VCM < (V+) – 1.4 V
Figure 6. Open-Loop Gain and Phase vs Frequency
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Typical Characteristics (continued)
At TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.
100
100
75
75
AOL (µV/V)
50
50
AOL (µV/V)
VS = 1.8 V
25
VS = 1.8 V
25
0
0
VS = 5.5 V
VS = 5.5 V
-25
-25
-50
-50
±75
±50
±25
0
25
50
75
100
125
150
Temperature (ƒC)
±75
±50
0
±25
RL = 10 kΩ
75
100
125
150
C001
Figure 8. Open-Loop Gain vs Temperature
100000
25
20
IB+
IB Ios
10000
Input Bias Current and
Input Offset Current (pA)
15
1000
10
Gain (dB)
50
RL = 2 kΩ
Figure 7. Open-Loop Gain vs Temperature
5
0
-5
G = +1
-10
100
10
1
G = +10
-15
G = -1
0
-20
10k
100k
1M
Frequency (Hz)
10M
±75
100M
±50
0
±25
Figure 9. Closed-Loop Gain vs Frequency
25
50
75
100
125
Temperature (ƒC)
C007
150
C001
Figure 10. Input Bias and Offset Current vs Temperature
3
25°C
Common-Mode Rejection Ratio (dB),
Power-Supply Rejection Ratio (dB)
120
-40°C
2
1
Vout (V)
25
Temperature (ƒC)
C001
85°C
125°C
0
125°C
-1
85°C
-2
25°C
-40°C
100
80
60
40
PSRR
20
CMRR
0
-3
0
10
20
30
40
Iout (mA)
50
60
C001
1
10
100
1k
10k
100k
Frequency (Hz)
1M
C011
V+ = 2.75 V, V– = –2.75 V
Figure 11. Output Voltage Swing vs Output Current
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Figure 12. CMRR and PSRR vs Frequency
(Referred to Input)
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Typical Characteristics (continued)
200
Common-Mode Rejection Ratio (µV/V)
Common-Mode Rejection Ratio (µV/V)
At TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.
150
9 ” 9CM ” 9
VS = 1.8 V, (V-) -
100
- 1.4 V
50
0
9 ” 9CM ” 9
VS = 5.5 V, (V-) -
±50
- 1.4 V
±100
±150
±200
1000
750
500
9 ” 9CM ” 9
VS = 1.8 V, (V-) -
250
0
VS = 5.5 V, (V-) -
±250
9 ” 9CM ” 9
9
±500
±750
±1000
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
150
±75
±50
0
±25
25
50
75
100
125
150
Temperature (ƒC)
C001
Figure 13. CMRR vs Temperature (Narrow Range)
C001
Figure 14. CMRR vs Temperature (Wide Range)
80
60
1 V/div
Power-Supply Rejection Ratio (µV/V)
100
40
20
0
Peak-to-Peak Noise = VRMS × 6.6 = 3 Vpp
-20
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
Time (1 s/div)
150
C014
C001
Figure 16. 0.1-Hz to 10-Hz Input Voltage Noise
Figure 15. PSRR vs Temperature
16
15
Voltage Noise (nV/rtHz)
9ROWDJH 1RLVH 'HQVLW\ Q9 ¥+]
1000
100
10
14
13
12
11
10
9
1
8
0.1
1
10
100
Frequency (Hz)
1k
10k
100k
C015
0
0.5
1
1.5
2
2.5
3
3.5
4
Common-Mode Voltage (V)
4.5
5
5.5
C039
ƒ = 1 kHz
Figure 17. Input Voltage Noise Spectral Density vs
Frequency
12
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Figure 18. Input Voltage Noise vs Common-Mode Voltage
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SBOS703E – APRIL 2014 – REVISED JUNE 2016
Typical Characteristics (continued)
Total Harmonic Distortion + Noise (%)
G = +1
G
+1 V/V,
V/V,RL
RL = 2 kN
G
V/V,RL
RL = 10 kN
G = -1 V/V,
0.01
-80
G
V/V,RL
RL = 2 kN
G = -1 V/V,
-100
0.001
-120
100k
0.0001
10
100
1k
10k
Frequency (Hz)
1.
-40
0.1
-60
0.01
-80
0.001
-100
G = +1 V/V, RL
N
G = +1
+1 V/V,
V/V,RL
RL = 2 kN
0.0001
-120
G = -1
G
-1 V/V,
V/V,RL
RL = 10 kN
G = -1
-1 V/V,
V/V,RL
RL = 2 kN
0.00001
0.001
0.01
-140
0.1
1
10
Output Amplitude (VRMS)
C017
BW = 80 kHz, VOUT = 0.5 VRMS
Total Harmonic Distortion + Noise (dB)
G = +1
G
+1 V/V,
V/V,RL
RL = 10 kN
Total Harmonic Distortion + Noise (dB)
-60
0.1
Total Harmonic Distortion + Noise (%)
At TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.
C018
ƒ = 1 kHz, BW = 80 kHz
Figure 19. THD + N vs Frequency
Figure 20. THD + N vs Amplitude
450
450
425
425
400
IQ (µA)
IQ (µA)
375
350
VS = 5.5 V
400
VS = 1.8 V
325
375
300
275
250
350
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Supply Voltage (V)
6
±75
±50
±25
0
25
50
75
100
125
150
Temperature (ƒC)
C001
Figure 21. Quiescent Current vs Supply Voltage
C001
Figure 22. Quiescent Current vs Temperature
10k
50
40
ZO ( )
Overshoot (%)
1k
100
30
RI = 1 kohm
RF = 1 kohm
20
+ 2.75 V
±
+
10
Device
VIN = 100 mVpp
+
±
10
CL
± 2.75 V
0
1
10
100
1k
10k
100k
1M
Frequency (Hz)
10M 100M 1000M
C024
0p
100p
200p
Capacitive Load (F)
300p
C025
V+ = 2.75 V, V– = –2.75 V, G = –1 V/V
Figure 23. Open-Loop Output Impedance vs Frequency
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Figure 24. Small-Signal Overshoot vs Load Capacitance
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Typical Characteristics (continued)
At TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.
80
VIN
70
VOUT
50
1 V/div
Overshoot (%)
60
40
+ 2.75 V
30
+ 2.75 V
±
±
Device
Device
20
+
VIN = 100 mVpp
+
± 2.75 V
RL
CL
10
0
0p
100p
200p
Time (100 s/div)
300p
Capacitive Load (F)
C027
C026
V+ = 2.75 V, V– = –2.75 V
V+ = 2.75 V, V– = –2.75 V , G = +1 V/V, RL = 1 kΩ
Figure 26. No Phase Reversal
Figure 25. Small-Signal Overshoot vs Load Capacitance
1V
VOUT
5.5 V
RI = 1 kohm
RF = 10 kohm
0V
+ 2.75 V
VIN = 1 Vpp
±
Device
VIN
VOUT
+
±
500 mV/div
500 mV/div
+
± 2.75 V
6.1 VPP
Sine Wave
±
±
VOUT
+
+
± 2.75 V
Saturated
Slewing
Recovering
Saturated
RI = 1 kohm
Slewing
+ 2.75 V
+
VIN
Recovering
RF = 10 kohm
VIN = 1 Vpp
Device
VOUT
+
±
0V
±
± 2.75 V
-5.5 V
VOUT
-1 V
Time (100 ns/div)
Time (100 ns/div)
C028
C029
V+ = 2.75 V, V– = –2.75 V , G = –10 V/V
V+ = 2.75 V, V– = –2.75 V, G = –10 V/V
Figure 27. Positive Overload Recovery
Figure 28. Negative Overload Recovery
+ 2.75 V
±
Device
CL
= 100
100 pF
pF
C
L =
+
VIN = 1 Vpp
+
± 2.75 V
RL
CL
±
200 mV/div
Output Voltage (20 mV/div)
CL
= 10 pF
C
L = 10 pF
+ 2.75 V
VOUT
±
Device
+
VIN = 100 mVpp
+
± 2.75 V
RL
CL
±
VIN
Time (200 ns/div)
Time (100 ns/div)
C030
V+ = 2.75 V, V– = –2.75 V, G = +1 V/V
Figure 29. Small-Signal Step Response
14
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C031
V+ = 2.75 V, V– = –2.75 V, CL = 100 pF, G = +1 V/V
Figure 30. Large-Signal Step Response
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Typical Characteristics (continued)
At TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.
40
Output Delta from Final Value (mV)
Output Delta from Final Value (mV)
100
80
60
40
20
0.1% Settling = ±2 mV
0
-20
20
0
0.1% Settling = ±2 mV
-20
-40
-60
-80
-40
0
0.5
1
1.5
0
2
Time ( s)
0.5
CL = 100 pF, G = +1 V/V
1.5
2
C033
CL = 100 pF, G = +1 V/V
Figure 31. Positive Large-Signal Settling Time
Figure 32. Negative Large-Signal Settling Time
70
7
6
Output Voltage (VPP)
60
ISC, Source
ISC (mA)
1
Time ( s)
C032
50
ISC, Sink
40
VS = 5.5 V
5
VS = 5 V
Maximum output voltage without
slew-rate induced distortion.
4
3
VS = 1.8 V
2
1
30
±75
±50
±25
0
25
50
75
100
125
0
100k
150
Temperature (ƒC)
C001
Figure 33. Short-Circuit Current vs Temperature
10M
C035
Figure 34. Maximum Output Voltage vs
Frequency and Supply Voltage
100
0
80
±20
Crosstalk (dB)
EMIRR IN+ (dB)
1M
Frequency (Hz)
60
40
20
±40
±60
±80
±100
0
±120
10M
100M
1G
Frequency (Hz)
10G
PRF = –10 dBm
Figure 35. Electromagnetic Interference Rejection Ratio
Referred to Noninverting Input (EMIRR IN+) vs Frequency
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10
100
1k
10k
100k
1M
Frequency (Hz)
C036
10M
C001
V+ = 2.75 V, V– = –2.75 V
Figure 36. Channel Separation vs Frequency
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7 Detailed Description
7.1 Overview
The OPA316 is a family of low-power, rail-to-rail input and output operational amplifiers. These devices operate
from 1.8 V to 5.5 V, are unity-gain stable, and are suitable for a wide range of general-purpose applications. The
class AB output stage is capable of driving leass than or equal to 10-kΩ loads connected to any point between
V+ and ground. The input common-mode voltage range includes both rails and allows the OPA316 series to be
used in virtually any single-supply application. Rail-to-rail input and output swing significantly increases dynamic
range, especially in low-supply applications, and makes them ideal for driving sampling analog-to-digital
converters (ADCs).
The OPA316 features 10-MHz bandwidth and 6-V/μs slew rate with only 400-μA supply current per channel,
providing good ac performance at very-low power consumption. DC applications are also well served with a verylow input noise voltage of 11 nV/√Hz at 1 kHz, low input bias current (5 pA), and an input offset voltage of
0.5 mV (typical).
7.2 Functional Block Diagram
V+
Reference
Current
VIN+
VINVBIAS1
Class AB
Control
Circuitry
VO
VBIAS2
V(Ground)
7.3 Feature Description
7.3.1 Operating Voltage
The OPA316 series operational amplifiers are fully specified and ensured for operation from 1.8 V to 5.5 V. In
addition, many specifications apply from –40°C to +125°C. Parameters that vary significantly with operating
voltages or temperature are illustrated in the Typical Characteristics graphs.
7.3.2 Rail-to-Rail Input
The input common-mode voltage range of the OPA316 series extends 200 mV beyond the supply rails for supply
voltages greater than 2.5 V. This performance is achieved with a complementary input stage: an N-channel input
differential pair in parallel with a P-channel differential pair, as shown in the Functional Block Diagram section.
The N-channel pair is active for input voltages close to the positive rail, typically (V+) – 1.4 V to 200 mV above
the positive supply, whereas the P-channel pair is active for inputs from 200 mV below the negative supply to
16
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Feature Description (continued)
approximately (V+) – 1.4 V. There is a small transition region, typically (V+) – 1.2 V to (V+) – 1 V, in which both
pairs are on. This 200-mV transition region can vary up to 200 mV with process variation. Thus, the transition
region (both stages on) can range from (V+) – 1.4 V to (V+) – 1.2 V on the low end, up to (V+) – 1 V to (V+) –
0.8 V on the high end. Within this transition region, PSRR, CMRR, offset voltage, offset drift, and THD can be
degraded compared to device operation outside this region.
7.3.3 Input and ESD Protection
The OPA316 family incorporates internal ESD protection circuits on all pins. In the case of input and output pins,
this protection primarily consists of current-steering diodes connected between the input and power-supply pins.
These ESD protection diodes also provide in-circuit, input overdrive protection, as long as the current is limited to
10 mA as stated in the Absolute Maximum Ratings table. Figure 37 shows how a series input resistor can be
added to the driven input to limit the input current. The added resistor contributes thermal noise at the amplifier
input and its value must be kept to a minimum in noise-sensitive applications.
V+
IOVERLOAD
10-mA max
Device
VOUT
VIN
5 kW
Figure 37. Input Current Protection
7.3.4 Common-Mode Rejection Ratio (CMRR)
CMRR for the OPA316 is specified in several ways so the user can select the best match for a given application
(see the Electrical Characteristics table). First, the data sheet gives the CMRR of the device in the commonmode range below the transition region [VCM < (V+) – 1.4 V]. This specification is the best indicator of device
capability when the application requires use of one of the differential input pairs. Second, the CMRR over the
entire common-mode range is specified at VCM = –0.2 V to 5.7 V for VS = 5.5 V. This last value includes the
variations shown in Figure 4 through the transition region.
7.3.5 EMI Susceptibility and Input Filtering
Operational amplifiers vary with regard to the susceptibility of the device to electromagnetic interference (EMI). If
conducted EMI enters the operational amplifier, the dc offset observed at the amplifier output can shift from its
nominal value when EMI is present. This shift is a result of signal rectification associated with the internal
semiconductor junctions. Although all operational amplifier pin functions can be affected by EMI, the signal input
pins are likely to be the most susceptible. The OPA316 operational amplifier family incorporates an internal input
low-pass filter that reduces the amplifier response to EMI. This filter provides both common-mode and
differential-mode filtering. The filter is designed for a cutoff frequency of approximately 80 MHz (–3 dB), with a
roll-off of 20 dB per decade.
TI developed the ability to accurately measure and quantify the immunity of an operational amplifier over a broad
frequency spectrum extending from 10 MHz to 6 GHz. The EMI rejection ratio (EMIRR) metric allows operational
amplifiers to be directly compared by the EMI immunity. Figure 35 illustrates the results of this testing on the
OPA316. Detailed information can also be found in the application report, EMI Rejection Ratio of Operational
Amplifiers (SBOA128).
7.3.6 Rail-to-Rail Output
Designed as a low-power, low-noise operational amplifier, the OPA316 delivers a robust output drive capability.
A class AB output stage with common-source transistors is used to achieve full rail-to-rail output swing capability.
For resistive loads of 10 kΩ, the output swings typically to within 30 mV of either supply rail regardless of the
power-supply voltage applied. Different load conditions change the ability of the amplifier to swing close to the
rails; see the typical characteristic graph Output Voltage Swing vs Output Current (Figure 11).
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Feature Description (continued)
7.3.7 Capacitive Load and Stability
The OPA316 is designed to be used in applications where driving a capacitive load is required. As with all
operational amplifiers, there may be specific instances where the OPA316 can become unstable. The particular
operational amplifier circuit configuration, layout, gain, and output loading are some of the factors to consider
when establishing whether or not an amplifier is stable in operation. An operational amplifier in the unity-gain
(+1 V/V) buffer configuration that drives a capacitive load exhibits a greater tendency to be unstable than an
amplifier operated at a higher noise gain. The capacitive load, in conjunction with the operational amplifier output
resistance, creates a pole within the feedback loop that degrades the phase margin. The degradation of the
phase margin increases as the capacitive loading increases. As a conservative best practice, designing for 25%
overshoot (40° phase margin) provides improved stability over process variations. The equivalent series
resistance (ESR) of some very-large capacitors (CL greater than 1 μF) is sufficient to alter the phase
characteristics in the feedback loop such that the amplifier remains stable. Increasing the amplifier closed-loop
gain allows the amplifier to drive increasingly larger capacitance. This increased capability is evident when
observing the overshoot response of the amplifier at higher voltage gains. See the typical characteristic graphs,
Small-Signal Overshoot vs Capacitive Load (Figure 24, G = –1 V/V) and Small-Signal Overshoot vs Capacitive
Load (Figure 25, G = +1 V/V).
One technique for increasing the capacitive load drive capability of the amplifier operating in a unity-gain
configuration is to insert a small resistor (typically 10 Ω to 20 Ω) in series with the output, as shown in Figure 38.
This resistor significantly reduces the overshoot and ringing associated with large capacitive loads. One possible
problem with this technique, however, is that a voltage divider is created with the added series resistor and any
resistor connected in parallel with the capacitive load. The voltage divider introduces a gain error at the output
that reduces the output swing.
V+
RS
VOUT
Device
VIN
10 W to
20 W
RL
CL
Figure 38. Improving Capacitive Load Drive
7.3.8 Overload Recovery
Overload recovery is defined as the time required for the operational amplifier output to recover from a saturated
state to a linear state. The output devices of the operational amplifier enter a saturation region when the output
voltage exceeds the rated operating voltage, either because of the high input voltage or the high gain. After the
device enters the saturation region, the charge carriers in the output devices require time to return back to the
linear state. After the charge carriers return back to the linear state, the device begins to slew at the specified
slew rate. Thus, the propagation delay in case of an overload condition is the sum of the overload recovery time
and the slew time. The overload recovery time for the OPA316 is approximately 300 ns.
7.3.9 DFN Package
The OPA2316 (dual version) uses the DFN style package (also known as SON); this package is a QFN with
contacts on only two sides of the package bottom. This leadless package maximizes printed circuit board (PCB)
space and offers enhanced thermal and electrical characteristics through an exposed pad. One of the primary
advantages of the DFN package is its low, 0.9-mm height. DFN packages are physically small, have a smaller
routing area, improved thermal performance, reduced electrical parasitics, and use a pinout scheme that is
consistent with other commonly-used packages (such as SOIC and MSOP). Additionally, the absence of external
leads eliminates bent-lead issues.
The DFN package can be easily mounted using standard PCB assembly techniques. See application notes,
QFN/SON PCB Attachment (SLUA271), and Quad Flatpack No-Lead Logic Packages (SCBA017).
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Feature Description (continued)
NOTE
Connect the exposed lead frame die pad on the bottom of the DFN package to the most
negative potential (V–).
7.4 Device Functional Modes
The OPA316, OPA2316, and OPA4316 are powered on when the supply is connected. The devices can be
operated as a single-supply operational amplifier or a dual-supply amplifier, depending on the application.
The OPA2316S has a SHDN (enable) pin function referenced to the negative supply voltage of the operational
amplifier. A logic level high enables the operational amplifier. A valid logic high is defined as voltage [(V+) – 0.1
V], up to (V+), applied to the SHDN pin. A valid logic low is defined as [(V–) + 0.1 V], down to (V–), applied to the
enable pin. The maximum allowed voltage applied to SHDN is 5.5 V with respect to the negative supply,
independent of the positive supply voltage. Connect this pin to a valid high or a low voltage or driven, but not left
as an open circuit.
The logic input is a high-impedance CMOS input. Both inputs are independently controlled. For battery-operated
applications, this feature can be used to greatly reduce the average current and extend battery life.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 General Configurations
When receiving low-level signals, the device often requires limiting the bandwidth of the incoming signals into the
system. The simplest way to establish this limited bandwidth is to place an RC filter at the noninverting pin of the
amplifier, as Figure 39 shows.
RG
RF
R1
VOUT
VIN
C1
f-3 dB =
(
RF
VOUT
= 1+
RG
VIN
((
1
1 + sR1C1
1
2pR1C1
(
Figure 39. Single-Pole Low-Pass Filter
If even more attenuation is needed, the device requires a multiple-pole filter. The Sallen-Key filter can be used
for this task, as Figure 40 shows. For best results, the amplifier must have a bandwidth that is 8 times to 10
times the filter frequency bandwidth. Failure to follow this guideline can result in phase shift of the amplifier.
C1
R1
R1 = R2 = R
C1 = C2 = C
Q = Peaking factor
(Butterworth Q = 0.707)
R2
VIN
VOUT
C2
1
2pRC
f-3 dB =
RF
RF
RG =
RG
(
2-
1
Q
(
Figure 40. Two-Pole, Low-Pass, Sallen-Key Filter
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8.2 Typical Application
Some applications require differential signals. Figure 41 shows a simple circuit to convert a single-ended input of
0.1 V to 2.4 V into a differential output of ±2.3 V on a single 2.7-V supply. The output range is intentionally limited
to maximize linearity. The circuit is composed of two amplifiers. One amplifier functions as a buffer and creates a
voltage, Vout+. The second amplifier inverts the input and adds a reference voltage to generate Vout–. Both
Vout+ and Vout– range from 0.1 V to 2.4 V. The difference, Vdiff, is the difference between Vout+ and Vout–
which makes the differential output voltage range 2.3 V.
R2
2.7V
R1
-
Vout-
+
R3
+
Vref
2.5V
R4
V
+
2.7V
-
Vdiff
Vout+
+
+
+
Vin
Figure 41. Schematic for a Single-Ended Input to Differential Output Conversion
8.2.1 Design Requirements
Table 1 lists the design requirements:
Table 1. Design Parameters
DESIGN PARAMETER
VALUE
Supply voltage
2.7 V
Reference voltage
2.5 V
Input voltage
0.1 V to 2.4 V
Output differential voltage
±2.3 V
Output common-mode voltage
1.25 V
Small-signal bandwidth
5 MHz
8.2.2 Detailed Design Procedure
The circuit in Figure 41 takes a single-ended input signal, Vin, and generates two output signals, Vout+ and
Vout– using two amplifiers and a reference voltage, Vref. Vout+ is the output of the first amplifier and is a
buffered version of the input signal, Vin (as shown in Equation 1). Vout– is the output of the second amplifier
which uses Vref to add an offset voltage to Vin and feedback to add inverting gain. The transfer function for
Vout– is given in Equation 2.
Vout
Vin
(1)
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Vout
www.ti.com
§ R 4 · § R2 ·
R2
Vref u ¨
Vin u
¸ u ¨1
¸
R1 ¹
R1
© R3 R 4 ¹ ©
(2)
The differential output signal, Vdiff, is the difference between the two single-ended output signals, Vout+ and
Vout–. Equation 3 shows the transfer function for Vdiff. Using conditions in Equation 4 and Equation 5 and
applying the conditions that R1 = R2 and R3 = R4, the transfer function is simplified into Equation 6. Using this
configuration, the maximum input signal is equal to the reference voltage and the maximum output of each
amplifier is equal to Vref. The differential output range is 2 × Vref. Furthermore, the common-mode voltage is one
half of Vref (see Equation 7).
Vout
Vout
Vout
Vdiff
Vin
Vref Vin
2 u Vin Vref
Vout ·
§ Vout
¨
¸
2
©
¹
Vcm
Vout
§
Vin u ¨1
©
Vdiff
R2 ·
R1 ¸¹
§ R4 · §
Vref u ¨
¸ u ¨1
© R3 R4 ¹ ©
R2 ·
R1 ¸¹
(3)
(4)
(5)
(6)
1
Vref
2
(7)
8.2.2.1 Amplifier Selection
Linearity over the input range is key for good dc accuracy. The common-mode input range and output swing
limitations determine the linearity. In general, an amplifier with rail-to-rail input and output swing is required.
Bandwidth is a key concern for this design, so the OPA316 is selected because its bandwidth is greater than the
target of 5 MHz. The bandwidth and power ratio makes this device power efficient and the low offset and drift
ensure good accuracy for moderate precision applications.
8.2.2.2 Passive Component Selection
Because the transfer function of Vout– is heavily reliant on resistors (R1, R2, R3, and R4), use resistors with low
tolerances to maximize performance and minimize error. This design uses resistors with resistance values of
49.9 kΩ and tolerances of 0.1%. However, if the noise of the system is a key parameter, smaller resistance
values (6 kΩ or lower) can be selected to keep the overall system noise low. This ensures that the noise from the
resistors is lower than the amplifier noise.
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8.2.3 Application Curves
2.50
2.50
2.00
2.00
1.50
1.50
Vout- (V)
Vout+ (V)
The measured transfer functions in Figure 42, Figure 43, and Figure 44 are generated by sweeping the input
voltage from 0.1 V to 2.4 V. The full input range is actually 0 V to 2.5 V, but is restricted by 0.1 V to maintain
optimal linearity. For more details on this design and other alternative devices that can be used in place of the
OPA316, see the Precision Design, Single-Ended Input to Differential Output Conversion Circuit Reference
Design (TIPD131).
1.00
0.50
0.00
0.00
1.00
0.50
0.50
1.00
1.50
2.00
0.00
0.00
2.50
Input voltage (V)
0.50
1.00
1.50
2.00
Input voltage (V)
C027
Figure 42. Vout+ vs Input Voltage
2.50
C027
Figure 43. Vout– vs Input Voltage
2.50
2.00
1.50
Vdiff (V)
1.00
0.50
0.00
-0.50
-1.00
-1.50
-2.00
-2.50
0.00
0.50
1.00
1.50
2.00
Input voltage (V)
2.50
C027
Figure 44. Vdiff vs Input Voltage
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9 Power Supply Recommendations
The OPA316 is specified for operation from 1.8 V to 5.5 V (±0.9 V to ±2.75 V); many specifications apply from
–40°C to 125°C. The section presents parameters that can exhibit significant variance with regard to operating
voltage or temperature.
CAUTION
Supply voltages larger than 7 V can permanently damage the device (see the Absolute
Maximum Ratings) table.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
Guidelines section.
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10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing lowimpedance power sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of the circuitry is one of the simplest and most
effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to
ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to
physically separate digital and analog grounds, paying attention to the flow of the ground current. For
more detailed information, see Circuit Board Layout Techniques, SLOA089.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicularly is much
better than crossing in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keeping RF and RG close to the
inverting input minimizes parasitic capacitance, as shown in the Layout Example section.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
10.2 Layout Example
Run the input traces
as far away from
the supply lines
as possible
Place components
close to device and to
each other to reduce
parasitic errors
VS+
RF
N/C
N/C
GND
±IN
V+
VIN
+IN
OUTPUT
V±
N/C
RG
Use low-ESR,
ceramic bypass
capacitor
GND
VS±
GND
Use low-ESR, ceramic
bypass capacitor
VOUT
Ground (GND) plane on another layer
Figure 45. Operational Amplifier Board Layout for Noninverting Configuration
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• EMI Rejection Ratio of Operational Amplifiers, SBOA128
• QFN/SON PCB Attachment, SLUA271
• Quad Flatpack No-Lead Logic Packages, SCBA017
• Single-Ended Input to Differential Output Conversion Circuit Reference Design, TIPD131
• Circuit Board Layout Techniques, SLOA089
11.2 Related Links
The following table lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
OPA316
Click here
Click here
Click here
Click here
Click here
OPA2316
Click here
Click here
Click here
Click here
Click here
OPA2316S
Click here
Click here
Click here
Click here
Click here
OPA4316
Click here
Click here
Click here
Click here
Click here
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
2-Sep-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA2316ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O2316
OPA2316IDGK
ACTIVE
VSSOP
DGK
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
OVMQ
OPA2316IDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
OVMQ
OPA2316IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O2316
OPA2316IDRGR
ACTIVE
SON
DRG
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
SMD
OPA2316IDRGT
ACTIVE
SON
DRG
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
SMD
OPA2316SIDGS
ACTIVE
VSSOP
DGS
10
80
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
SMG
OPA2316SIDGSR
ACTIVE
VSSOP
DGS
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
SMG
OPA2316SIRUGR
ACTIVE
X2QFN
RUG
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
1QU
OPA2316SIRUGT
ACTIVE
X2QFN
RUG
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
1QU
OPA316IDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
SLE
OPA316IDBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
SLE
OPA316IDCKR
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
SLD
OPA316IDCKT
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
SLD
OPA4316ID
PREVIEW
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O4316D
OPA4316IDR
PREVIEW
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O4316D
OPA4316IPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA4316
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
2-Sep-2016
Status
(1)
OPA4316IPWR
ACTIVE
Package Type Package Pins Package
Drawing
Qty
TSSOP
PW
14
2000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
OPA4316
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
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of the previous line and the two combined represent the entire Device Marking for that device.
(6)
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Addendum-Page 2
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
16-May-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
OPA2316IDGKR
VSSOP
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
OPA2316IDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
OPA2316IDRGR
SON
DRG
8
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
OPA2316IDRGT
SON
DRG
8
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
OPA2316SIDGSR
VSSOP
DGS
10
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
OPA316IDBVR
SOT-23
DBV
5
3000
178.0
9.0
3.3
3.2
1.4
4.0
8.0
Q3
OPA316IDBVT
SOT-23
DBV
5
250
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
OPA316IDCKR
SC70
DCK
5
3000
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
OPA316IDCKT
SC70
DCK
5
250
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
OPA4316IPWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-May-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA2316IDGKR
VSSOP
DGK
8
2500
366.0
364.0
50.0
OPA2316IDR
SOIC
D
8
2500
533.4
367.0
36.0
OPA2316IDRGR
SON
DRG
8
3000
367.0
367.0
35.0
OPA2316IDRGT
SON
DRG
8
250
210.0
185.0
35.0
OPA2316SIDGSR
VSSOP
DGS
10
2500
366.0
364.0
50.0
OPA316IDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
OPA316IDBVT
SOT-23
DBV
5
250
180.0
180.0
18.0
OPA316IDCKR
SC70
DCK
5
3000
180.0
180.0
18.0
OPA316IDCKT
SC70
DCK
5
250
180.0
180.0
18.0
OPA4316IPWR
TSSOP
PW
14
2000
367.0
367.0
35.0
Pack Materials-Page 2
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