RBIAS VREF DVDD33x DVDD18 SFLAG AVDD33 PDWN FUNCTIONAL BLOCK DIAGRAM REFERENCE INA+ INA– AD8284 SATURATION DETECTION INB+ INB– MUX LNA INC+ PGA AAF IND+ MUX 12-BIT ADC CLK+ CLK– INC– AUX D0 TO D11 IND– INADC+ INADC– SPI SDI SDO Automotive radar Adaptive cruise control Collision avoidance Blind spot detection Self parking Electronic bumper SCLK CS APPLICATIONS Figure 1. GENERAL DESCRIPTION The AD8284 is an integrated analog front end designed for low cost, compact size, flexibility, and ease of use. It contains a 4-channel differential multiplexer (mux), a 1-channel low noise preamplifier (LNA) with a programmable gain amplifier (PGA) and an antialiasing filter (AAF), as well as one direct-to-ADC channel, all integrated with a single, 12-bit analog-to-digital converter (ADC). The AD8284 also incorporates a saturation detection circuit for high frequency overvoltage conditions that would otherwise be filtered by the AAF. The analog channel features a gain range of 17 dB to 35 dB in 6 dB increments, and an ADC with a conversion rate of up to 60 MSPS. The combined input referred voltage noise of the entire channel is 3.5 nV/√Hz at maximum gain. The channel is optimized Rev. D for dynamic performance and low power in applications where a small package size is critical. Fabricated in an advanced CMOS process, the AD8284 is available in a 10 mm × 10 mm, RoHS compliant, 64-lead TQFP. It is specified over the automotive temperature range of −40°C to +105°C. Table 1. Related Devices Part No. AD8285 AD8283 ADA8282 Description 4-Channel LNA/PGA/AAF, pseudosimultaneous channel sampling with ADC 6-Channel LNA/PGA/AAF, pseudosimultaneous channel sampling with ADC 4-Channel LNA/PGA Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2012–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 10992-001 4-channel mux to LNA, PGA, AAF 1 direct-to-ADC channel Programmable gain amplifier (PGA) Includes low noise preamplifier (LNA) SPI-programmable gain = 17 dB to 35 dB in 6 dB steps Antialiasing filter (AAF) Programmable third-order low-pass elliptic filter (LPF) from 9 MHz to 15 MHz Analog-to-digital converter (ADC) 12 bits of accuracy of up to 60 MSPS SNR = 67 dB SFDR = 68 dBc Low power, 345 mW at 12 bits per 60 MSPS Low noise, 3.5 nV/√Hz maximum of input referred voltage noise Power-down mode 64-lead, 10 mm × 10 mm TQFP package Specified from −40°C to +105°C Qualified for automotive applications ZSEL FEATURES MUX[1] TO MUX[0] AVDD18 Data Sheet Radar Receive Path AFE: 4-Channel Mux with LNA, PGA, AAF, and ADC AD8284 AD8284* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS DISCUSSIONS View a parametric search of comparable parts. View all AD8284 EngineerZone Discussions. DOCUMENTATION SAMPLE AND BUY Data Sheet Visit the product page to see pricing options. • AD8284: Radar Receive Path AFE: 4-Channel Mux with LNA, PGA, AAF, and ADC Data Sheet TECHNICAL SUPPORT DESIGN RESOURCES Submit a technical question or find your regional support number. • AD8284 Material Declaration • PCN-PDN Information DOCUMENT FEEDBACK • Quality And Reliability Submit feedback for this data sheet. • Symbols and Footprints This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified. AD8284 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Clock Jitter Considerations ....................................................... 16 Applications ....................................................................................... 1 SDI and SDO Pins ...................................................................... 16 Functional Block Diagram .............................................................. 1 SCLK Pin ..................................................................................... 16 General Description ......................................................................... 1 CS Pin........................................................................................... 16 Revision History ............................................................................... 2 RBIAS Pin .................................................................................... 16 Specifications..................................................................................... 3 Voltage Reference ....................................................................... 16 AC Specifications.......................................................................... 3 Power and Ground Recommendations ................................... 16 Digital Specifications ................................................................... 5 Exposed Pad Thermal Heat Slug Recommendations ............ 17 Switching Specifications .............................................................. 6 Serial Port Interface (SPI) .............................................................. 18 Absolute Maximum Ratings ....................................................... 7 Hardware Interface ..................................................................... 18 ESD Caution .................................................................................. 7 Memory Map .................................................................................. 20 Pin Configuration and Function Descriptions ............................. 8 Reading the Memory Map Table .............................................. 20 Typical Performance Characteristics ........................................... 10 Logic Levels ................................................................................. 20 Theory of Operation ...................................................................... 12 Reserved Locations .................................................................... 20 Radar Receive Path AFE ............................................................ 12 Default Values ............................................................................. 20 Channel Overview...................................................................... 13 Application Circuits ....................................................................... 24 ADC ............................................................................................. 15 Packaging and Ordering Information ......................................... 26 AUX Channel .............................................................................. 15 Outline Dimensions ................................................................... 26 Clock Input Considerations ...................................................... 15 Ordering Guide .......................................................................... 26 Clock Duty Cycle Considerations ............................................ 16 Automotive Products ................................................................. 26 REVISION HISTORY 8/15—Rev. C to Rev. D Changed AD951x/AD952x to AD9515/AD9520-0.... Throughout Added Table 1; Renumbered Sequentially .................................... 1 6/14—Rev. B to Rev. C Changed 80 MSPS to 60 MSPS .................................... Throughout Changes to Table 1 ............................................................................ 3 Changed 6.25 to 8.33, Clock Pulse Width High Parameter, Clock Pulse Width Low Parameter, and Data Setup Time Parameter, Table 3............................................................................. 6 7/13—Rev. A to Rev. B Changes to Input Resistance and Power-Down Dissipation Parameters; Table 1 ........................................................................... 3 Updated Outline Dimensions ....................................................... 26 Changes to Ordering Guide .......................................................... 26 1/13—Rev. 0 to Rev. A Changes to Figure 16 ...................................................................... 14 10/12—Revision 0: Initial Version Rev. D | Page 2 of 28 Data Sheet AD8284 SPECIFICATIONS AC SPECIFICATIONS AVDD18x = 1.8 V, AVDD33x = 3.3 V, DVDD18x = 1.8 V, DVDD33x = 3.3 V, 1.0 V internal ADC reference, fIN = 2.5 MHz, fS = 60 MSPS, RS = 50 Ω, LNA + PGA gain = 35 dB, LPF cutoff = fSAMPLECH/4, 12-bit operation, temperature = −40°C to +105°C, all specifications guaranteed by testing, unless otherwise noted. Table 2. Parameter1 ANALOG CHANNEL CHARACTERISTICS Gain Gain Range Gain Error Input Voltage Range2 Input Resistance Input Capacitance2 Input Referred Voltage Noise2 Noise Figure2 Output Offset AAF Low-Pass Filter Cutoff Tolerance AAF Attenuation in Stop Band2 Group Delay Variation2 1 dB Compression2 Saturation Flag Response Time Saturation Flag Accuracy Off On Mux2 On Resistance Switching Time POWER SUPPLY AVDD18x2 AVDD33x2 DVDD18x2 DVDD33x2 IAVDD18 IAVDD33 IDVDD18 IDVDD33 Total Power Dissipation Test Conditions/Comments LNA, PGA, and AAF channel Programmable Min Typ 17/23/29/35 18 −1.25 Channel gain = 17 dB Channel gain = 23 dB Channel gain = 29 dB Channel gain = 35 dB 200 Ω input impedance 200 kΩ input impedance Maximum gain at 1 MHz Minimum gain at 1 MHz Maximum gain, RS = 50 Ω, not terminated Maximum gain, RS = RIN = 50 Ω Gain = 17 dB Gain = 35 dB −3 dB, programmable After filter autotune Third-order elliptic filter 2× cutoff 3× cutoff Filter set at 9 MHz Relative to output Time between saturation event and saturation flag going high (1 dB overdrive) Time between end of saturation event and saturation flag going low Gain = 29 dB For PGA voltages below 2 V p-p For PGA voltages above 2.25 V p-p 0.200 160 Rev. D | Page 3 of 28 +10 100 dB dB ns dBm ns +1.25 0.283 0.142 0.071 0.036 0.265 200 7 0.300 240 7.1 12.7 −60 −250 −10 +60 +250 9.0 to 15.0 ±5 30 40 400 11.9 30 25 Unit dB dB dB V p-p V p-p V p-p V p-p kΩ kΩ pF nV/√Hz nV/√Hz dB dB LSB LSB MHz % 1.85 6.03 1.7 3.1 1.7 3.1 fS = 60 MSPS fS = 60 MSPS fS = 60 MSPS fS = 60 MSPS No signal, typical supply voltage × maximum supply current; excludes output current Max 40 ns 2 2.25 V p-p V p-p 50 200 Ω ns 1.8 3.3 1.8 3.3 1.9 3.5 1.9 3.5 54 65 15 2 345 V V V V mA mA mA mA mW AD8284 Parameter1 Power-Down Dissipation Power Supply Rejection Ratio (PSRR)2 ADC Resolution2 Maximum Sample Rate Signal-to-Noise Ratio (SNR) Signal-to-Noise-and-Distortion Ratio (SINAD) 2 SNRFS2 Differential Nonlinearity (DNL) Integral Nonlinearity (INL) Effective Number of Bits (ENOB)2 ADC Output Characteristics2 Maximum Capacitor Load IDVDD33 Peak Current with Capacitor Load2 ADC REFERENCE Output Voltage Error Load Regulation Current Output Input Resistance FULL CHANNEL CHARACTERISTICS SNRFS SINAD2 Spurious-Free Dynamic Range (SFDR) Harmonic Distortion2 Second Harmonic Third Harmonic IM3 Distortion Gain Response Time Overdrive Recovery Time 1 2 Data Sheet Test Conditions/Comments TA = −25°C to +105°C TA = −40°C to +25°C Relative to input Min Typ 2.5 2.5 1.6 Max 4.0 8.0 12 60 67 66 fIN = 1 MHz Bits MSPS dB dB 68 Guaranteed no missing codes fS = 60 MSPS 4 10.67 Per bit Peak current per bit when driving a 20 pF load; can be programmed via the SPI port, if required 40 ±20 60 60 60 60 62 62 62 62 pF mA 6 64 64 64 64 dBFS dBFS dBFS dBFS 62 63 64 63 dB dB dB dB 68 68 68 71 dBc dBc dBc dBc −70 −70 −66 −75 −69 600 200 dBc dBc dBc dBc dBc ns ns +1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and testing methodology. Guaranteed by design only. Rev. D | Page 4 of 28 dB LSB LSB LSB mV mV mA kΩ 2 −1 LNA, PGA, AAF, and ADC fIN = 1 MHz, −10 dBFS output Gain = 17 dB, fS = 60 MSPS Gain = 23 dB, fS = 60 MSPS Gain = 29 dB, fS = 60 MSPS Gain = 35 dB, fS = 60 MSPS fIN = 1 MHz Gain = 17 dB Gain = 23 dB Gain = 29 dB Gain = 35 dB fIN = 1 MHz, −10 dBFS output Gain = 17 dB, fS = 60 MSPS Gain = 23 dB, fS = 60 MSPS Gain = 29 dB, fS = 60 MSPS Gain = 35 dB, fS = 60 MSPS fIN = 1 MHz at −10 dBFS output Gain = 17 dB Gain = 35 dB Gain = 17 dB Gain = 35 dB fIN1 = 1 MHz, fIN2 = 1.1 MHz, −1 dBFS, gain = 35 dB 1 10 20 VREF = 1.000 V At 1.0 mA, VREF = 1.000 V Unit mW mW mV/V Data Sheet AD8284 DIGITAL SPECIFICATIONS AVDD18x = 1.8 V, AVDD33x = 3.3 V, DVDD18x = 1.8 V, DVDD33x = 3.3 V, 1.00 V internal ADC reference, fIN = 2.5 MHz, fS = 60 MSPS, RS = 50 Ω, LNA + PGA gain = 35 dB, LPF cutoff = fSAMPLECH/4, 12-bit operation, temperature = −40°C to +105°C, all specifications guaranteed by testing, unless otherwise noted. Table 3. Parameter1 CLOCK INPUTS (CLK+, CLK−)2 Logic Compliance Differential Input Voltage3 Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance LOGIC INPUTS (PDWN, SCLK, AUX, MUX[0], MUX[1], ZSEL)2 Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC INPUT (CS)2 Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC INPUT (SDI)2 Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC OUTPUT (SDO) Logic 1 Voltage (IOH = 800 μA) Logic 0 Voltage (IOL = 50 μA) LOGIC OUTPUTS (D11 to D0, SFLAG) Logic 1 Voltage (IOH = 2 mA) Logic 0 Voltage (IOL = 2 mA) 1 2 3 Temperature Min Full Full 25°C 25°C 250 Full Full 25°C 25°C 1.2 Full Full 25°C 25°C 1.2 Full Full 25°C 25°C 1.2 0 Full Full 3.0 Full Full 3.0 Typ Max Unit CMOS/LVDS/LVPECL mV p-p V kΩ pF 1.2 20 1.5 3.6 0.3 V V kΩ pF 3.6 0.3 V V kΩ pF DVDD33x + 0.3 0.3 V V kΩ pF 30 0.5 70 0.5 30 2 0.3 V V 0.3 V V See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and testing methodology. Guaranteed by design only. Specified for LVDS and LVPECL only. Rev. D | Page 5 of 28 AD8284 Data Sheet SWITCHING SPECIFICATIONS AVDD18x = 1.8 V, AVDD33x = 3.3 V, DVDD18x = 1.8 V, DVDD33x = 3.3 V, 1.00 V internal ADC reference, fIN = 2.5 MHz, fS = 60 MSPS, RS = 50 Ω, LNA + PGA gain = 35 dB, LPF cutoff = fSAMPLECH/4, 12-bit operation, temperature = −40°C to +105°C, unless otherwise noted. All specifications guaranteed by design only. Table 4. Parameter1 CLOCK Clock Rate Clock Pulse Width High at 60 MSPS Clock Pulse Width Low at 60 MSPS Clock Pulse Width High at 40 MSPS Clock Pulse Width Low at 40 MSPS OUTPUT PARAMETERS Propagation Delay at 60 MSPS Rise Time Fall Time Data Setup Time at 60 MSPS Data Hold Time at 60 MSPS Data Setup Time at 40 MSPS Data Hold Time at 40 MSPS Pipeline Latency 1 Symbol Temperature Min Full Full Full Full Full 10 tEH tEL tEH tEL tPD tR tF tDS tDH tDS tDH Full Full Full Full Full Full Full Full Typ Max Unit 60 8.33 8.33 12.5 12.5 MSPS ns ns ns ns 6 1.9 1.2 8.33 6.0 18 6 7 ns ns ns ns ns ns ns Clock cycles See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and testing methodology. Timing and Switching Diagram N N –1 INAx tEL tEH CLK– CLK+ D11 to D0 N–7 N–6 tDH N–5 N–4 N–3 Figure 2. Timing Definitions for Switching Specifications Rev. D | Page 6 of 28 N–2 N–1 N 10992-002 tDS tPD Data Sheet AD8284 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Electrical AVDD18, AVDD18 ADC to AGND AVDD33, AVDD33REF to AGND DVDD18, DVDD18CLK to AGND DVDD33CLK, DVDD33DRV, and DVDD33SPI to AGND Analog Inputs INx+, INx− to AGND Auxiliary Inputs INADC+, INADC− to AGND Digital Outputs (D11 to D0, SDO) and SDI to AGND CLK+, CLK− to AGND PDWN, SCLK, CS, AUX, ZSEL to AGND RBIAS, VREF to AGND Environmental Operating Temperature Range (Ambient) Storage Temperature Range (Ambient) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Rating −0.3 V to +2.0 V −0.3 V to +3.9 V −0.3 V to +2.0 V −0.3 V to +3.9 V −0.3 V to +3.9 V Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION −0.3 V to +2.0 V −0.3 V to +3.9 V −0.3 V to +3.9 V −0.3 V to +3.9 V −0.3 V to +2.0 V −40°C to +105°C −65°C to +150°C 150°C 300°C Rev. D | Page 7 of 28 AD8284 Data Sheet NC DVDD33DRV D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DVDD33DRV NC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 NC NC 1 SFLAG 2 PDWN 3 DVDD18 4 45 CLK+ SCLK 5 44 CLK– PIN 1 47 TEST4 46 DVDD18CLK 43 DVDD33CLK CS 6 AD8284 SDI 7 SDO 8 TOP VIEW (Not to Scale) AUX 9 42 AVDD33REF 41 BAND 40 VREF MUX[0] 10 39 RBIAS MUX[1] 11 38 APOUT ZSEL 12 37 ANOUT TEST1 13 36 TEST3 TEST2 14 35 AVDD18ADC DVDD33SPI 15 34 AGND NC 16 33 NC NOTES 1. TIE THE EXPOSED PAD ON THE BOTTOM SIDE TO THE ANALOG GROUND PLANE. 2. NC = NO CONNECTION. TIE NC TO ANY POTENTIAL. 10992-003 NC AVDD18 INADC– INADC+ AVDD33 IND– IND+ INC– INC+ INB– INB+ INA– INA+ AVDD33 NC AVDD18 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Figure 3. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1 2 3 Mnemonic NC SFLAG PDWN 4 5 6 7 8 9 10 11 12 DVDD18 SCLK CS SDI SDO AUX MUX[0] MUX[1] ZSEL 13 14 15 16 17 18 19 20 21 22 23 TEST1 TEST2 DVDD33SPI NC NC AVDD18 AVDD33 INA+ INA− INB+ INB− Description No Connection. Tie NC to any potential. Saturation Flag. Full Power-Down. A logic high on PDWN overrides the SPI and powers down the part; a logic low allows selection through the SPI. 1.8 V Digital Supply. Serial Clock. Chip Select. Serial Data Input. Serial Data Output. Auxiliary Channel. A logic high on AUX switches the AUX channel to ADC (INADC+/INADC−). Digital Control for Mux Channel Selection. Digital Control for Mux Channel Selection. Input Impedance Select. A logic high on ZSEL overrides the SPI and sets the input impedance to 200 kΩ; a logic low allows selection through the SPI. Test. Do not use the TEST1 pin; tie TEST1 to ground. Test. Do not use the TEST2 pin; tie TEST2 to ground. 3.3 V Digital Supply, SPI Port. No Connection. Tie NC to any potential. No Connection. Tie NC to any potential. 1.8 V Analog Supply. 3.3 V Analog Supply. Positive Mux Analog Input for Channel A. Negative Mux Analog Input for Channel A. Positive Mux Analog Input for Channel B. Negative Mux Analog Input for Channel B. Rev. D | Page 8 of 28 Data Sheet Pin No. 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Mnemonic INC+ INC− IND+ IND− AVDD33 INADC+ INADC− AVDD18 NC NC AGND AVDD18ADC TEST3 ANOUT APOUT RBIAS VREF BAND AVDD33REF DVDD33CLK CLK− CLK+ DVDD18CLK TEST4 NC NC DVDD33DRV D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DVDD33DRV NC EP AD8284 Description Positive Mux Analog Input for Channel C. Negative Mux Analog Input for Channel C. Positive Mux Analog Input for Channel D. Negative Mux Analog Input for Channel D. 3.3 V Analog Supply. Positive Analog Input for Alternate Channel (ADC Only). Negative Analog Input for Alternate Channel (ADC Only). 1.8 V Analog Supply. No Connection. Tie NC to any potential. No Connection. Tie NC to any potential. Ground. 1.8 V Analog Supply. Test. Do not use the TEST3 pin; tie TEST3 to ground. Analog Output. ANOUT is for debug purposes only. Leave ANOUT floating. Analog Output. APOUT is for debug purposes only. Leave APOUT floating. External Resistor. The RBIAS pin sets the internal ADC core bias current. Voltage Reference Input/Output. Band Gap Voltage. BAND is for debug purposes only. Leave BAND floating. 3.3 V Analog Supply. 3.3 V Digital Supply. Clock Input Complement. Clock Input True. 1.8 V Digital Supply. Test. Do not use the TEST4 pin; tie TEST4 to ground. No Connection. Tie NC to any potential. No Connection. Tie NC to any potential. 3.3 V Digital Supply. ADC Data Output (MSB). ADC Data Output. ADC Data Output. ADC Data Output. ADC Data Output. ADC Data Output. ADC Data Output. ADC Data Output. ADC Data Output. ADC Data Output. ADC Data Output. ADC Data Output (LSB). 3.3 V Digital Supply. No Connection. Tie NC to any potential. Exposed Pad. Tie the exposed pad on the bottom side to the analog ground plane. Rev. D | Page 9 of 28 AD8284 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS AVDD18x = 1.8 V, AVDD33x = 3.3 V, TA = 25°C, fS = 60 MSPS, RIN = 200 kΩ, VREF = 1.0 V. 60 10 35dB 40 9 29dB 8 7 NOISE (nV/√Hz) 23dB 17dB 0 –20 6 17dB 5 4 23dB 3 2 –40 1 1 10 100 FREQUENCY (MHz) 35dB 0 0.1 10992-004 –60 0.1 29dB 1 10992-007 GAIN (dB) 20 10 FREQUENCY (MHz) Figure 4. Channel Gain vs. Frequency Figure 7. Short-Circuit Input Referred Noise vs. Frequency 30 210 20 180 GAIN (dB) 120 90 –10 –20 60 –30 30 17.0 17.2 17.4 –40 10992-005 0 16.8 0 17.6 CODE 00 80 08 88 10 90 18 98 20 A0 1 28 A8 30 B0 38 B8 40 C0 10 10992-008 NUMBER OF HITS 10 150 50 FREQUENCY (MHz) Figure 8. Filter Frequency Response Figure 5. Gain Histogram (Gain = 17 dB) 200 180 350 160 300 NOISE (nV/√Hz) 200 150 35dB 120 100 80 29dB 60 100 40 0 28.5 28.8 29.1 29.4 29.7 CODE 30.0 0 0.1 23dB 17dB 1 10 FREQUENCY (MHz) Figure 9. Short-Circuit Output Referred Noise vs. Frequency Figure 6. Gain Histogram (Gain = 29 dB) Rev. D | Page 10 of 28 10992-009 20 50 10992-006 NUMBER OF HITS 140 250 Data Sheet AD8284 1,000,000 100,000 80 NUMBER OF HITS 1,000 100 60 40 10 0.1 1 10 10992-010 1 0.01 20 100 FREQUENCY (MHz) 0 –60 –40 –20 0 20 40 60 CODE Figure 10. RIN vs. Frequency Figure 12. Channel Offset Distribution (Gain = 17 dB) 30 80 17dB NUMBER OF HITS 20 23dB 15 35dB 40 20 5 0 0.1 60 1 FREQUENCY (MHz) 10 0 –200 –100 0 100 CODE Figure 13. Channel Offset Distribution (Gain = 35 dB) Figure 11. Noise Figure vs. Frequency Rev. D | Page 11 of 28 200 10992-013 10 29dB 10992-011 NOISE FIGURE (dB) 25 10992-012 IMPEDANCE (Ω) 10,000 AD8284 Data Sheet THEORY OF OPERATION RADAR RECEIVE PATH AFE these performance metrics include the LNA noise, PGA gain range, AAF cutoff characteristics, and ADC sample rate and resolution. The primary application for the AD8284 is high speed ramp, frequency modulated, continuous wave (HSR-FMCW) radar requiring baseband signal bandwidths of up to 15 MHz. Figure 14 shows a simplified block diagram of an HSR-FMCW radar system. The AD8284 includes a multiplexer (mux) in front of the analog signal chain as a cost-saving alternative to having an AFE for each channel. The mux can be switched between active inputs using the mux pins or through the SPI port. The signal chain requires multiple channels, each of which is routed into a low noise amplifier (LNA), a programmable gain amplifier (PGA), an antialiasing filter (AAF), and an analog-todigital converter (ADC). The AD8284 provides all of these key components in a single 10 mm × 10 mm TQFP package. The AD8284 also includes a saturation detection circuit that indicates when the LNA or PGA signals are no longer in the linear region. This feature helps detect fault conditions that might otherwise be filtered out by the AAF. The performance of each component is designed to meet the demands of an HSR-FMCW radar system. Some examples of REF. OSCILLATOR PA VCO CHIRP RAMP GENERATOR AD8284 SATURATION DETECTION DSP LNA PGA AAF 10992-014 MUX 12-BIT ADC ANTENNA Figure 14. Simplified Block Diagram, HSR-FMCW Radar System Rev. D | Page 12 of 28 RBIAS VREF DVDD33x DVDD18 SFLAG PDWN AVDD33 ZSEL AD8284 MUX[1] TO MUX[0] AVDD18 Data Sheet REFERENCE INA+ INA– AD8284 SATURATION DETECTION INB+ INB– MUX LNA INC+ PGA AAF MUX 12-BIT ADC CLK+ CLK– IND+ AUX INC– IND– D0 TO D11 INADC+ INADC– 10992-015 SDI SDO SCLK CS SPI Figure 15. Simplified Block Diagram CHANNEL OVERVIEW The AD8284 contains a four-input mux, an LNA, a PGA, and an AAF in the signal path, as shown in Figure 15. The signal chain input impedance can be either 200 Ω or 200 kΩ. The PGA has selectable gains that result in channel gains ranging from 17 dB to 35 dB. The AAF has a three-pole elliptical response with a selectable cutoff frequency from 9 MHz to 15 MHz. The signal path is fully differential throughout to maximize signal swing and reduce even-order distortion. The LNA is designed to be driven from either a differential or single-ended signal source. Multiplexer The AD8284 has a multiplexer (mux) at the input to switch as many as four differential channels into the signal chain. The active mux channel is controlled by the SPI port or by using the external pins, MUX[0] and MUX[1]. The relationship between the input code and the selected mux channel is listed in Table 7. Table 7. Digital Input Values to Select the Active ADC Channel AUX 1 0 0 0 0 MUX[1] X 0 0 1 1 MUX[0] X 0 1 0 1 Active Channel AUX A B C D The external pins are the default method for selecting the active mux channel but the SPI Register 0x0C can also control the mux. Bit 3 of Register 0x0C specifies whether the SPI or the external pins control the mux. Low Noise Amplifier Good noise performance relies on a proprietary ultralow noise LNA at the beginning of the signal chain; the LNA minimizes the noise contributions from the PGA and AAF that are next in the signal chain. The input impedance can be either 200 Ω or 200 kΩ, the value of which is selected through the SPI port or by the ZSEL pin. The LNA supports differential output voltages as high as 5.0 V p-p with positive and negative excursions of ±1.25 V from a commonmode voltage of 1.5 V. Because the output saturation level is fixed, the channel gain sets the maximum input signal before saturation. Low value feedback resistors and the current driving capability of the output stage allow the LNA to achieve a low input referred noise voltage of 3.5 nV/√Hz at a channel gain of 35 dB. The use of a fully differential topology and negative feedback minimizes second-order distortion. Differential signaling enables smaller swings at each output, further reducing third-order distortion. Recommendation To achieve the best possible noise performance, it is important to match the impedances seen by the positive and negative inputs. Matching the impedances ensures that the signal path rejects any common-mode noise. Rev. D | Page 13 of 28 AD8284 Data Sheet Antialiasing Filter reprogramming the filter cutoff scaling via the SPI, or after changing the ADC sample rate. Occasional retuning during an idle time is recommended to compensate for temperature drift. The AAF uses a combination of poles and zeros to create a third-order elliptic filter. An elliptic filter is used to achieve a sharp roll-off after the cutoff frequency. This architecture achieves a −30 dB per octave roll-off in the first octave after the cutoff frequency. A cutoff frequency range of 9 MHz to 15 MHz is possible, for example • • The filter uses on-chip tuning to trim the internal resistors and capacitors to set the desired cutoff frequency. The tuning method reduces variations in the cutoff frequency due to standard IC process tolerances of resistors and capacitors. ADC clock: 40 MHz Default tuned cutoff frequency = (40 MHz ÷ 3) × 1.125 = 15 MHz The autotune cycle takes several clock cycles to complete. During this time, the mux channels, A to D, are not operational; however, the AUX input can be used during the autotuning cycle. The default tuning settings for a −3 dB low-pass filter cutoff is 1/3 × 1.125 × the ADC sample clock frequency. This setting can be changed to 1/4 the ADC sample clock frequency. The cutoff can also be scaled from 0.75 to 1.25 (in 0.0625 increments) times these frequencies through the SPI. Saturation Flag The saturation flag function detects overvoltage conditions that may push the LNA or PGA out of their linear regions. The flag is set when the PGA output voltage exceeds 2.0 V p-p or the LNA output voltage exceeds 4.0 V p-p. This function is particularly useful for detecting saturation events that may be filtered out by the AAF and are, therefore, undetectable by monitoring the ADC output. Tuning is normally off and is initiated by the user via the SPI port. After the filter is tuned to a specific frequency, it remains at that frequency until another tuning sequence is initiated. The tuning process can take up to 2048 clock cycles. The filter defaults to its highest frequency setting before it is tuned. To maintain the expected ratio of clock frequency to cutoff frequency, tune the filter after initial power-up, after When the saturation flag trips, it remains on for a minimum of 25 ns after the saturation event has ended. SATURATION DETECTION +REF VX –REF +REF VMID VMID VX MUX 200Ω 200kΩ –REF 2pF 20kΩ 50Ω INx+ LNA 50Ω 200Ω VMID 200kΩ ADC PGA AAF 2pF 20kΩ VMID AD8284 Figure 16. Simplified Block Diagram of the Analog Channel Rev. D | Page 14 of 28 10992-016 INx– Data Sheet AD8284 ADC 3.3V 50Ω* VFAC3 OUT AD9515/AD9520-0 0.1µF 0.1µF 0.1µF ADC AD8284 CLK– 240Ω *50Ω RESISTOR IS OPTIONAL. Figure 18. Differential PECL Sample Clock Figure 17 shows the preferred method for clocking the AD8284. A low jitter clock source, such as the Valpey Fisher oscillator, VFAC3-BHL (50 MHz), is converted from single-ended to differential using an RF transformer. The back-to-back Schottky diodes across the secondary transformer limit clock excursions into the AD8284 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD8284 and preserves the fast rise and fall times of the signal, which are critical to low jitter performance. 50Ω* VFAC3 AD9515/AD9520-0 0.1µF OUT 0.1µF 50Ω 100Ω 100Ω 0.1µF LVDS DRIVER 10992-019 *50Ω RESISTOR IS OPTIONAL. Figure 19. Differential LVDS Sample Clock In some applications, it is acceptable to drive the sample clock inputs with a single-ended CMOS signal. In such applications, drive CLK+ directly from a CMOS gate, and bypass the CLK− pin to ground with a 0.1 μF capacitor in parallel with a 39 kΩ resistor (see Figure 20). Although the CLK+ input circuit supply is via Pin 46, DVDD18CLK, this input is designed to withstand input voltages of up to 3.3 V, making the selection of the logic voltage of the driver very flexible. The AD9515/AD9520-0 family of parts can be used to provide 3.3 V inputs (see Figure 21). In this case, the 39 kΩ resistor is not needed. 3.3V AD9515/AD9520-0 VFAC3 OUT 0.1µF CLK 50Ω* 1.8V CMOS DRIVER OPTIONAL 0.1µF 100Ω CLK– CLK+ 0.1µF ADC AD8284 *50Ω 39kΩ RESISTOR IS OPTIONAL. 10992-017 CLK– CLK+ ADC AD8284 CLK SCHOTTKY DIODES: HSM2812 ADC AD8284 CLK– 0.1µF 0.1µF 0.1µF CLK+ CLK 3.3V MINI-CIRCUITS® ADT1-1WT, 1:1Z 0.1µF XFMR 0.1µF CLK 10992-020 For optimum performance, clock the AD8284 sample clock inputs (CLK+ and CLK−) with a differential signal. This signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or by using capacitors; these pins are biased internally and require no additional bias. 3.3V Figure 20. Single-Ended 1.8 V CMOS Sample Clock 3.3V Figure 17. Transformer-Coupled Differential Clock VFAC3 OUT If a low jitter clock is available, another option is to ac-couple a differential PECL or LVDS signal to the sample clock input pins as shown in Figure 18 and Figure 19. The AD9515/AD9520-0 family of clock drivers offers excellent jitter performance. AD9515/AD9520-0 0.1µF CLK 50Ω* 3.3V CMOS DRIVER OPTIONAL 0.1µF 100Ω CLK 0.1µF *50Ω 0.1µF CLK+ ADC AD8284 CLK– RESISTOR IS OPTIONAL. Figure 21. Single-Ended 3.3 V CMOS Sample Clock Rev. D | Page 15 of 28 10992-021 CLOCK INPUT CONSIDERATIONS VFAC3 100Ω PECL DRIVER 240Ω The AD8284 allows direct access to the ADC when the mux settings are used to select the AUX channel. When this channel is selected, the inputs of the ADC can be accessed using the INADC+ and INADC− pins. To ensure enough headroom for full-scale, differential, 2.0 V p-p input signals, bias the INADC± pins with a 0.9 V common-mode voltage. 0.1µF CLK+ CLK AUX CHANNEL OUT 0.1µF CLK 10992-018 The AD8284 uses a pipelined ADC architecture. The quantized output from each stage is combined into a 12-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample while the remaining stages operate on preceding samples. Sampling occurs on the rising edge of the clock. The output staging block aligns the data and passes the data to the output buffers. AD8284 Data Sheet CLOCK DUTY CYCLE CONSIDERATIONS CS PIN Typical high speed ADCs use both clock edges to generate a variety of internal timing signals. As a result, these ADCs may be sensitive to the clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD8284 contains a duty cycle stabilizer (DCS) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of the AD8284. The CS pin is required to operate the SPI. It has an internal 70 kΩ pull-up resistor that pulls this pin high and is both 1.8 V and 3.3 V tolerant. When the DCS is on, noise and distortion performance are nearly flat for a wide range of duty cycles. However, some applications may require the DCS function to be off. If so, note that the dynamic range performance can be affected when operating in this mode. See Table 10 for more details on using this feature. The duty cycle stabilizer uses a delay locked loop (DLL) to create the nonsampling edge. As a result, any changes to the sampling frequency require approximately eight clock cycles to allow the DLL to acquire and lock to the new rate. CLOCK JITTER CONSIDERATIONS High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fA) due only to aperture jitter (tJ) can be calculated by SNR Degradation = 20 × log 10[1/2 × π × fA × tJ] In this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and ADC aperture jitter. IF undersampling applications are particularly sensitive to jitter. In cases where aperture jitter may affect the dynamic range of the AD8284, treat the clock input as an analog signal. Separate power supplies for clock drivers from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal controlled oscillators make the best clock sources, such as the Valpey Fisher VFAC3 series. If the clock is generated from another type of source by using the sequential steps of gating, dividing, or other methods, it should be retimed by the original clock during the last step in that sequence. See the AN-501 Application Note and the AN-756 Application Note for more information about how jitter performance relates to ADCs. SDI AND SDO PINS The SDI and SDO pins are required to operate the SPI. The SDI pin has an internal 30 kΩ pull-down resistor that pulls this pin low and is 1.8 V and 3.3 V tolerant. The SDO output pin is 3.3 V logic. SCLK PIN The SCLK pin is required to operate the SPI. It has an internal 30 kΩ pull-down resistor that pulls this pin low and is both 1.8 V and 3.3 V tolerant. RBIAS PIN To set the internal core bias current of the ADC, place a resistor nominally equal to 10.0 kΩ to ground at the RBIAS pin. Using a resistor other than the recommended 10.0 kΩ resistor for RBIAS degrades the performance of the device. Therefore, it is imperative that at least a 1.0% tolerance on this resistor be used to achieve consistent performance. VOLTAGE REFERENCE A stable and accurate 0.5 V voltage reference is built into the AD8284. This is gained up internally by a factor of 2, setting VREF to 1.0 V, which results in a full-scale differential input span of 2.0 V p-p for the ADC. VREF is set internally by default, but the VREF pin can be driven externally with a 1.0 V reference to achieve more accuracy. However, the AD8284 is not specified for ADC full-scale ranges below 2.0 V p-p. When applying decoupling capacitors to the VREF pin, use ceramic, low ESR capacitors. Place these capacitors close to the reference pin and on the same layer of the PCB as the AD8284. The VREF pin should have both a 0.1 μF capacitor and a 1 μF capacitor connected in parallel to the analog ground. These capacitor values are recommended for the ADC to properly settle and acquire the next valid sample. POWER AND GROUND RECOMMENDATIONS When connecting power to the AD8284, it is recommended that two separate 1.8 V supplies and two separate 3.3 V supplies be used: one supply each for analog 1.8 V (AVDD18x), digital 1.8 V (DVDD18x), analog 3.3 V (AVDD33x), and digital 3.3 V (DVDD33x). If only one supply is available for both analog and digital, for example, AVDD18x and DVDD18x, route the supply to AVDD18x first and then tap the supply off and isolate it with a ferrite bead or a filter choke preceded by decoupling capacitors for the DVDD18x. The same method is used for the analog and digital 3.3 V supplies. Use several decoupling capacitors on all supplies to cover both high and low frequencies. Locate these capacitors close to the point of entry at the printed circuit board (PCB) level and close to the AD8284 using minimal trace lengths. The 12 power supply pins are separated into four power supply domains, AVDD18, AVDD33, DVDD18, and DVDD33. Each pin within a domain must be powered simultaneously, but each domain can be turned on independently of the other domains. A single PCB ground plane should be sufficient when using the AD8284. With proper decoupling and smart partitioning of the analog, digital, and clock sections of the PCB, optimum performance can be easily achieved. Rev. D | Page 16 of 28 Data Sheet AD8284 EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS It is required that the exposed pad on the underside of the device be connected to a quiet analog ground to achieve the best electrical and thermal performance of the AD8284. Mate an exposed continuous copper plane on the PCB to the AD8284 exposed pad, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. To maximize the coverage and adhesion between the device and the PCB, it is recommended that the continuous copper pad be partitioned by overlaying a silkscreen or solder mask to divide the copper pad into uniform sections. This partitioning helps to ensure several tie points between the PCB and the device during the reflow process. Using one continuous plane with no partitions guarantees only one tie point between the AD8284 and the PCB. For more information about packaging and for additional PCB layout examples, see the AN-772 Application Note. Rev. D | Page 17 of 28 AD8284 Data Sheet SERIAL PORT INTERFACE (SPI) The AD8284 serial port interface allows the user to configure the signal chain for specific functions or operations through a structured register space provided inside the chip. The SPI offers the user added flexibility and customization depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided into fields, as documented in the Memory Map section. Detailed operational information can be found in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Four pins define the serial port interface, or SPI: the SCLK, SDI, SDO, and CS pins. The serial clock pin (SCLK) synchronizes the read and write data presented to the device. The serial data input and output pins, SDI and SDO, allow data to be sent to and read from the internal memory map registers of the device. The chip select pin (CS) is an active low control that enables or disables the read and write cycles (see Table 8). Table 8. Serial Port Interface Pins Pin SCLK SDI SDO CS Function Serial clock. The serial shift clock input. SCLK is used to synchronize serial interface reads and writes. Serial data input. Serial data output. Chip select (active low). This control gates the read and write cycles. The falling edge of CS, in conjunction with the rising edge of SCLK, determines the start of the framing sequence. During an instruction phase, a 16-bit instruction is transmitted, followed by one or more data bytes, which is determined by Bit Field W0 and Bit Field W1. See Figure 22 and Table 9 for an example of the serial timing and its definitions. In normal operation, CS signals to the device that SPI commands are about to be received and processed. When CS is brought low, the device processes SCLK and SDI to process instructions. Normally, CS remains low until the communication cycle is complete. However, if the AD8284 is connected to a slow device, CS can be brought high between bytes, allowing older microcontrollers enough time to transfer data into the shift registers. CS can be stalled when transferring one, two, or three bytes of data. When W0 and W1 are set to 11, the device enters streaming mode and continues to process data, either reading or writing, until CS is taken high to end the communication cycle. This allows complete memory transfers without the need to provide additional instructions. Regardless of the mode, if CS is taken high in the middle of any byte transfer, the SPI state machine is reset and the device waits for a new instruction. In addition to the operation modes, the SPI port can be configured to operate in different manners. For applications that do not require a control port, the CS line can be tied and held high. This places the remainder of the SPI pins in their secondary mode as defined in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. CS can also be tied low to enable 3-wire mode. When CS is tied low, SCLK, SDO, and SDI are the only pins required for communication. Although the device is synchronized during power-up, caution must be exercised when using this mode to ensure that the serial port remains synchronized with the CS line. When operating in 3-wire mode, it is recommended that a 1-, 2-, or 3-byte transfer be used exclusively. Without an active CS line, streaming mode can be entered but not exited. Data can be sent in MSB-first or LSB-first mode. MSB-first mode is the default at power-up and can be changed by adjusting the configuration register. For more information about this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. HARDWARE INTERFACE The pins described in Table 8 constitute the physical interface between the user’s programming device and the serial port of the AD8284. The SCLK, SDI, and CS pins function as inputs when using the SPI interface. The SDO pin is an output during readback. This interface is flexible enough to be controlled by either serialprogrammable read-only memory (PROM) or PIC microcontrollers. This provides the user with alternative means, other than a full SPI controller, for programming the device (see the AN-812 Application Note). Rev. D | Page 18 of 28 Data Sheet AD8284 tDS tS tHI CS tH tCLK tDH tLO SCLK DON’T CARE SDI DON’T CARE DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 SDO DON’T CARE D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 DON’T CARE D0 DON’T CARE SCLK OUTPUT DRIVER OFF tDIS_SDO Figure 22. Serial Timing Details Table 9. Serial Timing Definitions Parameter tDS tDH tCLK tS tH tHI tLO tDIS_SDO Minimum Timing (ns) 5 2 40 5 2 16 16 10 Description Setup time between the data and the rising edge of SCLK. Hold time between the data and the rising edge of SCLK. Period of the clock. Setup time between CS and SCLK. Hold time between CS and SCLK. Minimum period that SCLK should be in a logic high state. Minimum period that SCLK should be in a logic low state. Minimum time it takes the SDO pin to switch between an output and a high impedance node, relative to the rising edge of SCLK. Rev. D | Page 19 of 28 10992-022 OUTPUT DRIVER ON AD8284 Data Sheet MEMORY MAP READING THE MEMORY MAP TABLE Caution Each row in the memory map table has eight address locations. The memory map is roughly divided into three sections: the chip configuration registers map (Address 0x00 and Address 0x01), the device index and transfer registers map (Address 0x04 to Address 0xFF), and the ADC channel functions registers map (Address 0x08 to Address 0x2C). All registers except for Register 0x00 and Register 0xFF are buffered with a master slave latch and require writing to the transfer bit. For more information about this and other functions, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. LOGIC LEVELS The leftmost column of the memory map indicates the register address number, and the default value is shown in the second rightmost column. An explanation of various registers follows: “bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit.” Similarly, “bit is cleared” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit. The Bit 7 (MSB) column is the start of the default hexadecimal value that is given. For example, Address 0x09, the GLOBAL_ CLOCK register, has a default value of 0x01, meaning that Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001 in binary. This setting is the default for the duty cycle stabilizer in the on condition. By writing a 0 to Bit 0 of this address followed by writing 0x01 to the SW transfer bit in Register 0xFF, the duty cycle stabilizer is turned off. It is important to follow each writing sequence with a write to the SW transfer bit to update the SPI registers. RESERVED LOCATIONS Do not write to undefined memory except when writing the default values suggested in this data sheet. Addresses that have values marked as 0 should be considered reserved and have a 0 written into their registers during power-up. DEFAULT VALUES After a reset, critical registers are automatically loaded with default values. These values are indicated in Table 10, where an X refers to an undefined feature. Rev. D | Page 20 of 28 Data Sheet AD8284 Table 10. Memory Map Registers1 Addr. (Hex) Register Name Chip Configuration Registers 0x00 CHIP_PORT_CONFIG 0x01 Bit 7 (MSB) 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB first 1 = on 0 = off (default) Soft reset 1 = on 0 = off (default) 1 1 Soft reset 1 = on 0 = off (default) LSB first 1 = on 0 = off (default) Default Value Default Notes/ Comments 0 0x18 Mirror the nibbles to correctly set LSB-first or MSB-first mode, regardless of shift mode. The default is a unique chip ID, specific to the AD8284. This is a read-only register. Chip ID Bits[7:0] (AD8284 = 0xAA, default) CHIP_ID Device Index and Transfer Registers 0xFF DEVICE_UPDATE X Channel Functions Registers 0x08 GLOBAL_MODES Bit 0 (LSB) Read only 0x00 Synchronously transfers data from the master shift register to the slave. Internal powerdown mode 00 = chip run (default) 01 = full powerdown 11 = reset 0xF0 Determines the power-down mode (global). Duty cycle stabilizer 1 = on (default) 0 = off 00 = Channel A (default) 01 = Channel B 10 = Channel C 11 = Channel D 0x01 Turns the internal duty cycle stabilizer on and off (global). 0x04 Sets which mux input channel is in use and whether to power down unused channels. 0x00 When this register is set, the test data is placed on the output pins in place of normal data. (Local, except for PN sequence.) X X X X Channel A buffer power 0 = power off 1 = power on (default) Channel B buffer power 0= power off 1= power on (default) Channel C buffer power 0 = power off 1 = power on (default) Channel D buffer power 0 = power off 1 = power on (default) X X X X Channel powerdown 0= power on (default) 1= power off X X 0 = signal channel (A, B, C, D) on (default) 1 = AUX channel on 0 = use external pins (default) 1 = use internal registers Reset PN long gen 1 = on 0 = off (default) Reset PN short gen 1 = on 0 = off (default) Output test mode—see Table 11 0000 = off (default) 0001 = midscale short 0010 = +FS short 0011 = −FS short 0100 = checkerboard output 0101 = PN sequence long 0110 = PN sequence short 0111 = one-/zero-word toggle 1000 = user input 1001 = 1-bit/0-bit toggle 1010 = 1× sync 1011 = one bit high 1100 = mixed bit frequency (format determined by the OUTPUT_MODE register) 0x09 GLOBAL_CLOCK X 0x0C FLEX_MUX_CONTROL X 0x0D FLEX_TEST_IO Power down unused channels 0 = PD powerdown (default) 1= power on User test mode 00 = off (default) 01 = on, single alternate 10 = on, single once 11 = on, alternate once Rev. D | Page 21 of 28 X 0 = all channels are off 1= selected channel is on (default) X SW transfer 1 = on 0 = off (default) X X AD8284 Addr. (Hex) 0x0E Register Name TEST_REGISTER 0x0F FLEX_CHANNEL_INPUT Data Sheet Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Enable analog outputs (APOUT, ANOUT) 0x01 = analog output enabled Filter cutoff frequency control 00000 = 1.25 × 1/4 × fSAMPLECH 00001 = 1.1875 × 1/4 × fSAMPLECH 00010 = 1.125 × 1/4 × fSAMPLECH 00011 = 1.0625 × 1/4 × fSAMPLECH 00100 = 1.0 × 1/4 × fSAMPLECH 00101 = 0.9375 × 1/4 × fSAMPLECH 00110 = 0.875 × 1/4 × fSAMPLECH 00111 = 0.8125 × 1/4 × fSAMPLECH 01000 = 0.75 × 1/4 × fSAMPLECH 01001 to 01111 = reserved X Bit 1 Bit 0 (LSB) Default Value 0x00 X X 0x90 Default Notes/ Comments Routes the differential output of the AAF to APOUT and ANOUT. Low-pass filter cutoff (global). fSAMPLECH = ADC sample rate. Note that the absolute range is limited to 9 MHz to 15 MHz. 10000 = 1.25 × 1/3 × fSAMPLECH 10001 = 1.1875 × 1/3 × fSAMPLECH 10010 = 1.125 × 1/3 × fSAMPLECH (default) 10011 = 1.0625 × 1/3 × fSAMPLECH 10100 = 1.0 × 1/3 × fSAMPLECH 10101 = 0.9375 × 1/3 × fSAMPLECH 10110 = 0.875 × 1/3 × fSAMPLECH 10111 = 0.8125 × 1/3 × fSAMPLECH 11000 = 0.75 × 1/3 × fSAMPLECH 11001 to 11111 = reserved 6-bit LNA offset adjustment 00 0000 for LNA offset low 10 0000 for LNA offset mid (default) 11 1111 for LNA offset high 000 = 17 dB X 001 = 17 dB 010 = 17 dB 011 = 23 dB 100 = 29 dB (default) 101 = 35 dB LNA bias X X 00 = high (default) 01 = mid to high 10 = mid to low 11 = low 0 = offset binary 1= X 1 = twos compleoutput ment (default) invert (local) Output drive current 0000 = low … 1111 = high (default) 0x20 LNA force offset correction. 0x04 Total LNA + PGA gain adjustment (local). 0x00 LNA bias current adjustment (global). 0x01 Configures the outputs and the format of the data. Selects output drive strength to limit the noise added to the channels by output switching. Select internal reference (recommended default) or external reference (global); adjust internal reference. User defined Pattern 1, LSB. User defined Pattern 1, MSB. 0x10 FLEX_OFFSET X X 0x11 FLEX_GAIN_1 X X X X 0x12 FLEX_BIAS_CURRENT X X X X 0x14 FLEX_OUTPUT_MODE X X X X 0x15 FLEX_OUTPUT_ADJUST X X X 0x18 FLEX_VREF 0 = enable Data Bits[11:0] 1= disable Data Bits[11:0] X 0= internal reference (default) 1= external reference X X X X 0x19 FLEX_USER_PATT1_LSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 0x1A FLEX_USER_PATT1_ MSB B15 B14 B13 B12 B11 B10 B9 B8 0x00 Rev. D | Page 22 of 28 Internal reference adjust 00 = 0.625 V 01 = 0.750 V 10 = 0.875 V 11 = 1.000 V (default) 0x0F 0x03 Data Sheet Addr. (Hex) 0x1B AD8284 Register Name FLEX_USER_PATT2_LSB 0x2B FLEX_USER_PATT2_ MSB FLEX_FILTER 0x2C CH_IN_IMP 0x1C 1 Bit 7 (MSB) B7 Bit 6 B6 Bit 5 B5 Bit 4 B4 Bit 3 B3 Bit 2 B2 Bit 1 B1 Bit 0 (LSB) B0 Default Value 0x00 B15 B14 B13 B12 B11 B10 B9 B8 0x00 X X X X X 0x00 Saturation detect hysteresis 0 = low hysteresis (25 mV nominal at PGA output) (default) 1 = high hysteresis (nominally 60 mV at PGA output) X X X Input impedance 0 = 200 Ω 1= 200 kΩ (default) 0x61 X Enable X automatic low-pass tuning 1 = on (self clearing) Saturation detector limit adjust 000 = 1.90 V p-p at PGA output 011 = 2.00 V p-p at PGA output (default) 111 = 2.15 V p-p at PGA output Other values reserved (001, 010, 100, 101, 110) Default Notes/ Comments User defined Pattern 2, LSB. User defined Pattern 2, MSB. Enables lowpass filter tuning Saturation detector adjustment and input impedance adjustment (global). X = undefined feature. Table 11. Flexible Output Test Modes1 Output Test Mode Bit Sequence 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1 Pattern Name Off (default) Midscale short +Full-scale short −Full-scale short Checkerboard output PN sequence long PN sequence short One-/zero-word toggle User input 1-bit/0-bit toggle 1× sync One bit high Mixed bit frequency Digital Output Word 1 N/A 1000 0000 0000 1111 1111 1111 0000 0000 0000 1010 1010 1010 N/A N/A 1111 1111 1111 Register 0x19 and Register 0x1A 1010 1010 1010 0000 0011 1111 1000 0000 0000 1010 0011 0011 N/A means not applicable. Rev. D | Page 23 of 28 Digital Output Word 2 N/A Same Same Same 0101 0101 0101 N/A N/A 0000 0000 0000 Register 0x1B and Register 0x1C N/A N/A N/A N/A Subject to Data Format Select N/A Yes Yes Yes No Yes Yes No No No No No No AD8284 Data Sheet APPLICATION CIRCUITS 3.3V AVDD33REF 3.3V 0.1µF DVDD33SPI 0.1µF AVDD33 0.1µF DVDD33CLK 0.1µF AVDD33 0.1µF DVDD33DRV 0.1µF DVDD18 0.1µF 1.8V AVDD18 0.1µF 1.8V AVDD18 0.1µF DVDD18CLK 0.1µF AVDD18ADC 0.1µF DVDD33DRV 0.1µF D0 NC NC 2 3 SFLAG 4 5 6 7 8 12 NC D11 D9 D10 D8 D7 D6 D5 D4 D3 D2 D1 SDI TOP VIEW (Not to Scale) AVDD33REF BAND VREF 13 14 15 RBIAS MUX[1] APOUT ZSEL ANOUT TEST1 TEST3 TEST2 AVDD18ADC DVDD33SPI NC 48 NC 47 46 45 CLK+ 44 CLK– 43 42 41 NC 40 39 10kΩ 38 1% 37 36 NC AVDD18 34 INADC– NC 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AVDD18 NC NC INA+ INADC+ 0.1µF 0.1µF INA– 1µF NC 35 33 0.1µF NC AVDD18 INADC– INADC+ AVDD33 IND– IND+ NC NC AGND INC– NC INC+ 16 INB– IND– 0.1µF 0.1µF INB+ INB– 0.1µF 0.1µF 0.1µF 0.1µF IND+ INC– INC+ NOTES 1. ALL CAPACITORS FOR SUPPLIES AND REFERENCES SHOULD BE PLACED CLOSE TO THE PART. 2. TIE THE EXPOSED PAD ON THE BOTTOM SIDE TO THE ANALOG GROUND PLANE. Figure 23. Differential Inputs Rev. D | Page 24 of 28 10992-023 ZSEL DVDD33CLK MUX[0] 11 MUX[1] AD8284 AUX 10 MUX[0] CS SDO 9 AUX CLK– INB+ SDO SCLK INA– SDI DVDD18 INA+ CS TEST4 CLK+ AVDD33 PDWN SCLK D11 NC DVDD18CLK PDWN AVDD18 SFLAG DVDD33DRV NC D0 NC 1 NC DVDD33DRV 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Data Sheet AD8284 3.3V AVDD33REF 3.3V 0.1µF DVDD33SPI 0.1µF AVDD33 0.1µF DVDD33CLK 0.1µF AVDD33 0.1µF DVDD33DRV 0.1µF DVDD18 0.1µF 1.8V AVDD18 0.1µF 1.8V AVDD18 0.1µF DVDD18CLK 0.1µF AVDD18ADC 0.1µF DVDD33DRV 0.1µF D0 NC NC 15 16 NC D11 DVDD33DRV D9 D10 D8 D7 D6 D5 D4 D3 D2 D1 MUX[0] RBIAS MUX[1] APOUT ZSEL ANOUT TEST1 TEST3 TEST2 AVDD18ADC DVDD33SPI NC NC NC VREF AGND NC NC 47 46 45 CLK+ 44 CLK– 43 42 41 NC 40 39 10kΩ 38 1% 37 36 NC AVDD18 34 INADC– NC 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AVDD18 NC NC INA+ INADC+ 0.1µF 0.1µF INB+ 0.1µF 1µF NC 35 33 0.1µF 0.1µF IND+ INC+ NOTES 1. RESISTOR R (INX– INPUTS) SHOULD MATCH THE OUTPUT IMPEDANCE OF THE INPUT DRIVER. 2. ALL CAPACITORS FOR SUPPLIES AND REFERENCES SHOULD BE PLACED CLOSE TO THE PART. 3. TIE THE EXPOSED PAD ON THE BOTTOM SIDE TO THE ANALOG GROUND PLANE. Figure 24. Single-Ended Inputs Rev. D | Page 25 of 28 10992-024 13 14 BAND AUX 48 NC 12 ZSEL SDO AVDD18 MUX[1] AVDD33REF INADC– 11 TOP VIEW (Not to Scale) INADC+ MUX[0] SDI AVDD33 10 DVDD33CLK IND– 9 AUX AD8284 IND+ SDO CS INC– 8 CLK– INC+ 7 SDI SCLK INB– 6 CS CLK+ INB+ 5 TEST4 DVDD18 INA– PDWN SCLK D11 NC DVDD18CLK PDWN INA+ 4 AVDD33 SFLAG SFLAG AVDD18 2 3 NC D0 NC 1 NC DVDD33DRV 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AD8284 Data Sheet PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS 12.20 12.00 SQ 11.80 1.20 MAX 64 49 48 1 10.20 10.00 SQ 9.80 EXPOSED PAD 0.08 COPLANARITY (PINS DOWN) 16 0.20 0.09 17 7° 3.5° 0° 6.64 BSC SQ BOTTOM VIEW TOP VIEW 1.05 1.00 0.95 64 48 PIN 1 SEATING PLANE 0.15 0.05 49 1 1.00 REF 33 32 (PINS UP) 33 VIEW A 0.50 BSC LEAD PITCH 16 17 32 0.27 0.22 0.17 VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-ACD-HD FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 02-28-2013-A 0.75 0.60 0.45 Figure 25. 64-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] (SV-64-5) Dimensions shown in millimeters ORDERING GUIDE Model1, 2, 3 AD8284WCSVZ AD8284WCSVZ-RL Temperature Range −40°C to +105°C −40°C to +105°C Package Description 64-Lead TQFP_EP, Waffle Pack 64-Lead TQFP_EP, 13” Tape and Reel Package Option SV-64-5 SV-64-5 1 Z = RoHS Compliant Part. W = Qualified for Automotive Applications. 3 Compliant to JEDEC Standard MS-026-ACD-HD. 2 AUTOMOTIVE PRODUCTS The AD8284WCSVZ models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. Rev. D | Page 26 of 28 Data Sheet AD8284 NOTES Rev. D | Page 27 of 28 AD8284 Data Sheet NOTES ©2012–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10992-0-8/15(D) Rev. D | Page 28 of 28