IDT IDT71256L25LB Cmos static ram 256k (32k x 8-bit) Datasheet

CMOS STATIC RAM
256K (32K x 8-BIT)
IDT71256S
IDT71256L
Integrated Device Technology, Inc.
FEATURES:
• High-speed address/chip select time
— Military: 25/30/35/45/55/70/85/100/120/150ns (max.)
— Commercial: 20/25/35/45ns (max.) Low Power only.
• Low-power operation
• Battery Backup operation — 2V data retention
• Produced with advanced high-performance CMOS
technology
• Input and output directly TTL-compatible
• Available in standard 28-pin (300 or 600 mil) ceramic
DIP, 28-pin (600 mil) plastic DIP, 28-pin (300 mil) SOJ
and 32-pin LCC
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT71256 is a 262,144-bit high-speed static RAM
organized as 32K x 8. It is fabricated using IDT’s highperformance, high-reliability CMOS technology.
Address access times as fast as 20ns are available with
power consumption of only 350mW (typ.). The circuit also
offers a reduced power standby mode. When CS goes HIGH,
the circuit will automatically go to, and remain in, a low-power
standby mode as long as CS remains HIGH. In the full standby
mode, the low-power device consumes less than 15µW,
typically. This capability provides significant system level
power and cooling savings. The low-power (L) version also
offers a battery backup data retention capability where the
circuit typically consumes only 5µW when operating off a 2V
battery.
The lDT71256 is packaged in a 28-pin (300 or 600 mil)
ceramic DIP, a 28-pin 300 mil J-bend SOlC, and a 28-pin (600
mil) plastic DIP, and 32-pin LCC providing high board-level
packing densities.
The IDT71256 military RAM is manufactured in compliance
with the latest revision of MIL-STD-883, Class B, making it
ideally suited to military temperature applications demanding
the highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
A0
V CC
262,144 BIT
MEMORY ARRAY
ADDRESS
DECODER
GND
A14
I/O 0
I/O CONTROL
INPUT
DATA
CIRCUIT
I/O 7
CS
OE
WE
CONTROL
CIRCUIT
2946 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AUGUST 1996
1996 Integrated Device Technology, Inc.
DSC-2946/7
7.2
1
IDT71256 S/L
CMOS STATIC RAM 256K (32K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O 0
I/O 1
I/O 2
GND
1
28
2
27
3
26
4
25
24
5
D28-3
P28-1
P28-2
D28-1
SO28-5
6
7
8
9
23
22
21
20
10
12
19
18
17
13
16
14
15
11
TRUTH TABLE(1)
V CC
WE
A13
A8
A9
A11
OE
A10
CS
I/O 7
I/O 6
I/O 5
I/O 4
I/O 3
WE
CS
OE
I/O
X
H
X
High-Z
Standby (ISB)
X
VHC
X
High-Z
Standby (ISB1)
H
L
H
High-Z
Output Disabled
H
L
L
DOUT
Read Data
L
L
X
DIN
Write Data
Function
NOTE:
1. H = VIH, L = VIL, X = Don’t Care
2946 tbl 02
2946 drw 02
ABSOLUTE MAXIMUM RATINGS(1)
WE
INDEX
4
3
2
5
1
29
6
28
7
27
8
26
L32-1
9
25
10
24
11
23
12
22
21
13
14 15 16 17 18 19 20
Rating
Com’l.
Mil.
Unit
VTERM
Terminal Voltage –0.5 to +7.0
with Respect
to GND
–0.5 to +7.0
V
TA
Operating
Temperature
0 to +70
–55 to +125
°C
TBIAS
Temperature
Under Bias
–55 to +125
–65 to +135
°C
TSTG
Storage
Temperature
–55 to +125
–65 to +150
°C
OE
PT
Power Dissipation
1.0
1.0
W
CS
IOUT
DC Output
Current
50
50
mA
32 31 30
I/O 1
I/O 2
GND
NC
I/O 3
I/O 4
I/O 5
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
Symbol
A13
A7
A 12
A14
NC
VCC
DIP/SOJ
TOP VIEW
A8
A9
A11
NC
A10
I/O7
I/O 6
NOTE:
2946 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2946 drw 03
32-Pin LCC
TOP VIEW
PIN DESCRIPTIONS
Name
A0–A14
Addresses
I/O0–I/O7
Data Input/Output
CS
WE
OE
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Description
Symbol
Chip Select
Output Enable
Ground
VCC
Power
CIN
Input Capacitance
CI/O
I/O Capacitance
Conditions
Max. Unit
VIN = 0V
11
pF
VOUT = 0V
11
pF
NOTE:
2946 tbl 04
1. This parameter is determined by device characterization, but is not
production tested.
Write Enable
GND
Parameter(1)
2946 tbl 01
7.2
2
IDT71256S/L
CMOS STATIC RAM 256K (32K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Military
Commercial
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
Min.
Typ.
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
Input High Voltage
—
6.0
V
—
0.8
V
Temperature
GND
VCC
–55°C to +125°C
0V
5.0V ± 10%
VCC
0°C to +70°C
0V
5.0V ± 10%
2946 tbl 05
Parameter
Input Low Voltage
VIL
2.2
–0.5
(1)
Max. Unit
NOTE:
2946 tbl 06
1. VIL (min.) = –3.0V for pulse width less than 20ns, once per cycle.
DC ELECTRICAL CHARACTERISTICS(1, 2)
(VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V)
71256S/L20
Symbol
ICC
ISB
ISB1
Parameter
Power Com’l.
ICC
ISB
ISB1
71256S/L30
71256S/L35
Mil.
Com’l.
Mil.
Com’l.
Mil.
Com’l.
Mil.
Unit
mA
Dynamic Operating Current
CS ≤ VIL, Outputs Open
VCC = Max., f = fMAX(2)
S
—
—
—
150
—
145
—
140
L
135
—
115
130
—
125
105
120
Standby Power Supply
Current (TTL Level)
CS ≥ VIH, VCC = Max.,
Outputs Open, f = fMAX(2)
S
—
—
—
20
—
20
—
20
L
3
—
3
3
—
3
3
3
Full Standby Power Supply
Current (CMOS Level)
CS ≥ VHC, VCC = Max., f = 0
S
—
—
—
20
—
20
—
20
L
0.4
—
0.4
1.5
—
1.5
0.4
1.5
71256S/L45
Symbol
71256S/L25
Parameter
71256S/L55
Power Com’l. Mil. Com’l. Mil.
71256S/L70
Com’l.
Mil. Com’l. Mil. Com'l.
Mil.
Unit
mA
S
—
135
—
135
—
135
—
135
—
135
L
100
115
—
115
—
115
—
115
—
115
Standby Power Supply
Current (TTL Level)
CS ≥ VIH, VCC = Max.,
Outputs Open, f = fMAX(2)
S
—
20
—
20
—
20
—
20
—
20
L
3
3
—
3
—
3
—
3
—
3
Full Standby Power Supply
Current (CMOS Level)
CS ≥ VHC, VCC = Max., f = 0
S
—
20
—
20
—
20
—
20
—
20
L
0.4
1.5
—
1.5
—
1.5
—
1.5
—
1.5
7.2
mA
71256S/L85(3) 71256S/L100(3)
Dynamic Operating Current
CS ≤ VIL, Outputs Open
VCC = Max., f = fMAX(2)
NOTES:
1. All values are maximum guaranteed values.
2. fMAX = 1/tRC, all address inputs cycling at fMAX; f = 0 means no address pins are cycling.
3. Also available: 120 and 150 ns military devices.
mA
mA
mA
2946 tbl 07
3
IDT71256 S/L
CMOS STATIC RAM 256K (32K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
AC Test Load
See Figures 1 and 2
2946 tbl 08
5V
5V
480Ω
480Ω
DATAOUT
DATAOUT
255Ω
255Ω
30pF*
5pF*
2946 drw 05
2946 drw 04
Figure 2. AC Test Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, tWHZ)
Figure 1. AC Test Load
*Includes scope and jig capacitances
DC ELECTRICAL CHARACTERISTICS
VCC = 5.0V ± 10%
IDT71256S
Symbol
Parameter
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
VCC = Max.,
VIN = GND to VCC
MIL.
COM’L.
—
—
—
—
10
5
—
—
—
—
5
2
µA
Output Leakage Current
VCC = Max., CS = VIH,
VOUT = GND to VCC
MIL.
COM’L.
—
—
—
—
10
5
—
—
—
—
5
2
µA
Output Low Voltage
IOL = 8mA, VCC = Min.
—
0.4
—
—
0.4
V
|ILI|
Input Leakage Current
|ILO|
VOL
VOH
Test Condition
IDT71256L
Output High Voltage
IOL = 10mA, VCC = Min.
—
—
0.5
—
—
0.5
IOH = –4mA, VCC = Min.
2.4
—
—
2.4
—
—
V
2946 tbl 09
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L Version Only) VLC = 0.2V, VHC = VCC – 0.2V
Typ. (1)
VCC @
Symbol
Parameter
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR
Chip Deselect to Data
Retention Time
tR(3)
Operation Recovery Time
Test Condition
—
MIL.
COM’L.
CS ≥ VHC
NOTES:
1. TA = +25°C.
2. tRC = Read Cycle Time.
3. This parameter is guaranteed, but not tested.
Max.
VCC @
Min.
2.0v
3.0V
2.0V
3.0V
Unit
2.0
—
—
—
—
V
—
—
—
—
—
—
500
120
800
200
µA
0
—
—
—
—
ns
tRC(2)
—
—
—
—
ns
2946 tbl 10
7.2
4
IDT71256S/L
CMOS STATIC RAM 256K (32K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
LOW VCC DATA RETENTION WAVEFORM
VCC
DATA
RETENTION
MODE
4.5V
VDR ≥2V
t CDR
VIH
CS
4.5V
tR
VIH
VDR
2946 drw 06
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, All Temperature Ranges)
71256L20
71256S25
71256L25
71256S30(3)
71256L30(3)
71256S35
71256L35
71256S45
71256L45
Min.
Max.
Min. Max.
Min.
Max.
Min.
Max.
Min. Max. Unit
(1)
Symbol
Parameter
Read Cycle
tRC
Read Cycle Time
20
—
25
—
30
—
35
—
45
—
ns
tAA
Address Access Time
—
20
—
25
—
30
—
35
—
45
ns
tACS
tCLZ
Chip Select Access Time
—
20
—
25
—
30
—
35
—
45
ns
(2)
Chip Select to Output in Low-Z
5
—
5
—
5
—
5
—
5
—
ns
(2)
Chip Deselect to Output in High-Z
—
10
—
11
—
15
—
15
—
20
ns
tCHZ
tOE
Output Enable to Output Valid
—
10
—
11
—
13
—
15
—
20
ns
(2)
Output Enable to Output in Low-Z
2
—
2
—
2
—
2
—
0
—
ns
(2)
tOHZ
Output Disable to Output in High-Z
2
8
2
10
2
12
2
15
—
20
ns
tOH
Output Hold from Address Change
5
—
5
—
5
—
5
—
5
—
ns
tOLZ
Write Cycle
tWC
Write Cycle Time
20
—
25
—
30
—
35
—
45
—
ns
tCW
Chip Select to End-of-Write
15
—
20
—
25
—
30
—
40
—
ns
tAW
Address Valid to End-of-Write
15
—
20
—
25
—
30
—
40
—
ns
tAS
Address Set-up Time
0
—
0
—
0
—
0
—
0
—
ns
tWP
Write Pulse Width
15
—
20
—
25
—
30
—
35
—
ns
tWR
Write Recovery Time
0
—
0
—
0
—
0
—
0
—
ns
Data to Write Time Overlap
11
—
13
—
14
—
15
—
20
—
ns
tWHZ
Write Enable to Output in High-Z
—
10
—
11
—
15
—
15
—
20
ns
tDH
Data Hold from Write Time
0
—
0
—
0
—
0
—
0
—
ns
Output Active from End-of-Write
5
—
5
—
5
—
5
—
5
—
tDW
(2)
(2)
tOW
NOTES:
1. 0° to +70°C temperature range only.
2. This parameter guaranteed by device characterization, but is not production tested.
3. –55° to +125°C temperature range only.
7.2
ns
2946 tbl 11
5
IDT71256 S/L
CMOS STATIC RAM 256K (32K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, All Temperature Ranges)
71256S55(1)
71256L55(1)
Symbol
Parameter
71256S70(1)
71256L70(1)
71256S85(1)
71256L85(1)
71256S100(1,3)
71256L100(1,3)
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
55
—
70
—
85
—
100
—
ns
tAA
Address Access Time
—
55
—
70
—
85
—
100
ns
tACS
Chip Select Access Time
—
55
—
70
—
85
—
100
ns
tCLZ(2)
Chip Deselect to Output in Low-Z
5
—
5
—
5
—
5
—
ns
(2)
Output Enable to Output in Low-Z
—
25
—
30
—
35
—
40
ns
tCHZ
tOE
Output Enable to Output Valid
—
25
—
30
—
35
—
40
ns
(2)
Output Enable to Output in Low-Z
0
—
0
—
0
—
0
—
ns
(2)
tOHZ
Output Disable to Output in High-Z
0
25
0
30
—
35
—
40
ns
tOH
Output Hold from Address Change
5
—
5
—
5
—
5
—
ns
tOLZ
Write Cycle
tWC
Write Cycle Time
55
—
70
—
85
—
100
—
ns
tCW
Chip Select to End-of-Write
50
—
60
—
70
—
80
—
ns
tAW
Address Valid to End-of-Write
50
—
60
—
70
—
80
—
ns
tAS
Address Set-up Time
0
—
0
—
0
—
0
—
ns
tWP
Write Pulse Width
40
—
45
—
50
—
55
—
ns
tWR
Write Recovery Time
0
—
0
—
0
—
0
—
ns
tDW
Data to Write Time Overlap
25
—
30
—
35
—
40
—
ns
Data Hold from Write Time (WE)
0
—
0
—
0
—
0
—
ns
Write Enable to Output in High-Z
—
25
—
30
—
35
—
40
ns
Output Active from End-of-Write
5
—
5
—
5
—
5
—
ns
tDH
(2)
tWHZ
(2)
tOW
NOTES:
1. –55°C to +125°C temperature range only.
2. This parameter guaranteed by device characterization, but is not production tested.
3. Also available: 120 and 150 ns military devices.
7.2
2946 tbl 11
6
IDT71256S/L
CMOS STATIC RAM 256K (32K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
tRC
ADDRESS
tAA
tOH
OE
tOE
tOLZ
(5)
tOHZ
(5)
tCHZ
(5)
CS
tACS
tCLZ
(5)
DATA OUT
2946 drw 07
TIMING WAVEFORM OF READ CYCLE NO. 2(1, 2, 4)
tRC
ADDRESS
tAA
tOH
tOH
DATA OUT
2946 drw 08
TIMING WAVEFORM OF READ CYCLE NO. 3(1, 3, 4)
CS
tACS
tCHZ
tCLZ (5)
(5)
DATA OUT
2946 drw 09
NOTES:
1. WE is HIGH for Read cycle.
2. Device is continuously selected, CS is LOW.
3. Address valid prior to or coincident with CS transition LOW.
4. OE is LOW.
5. Transition is measured ±200mV from steady state.
7.2
7
IDT71256 S/L
CMOS STATIC RAM 256K (32K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED TIMING)(1, 2, 3, 5, 7)
tWC
ADDRESS
tOHZ
(6)
OE
tAW
CS
tWP
tAS
(7)
tWR
WE
tWHZ
DATA OUT
(6)
tOW
(4)
(4)
tDW
tDH
DATA IN
2946 drw 10
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS CONTROLLED TIMING)(1, 2, 3, 5)
tWC
ADDRESS
tAW
CS
tAS
tCW (7)
ttWR
WE
tDW
tDH2
DATA IN
2946 drw 11
NOTES:
1. WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap of a LOW CS and a LOW WE.
3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
4. During this period, I/O pins are in the output state so that the input signals must not be applied.
5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
6. Transition is measured ±200mV from steady state.
7. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data
to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can
be as short as the spectified tWP. For a CS controlled write cycle, OE may be LOW with no degradation to tCW.
7.2
8
IDT71256S/L
CMOS STATIC RAM 256K (32K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT 71256
Device
Type
X
XXX
XXX
X
Power
Speed
Package
Process/
Temperature
Range
Blank
Commercial (0°C to +70°C)
B
Military (–55°C to +125°C)
Compliant to MIL-STD-883, Class B
TD
D
Y
P
L
300 mil CERDIP (D28-3)
600 mil CERDIP (D28-1)
300 mil SOJ (SO28-5)
600 mil Plastic DIP (P28-1)
Leadless Chip Carrier (32-pin) (L32-1)
20
25
30
35
45
55
70
85
100
120
150
Commercial Only
S
L
Military Only
Military Only
Military Only
Military Only
Military Only
Military Only
Military Only
Speed in nanoseconds
Standard Power
Low Power
2946 drw 12
7.2
9
Similar pages