MTY20N50E Preferred Device Power MOSFET 20 Amps, 500 Volts N−Channel TO−264 This high voltage MOSFET uses an advanced termination scheme to provide enhanced voltage−blocking capability without degrading performance over time. In addition, this advanced Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for high voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. • Robust High Voltage Termination • Avalanche Energy Specified • Diode is Characterized for Use in Bridge Circuits • IDSS and VDS(on) Specified at Elevated Temperature http://onsemi.com 20 AMPERES 500 VOLTS RDS(on) = 260 mΩ N−Channel D G MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Rating Symbol Value Unit Drain−to−Source Voltage VDSS 500 Vdc Drain−to−Gate Voltage (RGS = 1.0 MΩ) VDGR 500 Vdc Gate−Source Voltage − Continuous − Non−Repetitive (tp ≤ 10 ms) VGS VGSM ± 20 ± 40 Vdc Vpk ID ID 20 13.9 60 Adc PD 250 2.0 Watts W/°C TJ, Tstg −55 to 150 °C Drain Current − Continuous Drain Current − Continuous @ 100°C Drain Current − Single Pulse (tp ≤ 10 μs) Total Power Dissipation Derate above 25°C Operating and Storage Temperature Range IDM S TO−264 CASE 340G Style 1 1 2 3 MARKING DIAGRAM & PIN ASSIGNMENT Apk Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = 100 Vdc, VGS = 10 Vdc, IL = 20 Apk, L = 10 mH, RG = 25 Ω) EAS Thermal Resistance − Junction to Case Thermal Resistance − Junction to Ambient RθJC RθJA 0.50 40 °C/W Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds TL 260 °C MTY20N50E LLYWW mJ 2000 1 Gate 3 Source 2 Drain LL Y WW = Location Code = Year = Work Week ORDERING INFORMATION Device MTY20N50E Package Shipping TO−264 25 Units/Rail Preferred devices are recommended choices for future use and best overall value. © Semiconductor Components Industries, LLC, 2006 August, 2006 − Rev. 2 1 Publication Order Number: MTY20N50E/D MTY20N50E ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 500 − − 583 − − Vdc mV/°C − − − − 10 100 − − 100 nAdc 2.0 − 3.0 7.0 4.0 − Vdc mV/°C − 0.22 0.26 Ohm − − 4.75 − 6.2 6.5 gFS 11 16.2 − mhos Ciss − 3880 6980 pF Coss − 452 920 Crss − 96 140 td(on) − 29 60 tr − 90 170 td(off) − 97 190 tf − 84 170 QT − 100 140 Q1 − 20 − Q2 − 44 − Q3 − 36 − − − 0.92 0.81 1.1 − trr − 431 − ta − 272 − tb − 159 − QRR − 6.67 − − − 3.5 4.5 − − − 7.5 − OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 500 Vdc, VGS = 0 Vdc) (VDS = 500 Vdc, VGS = 0 Vdc, TJ = 125°C) IDSS Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc) IGSS μAdc ON CHARACTERISTICS (Note 1) Gate Threshold Voltage (VDS = VGS, ID = 250 μAdc) Temperature Coefficient (Negative) VGS(th) Static Drain−to−Source On−Resistance (VGS = 10 Vdc, ID = 10 Adc) RDS(on) Drain−to−Source On−Voltage (VGS = 10 Vdc, ID = 20 Adc) (VGS = 10 Vdc, ID = 10 Adc, TJ = 125°C) VDS(on) Forward Transconductance (VDS = 13 Vdc, ID = 10 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2) Turn−On Delay Time (VDD = 250 Vdc, ID = 20 Adc, VGS = 10 Vdc, RG = 9.1 Ω) Rise Time Turn−Off Delay Time Fall Time Gate Charge (See Figure 8) (VDS = 400 Vdc, ID = 20 Adc, VGS = 10 Vdc) ns nC SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (Note 1) (IS = 20 Adc, VGS = 0 Vdc) (IS = 20 Adc, VGS = 0 Vdc, TJ = 125°C) Reverse Recovery Time (See Figure 14) (IS = 20 Adc, VGS = 0 Vdc, dIS/dt = 100 A/μs) Reverse Recovery Stored Charge VSD Vdc ns μC INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25″ from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25″ from package to source bond pad) LS 1. Pulse Test: Pulse Width ≤ 300 μs, Duty Cycle ≤ 2%. 2. Switching characteristics are independent of operating junction temperature. http://onsemi.com 2 nH nH MTY20N50E TYPICAL ELECTRICAL CHARACTERISTICS TJ = 25°C 40 VGS = 10 V VDS ≥ 10 V 9V 32 I D , DRAIN CURRENT (AMPS) I D , DRAIN CURRENT (AMPS) 40 8V 7V 6V 24 16 5V 8 32 24 16 100°C 25°C 8 TJ = − 55°C 0 0 4 8 12 16 6 10 14 18 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 2 0 2.0 2.4 20 0.6 VGS = 10 V 0.5 TJ = 100°C 0.4 25°C 0.3 0.2 − 55°C 0.1 0 0 8 4 16 24 12 20 28 ID, DRAIN CURRENT (AMPS) 32 40 36 TJ = 25°C 0.32 0.30 VGS = 10 V 0.28 0.26 0.24 15 V 0 4 8 16 24 12 20 28 ID, DRAIN CURRENT (AMPS) 32 36 40 Figure 4. On−Resistance versus Drain Current and Gate Voltage 2.4 10000 VGS = 10 V ID = 10 A VGS = 0 V TJ = 125°C I DSS , LEAKAGE (nA) R DS(on) , DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 6.8 0.34 Figure 3. On−Resistance versus Drain Current and Temperature 2.0 6.4 Figure 2. Transfer Characteristics RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS) Figure 1. On−Region Characteristics 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6 6.0 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 1.6 1.2 0.8 1000 100°C 100 10 25°C 0.4 0 −50 −25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) 125 150 1 0 Figure 5. On−Resistance Variation with Temperature 50 100 150 200 250 300 350 400 450 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 6. Drain−To−Source Leakage Current versus Voltage http://onsemi.com 3 500 MTY20N50E POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (Δt) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain−gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off−state condition when calculating td(on) and is read at a voltage corresponding to the on−state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG − VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn−on and turn−off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG − VGSP)] td(off) = RG Ciss In (VGG/VGSP) 9000 VDS = 0 V VGS = 0 V Ciss 6000 5000 Ciss Crss 4000 3000 2000 1000 Coss 100 Coss 1000 0 TJ = 25°C Ciss 7000 C, CAPACITANCE (pF) C, CAPACITANCE (pF) 8000 10000 TJ = 25°C VGS = 0 V Crss Crss 10 5 0 VGS 5 10 15 20 10 25 10 VDS 100 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 7b. High Voltage Capacitance Variation Figure 7a. Capacitance Variation http://onsemi.com 4 1000 MTY20N50E 8 Q2 6 300 4 200 ID = 20 A TJ = 25°C 2 100 VDS Q3 0 0 10 20 30 40 50 60 70 QT, TOTAL GATE CHARGE (nC) 80 90 0 100 td(off) VDD = 250 V ID = 20 A VGS = 10 V TJ = 25°C 400 VGS Q1 1000 t, TIME (ns) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 500 QT VDS , DRAIN−TO−SOURCE VOLTAGE (VOLTS) 10 tr tf 100 10 td(on) 1 Figure 8. Gate−To−Source and Drain−To−Source Voltage versus Total Gate Charge 10 RG, GATE RESISTANCE (OHMS) 100 Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN−TO−SOURCE DIODE CHARACTERISTICS I S , SOURCE CURRENT (AMPS) 20 16 VGS = 0 V TJ = 25°C 12 8 4 0 0.50 0.54 0.58 0.62 0.66 0.70 0.74 0.78 0.82 0.86 0.90 0.94 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain−to−source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance−General Data and Its Use.” Switching between the off−state and the on−state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 μs. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) − TC)/(RθJC). A Power MOSFET designated E−FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non−linearly with an increase of peak current in avalanche and peak junction temperature. Although many E−FETs can withstand the stress of drain−to−source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. http://onsemi.com 5 MTY20N50E I D , DRAIN CURRENT (AMPS) 100 EAS, SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) SAFE OPERATING AREA VGS = 20 V SINGLE PULSE TC = 25°C 10 100 μs 1 ms 1.0 10 ms RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 0.01 dc 100 1.0 10 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 0.1 2000 ID = 20 A 1600 1200 800 400 0 1000 25 Figure 11. Maximum Rated Forward Biased Safe Operating Area r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 1.0 150 50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature D = 0.5 0.2 0.1 0.1 0.05 P(pk) 0.02 0.01 0.01 t1 SINGLE PULSE 0.001 1.0E−05 t2 DUTY CYCLE, D = t1/t2 1.0E−04 1.0E−03 1.0E−02 t, TIME (s) 1.0E−01 Figure 13. Thermal Response di/dt IS trr ta tb TIME 0.25 IS tp IS Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 6 RθJC(t) = r(t) RθJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) − TC = P(pk) RθJC(t) 1.0E+00 1.0E+01 MTY20N50E PACKAGE DIMENSIONS TO−264 CASE 340G−02 ISSUE H 0.25 (0.010) M T B M −Q− −B− −T− C E U N A 1 R 2 L 3 −Y− F 2 PL P K W G J H D 3 PL 0.25 (0.010) M Y Q S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. DIM A B C D E F G H J K L N P Q R U W MILLIMETERS MIN MAX 28.0 29.0 19.3 20.3 4.7 5.3 0.93 1.48 1.9 2.1 2.2 2.4 5.45 BSC 2.6 3.0 0.43 0.78 17.6 18.8 11.0 11.4 3.95 4.75 2.2 2.6 3.1 3.5 2.15 2.35 6.1 6.5 2.8 3.2 INCHES MIN MAX 1.102 1.142 0.760 0.800 0.185 0.209 0.037 0.058 0.075 0.083 0.087 0.102 0.215 BSC 0.102 0.118 0.017 0.031 0.693 0.740 0.433 0.449 0.156 0.187 0.087 0.102 0.122 0.137 0.085 0.093 0.240 0.256 0.110 0.125 STYLE 1: PIN 1. GATE 2. DRAIN 3. SOURCE ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 7 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative MTY20N50E/D