TI1 ADC0848CCN/NOPB 8-bit î¼p compatible a/d converters with multiplexer option Datasheet

ADC0844, ADC0848
www.ti.com
SNAS523D – JUNE 1999 – REVISED MARCH 2013
ADC0844/ADC0848 8-Bit μP Compatible A/D Converters with Multiplexer Options
Check for Samples: ADC0844, ADC0848
FEATURES
DESCRIPTION
•
•
The ADC0844 and ADC0848 are CMOS 8-bit
successive approximation A/D converters with
versatile analog input multiplexers. The 4-channel or
8-channel multiplexers can be software configured for
single-ended, differential or pseudo-differential modes
of operation.
1
2
•
•
•
•
•
•
Easy Interface to All Microprocessors
Operates Ratiometrically or with 5 VDC Voltage
Reference
No Zero or Full-Scale Adjust Required
4-Channel or 8-Channel Multiplexer with
Address Logic
Internal Clock
0V to 5V Input Range with Single 5V Power
Supply
Standard Width 20-Pin or 24-Pin PDIP
28 Pin PLCC Package
KEY SPECIFICATIONS
•
•
•
•
•
Resolution: 8 Bits
Total Unadjusted Error: ±½ LSB and ± 1 LSB
Single Supply: 5 VDC
Low Power: 15 mW
Conversion Time: 40 μs
The differential mode provides low frequency input
common mode rejection and allows offsetting the
analog range of the converter. In addition, the A/D's
reference can be adjusted enabling the conversion of
reduced analog ranges with 8-bit resolution.
The A/Ds are designed to operate from the control
bus of a wide variety of microprocessors. TRI-STATE
output latches that directly drive the data bus permit
the A/Ds to be configured as memory locations or I/O
devices to the microprocessor with no interface logic
necessary.
Block Diagram
* ADC0848 shown in PDIP Package CH5-CH8 not included on the ADC0844
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2013, Texas Instruments Incorporated
ADC0844, ADC0848
SNAS523D – JUNE 1999 – REVISED MARCH 2013
www.ti.com
Connection Diagram
Figure 1. PLCC Package (Top View)
Figure 2. 20-Pin PDIP (Top View)
Figure 3. 28-Pin PDIP (Top View)
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2) (3)
Supply Voltage (VCC)
6.5V
−0.3V to +15V
Logic Control Inputs
Voltage
−0.3V to VCC+0.3V
At Other Inputs and Outputs
Input Current at Any Pin (4)
Package Input Current
5 mA
(4)
20 mA
−65°C to +150°C
Storage Temperature
Package Dissipation at TA=25°C
ESD Susceptibility
875 mW
(5)
800V
PDIP Package
Lead Temperature (Soldering, 10 seconds)
(1)
(2)
(3)
(4)
(5)
2
PLCC Package
260°C
Vapor Phase (60 seconds)
215°C
Infrared (15 seconds)
220°C
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not
apply when operating the device beyond its specified operating conditions.
All voltages are measured with respect to the ground pins.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < V−or VIN > V+) the absolute value of the current at that pin
should be limited to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply
boundaries with a 5 mA current limit to four.
Human body model, 100 pF discharged through a 1.5 kΩ resistor.
Submit Documentation Feedback
Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: ADC0844 ADC0848
ADC0844, ADC0848
www.ti.com
SNAS523D – JUNE 1999 – REVISED MARCH 2013
Operating Conditions (1) (2)
Supply Voltage (VCC)
4.5 VDC to 6.0 VDC
0°C≤TA≤70°C
ADC0844CCN, ADC0848BCN, ADC0848CCN
Temperature Range (TMIN≤TA≤TMAX)
(1)
(2)
(3)
ADC0844BCJ (3), ADC0844CCJ (3), ADC0848BCV,
ADC0848CCV
−40°C≤TA≤85°C
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not
apply when operating the device beyond its specified operating conditions.
All voltages are measured with respect to the ground pins.
Product/package combination obsolete; shown for reference only.
Electrical Characteristics
The following specifications apply for VCC = 5 VDC unless otherwise specified. Boldface limits apply from TMIN to TMAX; all
other limits TA = Tj = 25°C.
Parameter
Conditions
ADC0844CCN,
ADC0848BCN,
ADC0848CCN,
ADC0848BCV,
ADC0848CCV
ADC0844BCJ (1)
ADC0844CCJ (1)
Typ (2)
Tested Design
Limit (3) Limit (4)
Typ (2)
Limit
Units
Tested Design
Limit (3) Limit (4)
CONVERTER AND MULTIPLEXER CHARACTERISTICS
Maximum Total
ADC0844BCN,
ADC0848BCN, BCV
Unadjusted
Error
ADC0844CCN,
ADC0848CCN, CCV
±½
±½
LSB
±1
±1
LSB
VREF = 5.00 VDC (5)
ADC0844CCJ (1)
±1
LSB
Minimum Reference Input Resistance
2.4
1.1
2.4
1.2
1.1
kΩ
Maximum Reference Input Resistance
2.4
5.9
2.4
5.4
5.9
kΩ
VCC +
0.05
VCC +
0.05
V
GND −
0.05
GND −
0.05
V
Maximum Common-Mode Input Voltage
See (6)
VCC +
0.05
Minimum Common-Mode Input Voltage
See (6)
GND −
0.05
DC Common-Mode Error
Differential Mode
±1/16
±¼
±1/16
±¼
±¼
LSB
Power Supply Sensitivity
VCC = 5V±5%
±1/16
±⅛
±1/16
±⅛
±⅛
LSB
Off Channel Leakage Current
On Channel = 5V, Off
Channel = 0V (7)
−1
−0.1
−1
μA
On Channel = 0V, Off
Channel = 5V
1
0.1
1
μA
2.0
2.0
2.0
V
0.8
DIGITAL AND DC CHARACTERISTICS
VIN(1), Logical “1” Input Voltage (Min)
VCC = 5.25V
VIN(0), Logical “0” Input Voltage (Max)
VCC = 4.75V
0.8
V
IIN(1), Logical “1” Input Current (Max)
VIN = 5.0V
0.005
1
0.005
1
μA
IIN(0), Logical “0” Input Current (Max)
VIN = 0V
−0.005
−1
−0.005
−1
μA
(1)
(2)
(3)
(4)
(5)
(6)
(7)
0.8
This product/package combination is obsolete. Shown for reference only.
Typical figures are at 25°C and represent most likely parametric norm.
Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).
Design limits are specified by not 100% tested. These limits are not used to calculate outgoing quality levels.
Total unadjusted error includes offset, full-scale, linearity, and multiplexer error.
For VIN (−) ≥ VIN(+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input, which will forwardconduct for analog input voltages one diode drop below ground or one diode drop greater than VCC supply. Be careful during testing at
low VCC levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct, especially at elevated temperatures, and
cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias of either diode. This means that as long as the
analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an absolute 0 VDC to 5
VDC input voltage range will therefore require a minimum supply voltage of 4.950 VDC over temperature variations, initial tolerance and
loading.
Off channel leakage current is measured after the channel selection.
Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: ADC0844 ADC0848
Submit Documentation Feedback
3
ADC0844, ADC0848
SNAS523D – JUNE 1999 – REVISED MARCH 2013
www.ti.com
Electrical Characteristics (continued)
The following specifications apply for VCC = 5 VDC unless otherwise specified. Boldface limits apply from TMIN to TMAX; all
other limits TA = Tj = 25°C.
Parameter
Conditions
Typ (2)
VOUT(1), Logical “1” Output Voltage (Min)
VOUT(0), Logical “0” Output Voltage (Max)
ADC0844CCN,
ADC0848BCN,
ADC0848CCN,
ADC0848BCV,
ADC0848CCV
ADC0844BCJ (1)
ADC0844CCJ (1)
Tested Design
Limit (3) Limit (4)
Limit
Units
Tested Design
Limit (3) Limit (4)
Typ (2)
VCC = 4.75V, IOUT = −360 μA
2.4
2.8
2.4
V
IOUT = −10 μA
4.5
4.6
4.5
V
VCC = 4.75V, IOUT = 1.6 mA
0.4
0.34
0.4
V
μA
VOUT = 0V
−0.01
−3
−0.01
−0.3
−3
VOUT = 5V
0.01
3
0.01
0.3
3
μA
ISOURCE, Output Source Current (Min)
VOUT = 0V
−14
−6.5
−14
−7.5
−6.5
mA
ISINK, Output Sink Current (Min)
VOUT = VCC
16
8.0
16
9.0
8.0
mA
ICC, Supply Current (Max)
CS = 1, VREF Open
1
2.5
1
2.3
2.5
mA
IOUT, TRI-STATE Output Current (Max)
AC Electrical Characteristics
The following specifications apply for VCC = 5VDC, tr = tf = 10 ns unless otherwise specified. Boldface limits apply from TMIN
to TMAX; all other limits TA = Tj = 25°C.
Parameter
Typ (1)
Conditions
tC, Maximum Conversion Time (See Figure 7)
Tested
Limit (2)
Design
Limit (3)
Units
60
μs
30
40
tW(WR), Minimum WR Pulse Width
See (4)
50
150
tACC, Maximum Access Time (Delay from Falling Edge of RD to
Output Data Valid)
CL = 100 pF (4)
145
225
ns
t1H, t0H, TRI-STATE Control (Maximum Delay from Rising Edge of
RD to Hi-Z State)
CL = 10 pF, RL = 10k (4)
125
200
ns
tWI, tRI, Maximum Delay from Falling Edge of WR or RD to Reset
of INTR
tDS, Minimum Data Set-Up Time
See (4)
ns
200
400
ns
50
100
ns
tDH, Minimum Data Hold Time
0
50
ns
CIN, Capacitance of Logic Inputs
5
pF
COUT, Capacitance of Logic Outputs
5
pF
(1)
(2)
(3)
(4)
4
Typical figures are at 25°C and represent most likely parametric norm.
Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).
Design limits are specified by not 100% tested. These limits are not used to calculate outgoing quality levels.
The temperature coefficient is 0.3%/°C.
Submit Documentation Feedback
Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: ADC0844 ADC0848
ADC0844, ADC0848
www.ti.com
SNAS523D – JUNE 1999 – REVISED MARCH 2013
Typical Performance Characteristics
Logic Input Threshold Voltage
vs. Supply Voltage
Output Current vs. Temperature
Figure 4.
Figure 5.
Power Supply Current vs. Temperature
Linearity Error vs. VREF
Figure 6.
Figure 7.
Conversion Time vs. VSUPPLY
Conversion Time vs.Temperature
Figure 8.
Figure 9.
Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: ADC0844 ADC0848
Submit Documentation Feedback
5
ADC0844, ADC0848
SNAS523D – JUNE 1999 – REVISED MARCH 2013
www.ti.com
Typical Performance Characteristics (continued)
Unadjusted Offset Error vs.
VREF Voltage
Figure 10.
TRI-STATE Test Circuits and Waveforms
t1H
t1H, CL = 10 pF
t0H
t0H, CL = 10 pF
tr = 20 ns
Leakage Current Test Circuit
6
Submit Documentation Feedback
Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: ADC0844 ADC0848
ADC0844, ADC0848
www.ti.com
SNAS523D – JUNE 1999 – REVISED MARCH 2013
Timing Diagrams
Read strobe must occur at least 600 ns after the assertion of interrupt to ensure reset of INTR .
MA stands for MUX address.
Figure 11. Using the Previously Selected Channel Configuration and Starting a Conversion
Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: ADC0844 ADC0848
Submit Documentation Feedback
7
ADC0844, ADC0848
SNAS523D – JUNE 1999 – REVISED MARCH 2013
www.ti.com
ADC0848 Functional Block Diagram
8
Submit Documentation Feedback
Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: ADC0844 ADC0848
ADC0844, ADC0848
www.ti.com
SNAS523D – JUNE 1999 – REVISED MARCH 2013
Functional Description
The ADC0844 and ADC0848 contain a 4-channel and 8-channel analog input multiplexer (MUX) respectively.
Each MUX can be configured into one of three modes of operation differential, pseudo-differential, and single
ended. These modes are discussed in Applications Information. The specific mode is selected by loading the
MUX address latch with the proper address (see Table 1 and Table 2). Inputs to the MUX address latch (MA0MA4) are common with data bus lines (DB0-DB4) and are enabled when the RD line is high. A conversion is
initiated via the CS and WR lines. If the data from a previous conversion is not read, the INTR line will be low.
The falling edge of WR will reset the INTR line high and ready the A/D for a conversion cycle. The rising edge of
WR, with RD high, strobes the data on the MA0/DB0-MA4/DB4 inputs into the MUX address latch to select a
new input configuration and start a conversion. If the RD line is held low during the entire low period of WR the
previous MUX configuration is retained, and the data of the previous conversion is the output on lines DB0-DB7.
After the conversion cycle (tC ≤ 40 μs), which is set by the internal clock frequency, the digital data is transferred
to the output latch and the INTR is asserted low. Taking CS and RD low resets INTR output high and outputs the
conversion result on the data lines (DB0-DB7).
APPLICATIONS INFORMATION
MULTIPLEXER CONFIGURATION
The design of these converters utilizes a sampled-data comparator structure which allows a differential analog
input to be converted by a successive approximation routine.
The actual voltage converted is always the difference between an assigned “+” input terminal and a “−” input
terminal. The polarity of each input terminal of the pair being converted indicates which line the converter expects
to be the most positive. If the assigned “+” input is less than the “−” input the converter responds with an all zeros
output code.
A unique input multiplexing scheme has been utilized to provide multiple analog channels. The input channels
can be software configured into three modes: differential, single ended, or pseudo-differential. Figure 12 shows
the three modes using the 4-channel MUX ADC0844. The eight inputs of the ADC0848 can also be configured in
any of the three modes. In the differential mode, the ADC0844 channel inputs are grouped in pairs, CH1 with
CH2 and CH3 with CH4. The polarity assignment of each channel in the pair is interchangeable. The singleended mode has CH1–CH4 assigned as the positive input with the negative input being the analog ground
(AGND) of the device. Finally, in the pseudo-differential mode CH1–CH3 are positive inputs referenced to CH4
which is now a pseudo-ground. This pseudo-ground input can be set to any potential within the input commonmode range of the converter. The analog signal conditioning required in transducer-based data acquisition
systems is significantly simplified with this type of input flexibility. One converter package can now handle ground
referenced inputs and true differential inputs as well as signals with some arbitrary reference voltage.
The analog input voltages for each channel can range from 50 mV below ground to 50 mV above VCC (typically
5V) without degrading conversion accuracy.
Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: ADC0844 ADC0848
Submit Documentation Feedback
9
ADC0844, ADC0848
SNAS523D – JUNE 1999 – REVISED MARCH 2013
www.ti.com
Table 1. ADC0844 MUX ADDRESSING (1)
MUX Address
CS
RD
MA2
MA1
X
L
L
L
L
X
L
L
H
L
X
L
H
L
L
X
L
H
H
L
L
H
L
L
L
L
H
L
H
L
L
H
H
L
L
H
(1)
MA0
WR
MA3
NP
CH2
CH3
CH4
H
+
−
H
−
H
+
+
−
H
−
+
H
NP
L
H
H
H
L
H
H
L
L
L
H
H
H
L
H
L
H
H
H
L
L
X
X
X
X
L
H
L
MUX Mode
Differential
−
+
−
+
+
Single-Ended
−
−
+
−
+
H
NP
AGND
−
+
H
H
NP
Channel#
CH1
+
Pseudo- Differential
−
Previous Channel Configuration
X = don't care, NP = negative pulse
4 Single-Ended
2 Differential
3 Pseudo-Differential
Combined
Figure 12. Analog Input Multiplexer Options
REFERENCE CONSIDERATIONS
The voltage applied to the reference input of these converters defines the voltage span of the analog input (the
difference between VIN(MAX) and VIN(MIN)) over which the 256 possible output codes apply. The devices can be
used in either ratiometric applications or in systems requiring absolute accuracy. The reference pin must be
connected to a voltage source capable of driving the minimum reference input resistance of 1.1 kΩ. This pin is
the top of a resistor divider string used for the successive approximation conversion.
In a ratiometric system (Figure 13), the analog input voltage is proportional to the voltage used for the A/D
reference. This voltage is typically the system power supply, so the VREF pin can be tied to VCC. This technique
relaxes the stability requirements of the system reference as the analog input and A/D reference move together
maintaining the same output code for a given input condition. For absolute accuracy (Figure 14), where the
analog input varies between very specific voltage limits, the reference pin can be biased with a time and
temperature stable voltage source. The LM385 and LM336 reference diodes are good low current devices to use
with these converters.
The maximum value of the reference is limited to the VCC supply voltage. The minimum value, however, can be
quite small (see Typical Performance Characteristics) to allow direct conversions of transducer outputs providing
less than a 5V output span. Particular care must be taken with regard to noise pickup, circuit layout and system
error voltage sources when operating with a reduced span due to the increased sensitivity of the converter (1
LSB equals VREF/256).
10
Submit Documentation Feedback
Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: ADC0844 ADC0848
ADC0844, ADC0848
www.ti.com
SNAS523D – JUNE 1999 – REVISED MARCH 2013
THE ANALOG INPUTS
Analog Differential Voltage Inputs and Common-Mode Rejection
The differential input of these converters actually reduces the effects of common-mode input noise, a signal
common to both selected “+” and “−” inputs for a conversion (60 Hz is most typical). The time interval between
sampling the “+” input and then the “−” inputs is ½ of a clock period. The change in the common-mode voltage
during this short time interval can cause conversion errors. For a sinusoidal common-mode signal this error is:
where
•
•
•
fCM is the frequency of the common-mode signal
Vpeak is its peak voltage value
tC is the conversion time
For a 60 Hz common-mode signal to generate a ¼ LSB error (≈5 mV) with the converter running at 40 μS, its
peak value would have to be 5.43V. This large a common-mode signal is much greater than that generally found
in a well designed data acquisition system.
Table 2. ADC0848 MUX Addressing (1)
MUX Address
MA3
MA2
MA1
X
L
L
L
L
L
X
L
L
L
H
L
X
L
L
H
L
L
X
L
L
H
H
L
X
L
H
L
L
L
X
L
H
L
H
X
L
H
H
L
X
L
H
H
L
H
L
L
H
L
L
H
L
(1)
MA0
CS
MA4
WR
RD
Channel
CH5
CH6
H
+
−
L
H
−
+
L
H
+
−
H
L
H
−
+
L
L
L
H
L
H
L
H
L
H
L
L
H
H
L
H
H
L
L
H
H
L
L
L
H
L
H
H
L
H
L
H
L
H
H
H
L
L
H
NP
NP
CH1
CH2
CH3
CH4
H
+
−
H
−
+
H
+
−
H
−
+
L
H
H
H
H
L
H
H
L
L
L
L
H
H
H
L
L
H
L
H
H
H
L
H
L
L
H
H
L
H
H
L
H
H
H
L
L
L
H
H
H
H
L
H
L
H
H
H
H
H
L
L
H
X
X
X
X
X
L
L
H
NP
H
CH8
AGND
MUX Mode
Differential
−
+
−
+
−
+
H
H
CH7
−
+
−
+
Single-Ended
−
+
−
+
+
−
−
+
−
+
−
+
−
+
PseudoDifferential
−
+
−
+
+
−
Previous Channel Configuration
X = don't care, NP = negative pulse
Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: ADC0844 ADC0848
Submit Documentation Feedback
11
ADC0844, ADC0848
SNAS523D – JUNE 1999 – REVISED MARCH 2013
www.ti.com
Input Current
Due to the sampling nature of the analog inputs, short duration spikes of current enter the “+” input and exit the
“−” input at the clock edges during the actual conversion. These currents decay rapidly and do not cause errors
as the internal comparator is strobed at the end of a clock period. Bypass capacitors at the inputs will average
these currents and cause an effective DC current to flow through the output resistance of the analog signal
source. Bypass capacitors should not be used if the source resistance is greater than 1 kΩ.
Input Source Resistance
The limitation of the input source resistance due to the DC leakage currents of the input multiplexer is important.
A worst-case leakage current of ± 1 μA over temperature will create a 1 mV input error with a 1 kΩ source
resistance. An op amp RC active low pass filter can provide both impedance buffering and noise filtering should
a high impedance signal source be required.
OPTIONAL ADJUSTMENTS
Zero Error
The zero of the A/D does not require adjustment. If the minimum analog input voltage value, VIN(MIN), is not
ground, a zero offset can be done. The converter can be made to output 0000 0000 digital code for this minimum
input voltage by biasing any VIN (−) input at this VIN(MIN) value. This is useful for either differential or pseudodifferential modes of input channel configuration.
The zero error of the A/D converter relates to the location of the first riser of the transfer function and can be
measured by grounding the V− input and applying a small magnitude positive voltage to the V+ input. Zero error
is the difference between actual DC input voltage which is necessary to just cause an output digital code
transition from 0000 0000 to 0000 0001 and the ideal ½ LSB value (½ LSB=9.8 mV for VREF=5.000 VDC).
Full-Scale
The full-scale adjustment can be made by applying a differential input voltage which is 1 ½ LSB down from the
desired analog full-scale voltage range and then adjusting the magnitude of the VREF input for a digital output
code changing from 1111 1110 to 1111 1111.
Adjusting for an Arbitrary Analog Input Voltage Range
If the analog zero voltage of the A/D is shifted away from ground (for example, to accommodate an analog input
signal which does not go to ground), this new zero reference should be properly adjusted first. A VIN (+) voltage
which equals this desired zero reference plus ½ LSB (where the LSB is calculated for the desired analog span, 1
LSB = analog span/256) is applied to selected “+” input and the zero reference voltage at the corresponding “−”
input should then be adjusted to just obtain the 00HEX to 01HEX code transition.
Figure 13. Referencing Examples - Ratiometric
12
Submit Documentation Feedback
Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: ADC0844 ADC0848
ADC0844, ADC0848
www.ti.com
SNAS523D – JUNE 1999 – REVISED MARCH 2013
Figure 14. Referencing Examples - Absolute with a Reduced Span
The full-scale adjustment should be made [with the proper VIN (−) voltage applied] by forcing a voltage to the VIN
(+) input which is given by:
where
•
•
VMAX = the high end of the analog input range
VMIN = the low end (the offset zero) of the analog range. (Both are ground referenced.)
(1)
The VREF (or VCC) voltage is then adjusted to provide a code change from FEHEX to FFHEX. This completes the
adjustment procedure.
For an example see the Zero-Shift and Span Adjust circuit below.
Figure 15. Zero-Shift and Span Adjust (2V ≤ VIN ≤ 5V)
Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: ADC0844 ADC0848
Submit Documentation Feedback
13
ADC0844, ADC0848
SNAS523D – JUNE 1999 – REVISED MARCH 2013
www.ti.com
Figure 16. Differential Voltage Input 9-Bit A/D
Figure 17. Span Adjust (0V ≤ VIN ≤ 3V)
Diodes are 1N914
DO = all 1s if VIN(+)>VIN(−)
DO = all 0s if VIN(+)<VIN(−)
Figure 18. Protecting the Input
Figure 19. High Accuracy Comparators
* VIN(−)=0.15 VCC
15% of VCC≤VXDR≤85% of VCC
Figure 20. Operating with Automotive Ratiometric Transducers
14
Submit Documentation Feedback
Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: ADC0844 ADC0848
ADC0844, ADC0848
www.ti.com
SNAS523D – JUNE 1999 – REVISED MARCH 2013
Note: DUT pin numbers in parentheses are for ADC0844, others are for ADC0848.
Figure 21. A Stand Alone Circuit
CS •WR will update the channel configuration and start a conversion.
CS •RD will read the conversion data and start a new conversion without updating the channel configuration.
Waiting for the end of this conversion is not necessary. A CS •WR can immediately follow the CS•RD .
Figure 22. Start a Conversion without Updating the Channel Configuration
Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: ADC0844 ADC0848
Submit Documentation Feedback
15
ADC0844, ADC0848
SNAS523D – JUNE 1999 – REVISED MARCH 2013
www.ti.com
Figure 23. ADC0844—INS8039 Interface
Sample Program for ADC0844 - INS8039 Interface Converting Two Ratiometric Differential Signals
ORG
JMP
ORG
MOV
0H
BEGIN
10H
R1,#0FFH
B8 20
89 FF
23 00
MOV
ORL
MOV
R0,#20H
P1,#0FFH
A,00H
0018
001A
14 50
23 02
CALL
MOV
CONV
A,#02H
001C
001D
18
14 50
INC
CALL
R0
CONV
0000
04 10
0010
B9 FF
0012
0014
0016
BEGIN:
;START PROGRAM AT ADDR 10
;MAIN PROGRAM
;LOAD R1 WITH AN UNUSED ADDR
;LOCATION
;A/D DATA ADDRESS
;SET PORT 1 OUTPUTS HIGH
;LOAD THE ACC WITH A/D MUX DATA
;CH1 AND CH2 DIFFERENTIAL
;CALL THE CONVERSION SUBROUTINE
;LOAD THE ACC WITH A/D MUX DATA
;CH3 AND CH4 DIFFERENTIAL
;INCREMENT THE A/D DATA ADDRESS
;CALL THE CONVERSION SUBROUTINE
;CONTINUE MAIN PROGRAM
;CONVERSION SUBROUTINE
;ENTRY:ACC-A/D MUX DATA
;EXIT:ACC-CONVERTED DATA
0050
0052
0053
0054
0056
0057
0059
005A
16
99 FE
91
09
32 53
81
89 01
A0
83
CONV:
LOOP:
ORG
ANL
MOVX
IN
JB1
MOVX
ORL
MOV
RET
Submit Documentation Feedback
50H
P1#0FEH
@R1,A
A,P1
LOOP
A,@R1
P1,&01H
@R0,A
;CHIP SELECT THE A/D
;LOAD A/D MUX & START CONVERSION
;INPUT INTR STATE
;IF INTR = 1 GOTO LOOP
;IF INTR = 0 INPUT A/D DATA
;CLEAR THE A/D CHIP SELECT
;STORE THE A/D DATA
;RETURN TO MAIN PROGRAM
Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: ADC0844 ADC0848
ADC0844, ADC0848
www.ti.com
SNAS523D – JUNE 1999 – REVISED MARCH 2013
Figure 24. I/O Interface to NSC800
Sample Program for ADC0848 - NSC800 Interface
0008
000F
001F
3C00
0000'
0004'
0008'
000A'
000C'
000F'
0012'
08
0C
0E
06
21
11
ED
09 0A 0B
0D 0E 0F
1F
16
0000'
003C
A3
0014'
EB
0015'
0017'
0018'
001B'
3E 0F
3D
C2 0013'
ED A2
001D'
001E'
EB
C2 000E'
NCONV
DEL
CS
ADDTA
EQU
EQU
EQU
EQU
16
15
1FH
003CH
MUXDTA:
DB
DB
LD
LD
LD
LD
OUTI
08H,09H,0AH,0BH
0CH,0DH,0EH,0FH
C,CS
B,NCONV
HL,MUXDTA
DE,ADDTA
EX
DE,HL
LD
DEC
JP
INI
A,DEL
A
NZ,WAIT
EX
JP
DE,HL
NZ,STCONV
START:
STCONV:
WAIT:
;DELAY 50 µSEC CONVERSION
;THE BOARD ADDRESS
;START OF RAM FOR A/D
;DATA
;MUX DATA
;LOAD A/D'S MUX DATA
;AND START A CONVERSION
;HL=RAM ADDRESS FOR THE
;A/D DATA
;WAIT 50 µSEC FOR THE
;CONVERSION TO FINISH
;STORE THE A/D'S DATA
;CONVERTED ALL INPUTS?
;IF NOT GOTO STCONV
END
Note: This routine sequentially programs the MUX data latch in the signal-ended mode. For CH1-CH8 a
conversion is started, then a 50 μs wait for the A/D to complete a conversion and the data is stored at address
ADDTA for CH1, ADDTA + 1 for CH2, etc.
Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: ADC0844 ADC0848
Submit Documentation Feedback
17
ADC0844, ADC0848
SNAS523D – JUNE 1999 – REVISED MARCH 2013
www.ti.com
REVISION HISTORY
Changes from Revision C (March 2013) to Revision D
•
18
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 17
Submit Documentation Feedback
Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: ADC0844 ADC0848
PACKAGE OPTION ADDENDUM
www.ti.com
27-Apr-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADC0844CCN
LIFEBUY
PDIP
NFH
20
18
TBD
Call TI
Call TI
0 to 70
ADC0844CCN
ADC0844CCN/NOPB
ACTIVE
PDIP
NFH
20
18
Green (RoHS
& no Sb/Br)
CU SN
Level-1-NA-UNLIM
0 to 70
ADC0844CCN
ADC0848BCV
NRND
PLCC
FN
28
35
TBD
Call TI
Call TI
-40 to 85
ADC0848
BCV
ADC0848BCV/NOPB
ACTIVE
PLCC
FN
28
35
Green (RoHS
& no Sb/Br)
CU SN
Level-2A-245C-4
WEEK
-40 to 85
ADC0848
BCV
ADC0848BCVX/NOPB
ACTIVE
PLCC
FN
28
750
Green (RoHS
& no Sb/Br)
CU SN
Level-2A-245C-4
WEEK
-40 to 85
ADC0848
BCV
ADC0848CCN
NRND
PDIP
NAM
24
15
TBD
Call TI
Call TI
-40 to 85
ADC0848CCN
ADC0848CCN/NOPB
LIFEBUY
PDIP
NAM
24
15
Pb-Free
(RoHS)
CU SN
Level-1-NA-UNLIM
-40 to 85
ADC0848CCN
ADC0848CCV
NRND
PLCC
FN
28
35
TBD
Call TI
Call TI
-40 to 85
ADC0848
CCV
ADC0848CCV/NOPB
ACTIVE
PLCC
FN
28
35
Green (RoHS
& no Sb/Br)
CU SN
Level-2A-245C-4
WEEK
-40 to 85
ADC0848
CCV
ADC0848CCVX
NRND
PLCC
FN
28
750
TBD
Call TI
Call TI
-40 to 85
ADC0848
CCV
ADC0848CCVX/NOPB
ACTIVE
PLCC
FN
28
750
Green (RoHS
& no Sb/Br)
CU SN
Level-2A-245C-4
WEEK
-40 to 85
ADC0848
CCV
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
27-Apr-2016
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
NAM0024D
www.ti.com
MECHANICAL DATA
NFH0020A
N0020A
N20A (Rev G)
www.ti.com
MECHANICAL DATA
MPLC004A – OCTOBER 1994
FN (S-PQCC-J**)
PLASTIC J-LEADED CHIP CARRIER
20 PIN SHOWN
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX
0.120 (3,05)
0.090 (2,29)
D
D1
0.020 (0,51) MIN
3
1
19
0.032 (0,81)
0.026 (0,66)
4
E
18
D2 / E2
E1
D2 / E2
8
14
0.021 (0,53)
0.013 (0,33)
0.007 (0,18) M
0.050 (1,27)
9
13
0.008 (0,20) NOM
D/E
D2 / E2
D1 / E1
NO. OF
PINS
**
MIN
MAX
MIN
MAX
MIN
MAX
20
0.385 (9,78)
0.395 (10,03)
0.350 (8,89)
0.356 (9,04)
0.141 (3,58)
0.169 (4,29)
28
0.485 (12,32)
0.495 (12,57)
0.450 (11,43)
0.456 (11,58)
0.191 (4,85)
0.219 (5,56)
44
0.685 (17,40)
0.695 (17,65)
0.650 (16,51)
0.656 (16,66)
0.291 (7,39)
0.319 (8,10)
52
0.785 (19,94)
0.795 (20,19)
0.750 (19,05)
0.756 (19,20)
0.341 (8,66)
0.369 (9,37)
68
0.985 (25,02)
0.995 (25,27)
0.950 (24,13)
0.958 (24,33)
0.441 (11,20)
0.469 (11,91)
84
1.185 (30,10)
1.195 (30,35)
1.150 (29,21)
1.158 (29,41)
0.541 (13,74)
0.569 (14,45)
4040005 / B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation
www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom
www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2016, Texas Instruments Incorporated
Similar pages