ETC MC3110 Pilotâ ¢ motion processor Datasheet

Pilot™ Motion Processor
MC3110 Single Chip
Technical Specifications
for Brushed Servo Motion Control
Performance Motion Devices, Inc.
55 Old Bedford Road
Lincoln, MA 01773
Revision 1.8, July 2003
NOTICE
This document contains proprietary and confidential information of Performance Motion Devices,
Inc., and is protected by federal copyright law. The contents of this document may not be disclosed
to third parties, translated, copied, or duplicated in any form, in whole or in part, without the express
written permission of PMD.
The information contained in this document is subject to change without notice. No part of this
document may be reproduced or transmitted in any form, by any means, electronic or mechanical,
for any purpose, without the express written permission of PMD.
Copyright 2000 by Performance Motion Devices, Inc.
Navigator, Pilot and C-Motion are trademarks of Performance Motion Devices, Inc
Warranty
PMD warrants performance of its products to the specifications applicable at the time of sale in
accordance with PMD's standard warranty. Testing and other quality control techniques are utilized
to the extent PMD deems necessary to support this warranty. Specific testing of all parameters of
each device is not necessarily performed, except those mandated by government requirements.
Performance Motion Devices, Inc. (PMD) reserves the right to make changes to its products or to
discontinue any product or service without notice, and advises customers to obtain the latest version
of relevant information to verify, before placing orders, that information being relied on is current
and complete. All products are sold subject to the terms and conditions of sale supplied at the time
of order acknowledgement, including those pertaining to warranty, patent infringement, and
limitation of liability.
Safety Notice
Certain applications using semiconductor products may involve potential risks of death, personal
injury, or severe property or environmental damage. Products are not designed, authorized, or
warranted to be suitable for use in life support devices or systems or other critical applications.
Inclusion of PMD products in such applications is understood to be fully at the customer's risk.
In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent procedural hazards.
Disclaimer
PMD assumes no liability for applications assistance or customer product design. PMD does not
warrant or represent that any license, either express or implied, is granted under any patent right,
copyright, mask work right, or other intellectual property right of PMD covering or relating to any
combination, machine, or process in which such products or services might be or are used. PMD's
publication of information regarding any third party's products or services does not constitute PMD's
approval, warranty or endorsement thereof.
MC3110 Technical Specifications
iii
MC3110 Technical Specifications
iv
Related Documents
Pilot Motion Processor User’s Guide (MC3000UG)
How to set up and use all members of the Pilot Motion Processor family.
Pilot Motion Processor Programmer’s Reference (MC3000PR)
Descriptions of all Pilot Motion Processor commands, with coding syntax and examples, listed
alphabetically for quick reference.
Pilot Motion Processor Technical Specifications
These booklets contain physical and electrical characteristics, timing diagrams, pinouts and pin
descriptions of each:
MC3110, for brushed servo motion control (MC3110TS)
MC3310, for brushless servo motion control (MC3310TS)
MC3410, for microstepping motion control (MC3410TS)
MC3510, for stepper motion control (MC3510TS)
Pilot Motion Processor Developer’s Kit Manual (DK3000M)
How to install and configure the DK3110 developer’s kit PC board.
MC3110 Technical Specifications
v
MC3110 Technical Specifications
vi
Table of Contents
Warranty...................................................................................................................................................... iii
Safety Notice ................................................................................................................................................ iii
Disclaimer..................................................................................................................................................... iii
Related Documents....................................................................................................................................... v
Table of Contents........................................................................................................................................ vii
1 The Pilot Family ........................................................................................................................................ 9
2 Functional Characteristics...................................................................................................................... 11
2.1
Configurations, parameters, and performance .............................................................................. 11
2.2
Physical characteristics and mounting dimensions....................................................................... 13
2.3
Environmental and electrical ratings ............................................................................................ 14
2.4
System configuration.................................................................................................................... 14
2.5
Peripheral device address mapping............................................................................................... 15
3 Electrical Characteristics........................................................................................................................ 16
3.1
DC characteristics......................................................................................................................... 16
3.2
AC characteristics......................................................................................................................... 16
4 I/O Timing Diagrams .............................................................................................................................. 18
4.1
Clock ............................................................................................................................................ 18
4.2
Quadrature encoder input ............................................................................................................. 18
4.3
Reset ............................................................................................................................................. 18
4.4
Host interface, 8/16 mode (requires external logic device) .......................................................... 19
4.4.1
Instruction write, 8/16 mode................................................................................................. 19
4.4.2
Data write, 8/16 mode........................................................................................................... 19
4.4.3
Data read, 8/16 mode............................................................................................................ 20
4.4.4
Status read, 8/16 mode.......................................................................................................... 20
4.5
Host interface, 16/16 mode (requires external logic device) ........................................................ 21
4.5.1
Instruction write, 16/16 mode............................................................................................... 21
4.5.2
Data write, 16/16 mode......................................................................................................... 21
4.5.3
Data read, 16/16 mode.......................................................................................................... 22
4.5.4
Status read, 16/16 mode........................................................................................................ 22
4.6
External memory timing............................................................................................................... 23
4.6.1
External memory read........................................................................................................... 23
4.6.2
External memory write ......................................................................................................... 23
4.7
Peripheral device timing ............................................................................................................... 24
4.7.1
Peripheral device read........................................................................................................... 24
4.7.2
Peripheral device write ......................................................................................................... 24
5 Pinouts and Pin Descriptions.................................................................................................................. 25
5.1
Pinouts for MC3110 ..................................................................................................................... 25
5.2
CP chip pin description table........................................................................................................ 26
MC3110 Technical Specifications
vii
6 Parallel Communication ......................................................................................................................... 29
6.1
Host interface pin description table .............................................................................................. 29
6.2
16-bit Host Interface (IOPIL16) ................................................................................................... 31
6.3
8-bit Host Interface (IOPIL8) ....................................................................................................... 45
7 Application Notes..................................................................................................................................... 60
7.1
Design Tips................................................................................................................................... 60
7.2
RS-232 Serial Interface ................................................................................................................ 62
7.3
RS 422/485 Serial Interface.......................................................................................................... 64
7.4
PWM Motor Interface .................................................................................................................. 66
7.5
12-bit Parallel DAC Interface....................................................................................................... 68
7.6
16-bit Serial DAC Interface.......................................................................................................... 70
7.7
RAM Interface.............................................................................................................................. 72
7.8
User-defined I/O ........................................................................................................................... 74
7.9
12-bit A/D Interface...................................................................................................................... 76
7.10 16-bit A/D Input ........................................................................................................................... 78
7.11 External Gating Logic Index ........................................................................................................ 80
MC3110 Technical Specifications
viii
1 The Pilot Family
Number of axes
Motor type supported
Output format
Incremental encoder
input
Parallel word device
input
Parallel communication
Serial communication
S-curve profiling
On-the-fly changes
Directional limit
switches
Programmable bit output
Software-invertable
signals
PID servo control
Feedforward (accel &
vel)
Derivative sampling time
Data trace/diagnostics
PWM output
Pulse & direction output
Index & Home signals
Motion error detection
Axis settled indicator
DAC-compatible output
Position capture
Analog input
User-defined I/O
External RAM support
Multi-chip
synchronization
Chip part numbers
Developer's Kit p/n's:
1
MC3110
MC3310
MC3410
MC3510
1
Brushed servo
Brushed servo
(single phase)
1
Brushless servo
Commutated (6step or sinusoidal)
1
Stepping
Microstepping
1
Stepping
Pulse and Direction
√
√
√
√
√
√1
√
√
√
√
√1
√
√
√
√
√1
√
√
√
√
√1
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
-
-
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√ (with encoder)
√ (with encoder)
√
√
√
√
√
√ (with encoder)
√ (with encoder)
√
√
√
√
√ (MC3113)
√ (MC3313)
√ (MC3413)
-
MC3110
DK3110
MC3310
DK3310
MC3410
DK3410
MC3510
DK3510
Parallel communication is available via an additional logic device
Introduction
This manual describes the operational characteristics of the MC3110 Motion Processor from PMD.
This device is a member of the MC3000 family of single-chip, single-axis motion processors.
MC3110 Technical Specifications
9
Each device of the MC3000 family is a complete chip-based motion processor providing trajectory
generation and related motion control functions for one axis including servo loop closure or onboard commutation where appropriate. This family of products provides a software-compatible
selection of dedicated motion processors that can handle a large variety of system configurations.
The chip architecture not only makes it ideal for the task of motion control, it allows for similarities
in software commands, so software written for one motor type can be re-used if the motor type is
changed.
Pilot Family Summary
MC3110 – This single-chip, single-axis motion processor outputs motor commands in either
Sign/Magnitude PWM or DAC-compatible format for use with brushed servo motors, or with
brushless servo motors having external commutation.
MC3310 – This single-chip, single-axis motion processor outputs sinusoidally commutated motor
signals appropriate for driving brushless motors. Depending on the motor type, the output is a twophase or three-phase signal in either PWM or DAC-compatible format.
MC3410 – This single-chip, single-axis motion processor outputs microstepping signals for stepping
motors. Two phased signals per axis are generated in either PWM or DAC-compatible format.
MC3510 – This single-chip, single-axis motion processor outputs pulse and direction signals for
stepping motor systems.
MC3110 Technical Specifications
10
2 Functional Characteristics
2.1
Configurations, parameters, and performance
Configuration
Operating modes
Communication modes
Serial port baud rate range
Position range
Velocity range
Acceleration/deceleration ranges
Jerk range
Profile modes
Filter modes
Filter parameter resolution
Position error tracking
Motor output modes
Maximum encoder rate
Parallel encoder word size
Parallel encoder read rate
Single axis, single chip.
Closed loop (motor command is driven from output of servo filter)
Open loop (motor command is driven from user-programmed register)
8/16 parallel (8 bit external parallel bus with 16 bit internal command word size)
16/16 parallel (16 bit external parallel bus with 16 bit internal command word
size)
Point to point asynchronous serial
Multi-drop asynchronous serial
1,200 baud to 416,667 baud
-2,147,483,648 to +2,147,483,647 counts
-32,768 to +32,767 counts/sample with a resolution of 1/65,536 counts/sample
-32,768 to +32,767 counts/sample2 with a resolution of 1/65,536 counts/sample2
0 to ½ counts/sample3, with a resolution of 1/4,294,967,296 counts/sample3
S-curve point-to-point (Velocity, acceleration, jerk, and position parameters)
Trapezoidal point-to-point (Velocity, acceleration, deceleration, and position
parameters)
Velocity-contouring (Velocity, acceleration, and deceleration parameters)
Scalable PID + Velocity feedforward + Acceleration feedforward + Bias. Also
includes integration limit, settable derivative sampling time, and output motor
command limiting
16 bits
Motion error window (allows axis to be stopped upon exceeding programmable
window)
Tracking window (allows flag to be set if axis exceeds a programmable position
window)
Axis settled (allows flag to be set if axis exceeds a programmable position
window for a programmable amount of time after trajectory motion is compete)
PWM (10-bit resolution at 20 kHz)
DAC (16 bits)
Incremental (up to 5 million counts/sec)
Parallel-word (up to 160 million counts/sec)
16 bits
20 kHz (reads all axes every 50 µsec)
Servo loop timing range
102.4 µsec to 32.767 milliseconds
Minimum servo loop time
102.4 µsec
Multi-chip synchronization
<10µsec difference between master and slave servo cycle
MC3113 chipset only
2 per axis: one for each direction of travel
2 per axis: index and home signals
1 AxisIn signal per axis, 1 AxisOut signal per axis
Limit switches
Position-capture triggers
Other digital signals (per axis)
MC3110 Technical Specifications
11
Software-invertable signals
Analog input
User defined discrete I/O
RAM/external memory support
Trace modes
Max. number of trace variables
Number of traceable variables
Number of host instructions
Index, Home, AxisIn, AxisOut, PositiveLimit, NegativeLimit (all individually
programmable)
8 10-bit analog inputs
256 16-bit wide user defined I/O
65,536 blocks of 32,768 16-bit words per block. Total accessible memory is
2,147,483,648 16 bit words
one-time
continuous
4
28
132
MC3110 Technical Specifications
12
2.2
Physical characteristics and mounting dimensions
All dimensions are in inches (with millimeters in brackets).
Dimension
Minimum
(inches)
D
D1
D2
D3
1.070
0.934
1.088
Maximum
(inches)
1.090
0.966
1.112
0.800 nominal
MC3110 Technical Specifications
13
2.3
Environmental and electrical ratings
Storage Temperature (Ts)
Operating Temperature (Ta)
Power Dissipation (Pd)
Nominal Clock Frequency (Fclk)
Supply Voltage limits (Vcc)
Supply Voltage operating range (Vcc)
-55 °C to 150 °C
0 °C to 70 °C*
400 mW
20.0 MHz
-0.3V to +7.0V
4.75V to 5.25V
* An industrial version with an operating range of -40°C to 85°C is also available. Please contact
PMD for more information.
System configuration
The following figure shows the principal control and data paths in an MC3110 system.
Host
Serial Port
HostCmd
~HostRead
HostRdy
~HostWrite
Home
Pilot Motion Processor
System clock
(40 MHz)
Index
Parallel Communication
PLD/FPGA
20MHz clock
CP
B
User I/O
PWM output
Positive
External memory
Negative
(MC3310 only)
AxisIn
Hall sensors
16 bit data/address bus
AxisOut
A
Encoder
Parallel port
~HostSlct
HostIntrpt
HostData0-15
2.4
Limit
switches
DAC output
D/A
converter
Motor
Amplifier
Parallel-word input
Serial port configuration
The shaded area shows the CPLD/FPGA that must be provided by the designer if parallel
communication is required. A description and the necessary logic (in the form of schematics) of this
device are detailed in section 6 of this manual. The CP chip contains the profile generator, which
calculates velocity, acceleration, and position values for a trajectory; and the digital servo filter, which
stabilizes the motor output signal.
MC3110 Technical Specifications
14
The filter produces one of two types of output:
•
a Pulse-Width Modulated (PWM) signal output; or
• a DAC-compatible value routed via the data bus to the appropriate D/A converter.
Axis position information returns to the motion processor in the form of encoder feedback using
either the incremental encoder input signals, or via the bus as parallel word input.
2.5
Peripheral device address mapping
Device addresses on the CP chip’s data bus are memory-mapped to the following locations:
Address
Device
Description
0200h
Serial port data
Contains the configuration data (transmission rate,
parity, stop bits, etc) for the asynchronous serial port
0800h
Parallel-word encoder
Base address for parallel-word feedback devices
1000h
User-defined
Base address for user-defined I/O devices
2000h
RAM page pointer
Page pointer to external memory
4000h
Motor-output DACs
Base address for motor-output D/A converters
8000h
Parallel interface
Base address for parallel interface communication
MC3110 Technical Specifications
15
3 Electrical Characteristics
3.1
DC characteristics
(Vcc and Ta per operating ratings, Fclk = 20.0 MHz)
Symbol
Vcc
Idd
Minimum
4.75 V
Vihreset
Input Voltages
Logic 1 input voltage
2.0 V
Logic 0 input voltage
-0.3 V
Logic 1 voltage for clock pin
3.0 V
(ClockIn)
Logic 0 voltage for clock pin
-0.3 V
(ClockIn)
Logic 1 voltage for reset pin (reset) 2.2 V
Voh
Vol
Logic 1 Output Voltage
Logic 0 Output Voltage
Iout
Tri-State output leakage current
Iin
Input current
-10 µA
Cio
Input/Output capacitance
15 pF
Vih
Vil
Vihclk
Voclk
Zai
Ednl
Einl
3.2
Parameter
Supply Voltage
Supply Current
Maximum
5.25 V
80 mA
0.7 V
Vcc + 0.3 V
0.33 V
Analog Input
Analog input source impedance
Differential nonlinearity error.
-1
Difference between the step width
and the ideal value.
Integral nonlinearity error.
Maximum deviation from the best
straight line through the ADC
transfer characteristics, excluding
the quantization error.
open outputs
Vcc + 0.3 V
0.8 V
Vcc + 0.3 V
Output Voltages
2.4 V
Other
-5 µA
Conditions
5 µA
10 µA
@CP Io = -23 mA
@CP Io = 6 mA
@CP
0 < Vout < Vcc
@CP
0 < Vi < Vcc
@CP typical
9kΩ
1.5 LSB
+/-1.5 LSB
AC characteristics
See timing diagrams, Section 4, for Tn numbers. The symbol “~” indicates active low signal.
Timing Interval
Clock Frequency (Fclk)
Clock Pulse Width
Clock Period (note 2)
Encoder Pulse Width
Dwell Time Per State
~HostSlct Hold Time
Tn
T1
T2
T3
T4
T6
Minimum
> 0 MHz
25 nsec
50 nsec
150 nsec
75 nsec
0 nsec
MC3110 Technical Specifications
16
Maximum
20 MHz (note 1)
Timing Interval
~HostSlct Setup Time
HostCmd Setup Time
HostCmd Hold Time
Read Data Access Time
Read Data Hold Time
~HostRead High to HI-Z Time
HostRdy Delay Time
~HostWrite Pulse Width
Write Data Delay Time
Write Data Hold Time
Read Recovery Time (note 2)
Write Recovery Time (note 2)
Read Pulse Width
Address Setup Delay Time
Data Access Time
Address Setup Delay Time
Address Setup to WriteEnable High
RAMSlct Low to WriteEnable High
Address Hold Time
WriteEnable Pulse Width
Data Setup Time
Data Setup before Write High Time
Address Setup Delay Time
Data Access Time
Data Hold Time
Address Setup Delay Time
Address Setup to WriteEnable High
PeriphSlct Low to WriteEnable High
Address Hold Time
WriteEnable Pulse Width
Data Setup Time
Data Setup before Write High Time
Read to Write Delay Time
Reset Low Pulse Width
RAMSlct Low to Strobe Low
Strobe High to RAMSlct High
WriteEnable Low to Strobe Low
Strobe High to WriteEnable High
PeriphSlct Low to Strobe Low
Strobe High to PeriphSlct High
Tn
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T23
T24
T25
T26
T27
T28
T29
T30
T31
T32
T33
T34
T35
T36
T37
T38
T39
T40
T50
T51
T52
T53
T54
T55
T56
Minimum
0 nsec
0 nsec
0 nsec
100 nsec
70 nsec
Maximum
25 nsec
10 nsec
20 nsec
150 nsec
35 nsec
0 nsec
60 nsec
60 nsec
70 nsec
7 nsec
19 nsec
7 nsec
72 nsec
79 nsec
17 nsec
39 nsec
3 nsec
42 nsec
7 nsec
71 nsec
2 nsec
7 nsec
122 nsec
129 nsec
17 nsec
89 nsec
3 nsec
92 nsec
50 nsec
5.0 µsec
1 nsec
4 nsec
1 nsec
3 nsec
1 nsec
4 nsec
Note 1 Performance figures and timing information valid at Fclk = 20.0 MHz only. For timing
information and performance parameters at Fclk < 20.0 MHz, refer to section 7.1.
Note 2 The clock low/high split has an allowable range of 45-55%.
MC3110 Technical Specifications
17
4 I/O Timing Diagrams
For the values of Tn, please refer to the table in Section 3.2.
The host interface timing shown in diagrams 4.4 and 4.5 is only valid when an external logic device is
used to provide a parallel communication interface. Refer to section 6 for more information.
4.1
Clock
ClockIn
T1
4.2
T1
T2
Quadrature encoder input
T3
T3
Quad A
T4
T4
Quad B
~Index
4.3
Reset
Vcc
ClockIn
~RESET
T50
MC3110 Technical Specifications
18
4.4
Host interface, 8/16 mode (requires external logic device)
4.4.1
Instruction write, 8/16 mode
T7
T6
see note
~HostSlct
T9
T8
HostCmd
see note
T18
T14
T14
~HostWrite
T16
HostData0-7
T16
High byte
Low byte
HostRdy
T15
T15
T13
Note: If setup and hold times are met, ~HostSlct and HostCmd may be de-asserted at this point.
4.4.2
Data write, 8/16 mode
~HostSlct
T7
T6
see note
HostCmd
T8
T9
see note
T18
T14
T14
~HostWrite
T16
HostData0-7
T16
High byte
Low byte
HostRdy
T15
T15
T13
Note: If setup and hold times are met, ~HostSlct and HostCmd may be de-asserted at this
point.
MC3110 Technical Specifications
19
4.4.3
Data read, 8/16 mode
T7
T6
~HostSlct
see note
T9
T8
HostCmd
see note
~HostRead
T19
T12
HostData0-7
High
byte
High-Z
T10
High-Z
High-Z
Low byte
T11
HostRdy
T13
Note: If setup and hold times are met, ~HostSlct and HostCmd may be de-asserted at this
point.
4.4.4
Status read, 8/16 mode
T7
~HostSlct
HostCmd
T6
T9
T8
T17
~HostRead
T19
T12
HostData0-7
High-Z
High-Z
High
byte
T10
T11
MC3110 Technical Specifications
20
Low byte
High-Z
4.5
Host interface, 16/16 mode (requires external logic device)
4.5.1
Instruction write, 16/16 mode
~HostSlct
T7
T6
HostCmd
T9
T8
T14
~HostWrite
T16
HostData0-15
HostRdy
T15
T13
4.5.2
Data write, 16/16 mode
T7
T6
~HostSlct
T9
T8
HostCmd
T14
~HostWrite
T16
HostData0-15
HostRdy
T15
T13
MC3110 Technical Specifications
21
4.5.3
Data read, 16/16 mode
~HostSlct
T6
T7
HostCmd
T8
T9
T19
~HostRead
T12
HostData0-15
High-Z
High-Z
T10
T11
HostRdy
T13
4.5.4
Status read, 16/16 mode
T7
T6
T8
T9
~HostSlct
HostCmd
T19
~HostRead
T12
HostData0-15
High-Z
High-Z
T10
T11
MC3110 Technical Specifications
22
4.6
External memory timing
4.6.1
External memory read
Note: PMD recommends using memory with an access time no greater than 15 nsec.
T20
T40
~RAMSlct
Addr0-Addr15
W/~R
~WriteEnbl
T21
Data0-Data15
T51
T52
~Strobe
4.6.2
External memory write
~RAMSlct
T23
T24
Addr0-Addr15
T25
T26
R/~W
W/~R
T29
~WriteEnbl
T28
T27
T27
Data0-Data15
T53
~Strobe
MC3110 Technical Specifications
23
T54
4.7
Peripheral device timing
4.7.1
Peripheral device read
T30
T40
~PeriphSlct
Addr0-Addr15
T31
W/~R
~WriteEnbl
T31
Data0-Data15
T55
T32
T56
~Strobe
4.7.2
Peripheral device write
~PeriphSlct
T33
T34
Addr0-Addr15
T35
T36
R/~W
W/~R
T39
~WriteEnbl
T38
T37
T37
Data0-Data15
T53
~Strobe
MC3110 Technical Specifications
24
T54
5 Pinouts and Pin Descriptions
5.1
Pinouts for MC3110
2, 7, 13, 21, 35, 36, 40, 47, 50,
52, 60, 62, 66, 93, 103, 121
1
4
6
130
129
41
132
43
44
99
98
58
110
111
112
114
115
116
117
118
119
122
123
124
125
126
127
128
9
10
11
12
15
16
17
18
19
22
23
24
25
26
27
28
~WriteEnbl
R/~W
~Strobe
~PeriphSlct
~RAMSlct
~Reset
W/~R
SrlRcv
SrlXmt
SrlEnable
~HostIntrpt
ClockIn
Addr0
Addr1
Addr2
Addr3
Addr4
Addr5
Addr6
Addr7
Addr8
Addr9
Addr10
Addr11
Addr12
Addr13
Addr14
Addr15
Data0
Data1
Data2
Data3
Data4
Data5
Data6
Data7
Data8
Data9
Data10
Data11
Data12
Data13
Data14
Data15
VCC
CP
AnalogVcc
AnalogRefHigh
AnalogRefLow
AnalogGnd
Analog1
Analog2
Analog3
Analog4
Analog5
Analog6
Analog7
Analog8
PosLim1
NegLim1
AxisOut1
AxisIn1
PWMMag1
PWMSign1
QuadA1
QuadB1
~Index1
~Home1
NC/Synch
I/OIntrpt
PrlEnable
GND
3, 8, 14, 20, 29, 37, 46, 56, 59,
61, 71, 92, 104, 113, 120
Unassigned
5, 30-34, 38, 39, 42, 45, 48, 49,
51, 55, 57, 73, 90, 91, 95, 97,
101, 102, 105, 106, 107-109, 131
AGND
78-81
MC3110 Technical Specifications
25
84
85
86
87
74
89
75
88
76
83
77
82
63
64
94
72
100
96
67
68
69
70
54
53
65
5.2
CP chip pin description table
Pin Name and number Direction
Description
~WriteEnbl
R/~W
1
4
output
output
~Strobe
6
output
~PeriphSlct
~RAMSlct
~Reset
130
129
41
output
output
input
W/~R
132
output
SrlRcv
43
input
SrlXmt
SrlEnable
44
99
output
output
~HostIntrpt
I/OIntrpt
98
53
output
input
PrlEnable
65
input
When low, this signal enables data to be written to the bus.
This signal is high when the CP chip is performing a read, and low when it is
performing a write.
This signal is low when the data and address are valid during CP
communications.
This signal is low when peripheral devices on the data bus are being addressed.
This signal is low when external memory is being accessed.
This is the master reset signal. When brought low, this pin resets the processor to
its initial conditions.
This signal is the inverse of R/~W; it is high when R/~W is low, and vice versa. For
some decode circuits, this is more convenient than R/~W.
This pin receives serial data from the asynchronous serial port. If serial
communication is not used, this pin should be tied to Vcc.
This pin transmits serial data to the asynchronous serial port.
This pin sets the serial port enable line. SrlEnable is always high for the point-topoint protocol and is high during transmission for the multi-drop protocol.
When low, this signal causes an interrupt to be sent to the host processor.
This signal interrupts the CP chip when a host I/O transfer is complete. It
should be connected to CPIntrpt of the parallel interface chip.
If the parallel interface is disabled (see below) this signal can be left unconnected
or tied to Vcc.
This signal enables/disables the parallel communication with the host. If this
signal is tied high, the parallel interface is enabled. If this signal is tied low the
parallel interface is disabled. See section 6 of this manual for more information
on parallel communication.
WARNING! This signal should only be tied high if an external
logic device that implements the parallel communication logic
included in the design. This signal is an output during device reset
and as such any connection to GND or Vcc must be via a series
resistor.
Data0
Data1
Data2
Data3
Data4
Data5
Data6
Data7
Data8
Data9
Data10
Data11
Data12
Data13
Data14
Data15
9
10
11
12
15
16
17
18
19
22
23
24
25
26
27
28
bi-directional
Multi-purpose data lines. These pins comprise the CP chip’s external data bus,
used for all communications with peripheral devices such as external memory or
DACs. They may also be used for parallel-word input and for user-defined I/O
operations.
MC3110 Technical Specifications
26
Pin Name and number Direction
Description
Addr0
Addr1
Addr2
Addr3
Addr4
Addr5
Addr6
Addr7
Addr8
Addr9
Addr10
Addr11
Addr12
Addr13
Addr14
Addr15
ClockIn
110
111
112
114
115
116
117
118
119
122
123
124
125
126
127
128
58
output
Multi-purpose Address lines. These pins comprise the CP chip’s external address
bus, used to select devices for communication over the data bus.
They may be used for DAC output, parallel word input, or user-defined I/O
operations. See the Pilot Motion Processor User’s Guide for a complete memory map.
input
AnalogVcc
84
input
AnalogRefHigh 85
input
AnalogRefLow
86
input
AnalogGND
87
Analog1
Analog2
Analog3
Analog4
Analog5
Analog6
Analog7
Analog8
PWMMag1
74
89
75
88
76
83
77
82
100
input
This is the clock signal for the motion processor. It is driven at a nominal 20
MHz.
CP chip analog power supply voltage. This pin must be connected to the analog
input supply voltage, which must be in the range 4.5-5.5 V
If the analog input circuitry is not used, this pin must be connected to Vcc.
CP chip analog high voltage reference for A/D input. The allowed range is
AnalogRefLow to AnalogVcc.
If the analog input circuitry is not used, this pin must be connected to Vcc.
CP chip analog low voltage reference for A/D input. The allowed range is
AnalogGND to AnalogRefHigh.
If the analog input circuitry is not used, this pin must be connected to GND.
CP chip analog input ground. This pin must be connected to the analog input
power supply return.
If the analog input circuitry is not used, this pin must be connected to GND.
These signals provide general-purpose analog voltage levels, which are sampled
by an internal A/D converter. The A/D resolution is 10 bits.
The allowed range is AnalogRefLow to AnalogRefHigh.
PWMSign1
96
output
QuadA1
QuadB1
67
68
input
Any unused pins should be tied to AnalogGND.
If the analog input circuitry is not used, these pins should be tied to GND.
output
This pin provides the Pulse Width Modulated signal to the motor. This is the
magnitude signal.
The PWM resolution is 10 bits at a frequency of 20.0 KHz.
This pin provides the sign (direction) of the PWM signal to the motor amplifier.
This signal is high when the PWM output is positive, and low when it is negative.
These pins provide the A and B quadrature signals for the incremental encoder.
When the axis is moving in the positive (forward) direction, signal A leads signal
B by 90°.
The theoretical maximum encoder pulse rate is 5.1 MHz. Actual maximum rate
will vary, depending on signal noise.
NOTE: Many encoders require a pull-up resistor on each signal to establish a
proper high signal. Check your encoder’s electrical specification.
MC3110 Technical Specifications
27
Pin Name and number Direction
Description
~Index1
This pin provides the Index signal for the incremental encoder. A valid index
pulse is recognized by the processor when this signal transitions from high to low.
69
input
There is no internal gating of the index signal with the encoder A
and B inputs. This must be performed externally if desired. Refer
to the section 7.11 for an example schematic.
~Home1
70
input
This pin provides the Home signal, general-purpose inputs to the positioncapture mechanism. A valid Home signal is recognized by the processor when
~Home goes low.
WARNING! If this pin is not used, its signal should be tied high.
PosLim1
63
input
This signal provides input from the positive-side (forward) travel limit switch.
On power-up or Reset this signal defaults to active low interpretation, but the
interpretation can be set explicitly using the SetSignalSense instruction.
WARNING! If this pin is not used, its signal should be tied high.
NegLim1
64
input
This signal provides input from the negative-side (reverse) travel limit switch. On
power-up or Reset this signal defaults to active low interpretation, but the
interpretation can be set explicitly using the SetSignalSense instruction.
WARNING! If this pin is not used, its signal should be tied high.
This signal is an output during device reset and as such any
connection to GND or Vcc must be via a series resistor.
AxisOut1
AxisIn1
NC/Synch
Vcc
94
output
This pin can be programmed to track the state of any bit in the Status registers.
If this pin is not used it may be left unconnected.
72
input
This is a general-purpose or programmable input. It can be used as a breakpoint
input, to stop a motion axis, or to cause an Update to occur.
If this pin is not used it may be left unconnected.
54
input/output On the MC3110 this pin is not used.
On the MC3113, this pin is the synchronization signal. In the disabled mode,
the pin is configured as an input and is not used. In the master mode, the pin
outputs a synchronization pulse that can be used by slave nodes or other devices
to synchronize with the internal chip cycle of the master node. In the slave
mode, the pin is configured as an input and a pulse on the pin synchronizes the
internal chip cycle.
2, 7, 13, 21, 35, 36, 40, CP digital supply voltage. All of these pins must be connected to the supply
47, 50, 52, 60, 62, 66, voltage. Vcc must be in the range 4.75 - 5.25 V
93, 103, 121
WARNING! Pin 35 must be tied HIGH with a pull-up resistor. A
nominal value of 22K Ohms is suggested.
GND
AGND
unassigned
unassigned
3, 8, 14, 20, 29, 37, 46, CP ground. All of these pins must be connected to the power supply return.
56, 59, 61, 71, 92, 104,
113, 120
78-81
These signals must be tied to AnalogGND.
If the analog input circuitry is not used, these pins must be tied to GND.
45, 48, 49, 51, 55, 73, These signals may be connected to GND for better noise immunity and reduced
90, 91, 105, 106, 107, power consumption or they can be left unconnected (floating).
108, 109
5, 30-34, 38, 39, 42,
These signals must be left unconnected (floating).
57, 95, 97, 101, 102,
131
MC3110 Technical Specifications
28
6 Parallel Communication
With the addition of an external logic device, the Pilot motion processor can communicate with a
host processor using a parallel data stream. This offers a higher communication rate than a serial
interface and may be used in configurations where a serial connection is not available or not
convenient. This section details the required logic that must be implemented in the external device
as well as the necessary connections to the CP chip.
The reference design files for the parallel interface chip, in Actel/ViewLogic format, are available
from PMD. There are two versions of the design, one for interfacing with host processors that have
an 8-bit data bus and one for host processors that have a 16-bit data bus. The designs are called
IOPIL8 and IOPIL16 respectively. The interface to the CP chip is essentially identical in both.
The function of the I/O chip is to provide a shared-memory style interface between the host and CP
chip, comprised of four 16-bit wide locations. These are used for transferring commands and data
between the host and Pilot motion processor. The CP chip accesses the command/data registers
using its 16-bit external data bus while the host accesses the registers via a parallel interface with chip
select, read, write and command/data signals. If necessary, the host side interface can be modified
by the designer to match specific requirements of the host processor.
6.1
Host interface pin description table
Pin Name
Direction
Description
HostCmd
input
HostRdy
output
~HostRead
~HostWrite
~HostSlct
CPIntrpt
input
input
input
output
CPR/~W
input
CPStrobe
input
This signal is asserted high to write a host instruction to the motion processor, or to
read the status of the HostRdy and HostIntrpt signals. It is asserted low to read or write
a data word.
This signal is used to synchronize communication between the motion processor
and the host. HostRdy will go low (indicating host port busy) at the end of a read or
write operation according to the interface mode in use, as follows:
Interface Mode HostRdy goes low
8/16
after the second byte of the instruction word
after the second byte of each data word is transferred
16/16
after the 16-bit instruction word
after each 16-bit data word
serial
n/a
HostRdy will go high, indicating that the host port is ready to transmit, when the last
transmission has been processed. All host port communications must be made
with HostRdy high (ready).
A typical busy-to-ready cycle is 12.5 microseconds, but can be substantially longer,
up to 100 microseconds.
When ~HostRead is low, a data word is read from the motion processor.
When ~HostWrite is low, a data word is written to the motion processor.
When ~HostSlct is low, the host port is selected for reading or writing operations.
I/O chip to CP chip interrupt. This signal sends an interrupt to the CP chip
whenever a host–chipset transmission occurs. It should be connected to CP chip
pin 53, I/OIntrpt.
This signal is high when the I/O chip is reading data from the I/O chip, and low
when it is writing data. It should be connected to CP chip pin 4, R/W.
This signal goes low when the data and address become valid during Motion
processor communication with peripheral devices on the data bus, such as external
memory or a DAC. It should be connected to CP chip pin 6, Strobe.
MC3110 Technical Specifications
29
Pin Name
Direction
Description
CPPeriphSlct
input
CPAddr0
CPAddr1
CPAddr15
input
MasterClkIn
input
CPClk
output
HostData0
HostData1
HostData2
HostData3
HostData4
HostData5
HostData6
HostData7
HostData8
HostData9
HostData10
HostData11
HostData12
HostData13
HostData14
HostData15
CPData0
CPData1
CPData2
CPData3
CPData4
CPData5
CPData6
CPData7
CPData8
CPData9
CPData10
CPData11
CPData12
CPData13
CPData14
CPData15
bi-directional,
tri-state
This signal goes low when a peripheral device on the data bus is being addressed. It
should be connected to CP chip pin 130, PeriphSlct.
These signals are high when the CP chip is communicating with the I/O chip (as
distinguished from any other device on the data bus). They should be connected to
CP chip pins 110 (Addr0), 111 (Addr1), and 128 (Addr15).
This is the master clock signal for the motion processor. It is driven at a nominal
40 MHz
This signal provides the clock pulse for the CP chip. Its frequency is half that of
MasterClkIn (pin 89), or 20 MHz nominal. It is connected directly to the CP chip
I/Oclk signal (pin 58).
These signals transmit data between the host and the Motion processor through
the parallel port. Transmission is mediated by the control signals ~HostSlct,
~HostWrite, ~HostRead and HostCmd.
In 16-bit mode, all 16 bits are used (HostData0-15). In 8-bit mode, only the loworder 8 bits of data are used (HostData0-7).
bi-directional
These signals transmit data between the I/O chip and pins Data0-15 of the CP chip,
via the motion processor data bus.
MC3110 Technical Specifications
30
6.2
16-bit Host Interface (IOPIL16)
This design implements a parallel interface with a host processor utilizing a 16-bit data bus. An
understanding of the underlying operation of the design is only necessary if the designer intends to
make modifications. In most cases this design can be implemented without changes. The following
notes should be read while referencing the schematics. IOPIL16 1 is the top level schematic. The
timing for the host to I/O chip communication can be found in section 4.5 and the timing for the
CP to I/O chip communication can be found in section 4.7.
The description below identifies the key elements of each schematic starting with the host side
signals. The paragraph title identifies the key schematic(s) being described in the text.
IOPIL16 3
The host interface is shown in sheet IOPIL16 3. The incoming data HD[15:0] is latched in the
transparent latches when ~HG1 and ~HG2 go high. This would be the result of a write from the
host to the CP. The latched data HI[15:8] and HI[7:0] go to schematic IOPIL16 1 and IOPIL16 5.
Data from the interface to the host, HO[15:8] and HO[7:0] is enabled onto the host bus, HD[15:0],
by HOES2 and HOES1 respectively. The output latches, which present the data during a host read,
are always transparent because GOUT is connected to VDD. The latched I/O is an I/O option on
the Actel part used and could be omitted in the host interface if a different CPLD or FPGA does not
have this feature.
IOPIL16 1
The control for the host interface starts on IOPIL16 1. HOES1 and HOES2 are the AND of
~HSEL and ~HRD and enable read data onto the host bus, as previously described. HRDY is a
handshaking signal to the host to allow asynchronous communication between the host and the CP.
The host must wait until HRDY is true before attempting to communicate with the CP. This signal
is copied as a bit in the host status register. The host status register may be read at any time to
determine the state of HRDY, or the HRDY output may be used as an interrupt to the host.
~HSEL, ~HRD, ~HWR, and HA0 are the buffered inputs of the host control signals.
HOST INTERFACE/IOPIL16 5
Data from the host HI[15:8] and HI[7:0] is written into REG1 and REG2 on the schematic HOST
INTERFACE by ~EN1 and ~EN2. These registers have a 2 to 1 multiplexed input with both the
host data and the CP data being written to these registers. This is convenient for diagnostic purposes
and is very efficient in the Actel A42MX FPGA's, which are multiplexer based but if the
configuration of the logic device used demands it, separate registers could be used for the host and
CP data. The schematic for this register is shown as DFME8. Only commands and checksums are
written to registers REG1 and REG2 while data is written and read from the set of data registers,
DATREG shown on IOPIL16 5. These 3 data registers buffer data sent to and from the CP,
reducing the number of interrupts the CP must handle. The output from REG1 and REG2,
CIQ[15:8] and CIQ[7:0] go to IOPIL16 5, where they are multiplexed with the other data registers.
The multiplexed result, IQ[15:8] and IQ[7:0], is multiplexed with HST[15:8] and HST[7:0] - the
output of the host status registers REG3 and REG4. As previously mentioned, HRDY becomes
HST15 so it can be read by the host. The rest of the status register is written by the CP to provide
information to the host. HA0 acts as an address bit, and usually is an address bit on the bus. When
the host is writing, HA0 low indicates data and HA0 high indicates a command. When the host is
reading, HAO low indicates data and HA0 high indicates status. Read status is the only transaction
MC3110 Technical Specifications
31
allowed while HRDY is low. During a host write the AND gate (G1:HOST INTERFACE) and two
flops latch the incoming data in the interface latches by driving ~HG1, and ~HG2 low from the
start of the write transaction until the first negative clock transition after the first positive transition
following the start of the write cycle. This tail-biting circuit removes the requirement for hold time
on the data bus.
HICTLA
Most of the control logic for the host interface is shown on schematic HICTLA. The sequencer at
the top generates HCYC one clock interval after the interface has been accessed and the host has
finished the transaction. The nature of the transaction, rd/wr, command/data, and read status is
preserved in the three flops F13, F8, and F9. A host write or a CP write, DSIW, enable REG1 and
REG2 on the HOST INTERFACE schematic discussed previously. A host data write generates
~ENHD1 and ~ENHD2 for the data registers on the DATREG schematic. The logic at the bottom
of the page generates the CP interrupt, the HRDY and the HCMDFL. The HCMDFL is used in the
CP status to indicate a command. DSIW, the CP writing to REG1 and REG2 on the HOST
INTERFACE schematic clears the interrupt and reasserts HRDY. HRDY is de-asserted during all
host transactions except read status, and stays de-asserted until the CP has completed the DSIW
cycle that clears the interrupt and reasserts HRDY. As mentioned previously data transfers to and
from the host use the data registers and do not interrupt the CP. The CP knows the number of data
transfers that must take place after decoding the command. It places this number, 0-3, in the 2 least
significant bits of the host status register, HST[1:0]. These become DPNT[1:0] on this page of the
schematic and enable an interrupt at 0 for a read and 1 or 0 for a write. The CP always leaves theses
bit set to 0 unless setting up a multiple word data transfer. If INTEN is true and LRDST, latched
read status, is false, HCYC will generate an interrupt to the CP. This will also hold HRDY false until
after the CP writes to the interface register, DSIW, thereby generating ~CLRFLGS.
IOPIL16 4
The CP interface is shown in sheet IOPIL16 4. The incoming data DSD[15:0] is latched in the
transparent latches when ~DG1 and ~DG2 go high. This occurs at the completion of a write from
the CP to the I/O chip. The latched data DSI[15:8] and DSI[7:0] go to schematic IOPIL16 1 and
IOPIL16 5. DSI[7:0] also goes to IOPIL16 2. Data from the interface to the CP, DO[15:8] and
DO[7:0] is enabled onto the CP bus, DSD[15:0], by DOE2 and DOE1 respectively. The output
latches, which present the data during a CP read, are always transparent because GOUT is connected
to VDD. The latched I/O in the Actel part contains both input and output latches. The output
latches could be omitted in the CP interface if a different CPLD or FPGA does not have this feature.
The two incoming CP address bits CPA0 and CPA1 are also latched using ~DG3. The 20CK signal
is the clock for the CP. This is a 20 MHz clock derived from a 40 MHz clock input.
IOPIL16 2
The CP control starts on IOPIL16 2. The I/O control is generated from ~CPSTRB, ~CPIS,
CPSEL and R/W. ~DG1, ~DG2, and ~DG3 latch the incoming data and DOE1 and DOE2 outenable the data from this chip to the CP. F2 and F4 tail-bite the write to avoid having to specify hold
times on the data. Flop F1 divides the 40MHz clock down to 20 MHz. A 20 MHz clock could be
used for this interface and the CP.
MC3110 Technical Specifications
32
DSPWA
The CP write control is contained on schematic DSPWA. The CP interface uses page addressing to
save I/O pins. F0, F1 and F2 make up the page register. In addition there are the 2 address bits,
LA0 and LA1. A write to address 0 selects the page register with DSI[2:0] going to the page register
and selecting the page for the successive transfers. A read from address 0 reads the status register on
all pages. Pages 4 and 6 are the only ones implemented in this device. L1 latches the r/w level. The
write decoding generates DSIW which enables writes to the DFME8 registers reg1 and reg2 shown
on the HOST INTERFACE schematic. DSIW also clears the CP interrupt and restores HRDY.
DSWST writes to the host status register also shown on the HOST INTERFACE schematic.
DSWDREG implements writing to the data registers shown on IOPIL16 5 and DATREG. Finally
the logic at the bottom of the page generates CPCYC, a 1-clock interval after the CP cycle is over
that implements the actual writes to the registers. The use of the data bus latches and the post bus
cycle transfers keeps as much of the logic synchronous as possible given two asynchronous devices,
without requiring clocking at several times the bus speed.
DSPRA
The CP read control is contained on schematic DSPRA. The 2 by 16 bit mux selects CP status if the
CP latched address is 0 and IQ[15:0] if the address is not 0. The only significant status bits are bits 15
(indicating the CP is interrupting the host), bits 13 and 14 (both 0 indicating a 16 bit host interface)
and bit 0 (set to 1 during a host command transfer and 0 during data transfer).
HOST INTERFACE
Both the CP and the host use a special mode to transfer data to avoid unnecessary CP interrupts.
This special mode is under the control of the CP and is transparent to the host. When the CP
receives a command from the host it initializes the transfer by setting the number of transfers
expected (0,1,2 or 3) in the 2 LSB's of the host status register, REG3 and REG4 on HOST
INTERFACE. This write (DSWST) also loads these bits into the 2 bit down counter DCNT2 on
IOPIL16 5. Note that a Q8 low, which indicates a host command, asynchronously clears this
register enabling interrupts on schematic HICTLA. If DPNT[1:0] is not 0 and Q8 is high, indicating
a host data transfer, and SINT goes high indicating the end of a host cycle the counter is
decremented. MXAD2 selects address RA from the CP latched address bits if the page register
contains 6, or the counter contents DPNT[1:0] if not. This allows the CP to have direct access to
registers 1, 2, and 3, using addresses 1,2,and 3 on page 6. The host on the other hand can only read
or write to the data register, HA0 low and the counter will auto decrement from 3 down to 0
allowing the host to access the registers on DATREG where REG1=R1 and R2, REG2=R3 and R4,
and REG3=R5 and R6. The writes are enabled by the two decoders DECE2X4, while the reads are
selected by the two 4x8 muxes, MUX1 and MUX2 controlled by the two 2x1 muxes MDS1 and
MDS0. The output data IQ[15:0] goes to HOST INTERFACE schematic below IOPIL16 1 and to
DSPRA below IOPIL16 2. The write data is HI[15:8], HI[7:0] from the host and DSI[15:8] and
DSI[7:0] from the CP.
MC3110 Technical Specifications
33
A
B
C
D
HINTF
IN17
INBUF
PAD
HSTSEL
Y
HSEL
HSEL
HOST INTERFACE
HRD
INBUF
PAD
HSTRD
IN18
Y
(HINTRFA)
HO[7:0]
HWR
HO[7:0]
HRD
HA0
1
1
HO[15:8]
HO[15:8]
INBUF
PAD
HSTWR
IN19
Y
HI[7:0]
HI[7:0]
HWR
HI[15:8]
HI[15:8]
INBUF
PAD
HADR0
IN20
Y
HA0
DSI[15:8]
CIQ[7:0]
DSI[15:8]
CIQ[7:0]
DSI[7:0]
CIQ[15:8]
DSI[7:0]
CIQ[15:8]
DPNT[1:0]
HST[1:0]
Q8
DSWST
DSWST
DSIW
DSIW
Q8
SINT
2
SINT
HG1
HG1
HG2
HG2
2
IQ[7:0]
IQ[7:0]
HST14
ST15
IQ[15:8]
IQ[15:8]
HCMDFL
ST0
DSPINTR
CLK
HRD
A
HSEL
B
HRD
A
3
HSEL
B
AND2B
Y
HOES1
Y
HOES2
DSPINTR
CLK
OUTBUF
D
HST15
RDY
ENHD1
ENHD1
ENHD2
ENHD2
PAD
HRDY
3
AND2B
OUTBUF
DSPINTR
D
PAD
DSPINT
OUT5
4
4
IOPIL16 1
22 OCT 2002
A
B
C
DBS
DRAWN BY:
D
A
B
C
PNT0
CSEL0
PNT1
CSEL1
D
DSPRA
DSWDREG
DSWDREG
1
DSI[7:0]
DSIW
ST0
ST0
ST15
ST15
1
DSIW
DSI[7:0]
DSWST
IQ[15:0]
DSWST
IQ[15:0]
PP6
PP6
PP4
PP4
IN27
CS
PAD
CPR-W
PAD
INBUF
Y
CPSEL
DG3
DG3
IN28
INBUF
Y
DO[15:0]
LA0
LA0
LA1
LA1
DO[15:0]
IN26
PAD
STRB
2
INBUF
Y
2
IN30
PAD
IS
INBUF
CPSEL
Y
R/W
CPSTRB
CPIS
CKBUF
A
20CK
Y
CLK
R/W
CPSTRB
CPIS
CPCYC
CPCYC
LA0
LA0
LA1
LA1
CLK
DSPRA
DSPWA
CLKINT
CPSTRB
A
CPIS
B
CPSEL
C
G1
NAND3B
Y CSACC
A
B
C
R/W
G2
AND4B
Y
F1
DOE1
D
IB1
D
3
CLKIN
A
B
C
PAD
INBUF
QN
20CK
DF1A
Y
40CK
3
CLK
G3
AND4B
Y
DOE2
D
A
B
G4
NAND3B
Y DG1
C
A
B
G5
NAND3B
Y DG2
C
F4
F2
CSACC
A G6
4
CSACC
B
CQ3
C
D
D
Q
DF1
NAND4B
Y DG3
CQ1
D
Q
CQ3
DF1
CLK
4
CLK
IOPIL16 2
CLK
24 OCT 2002
A
B
C
DBS
DRAWN BY:
D
A
B
C
D
HIGH SLEW
D
HO0
GOUT
E
D
PAD
Q
HIGH SLEW
HD0
G
1
D
VDD
D
HO4
GOUT
VDD
Q
Q
HIGH SLEW
PAD
Q
HD4
HI0
D
Q
Q
D
HO8
GOUT
VDD
G
BBDLHS
GIN
E
D
GIN
HIGH SLEW
PAD
Q
HD8
HI4
D
Q
Q
D
HO12
VDD
G
BBDLHS
G
E
D
GOUT
GIN
PAD
Q
HD12
1
G
HI8
D
BBDLHS
G
E
D
Q
Q
HI12
BBDLHS
GIN
G
G
HIGH SLEW
D
HO1
GOUT
E
D
PAD
Q
HIGH SLEW
HD1
G
D
D
HO5
GOUT
Q
Q
HIGH SLEW
PAD
Q
HD5
D
HO9
GOUT
G
HI1
D
BBDLHS
GIN
E
D
Q
Q
G
GIN
HIGH SLEW
PAD
Q
HD9
HI5
D
HO13
GOUT
G
D
BBDLHS
2
E
D
Q
Q
GIN
PAD
Q
HD13
G
HI9
D
BBDLHS
G
E
D
Q
Q
HI13
BBDLHS
GIN
G
G
2
HIGH SLEW
D
HO2
GOUT
E
D
PAD
Q
HIGH SLEW
HD2
G
D
D
HO6
GOUT
Q
Q
D
HI2
D
GOUT
GIN
E
Q
Q
Q
PAD
HD3
D
HO7
GOUT
Q
Q
HI3
HD10
D
HO14
GOUT
D
Q
Q
GIN
E
D
E
D
Q
HI10
D
Q
Q
HI14
BBDLHS
GIN
G
HIGH SLEW
HD7
D
HO11
GOUT
Q
E
D
Q
PAD
GOUT
G
HI7
D
GIN
HI[7:0]
D
HO15
HD11
Q
Q
G
E
D
PAD
Q
HD15
G
D
HI11
Q
Q
3
HI15
BBDLHS
BBDLHS
G
HD14
HIGH SLEW
PAD
G
Q
PAD
Q
G
BBDLHS
BBDLHS
GIN
G
HG1
PAD
Q
G
HI6
G
D
BBDLHS
GIN
E
D
HIGH SLEW
HIGH SLEW
G
3
D
D
HO10
BBDLHS
G
D
HD6
GOUT
HIGH SLEW
HO3
PAD
Q
G
BBDLHS
GIN
E
D
HIGH SLEW
GIN
G
G
HI[15:0]
HG1
HO[15:8]
HG2
HO[7:0]
HG2
VCC
HOES1
HOES2
Y
VDD
4
4
IOPIL16 3
21 OCT 2002
A
B
C
DBS
DRAWN BY:
D
A
B
C
D
DOE1
GOUT
VDD
E
D
PAD
Q
HIGH SLEW
DSD0
G
D
Q
D
GOUT
VDD
Q
E
D
DO4
1
HIGH SLEW
PAD
Q
D
DO8
DSD4
GOUT
VDD
G
E
D
HIGH SLEW
PAD
Q
GOUT
VDD
G
D
DO12
DSD8
E
D
PAD
Q
DSD12
G
1
DSI0
D
BBDLHS
GIN
DOE2
DOE2
DOE1
HIGH SLEW
D
DO0
Q
Q
DSI4
D
BBDLHS
G
GIN
Q
Q
DSI8
D
BBDLHS
GIN
G
Q
Q
DSI12
BBDLHS
GIN
G
G
DOE1
GOUT
E
D
PAD
Q
HIGH SLEW
DSD1
G
D
E
D
DO5
D
GOUT
Q
Q
D
GOUT
GIN
E
PAD
Q
DSD2
GIN
D
Q
Q
D
GOUT
Q
DSI6
GIN
E
D
GIN
HIGH SLEW
D
PAD
Q
E
D
DO7
D
DSD3
GOUT
GOUT
DSD10
D
Q
Q
GIN
Q
PAD
GOUT
Q
Q
E
D
2
PAD
Q
DSD14
G
DSI10
D
Q
Q
DSI14
BBDLHS
GIN
G
G
HIGH SLEW
HIGH SLEW
DSD7
D
DO11
GOUT
D
DSI3
Q
Q
GIN
G
E
D
Q
PAD
GOUT
D
Q
Q
GIN
DSI[7:0]
E
D
Q
PAD
DSD15
G
D
DSI11
Q
Q
DSI15
3
BBDLHS
BBDLHS
G
D
DO15
DSD11
G
DSI7
BBDLHS
BBDLHS
D
DO14
DOE2
G
G
3
G
DOE2
HIGH SLEW
E
DSI13
HIGH SLEW
PAD
Q
BBDLHS
DOE1
D
Q
Q
BBDLHS
DOE1
DO3
D
G
D
G
DSD13
G
DSI9
G
BBDLHS
GIN
PAD
Q
DOE2
DO10
DSD6
G
Q
E
D
HIGH SLEW
PAD
Q
D
D
DO13
GOUT
D
G
DSI2
G
HIGH SLEW
DSD9
BBDLHS
E
D
GOUT
Q
Q
HIGH SLEW
DO6
Q
D
PAD
DOE2
BBDLHS
GIN
DSI5
DOE1
G
D
Q
Q
E
G
BBDLHS
G
D
D
DO9
DSD5
GOUT
D
HIGH SLEW
DO2
Q
DSI1
DOE1
2
HIGH SLEW
PAD
G
BBDLHS
GIN
DOE2
DOE2
DOE1
HIGH SLEW
D
DO1
GIN
G
G
DSI[15:8]
DG1
DO[15:8]
DG2
DO[7:0]
DOE2
DOE2
DG2
DOE1
VCC
Y
GND
GND
HIGH SLEW
HIGH SLEW
D
GOUT
4
E
D
Q
D
PAD
CPA0
GOUT
G
E
D
PAD
Q
CPA1
VDD
G
IOPIL16 4
OUTBUF
D
Q
BBDLHS
DG3
GIN
G
Q
D
LA0
Q
Q
LA1
20CK
D
PAD
CLKOUT
BBDLHS
DG3
GIN
G
21 OCT 2002
A
4
B
C
DBS
DRAWN BY:
D
A
B
C
A
ENHD1
B
DSWDREG
Y
OR2A
D
END1
1
1
DREG
A
ENHD2
DOE1
DOE1
PP4
PP4
B
Y
OR2A
END2
CIQ[7:0]
CIQ[7:0]
CIQ[15:8]
CIQ[15:8]
HI[7:0]
Q8
HI[7:0]
HI[15:8]
A
SINT
HIH[15:8]
IQ[7:0]
IQ[7:0]
DSI[7:0]
DSI[7:0]
DPNT0
A
DPNT1
B
IQ[15:8]
IQ[15:8]
B
NAND2B
Y
AND3
Y
DPINC
C
DSI[15:8]
DSI[15:8]
RA[1:0]
RA[1:0]
2
2
LA[1:0]
LA[1:0]
PP6
PP6
END1
END1
END2
END2
CLK
CLK
DATREG
DCNT2
DSWST
SLOAD
DPINC
3
ENABLE
Q8
3
ACLR
CLK
CLOCK
DPNT[1:0]
MXAD2
Q[1:0]
DSI[1:0]
DATA[1:0]
RA[1:0]
DATA0_[1:0]
RESULT[1:0]
DATA1_[1:0]
LA[1:0]
LA0
LA1
SEL0
4
4
IOPIL16 5
PP6
22 OCT 2002
A
B
C
DBS
DRAWN BY:
D
A
B
C
D
REG1
HST[1:0]
EN1
MUX1
MUX2X8
EN1
IQ[7:0]
REG3
S
DFME8
REG6
CK
1
1
HI[7:0]
CIQ[7:0]
A[7:0]
DSWST
Q[7:0]
HO[7:0]
DATA0_[7:0]
HST[7:0]
ENABLE
RESULT[7:0]
DATA1_[7:0]
DSI[7:0]
CLK
B[7:0]
CLOCK
HST[7:2]
Q[5:0]
DSI[7:2]
DATA[5:0]
BUF1
BUF
Y
DSL
SEL0
A
DSIW
REG4
REG2
REG7
EN2
A
BUF2
BUF
Y
EN1
DSWST
S
DSLA
ENABLE
DFME8
VDD
CLK
CLK
CLOCK
HI[15:8]
CIQ[15:8]
A[7:0]
Q[7:0]
2
HA0
ACLR
CK
HST[14:8]
Q[6:0]
DSI[14:8]
2
DSI[15:8]
HST14
DATA[6:0]
B[7:0]
MUX2
IQ[15:8]
MUX2X8
HICTLA
HO[15:8]
DATA0_[7:0]
ENHD1
ENHD1
ENHD2
ENHD2
RESULT[7:0]
DATA1_[7:0]
HST[1:0]
DPNT[1:0]
SINT
Q8
SINT
HST[15:8]
Q8
HSEL
HWR
HWR
EN1
EN1
HRD
HRD
EN2
EN2
HA0
HA0
SEL0
HSEL
3
DSIW
CLK
HRDY
3
HST15
DSPINTR
DSPINTR
HCMDFL
HCMDFL
DSIW
HA0
CK
HICTLA
G2
A
G1
HWR
4
HSEL
A
B
AND2B
Y
D
Q
DF1
CLK
D
B
QN
NAND2
Y
HOST INTERFACE
(HINTRFA)
HG1
DF1C
G3
CLK
A
B
NAND2
Y
4
HG2
CLK
24 OCT 2002
A
B
C
DBS
DRAWN BY:
D
A
B
INV1
HRD
A
Y
INV
HWR
A
HRD
B
F1
HCYC
F2
G1
D
Q
Y
OA1C
Q1
D
DF1
D0
D1
D2
D3
GND
DF1
CLK
HSEL
A
B
Y
AND2B
J
F3
Q2
Q
CLK
HCYC
Q
JKF2C
CK
LWR
Q
CS
CLK
K
CLR
VDD
DFM6A
S0
S1
CLK
G2
HWR
1
D
F13
C
HSEL
C
HRD
HWR
Q1
VCC
CLR
HSEL
A
HWR
B
Y
AND2B
1
SHWR
F8
Y
INV3
Q8 A
HCYC
HCYC
CK
J
CK
JKF2C
Q
Y
INV
HCMD
CS
CLK
K
CLR
VDD
G7
HSEL
A
HWR
B
HA0
C
Y
AND3B
SHCMD
F9
HCYC
J
CK
JKF2C
INV4
Q9 A
Q
INV
Y
CLK
K
CLR
VDD
G10
2
HSEL
A
HRD
B
HA0
C
LRDST
CS
2
AND3B
Y
SLRDST
INV2
A
A
HWR
NOR2
B
DSIW
A
HWR
Y
EN2
NAND2
B
Q8
Y
Y
INV
DSPINTR
G21
ENHD2
A
B
C
A
Y
NOR2
B
F5
EN1
F10
D
A
Y
NAND2
B
ENHD1
Q
D
DF1
CLK
DPNT[1:0]
DPNT0
A
DPNT1
B
LWR
C
RDEN
A
WREN
B
NAND2B
OR3C
Y
A
Y
A
LRDST
B
HCYC
SINT
B
CLRFLGS
C
AND3
Y SINTR
Y
HRDY
CC
3
A
B
HCYC
C
Q9
D
OA4
Y
EBSY
DSPINTR
F6
J
JKF
Q
CLK
K
Y
AND2A
Q
Q2
INTEN
C
Q8
A
B
Y
NOR4
D
CLK
Q1
NAND3B
2
DF1
CK
3
2
G19
HCYC
A
HCMD
B
AND2
F7
Y
HCCYC
J
JKF
Q
HCMDFL
HICTLA
CLK
4
K
4
CK
DSIW
A
INV
Y
CLRFLGS
21 OCT 2002
DBS
DRAWN BY:
A
B
C
D
A
B
C
D
DSI[7:0]
DSI0
D
E
1
F0
A
PNT0
Q
B
DFE1B
Y
AND3B
PP4
C
CLK
1
A
DSI1
D
E
F1
B
PNT1
Q
Y
AND3A
PP6
C
DFE1B
CLK
DSI2
DSWPNT
D
CLK
E
F2
PNT2
Q
DFE1B
G2
CLK
CPCYC
A
ADW0
B
DEC2
Y0
LA0
A
LR/W
DSWPNT
Y1
E
ADW2
Y2
LA1
Y
NAND2
DECE2X4D
B
ADW3
Y3
2
2
L1
R/W
D
LR/W
Q
DL1B
DG3
G
G11
CPCYC1
A
PP4
B
ADW2
C
AND3
Y
DSIW
Y
DSWST
G12
3
CPCYC1
A
PP4
B
ADW3
C
ADW0
A
LR/W
B
CPCYC1
C
PP6
D
VCC
Y
AND3
3
Y
AND4B
DSWDREG
F4
D
Q3
Q
E
Q2
DFE3A
CLK
CLR
A
INV
Y
Q2
BUF2
A
F5
A
INV
Y
GND
CPS
4
G6
CPIS
A
CPSTRB
B
CPSEL
C
AND3B
Y
CPS
D0
D1
D2
D3
Q
BUF
Y
CPCYC
Y
CPCYC1
Q3
BUF3
A
BUF
DFM6A
S0
S1
CLK
DSPWA
VCC
4
CLR
Y
Q3
CLK
24 OCT 2002
A
B
C
DBS
DRAWN BY:
D
A
1
B
ST0
A
BUF
Y
CH0
ST15
A
BUF
Y
CH15
C
D
1
MUX2X16
CH15,GND,GND,GND[12:1],CH0
DO[15:0]
DATA0_[15:0]
RESULT[15:0]
IQ[15:0]
BUF
Y
GND[12:1]
SEL0
A
2
DATA1_[15:0]
2
$ARRAY=12
Y
GND
LA0
A
LA1
B
OR2
Y
IQSEL
3
3
DSPRA
4
24 OCT 2002
A
B
C
4
DBS
DRAWN BY:
D
A
B
C
D
A[7:0]
B[7:0]
1
1
B0
A0
B1
A1
B2
A2
B3
A3
B4
A4
B5
A5
B6
A6
B7
A7
S
EN1
CK
F0
F1
A
B
DFME1A
DFME1A
S
E
CLK
A
B
DFME1A
Q5
2
Q
Q
Q
Q
Q4
F7
S
E
CLK
A
B
DFME1A
Q
Q3
F6
S
E
CLK
A
B
DFME1A
Q
Q2
F5
S
E
CLK
A
B
DFME1A
Q
Q1
F4
S
E
CLK
A
B
DFME1A
Q
Q0
F3
S
E
CLK
A
B
DFME1A
S
E
CLK
A
B
S
E
CLK
2
F2
Q6
Q7
Q[7:0]
3
3
DFME8
4
19 NOV. 2002
A
B
C
4
DBS
DRAWN BY:
D
A
B
C
D
R1
R5
EN1R1
MUX1
MUX4X8
EN1
EN1R3
EN1
CIQ[7:0]
S
DSPSEL
DFME8
S
DSPSEL2
DFME8
R1[7:0]
CK
DATA0_[7:0]
CK
HI[7:0]
1
A[7:0]
Q[7:0]
DATA2_[7:0]
Q[7:0]
DSI[7:0]
DATA3_[7:0]
R3[7:0]
DSI[7:0]
1
RESULT[7:0]
R2[7:0]
R3[7:0]
A[7:0]
B[7:0]
IQ[7:0]
DATA1_[7:0]
HI[7:0]
R1[7:0]
B[7:0]
R2
R6
EN2R1
EN1
EN2R3
DFME8
CK
S
CLK
HIH[15:8]
SEL0
CLK
EN1
SEL1
S
DFME8
CK
R1[15:8]
A[7:0]
Q[7:0]
HIH[15:8]
MDS1
MDS0
R3[15:8]
A[7:0]
DSI[15:8]
Q[7:0]
B[7:0]
DSI[15:8]
B[7:0]
MUX2
R3
2
EN1R2
LA0
A
LA1
B
EN1
S
DSPSEL1
PP4
C
DOE1
D
DFME8
MUX4X8
2
AND4A
Y
CIQ[15:8]
DSIR
R1[15:8]
DATA0_[7:0]
CK
HI[7:0]
RA0
A
S
RA1
R2[7:0]
A[7:0]
Q[7:0]
MX2
DSI[7:0]
GND
Y
A
MDS0
S
MX2
B
GND
IQ[15:8]
DATA1_[7:0]
Y
RESULT[7:0]
R2[15:8]
DATA2_[7:0]
MDS1
B
DATA3_[7:0]
R3[15:8]
B[7:0]
R4
Y
EN2R2
DEC1
EN1
CLK
DFME8
EQ0
DATA1
EQ1
CK
EQ2
HIH[15:8]
A[7:0]
3
EQ3
R2[15:8]
SEL1
S
DECE2X4
DATA0
SEL0
GND
EN1R1
EN1R2
EN1R3
MDS1
MDS0
3
Q[7:0]
DSI[15:8]
B[7:0]
LA[1:0]
B1
PP6
A
BUF
Y
DSPSEL
BUF
Y
DSPSEL1
BUF
Y
DSPSEL2
END1
ENABLE
RA[1:0]
B2
A
B3
A
DEC2
DECE2X4
RA0
RA1
DATA0
EQ0
DATA1
EQ1
EQ2
EQ3
EN2R1
EN2R2
EN2R3
DATREG
4
END2
ENABLE
24 OCT 2002
A
B
4
C
DBS
DRAWN BY:
D
6.3
8-bit Host Interface (IOPIL8)
This design implements a parallel interface with a host processor utilizing an 8-bit data bus. An
understanding of the underlying operation of the design is only necessary if the designer intends to
make modifications. In most cases this design can be implemented without changes. The following
notes should be read while referencing the schematics. IOPIL16 1 is the top level schematic. The
timing for the host to I/O chip communication can be found in section 4.4 and the timing for the
CP to I/O chip communication can be found in section 4.7.
The description below identifies the key elements of each schematic starting with the host side
signals. The paragraph title identifies the key schematic(s) being described in the text.
IOPIL8 3
The host interface for IOPIL8 is shown in sheet IOPIL8 3. The incoming data HD[7:0] is latched in
the transparent latches when ~HG1 goes high. This would be a write from the host to the CP. The
latched data HI[7:0] goes to IOPIL8 1 and IOPIL8 5. Data from the interface to the host, HO[7:0]
is enabled onto the host bus, HD[7:0], by HOES1. The output latches, which present the data
during a host read, are always transparent because GOUT is connected to VDD. The latched I/O is
an I/O option on the Actel part used and could be omitted in the host interface if a different CPLD
or FPGA does not have this feature. HD[15:8] are tri-stated outputs because Actel grounds unused
I/O pins and this would interfere with using existing PMD test equipment. These reserved I/O's can
be ommitted in a different implementation with an 8 bit bus.
IOPIL8 1
The control for the host interface starts on IOPIL8 1. HOES1 is the AND of ~HSEL and ~HRD,
and enable read data onto the host bus, as previously described. HRDY is a handshaking signal to
the host to allow asynchronous communication between the host and the CP. The host must wait
until HRDY is true before attempting to communicate with the CP. This signal is copied as a bit in
the host status register. The host status register may be read at any time to determine the state of
HRDY, or the HRDY output may be used as an interrupt to the host. ~HSEL, ~HRD, ~HWR, and
HA0 are the buffered inputs of the host control signals.
HOST INTERFACE/IOPIL8 5
Data from the host HI[7:0] is written into REG1 and REG2 on the schematic HOST INTERFACE
by ~EN1 and ~EN2. All transfers are 16 bits and take two writes or reads on the 8-bit bus. These
registers have a 2 to 1 multiplexed input with both the host data and the CP data being written to this
register.
This is convenient for diagnostic purposes and is very efficient in the Actel A42MX FPGA's, which
are multiplexer based but if the configuration of the logic device used demands it, separate registers
could be used for the host and CP data. The schematic for this register is shown as DFME8. Only
commands and checksums are written to registers REG1 and REG2 while data is written and read
from the set of data registers, DATREG shown on IOPIL8 5. These 3 data registers buffer data sent
to and from the CP, reducing the number of interrupts the CP must handle. The output from REG1
and REG2, CIQ[15:8] and CIQ[7:0] go to IOPIL8 5, where they are multiplexed with the other data
registers. The multiplexed result, IQ[15:8] and IQ[7:0], is multiplexed with HST[15:8] and HST[7:0] the output of the host status registers REG3 and REG4. This four input mux, MUX4X8, also
muxes the 16 bit data onto the 8-bit bus. As previously mentioned HRDY becomes HST15 so it can
be read by the host. The rest of the status register is written by the CP to provide information to the
MC3110 Technical Specifications
45
host. HA0 acts as an address bit, and usually is an address bit on the bus. When the host is writing,
HA0 low indicates data and HA0 high indicates a command. When the host is reading, HAO low
indicates data and HA0 high indicates status. Read status is the only transaction allowed while
HRDY is low. During a host write the AND gate (G1:HOST INTERFACE) and two flops latch the
incoming data in the interface latches by driving ~HG1 low from the start of the write transaction
until the first negative clock transition after the first positive transition following the start of the write
cycle. This tail-biting circuit removes the requirement for hold time on the data bus.
HICTLA
Most of the control logic for the host interface is shown on schematic HICTLA. The sequencer at
the top generates HCYC one clock interval after the interface has been accessed and the host has
finished the transaction. The nature of the transaction, rd/wr, command/data, and read status is
preserved in the three flops F13, F8, and F9. Since 16 bit transfers must take place over an 8 bit bus
two transfers are required. The toggle flop is used to determine whether a cycle is the first or second
of the 2 required. The toggle flop may be initialized to the 0 state, which indicates that this is the
first transfer (high byte), by the CP writing a one to host status bit 15. This status bit is read by the
host as the HRDY bit and is not writable by the CP. In addition flop F12 and the associated gating
determine if the present command transaction is the first or second byte of a command. If the
toggle flop gets into the wrong state due to a missed or aborted transfer the next command will set it
back to the correct state. A host write or a CP write, DSIW, enable REG1 and REG2 on the HOST
INTERFACE schematic discussed previously. A host data write generates ~ENHD1 and
~ENHD2 for the data registers on the DATAREG schematic. For host writes ~EN2, ~EN1,
~ENHD2, and ~ENHD1 are also determined by the state of the toggle flop using HIEN and
LOEN. 1CMD is used in this logic to ensure correct behavior when the command is correcting the
state of the toggle. The logic at the bottom of the page generates the CP interrupt, the HRDY and
the HCMDFL. The HCMDFL is used in the CP status to indicate a command. DSIW, the CP
writing to REG1 and REG2 on the HOST INTERFACE schematic clears the interrupt and reasserts
HRDY. HRDY is de-asserted during all host transactions except read status, and stays de-asserted
until the CP has completed the DSIW cycle that clears the interrupt and reasserts HRDY. As
mentioned previously data transfers to and from the host use the data registers and do not interrupt
the CP. The CP knows the number of data transfers that must take place after decoding the
command. It places this number, 0-3, in the 2 least significant bits of the host status register,
HST[1:0]. These become DPNT[1:0] on this page of the schematic and enable an interrupt at 0 for a
read and 1 or 0 for a write. The CP always leaves these bits at 0 unless setting up a multiple word
data transfer. If INTEN is true and LRDST, latched read status, is false, HCYC will generate an
interrupt to the CP. This will also hold HRDY false until after the CP writes to the interface register,
DSIW, thereby generating ~CLRFLGS.
IOPIL8 4
The CP interface is shown in sheet IOPIL8 4. The incoming data DSD[15:0] is latched in the
transparent latches when ~DG1 and ~DG2 go high. This occurs at the completion of a write from
the CP to the I/O chip. The latched data DSI[15:8] and DSI[7:0] go to schematic IOPIL8 1 and
IOPIL16 5. DSI[7:0] also goes to IOPIL16 2. Data from the interface to the CP, DO[15:8] and
DO[7:0] is enabled onto the CP bus, DSD[15:0], by DOE2 and DOE1 respectively. The output
latches, which present the data during a CP read, are always transparent because GOUT is connected
to VDD. The latched I/O in the Actel part contains both input and output latches. The output
latches could be omitted in the CP interface if a different CPLD or FPGA does not have this feature.
The two incoming CP address bits CPA0 and CPA1 are also latched using ~DG3. The 20CK signal
is the clock for the CP. This is a 20 MHz clock derived from a 40 MHz clock input.
MC3110 Technical Specifications
46
IOPIL8 2
The CP control starts on IOPIL8 2. The I/O control is generated from ~CPSTRB, ~CPIS, CPSEL
and R/W. ~DG1, ~DG2, and ~DG3 latch the incoming data and DOE1 and DOE2 out-enable
the data from this chip to the CP. F2 and F4 tail-bite the write to avoid having to specify hold times
on the data. Flop F1 divides the 40MHz clock down to 20 MHz. A 20 MHz clock could be used for
this interface and the CP.
DSPWA
The CP write control is contained on schematic DSPWA. The CP interface uses page addressing to
save I/O pins. F0, F1 and F2 make up the page register. In addition there are the 2 address bits,
LA0 and LA1. A write to address 0 selects the page register with DSI[2:0] going to the page register
and selecting the page for the successive transfers. A read from address 0 reads the status register on
all pages. Pages 4 and 6 are the only ones implemented in this device. L1 latches the r/w level. The
write decoding generates DSIW which enables writes to the DFME8 registers reg1 and reg2 shown
on the HOST INTERFACE schematic. DSIW also clears the CP interrupt and restores HRDY.
DSWST writes to the host status register also shown on the HOST INTERFACE schematic.
DSWDREG implements writing to the data registers shown on IOPIL8 5 and DATREG. Finally
the logic at the bottom of the page generates CPCYC, a 1-clock interval after the CP cycle is over
that implements the actual writes to the registers. The use of the data bus latches and the post bus
cycle transfers keeps as much of the logic synchronous as possible given two asynchronous devices,
without requiring clocking at several times the bus speed.
DSPRA
The CP read control is contained on schematic DSPRA. The 2 by 16 bit mux selects CP status if the
CP latched address is 0 and IQ[15:0] if the address is not 0. The only significant status bits are bits 15
(indicating the CP is interrupting the host), bit 14 (1 indicating an 8-bit host interface) and bit 0 (set
to 1 during a host command transfer and 0 during data transfer).
HOST INTERFACE
Both the CP and the host use a special mode to transfer data to avoid unnecessary CP interrupts.
This special mode is under the control of the CP and is transparent to the host. When the CP
receives a command from the host it initializes the transfer by setting the number of transfers
expected (0,1,2 or 3) in the 2 LSB's of the host status register, REG3 and REG4 on HOST
INTERFACE. This write (DSWST) also loads these bits into the 2 bit down counter DCNT2 on
IOPIL8 5. Note that a Q8 low, which indicates a host command, asynchronously clears this register
enabling interrupts on schematic HICTLA. If DPNT[1:0] is not 0 and Q8 is high, indicating a host
data transfer, and SINT goes high indicating the end of a host cycle the counter is decremented.
MXAD2 selects address RA from the CP latched address bits if the page register contains 6, or the
counter contents DPNT[1:0] if not. This allows the CP to have direct access to registers 1, 2, and 3,
using address 1,2,and 3 on page 6. The host on the other hand can only read or write to the data
register, HA0 low and the counter will auto decrement from 3 down to 0 allowing the host to access
the registers on DATAREG where REG1=R1 and R2, REG2=R3 and R4, and REG3=R5 and R6.
The writes are enabled by the two decoders DECE2X4 while the reads are selected by the two 4x8
muxes, MUX1 and MUX2 controlled by the two 2x1 muxes MDS1 and MDS0. The output data
IQ[15:0] goes to HOST INTERFACE schematic below IOPIL8 1 and to DSPRA below IOPIL8 2.
The write data is HI[7:0] from the host and DSI[15:8] and DSI[7:0] from the CP. Note that END1
MC3110 Technical Specifications
47
and END2, the write enables, are both high for DSWDREG, while they are high one at a time for
host writes controlled by the toggle flop. SINT enables DPINC only when the toggle is high after
the second transfer.
MC3110 Technical Specifications
48
A
B
C
D
HINTF
IN17
INBUF
PAD
HSTSEL
Y
HSEL
HSEL
HOST INTERFACE
HRD
INBUF
PAD
HSTRD
IN18
Y
(HINTRFA)
HO[7:0]
HWR
HO[7:0]
HRD
HA0
1
HSTWR
PAD
HADR0
PAD
INBUF
INBUF
HI[7:0]
IN19
Y
1
HI[7:0]
HWR
IN20
Y
HA0
CIQ[7:0]
DSI[15:8]
DSI[15:8]
CIQ[7:0]
CIQ[15:8]
DSI[7:0]
DSI[7:0]
CIQ[15:8]
DPNT[1:0]
HST[1:0]
Q8
Q8
DSWST
DSWST
DSIW
DSIW
SINT
SINT
2
HG1
2
HG1
IQ[7:0]
IQ[7:0]
HST14
ST15
IQ[15:8]
IQ[15:8]
HCMDFL
ST0
DSPINTR
CLK
HRD
A
HSEL
B
AND2B
Y
DSPINTR
CLK
OUTBUF
D
HST15
RDY
ENHD1
ENHD1
ENHD2
ENHD2
PAD
HRDY
HOES1
3
3
OUTBUF
DSPINTR
D
PAD
DSPINT
OUT5
4
4
IOPIL8 1
22 OCT 2002
A
B
C
DBS
DRAWN BY:
D
A
B
C
PNT0
CSEL0
PNT1
CSEL1
DSWDREG
D
DSPRA
ST0
ST0
ST15
ST15
DSWDREG
1
1
DSIW
DSI[7:0]
DSIW
IQ[15:0]
IQ[15:0]
DSI[7:0]
DSWST
DSWST
PP4
PP4
PP6
PP6
IN27
CS
PAD
CPR-W
PAD
INBUF
Y
DG3
DG3
LA0
LA0
LA1
LA1
IN28
INBUF
Y
DO[15:0]
DO[15:0]
IN26
STRB
2
PAD
INBUF
Y
2
IN30
IS
PAD
INBUF
Y
CKBUF
A
20CK
CPSEL
CPSEL
R/W
R/W
CPSTRB
CPSTRB
CPIS
CPIS
LA0
LA0
LA1
LA1
CPCYC
CPCYC
DSPRA
Y
CLK
CLK
DSPWA
CLKINT
CPSTRB
A
CPIS
B
CPSEL
C
G1
NAND3B
Y
CSACC
Y
DOE1
A
B
C
R/W
G2
AND4B
F1
D
IB1
D
3
CLKIN
PAD
INBUF
QN
20CK
DF1A
Y
40CK
3
CLK
A
B
C
G3
AND4B
Y
DOE2
Y
DG1
Y
DG2
D
A
B
G4
NAND3B
C
A
B
G5
CSACC
D
Q
DF1
C
4
F4
F2
NAND3B
CQ1
D
Q
CQ3
DF1
CLK
CSACC
CQ3
B
C
G6
NAND4B
Y
CLK
DG3
D
A
4
IOPIL8 2
CLK
A
30 OCT 2002
B
C
DBS
DRAWN BY:
D
A
B
C
D
HIGH SLEW
D
HO0
E
D
PAD
Q
HIGH SLEW
HD0
D
HO4
E
D
PAD
Q
HD4
D
GOUT
G
1
D
VDD
GOUT
VDD
Q
Q
G
HI0
D
BBDLHS
GIN
Q
Q
HI4
D
BBDLHS
G
GIN
D
GOUT
E
D
PAD
Q
G
D
D
HO5
GOUT
Q
Q
E
D
D
PAD
Q
HD5
D
D
Q
D
Q
BBDLHS
GIN
E
D
D
G
HD2
D
HO6
G
D
GOUT
Q
Q
E
D
D
HI2
D
GIN
GOUT
E
Q
Q
Q
D
HD3
D
HO7
GOUT
Q
Q
HI3
PAD
HD11
E
PAD
HD12
2
E
PAD
HD13
D
E
PAD
HD14
PAD
HD15
TRIBUFF
E
D
Q
D
PAD
E
HD7
TRIBUFF
Y
G
Q
Q
BBDLHS
GIN
G
HG1
E
G
D
BBDLHS
GIN
HI6
HIGH SLEW
PAD
G
3
HD10
HD6
BBDLHS
G
D
PAD
TRIBUFF
HIGH SLEW
HO3
PAD
Q
G
BBDLHS
GIN
E
HIGH SLEW
D
GOUT
HD9
TRIBUFF
PAD
Q
PAD
HI5
HIGH SLEW
HO2
E
TRIBUFF
G
2
1
TRIBUFF
G
HI1
BBDLHS
GIN
HD8
G
HIGH SLEW
HD1
PAD
TRIBUFF
HIGH SLEW
HO1
E
TRIBUFF
3
GND
HI7
HI BYTE TRISTATE TO
G
HI[7:0]
AVOID LOADING 16 BIT BUSSES
HG1
HO[7:0]
VCC
HOES1
Y
VDD
4
4
IOPIL8 3
24 OCT 2002
A
B
C
DRAWN BY:
DBS
D
A
B
C
D
DOE1
DOE1
HIGH SLEW
D
DO0
GOUT
VDD
E
D
PAD
Q
G
D
Q
D
GOUT
VDD
Q
E
D
DO4
1
HIGH SLEW
PAD
Q
D
DO8
DSD4
GOUT
VDD
G
E
D
HIGH SLEW
PAD
Q
GOUT
VDD
G
D
DO12
DSD8
E
D
PAD
Q
DSD12
G
1
DSI0
D
BBDLHS
GIN
DOE2
DOE2
HIGH SLEW
DSD0
Q
Q
DSI4
D
BBDLHS
G
GIN
Q
Q
DSI8
D
BBDLHS
GIN
G
Q
Q
DSI12
BBDLHS
GIN
G
G
DOE1
DOE1
HIGH SLEW
D
DO1
GOUT
E
D
PAD
Q
G
D
E
D
DO5
D
GOUT
Q
Q
D
GOUT
GIN
E
PAD
Q
DSD2
GIN
D
Q
Q
D
GOUT
Q
DSI6
GIN
E
D
GIN
HIGH SLEW
D
PAD
Q
E
D
DO7
D
DSD3
GOUT
GOUT
DSD10
D
Q
Q
GIN
Q
PAD
GOUT
Q
Q
E
D
2
PAD
Q
DSD14
G
DSI10
D
Q
Q
DSI14
BBDLHS
GIN
G
G
HIGH SLEW
HIGH SLEW
DSD7
D
DO11
GOUT
D
DSI3
Q
Q
GIN
G
E
D
Q
PAD
D
DO15
DSD11
GOUT
G
DSI7
D
BBDLHS
BBDLHS
D
DO14
DOE2
G
G
3
G
DOE2
HIGH SLEW
E
DSI13
HIGH SLEW
PAD
Q
BBDLHS
DOE1
D
Q
Q
BBDLHS
DOE1
DO3
D
G
D
G
DSD13
G
DSI9
G
BBDLHS
GIN
PAD
Q
DOE2
DO10
DSD6
G
Q
E
D
HIGH SLEW
PAD
Q
D
D
DO13
GOUT
D
G
DSI2
G
HIGH SLEW
DSD9
BBDLHS
E
D
GOUT
Q
Q
HIGH SLEW
DO6
Q
D
PAD
DOE2
BBDLHS
GIN
DSI5
DOE1
G
D
Q
Q
E
G
BBDLHS
G
D
D
DO9
DSD5
GOUT
D
HIGH SLEW
DO2
Q
DSI1
DOE1
2
HIGH SLEW
PAD
G
BBDLHS
GIN
DOE2
DOE2
HIGH SLEW
DSD1
Q
Q
GIN
DSI[7:0]
Q
PAD
DSD15
G
D
DSI11
Q
Q
DSI15
3
BBDLHS
BBDLHS
G
E
D
GIN
G
G
DSI[15:8]
DG1
DO[15:8]
DG2
DO[7:0]
DOE2
DOE2
DG2
VCC
DOE1
Y
GND
GND
HIGH SLEW
HIGH SLEW
D
GOUT
4
E
D
Q
D
PAD
CPA0
GOUT
G
E
D
PAD
Q
CPA1
VDD
G
D
Q
BBDLHS
DG3
GIN
G
Q
D
LA0
Q
LA1
20CK
D
PAD
CLKOUT
BBDLHS
DG3
GIN
G
22 OCT 2002
A
4
IOPIL8 4
OUTBUF
Q
B
C
DBS
DRAWN BY:
D
A
B
C
A
ENHD1
B
DSWDREG
Y
OR2A
D
END1
1
1
DREG
A
ENHD2
DOE1
DOE1
PP4
PP4
B
Y
OR2A
END2
CIQ[7:0]
CIQ[7:0]
CIQ[15:8]
CIQ[15:8]
HI[7:0]
Q8
HI[7:0]
A
SINT
IQ[7:0]
IQ[7:0]
DSI[7:0]
DSI[7:0]
DPNT0
A
DPNT1
B
IQ[15:8]
IQ[15:8]
B
NAND2B
Y
AND3
Y
DPINC
C
DSI[15:8]
DSI[15:8]
RA[1:0]
RA[1:0]
2
2
LA[1:0]
LA[1:0]
PP6
PP6
END1
END1
END2
END2
CLK
CLK
DATREG
DCNT2
DSWST
SLOAD
DPINC
3
ENABLE
Q8
3
ACLR
CLK
CLOCK
DPNT[1:0]
MXAD2
Q[1:0]
DSI[1:0]
DATA[1:0]
RA[1:0]
DATA0_[1:0]
RESULT[1:0]
DATA1_[1:0]
LA[1:0]
LA0
LA1
SEL0
4
4
IOPIL8 5
PP6
22 OCT 2002
A
B
C
DBS
DRAWN BY:
D
A
B
C
D
REG1
HST[1:0]
EN1
EN1
MUX4X8
REG3
S
DFME8
REG6
IQ[7:0]
CK
1
1
HI[7:0]
CIQ[7:0]
A[7:0]
DSWST
Q[7:0]
DATA0_[7:0]
HST[7:0]
ENABLE
HO[7:0]
DATA1_[7:0]
RESULT[7:0]
DSI[7:0]
CLK
B[7:0]
DATA2_[7:0]
IQ[15:8]
CLOCK
HST[7:2]
DATA3_[7:0]
Q[5:0]
DSI[7:2]
HST[15:8]
DATA[5:0]
BUF1
A
DSIW
Y
BUF
DSL
REG2
REG4
A
BUF2
BUF
EN1
DSLA
S
DSWST
Y
ENABLE
DFME8
VDD
CLK
CLK
CLOCK
HI[7:0]
A[7:0]
TOGGLE A
ACLR
CK
CIQ[15:8]
INV
Y
HST[14:8]
HA0
Q[6:0]
DSI[14:8]
Q[7:0]
2
SEL0
SEL1
REG7
EN2
2
TOGGLE LO
DSI[15:8]
DATA[6:0]
B[7:0]
SELECTS [15:8], HI BYTE FIRST
HST14
DSWST
A
DSI15
B
NAND2
Y
RSTOG
HICTLA
ENHD1
ENHD1
ENHD2
ENHD2
HST[15:8]
HST[1:0]
3
SINT
DPNT[1:0]
SINT
RSTOG
RSTOG
Q8
HSEL
HSEL
TOGGLE
HWR
HWR
EN1
EN1
HRD
HRD
EN2
EN2
HA0
HA0
HRDY
Q8
3
TOGGLE
HST15
DSPINTR
DSPINTR
HCMDFL
HCMDFL
DSIW
DSIW
CK
CLK
HICTLA
G2
A
B
G1
4
HWR
A
HSEL
B
AND2B
Y
D
Q
DF1
CLK
D
NAND2
Y
HG1
HOST INTERFACE
(HINTRFA)
QN
DF1C
CLK
4
CLK
24 AUG 2001
A
B
C
DBS
DRAWN BY:
D
A
B
INV1
A
HRD
F1
Q1
Q
D
DF1
Y
OA1C
C
HSEL
HCYC
F2
D
G1
B
HRD
D0
D1
D2
D3
GND
DF1
CLK
A
B
HSEL
Y
AND2B
J
F3
Q2
Q
CLK
HCYC
Q
JKF2C
CK
LWR
Q
CS
CLK
K
CLR
VDD
DFM6A
S0
S1
CLK
G2
HWR
1
D
HRD
A
HWR
C
F13
Y
INV
Q1
HWR
VCC
CLR
HSEL
A
HWR
B
Y
AND2B
1
SHWR
Y
F8
HCYC
CK
HCYC
J
JKF2C
CK
D
HCYC
A
TOGGLE
B
B
LCMD
CLK
CLR
HSEL
A
HWR
B
HA0
C
Y
AND3B
Y
AND2A
1CMD
HCYC
J
HCYC
Q
E
CK
JKF2C
Q
INV
Y
LRDST
CS
CLK
K
CLR
VDD
D
TOGGLE LO (1ST BYTE) LD HI, RD HI
INV4
Q9 A
SHCMD
F12
2
HCMD
CLK
K
CLR
CK
Q8
Y
F9
A
DFE3A
RSTOG
INV
G7
Y
NAND2A
Q
E
CK
1CMD
INV3
Q8 A
CS
VDD
F4
Q
G10
DFE
CLK
HSEL
A
HRD
B
HA0
C
2
Y
AND3B
SLRDST
INV2
G12
A
TOGGLE
OR2A
B
1CMD
Y
HWR
A
HIEN
B
Y EN2
AOI1
C
DSIW
HIEN
A
HWR
B
Q8
C
TOGGLE
B
AND2A
Y
C
F5
Y
NAND3
F10
D
ENHD1
Q
D
DF1
DPNT[1:0]
DPNT0
A
DPNT1
B
LWR
C
Q1
NAND3B
1CMD
A
TOGGLE
B
AND2A
RDEN
A
WREN
B
NAND2B
Y
OR3C
Y
A
Y
LRDST
A
HCYC
B
ENINTR
C
SINT
B
CLRFLGS
C
AND3
Y SINTR
NOR4
Y
HRDY
CC
D
Q
3
A
Q2
B
HCYC
C
Q9
D
INTEN
C
Q8
A
B
Y
2
CLK
CK
3
2
DF1
CLK
Y EN1
AOI1
C
DSIW
G21
C
B
LOEN
DSPINTR
A
B
A
HWR
Y
INV
ENHD2
A
G14
A
Y
NAND3
B
LOEN
1CMD
A
OA4
Y
EBSY
F6
J
JKF
Q
DSPINTR
CLK
K
Y
AND3A
G19
HCYC
A
HCMD
B
AND2
F7
Y
HCCYC
J
JKF
Q
HCMDFL
CLK
4
HICTLA
K
CK
DSIW
A
INV
Y
CLRFLGS
22 OCT 2002
A
4
B
C
DRAWN BY:
DBS
D
A
B
C
D
DSI[7:0]
DSI0
D
E
F0
Q
A
PNT0
B
DFE1B
DSI1
D
E
D
DSWPNT
E
CLK
PP4
1
F1
Q
A
PNT1
B
DFE1B
Y
AND3A
PP6
C
CLK
DSI2
Y
AND3B
C
CLK
1
F2
Q
PNT2
G2
DFE1B
CPCYC
DEC2
CLK
ADW0
Y0
LA0
A
LR/W
B
Y
NAND2
DSWPNT
Y1
E
ADW2
Y2
LA1
A
DECE2X4D
B
ADW3
Y3
L1
R/W
2
D
LR/W
Q
2
DL1B
DG3
G11
G
CPCYC1
A
PP4
B
ADW2
C
AND3
Y
DSIW
Y
DSWST
Y
DSWDREG
G12
3
CPCYC1
A
PP4
B
ADW3
C
ADW0
A
LR/W
B
CPCYC1
C
PP6
D
AND3
AND4B
3
VCC
Y
F4
D
Q3
Q
E
Q2
DFE3A
CLK
CLR
A
INV
Y
Q2
BUF2
A
F5
A
INV
Y
GND
CPS
4
G6
CPIS
A
CPSTRB
B
CPSEL
C
AND3B
Y
D0
D1
D2
D3
Q
BUF
Y
CPCYC
Y
CPCYC1
Q3
BUF3
A
BUF
DFM6A
S0
S1
CLK
DSPWA
VCC
4
CLR
CPS
Y
Q3
CLK
24 OCT 2002
A
B
C
DBS
DRAWN BY:
D
A
B
C
D
VCC
A
ST0
BUF
Y
BUF
Y
Y
CH0
VDD
1
1
A
ST15
CH15
MUX2X16
CH15,VDD,GND,GND[12:1],CH0
A
GND[12:1]
Y
BUF
DO[15:0]
DATA0_[15:0]
$ARRAY=12
RESULT[15:0]
GND
DATA1_[15:0]
IQ[15:0]
SEL0
2
2
Y
GND
LA0
A
LA1
B
OR2
Y
IQSEL
3
3
DSPRA
4
30 OCT 2002
A
B
C
4
DBS
DRAWN BY:
D
A
B
C
D
A[7:0]
B[7:0]
1
1
B0
A0
B1
A1
B2
A2
B3
A3
B4
A4
B5
A5
B6
A6
B7
A7
S
EN1
CK
F0
F1
A
B
DFME1A
DFME1A
S
E
CLK
A
B
DFME1A
Q5
2
Q
Q
Q
Q
Q4
F7
S
E
CLK
A
B
DFME1A
Q
Q3
F6
S
E
CLK
A
B
DFME1A
Q
Q2
F5
S
E
CLK
A
B
DFME1A
Q
Q1
F4
S
E
CLK
A
B
DFME1A
Q
Q0
F3
S
E
CLK
A
B
DFME1A
S
E
CLK
A
B
S
E
CLK
2
F2
Q6
Q7
Q[7:0]
3
3
DFME8
4
19 NOV. 2002
A
B
C
4
DBS
DRAWN BY:
D
A
B
C
D
R1
R5
EN1R1
MUX1
MUX4X8
EN1
EN1R3
EN1
CIQ[7:0]
S
DSPSEL
DFME8
S
DSPSEL2
DFME8
CK
R1[7:0]
DATA0_[7:0]
CK
HI[7:0]
1
A[7:0]
R1[7:0]
Q[7:0]
R3[7:0]
A[7:0]
DATA2_[7:0]
Q[7:0]
DSI[7:0]
1
RESULT[7:0]
R2[7:0]
DSI[7:0]
B[7:0]
IQ[7:0]
DATA1_[7:0]
HI[7:0]
DATA3_[7:0]
R3[7:0]
B[7:0]
R2
R6
EN2R1
EN1
EN2R3
DFME8
CK
S
HI[7:0]
SEL0
CLK
EN1
SEL1
S
DFME8
CK
CLK
R1[15:8]
A[7:0]
Q[7:0]
MDS1
HI[7:0]
MDS0
R3[15:8]
A[7:0]
DSI[15:8]
Q[7:0]
B[7:0]
DSI[15:8]
B[7:0]
R3
MUX2
MUX4X8
2
EN1R2
EN1
S
DSPSEL1
DFME8
CK
LA0
A
LA1
B
PP4
C
DOE1
D
2
Y
AND4A
CIQ[15:8]
DSIR
R1[15:8]
DATA0_[7:0]
IQ[15:8]
DATA1_[7:0]
HI[7:0]
R2[7:0]
A[7:0]
RA0
A
S
Q[7:0]
MX2
DSI[7:0]
GND
B[7:0]
RESULT[7:0]
R2[15:8]
Y
DATA2_[7:0]
MDS0
DATA3_[7:0]
R3[15:8]
B
R4
EN2R2
EN1
DFME8
RA1
A
S
CK
MX2
HI[7:0]
R2[15:8]
A[7:0]
3
GND
SEL0
S
CLK
SEL1
DSIR
Y
MDS1
MDS1
B
MDS0
3
Q[7:0]
DSI[15:8]
B[7:0]
Y
GND
B1
PP6
A
BUF
Y
DSPSEL
BUF
Y
DSPSEL1
DECE2X4
B2
A
LA[1:0]
DATA0
END1
B3
A
BUF
Y
DSPSEL2
ENABLE
DATA1
RA[1:0]
EQ0
EQ1
EN1R1
EQ2
EN1R2
EQ3
EN1R3
DECE2X4
RA0
4
DATA0
END2
RA1
ENABLE
DATA1
DATREG
EQ0
EQ1
EN2R1
EQ2
EN2R2
EQ3
EN2R3
30 OCT 2002
A
B
C
4
DBS
DRAWN BY:
D
7 Application Notes
7.1
Design Tips
The following are recommendations for the design of circuits that utilize a PMD Motion Processor.
Serial Interface
If the serial configuration decode logic is not implemented (see section 7.2) the CP data bus should
be tied high. This places the serial interface in a default configuration of 9600,n,8,1 after power on
or reset.
Controlling PWM output during reset
When the motion processor is in a reset state (when the reset line is held low) or immediately after a
power on, the PWM outputs can be in an unknown state, causing undesirable motor movement. It is
recommended that the enable line of any motor amplifier be held in a disabled state by the host
processor or some logic circuitry until communication to the motion processor is established. This
can be in the form of a delay circuit on the amplifier enable line after power up, or the enable line can
be ANDed with the CP reset line.
Parallel word encoder input
When using parallel word input for motor position, it is useful to also decode this information into
the User I/O space. This allows the current input value to be read using the chip instruction ReadIO
for diagnostic purposes.
Using a non standard system clock frequency
It is often desirable to share a common clock among several components in a design. In the case of
the PMD Motion Processors it is possible to use a clock below the standard value of 20MHz. In this
case all system frequencies will be reduced as a fraction of the input clock verses the standard
20MHz clock. The list below shows the affected system parameters:•
Serial baud rate
•
PWM carrier frequency
•
Timing characteristics as shown in section 3.2
•
Cycle time
For example, if an input clock of 17MHz is used with a serial baud rate of 9600 the following timing
changes will result:•
Serial baud rate decreases to 9600 bps *17/20 = 8160 bps
•
PWM frequency decreases to 20 KHz *17/20 = 17 KHz
•
Cycle time increases to 102.4 µsec *20/17 = 120.48 µsec
MC3110 Technical Specifications
60
MC3110 Technical Specifications
61
7.2
RS-232 Serial Interface
The interface between the MC3110 chip and an RS-232 serial port is shown in the following figure.
Comments on Schematic
S1 and S2 encode the characteristics of the serial port such as baud rate, number of stop bits, parity,
etc. The CP will read these switches during initialization, but these parameters may also be set or
changed using the SetSerialPort chipset command. The DB9 connector wired as shown can be
connected directly to the serial port of a PC without requiring a null modem cable.
MC3110 Technical Specifications
62
8
7
6
5
4
R?
35
2
7
13
21
36
40
47
50
52
60
62
93
103
121
~RS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
DS[0..15]
D
DS0
DS1
DS2
DS3
DS4
DS5
DS6
DS7
DS8
DS9
DS10
DS11
DS12
DS13
DS14
DS15
9
10
11
12
15
16
17
18
19
22
23
24
25
26
27
28
63
64
C
72
94
67
68
69
70
73
90
91
2
RS1
VCC
22K
3
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
POSLIM1
NEGLIM1
AXISIN1
AXISOUT1
110
111
112
114
115
116
117
118
119
122
123
124
125
126
127
128
131
129
130
4
6
1
132
~HOSTINTRPT
98
PWMMAG1
PWMMAG2
PWMMAG3
PWMSIGN1
PWMSIGN2
96
97
SRLRCV
SRLXMT
SRLENABLE
43
44
99
I/OINTRPT
PRLENABLE
SYNCH
53
65
54
ANALOG1
ANALOG2
ANALOG3
ANALOG4
ANALOG5
ANALOG6
ANALOG7
ANALOG8
74
89
75
88
76
83
77
82
ANALOGVCC
ANALOGREFHIGH
ANALOGREFLOW
ANALOGGND
84
85
86
87
~RESET
58
CLOCKIN
3
8
14
20
29
37
46
56
59
61
71
92
104
113
120
41
CLK
RS2
1
2
3
4
5
6
7
8
9
VCC
SW1
SW2
SW3
SW4
SW5
SW6
SW7
SW8
COM
R1
R2
R3
R4
R5
R6
R7
R8
DS[0..15]
RSIP9
U2
16
15
14
13
12
11
10
9
SW1
SW2
SW3
SW4
SW5
SW6
SW7
SW8
SW DIP-8
ISR/W
STRB-
VCC
SW9
SW10
SW11
SW12
SW13
SW14
SW15
SW16
16
15
14
13
12
11
10
9
SW9
SW10
SW11
SW12
SW13
SW14
SW15
SW16
D
DS[0..15]
RSIP9
S1
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
9
2
4
6
8
11
13
15
17
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
1
19
1G
2G
S2
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
18
16
14
12
9
7
5
3
DS0
DS1
DS2
DS3
DS4
DS5
DS6
DS7
U3
1
2
3
4
5
6
7
8
2
4
6
8
11
13
15
17
SW DIP-8
1
19
74LS244
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
DS8
DS9
DS10
DS11
DS12
DS13
DS14
DS15
18
16
14
12
9
7
5
3
1G
2G
74LS244
U2
U2 AND U3 COULD BE IMPLEMENTED IN A PLD
IS-
2
1
2
3
A9
2
C
1
R/W
4
5
U2
STRB-
U2
NAND4
1
VCC
NOT
C1
.1UF
50V
C2
.1UF
50V
C3
.1UF
50V
U3
C1+
C1-
1
3
C2+
C2-
4
5
C2
C2-
SERXMIT
11
10
T1IN
T2IN
SERRCV
12
9
R1OUT
R2OUT
C1+
C1-
V+
2
V+
V-
6
V-
T1OUT
T2OUT
14
7
TXD
R1IN
R2IN
13
8
RXD
C5
.1UF
50V
C4
.1UF
50V
J1
GND
AD232
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
B
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
NOT
100
101
102
HALL1A
HALL1B
HALL1C
RS-
U1
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
N/C
~RAMSLCT
~PERIPHSLCT
R/~W
~STROBE
~WRITEENBL
W/~R
QUADA1
QUADB1
~INDEX1
~HOME1
COM
R1
R2
R3
R4
R5
R6
R7
R8
A[0..15]
1
B
5
9
4
8
3
7
2
6
1
CONNECTOR DB9
FEMALE DB9 WIRED
AS SHOWN WILL
CONNECT TO A PC
WITHOUT A DUMMY
MODEM.
CP2N11
GND
A
A
PERFORMANCE MOTION DEVICES
55 OLD BEDFORD RD
LINCOLN, MA 01773
Title
RS232 SERIAL INTERFACE
8
7
6
5
4
3
Size
B
Document Number
Date:
Monday, July 07, 2003
2
Rev
B
Sheet
1
of
1
0
7.3
RS 422/485 Serial Interface
The interface between the MC3110 chip and an RS-422/485 serial port is shown in the following
figure.
Comments on Schematic
Use the included table to determine the jumper setup that matches the chosen configuration. If
using RS485, the last CP must have its jumpers set to RS485 LAST. The DB9 connector wiring is
for example only. The DB9 should be wired according to the specification that accompanies the
connector to which it is attached.
For correct operation, logic should be provided that contains the start up serial configuration for the
motion processor. Refer to the RS232 Serial Interface schematic for an example of the required
logic.
Note that the RS485 interface cannot be used in point to point mode. It can only be used in a multidrop configuration where the chip SrlEnable line is used to control transmit/receive operation of the
serial transceiver.
Chips in a multi-drop environment should not be operated at different baud rates. This will result in
communication problems.
MC3110 Technical Specifications
64
8
7
6
5
4
3
JP3
1
1
TERMINATE
TRANSMIT
TX-RX +
D
2
TXT
3
2
D
JP1
1
JMP3
3
2
JMP3
VCC
R3
4.7K
R1
120
C1
DE
3
RE
2
+
RO
9
TX+
Z
10
TX-
A
12
RX+
B
11
RX-
P1
5
9
4
8
3
7
2
6
1
MAX491
6
4.7UF
10V
TANT
C2
4
Y
TO HOST
C
CONNECTOR DB9
RT ANGLE MALE
7
VCC
C
DI
GND
GND
5
GND
SRLXMT
SRLRCV
SRLENABLE
VCC
14
U1
GND
.1UF
50V
CER
R2
120
JP4
1
RXT
3
2
JMP3
TERMINATE
RECEIVE
B
JP1
JP2
JP3
JP4
RS422
1-2
1-2
2-3
2-3
RS485
2-3
2-3
1-2
1-2
RS485 LAST
1-2
2-3
1-2
1-2
3
2
JMP3
TX-RX -
COM TYPE
JP2
1
B
NOTE:RS422 IS CAPABLE OF FULL DUPLEX AND USES 2 PAIRS.
RS485 IS HALF-DUPLEX ON 1 PAIR AND MAY BE DAISY CHAINED
A
A
THE CP USES RS485. A SINGLE CP MAY COMMUNICATE WITH AN
PERFORMANCE MOTION DEVICES
55 OLD BEDFORD RD
LINCOLN, MA 01773
RS422 HOST AS SHOWN IN THE TABLE.
A SINGLE PAIR MAY BE WIRED TO EITHER P1-1,9 OR P1-2,3
Title
FOR RS485.
8
7
6
5
4
3
RS422/485 Interface
Size
B
Document Number
Date:
Thursday, April 11, 2002
2
Rev
A
Sheet
1
of
1
1
7.4
PWM Motor Interface
The following schematic shows a typical interface circuit between the MC3110 and an amplifier in
PWM output mode.
Comments on Schematic
The LMD18200 H-bridge driver is used.
MC3110 Technical Specifications
66
8
7
6
5
4
3
2
1
A 1 UF HIGH FREQUENCY CERAMIC CAP AND 100UF PER AMP CAP
SHOULD BE PLACED AS CLOSE AS POSSIBLE TO PINS 6 AND 7
OF THE LMD 18200. SEE NATIONAL SEMI APPLICATION INFORMATION
R?
VCC
~RS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
22K
35
2
7
13
21
36
40
47
50
52
60
62
93
103
121
D
9
10
11
12
15
16
17
18
19
22
23
24
25
26
27
28
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
63
64
POSLIM1
NEGLIM1
72
94
AXISIN1
AXISOUT1
AXIS1
QUADA1
QUADB1
INDX1
HOME1
67
68
69
70
QUADA1
QUADB1
~INDEX1
~HOME1
73
90
91
HALL1A
HALL1B
HALL1C
B
~RESET
58
CLOCKIN
110
111
112
114
115
116
117
118
119
122
123
124
125
126
127
128
131
129
130
4
6
1
132
~HOSTINTRPT
98
U3
5
3
GND
4
MPWR
6
BS1
OUT1
1
2
OUT2
BS2
10
11
MGND
7
PWM
DIR
BRAKE
.01UF
.01UF
LMD18200
>MOTORIN4001 TYPICAL DIODES
NATIONAL LMD18200
TYPICAL H-BRIDGE
MOTOR DRIVERS
PWMMAG1
PWMMAG2
PWMMAG3
100
101
102
MAG1
PWMSIGN1
PWMSIGN2
96
97
SIGN1
SRLRCV
SRLXMT
SRLENABLE
43
44
99
I/OINTRPT
PRLENABLE
SYNCH
53
65
54
ANALOG1
ANALOG2
ANALOG3
ANALOG4
ANALOG5
ANALOG6
ANALOG7
ANALOG8
74
89
75
88
76
83
77
82
ANALOGVCC
ANALOGREFHIGH
ANALOGREFLOW
ANALOGGND
84
85
86
87
3
8
14
20
29
37
46
56
59
61
71
92
104
113
120
41
>MOTOR+
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
N/C
~RAMSLCT
~PERIPHSLCT
R/~W
~STROBE
~WRITEENBL
W/~R
C
B
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
C
D
U1
CP24N11
GND
A
A
PERFORMANCE MOTION DEVICES
55 OLD BEDFORD RD
LINCOLN, MA 01773
Title
Single Phase SIGN MAGNITUDE PWM
8
7
6
5
4
3
Size
B
Document Number
Date:
Tuesday, November 19, 2002
2
Rev
A
Sheet
1
of
1
0
7.5
12-bit Parallel DAC Interface
The interface between the MC3110 chip and a quad 12 bit DAC is shown in the following figure.
Any single channel A/D can also be used provided it meets the interface timing requirements.
Comments on Schematic
The 12 data bits are written to the DAC addressed by address bits A1 and A2, when A0 is 0. In this
fashion CP address 4000 is used for axis 1. The odd address is reserved for chips with 2 drives per
axis.
MC3110 Technical Specifications
68
8R?
7
6
5
4
3
2
1
VCC
A[0..15]
QUADA1
QUADB1
~INDEX1
~HOME1
73
90
91
HALL1A
HALL1B
HALL1C
41
~RESET
CLK
58
CLOCKIN
PWMSIGN1
PWMSIGN2
96
97
SRLRCV
SRLXMT
SRLENABLE
43
44
99
I/OINTRPT
PRLENABLE
SYNCH
53
65
54
ANALOG1
ANALOG2
ANALOG3
ANALOG4
ANALOG5
ANALOG6
ANALOG7
ANALOG8
74
89
75
88
76
83
77
82
ANALOGVCC
ANALOGREFHIGH
ANALOGREFLOW
ANALOGGND
84
85
86
87
3
8
14
20
29
37
46
56
59
61
71
92
104
113
120
RS-
PWMMAG1
PWMMAG2
PWMMAG3
100
101
102
20
R/W
CS1-
23
/CS
1
25
24
GND
VDD
VLOG
8
9
10
11
12
13
14
15
16
17
18
19
STRBW E-
D
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
A1
22
A0
A2
21
A1
GND
7
/LDAC
RS-
6
/RESET
VOUTA
3
DACVA1
VOUTB
2
DACVA2
VOUTC
27
DACVA3
VOUTD
26
DACVA4
C
BURR-BROWN 7724,7725
SO or PLCC
GND
VREFL
VSS
4 DACS @ CP ADR
0X4000+ 0,2,4,6.
B
IF CLEAN SUPPLIES +- 10V ARE
PROVIDED FOR VREFH AND VREFL
IT IS GENERALLY NOT NECESSARY
TO PROVIDE OFFSET ADJUST.
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
B
98
IS-
DS4
DS5
DS6
DS7
DS8
DS9
DS10
DS11
DS12
DS13
DS14
DS15
VREFL
67
68
69
70
~HOSTINTRPT
DS[4..15]
U7
28
C
AXISIN1
AXISOUT1
VREFH
VSS
72
94
POSLIM1
NEGLIM1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
GND
63
64
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
110
111
112
114
115
116
117
118
119
122
123
124
125
126
127
128
131
129
130
4
6
1
132
5
9
10
11
12
15
16
17
18
19
22
23
24
25
26
27
28
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
N/C
~RAMSLCT
~PERIPHSLCT
R/~W
~STROBE
~WRITEENBL
W/~R
VREFH
VCC
~RS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
D
DS0
DS1
DS2
DS3
DS4
DS5
DS6
DS7
DS8
DS9
DS10
DS11
DS12
DS13
DS14
DS15
VDD
U1
4
35
2
7
13
21
36
40
47
50
52
60
62
93
103
121
22K
DS[0..15]
CP2N11
GND
ISA0
2
3
IS-
U2
U?
1
W EA14U2
2
4
5
1
CS1-
2
3
4
5
6
W E-
OR2
A14
STRB-
3
OR4
2
1
A0
A
U?
1
CS1A
OR5
PERFORMANCE MOTION DEVICES
55 OLD BEDFORD RD
LINCOLN, MA 01773
NOT
STRB-
A14-
THE LOGIC WITHIN THE DOTTED LINES
8
7
Title
PREFERRED LOGIC
IS EASILY IMPLEMENTED WITHIN A CPLD.
6
5
4
Single Phase DAC OUT
3
Size
B
Document Number
Date:
Tuesday, November 19, 2002
2
Rev
A
Sheet
1
of
1
1
7.6
16-bit Serial DAC Interface
The following schematic shows an interface circuit between the MC3110 and a dual 16-bit serial
DAC.
Comments on Schematic
The 16 data bits from the CP chip are latched in the two 74H165 shift registers when the CP writes
to address 400x hex, and the address bits A1 and A2 are latched in the 2 DLAT latches and decoded
by the 138 CPU cycle. The fed-back and-or gate latches, the decoded WRF, and the next clock will
clear the 1st sequencer flop DFF3. This will disable the WRF latch and the second clock will clear
the second DFF3 flop, forcing DACWRN low, and setting the first flop since WRF will have gone
high. DACWRN low will clear the 74109, SHFTCNTN. The 4 bit counter, 74161, is also parallel
loaded to 0, and the counter is enabled by ENP going high. The counter will not start counting nor
the shift register start shifting until the clock after the DACWRN flop sets since the load overrides
the count enable. When the DACWR flop is set the shift register will start shifting and the counter
will count the shifts. After 15 shifts CNT15 from the counter will go high and the next clock will set
the DACLAT flop and set the SHFTCNTN flop. This will stop the shift after 16 shifts and assert
L1 through L4 depending on the address stored in the latch. The 16th clock also was counted
causing the counter to roll over to 0 and CNT15 to go low. The next clock will therefore clear the
DACLAT flop causing the DAC latch signal L1 through L4 to terminate and the 16 bits of data to be
latched in the addressed DAC. The control logic is now back in its original state waiting for the next
write to the DACs by the CP. SERCK is a 10MHz clock, the 20MHz CP clock divided by 2, since
the AD1866 DACs will not run at 20MHz.
MC3110 Technical Specifications
70
8
7
6
5
4
3
2
1
U2
DACL
2
1
U2
2
CLK
3
NOT
D
Q
SERCK
1
NOT
SERCK
GND
2
CLK
3
U2
DS[0..15]
A14
2
A0
A1
A2
A14
ISR/W
A0
A1
A2
A14
ISR/W
STRB-
1
NOT
A14N
ISA0
R/W
STRB-
2
3
4
5
6
DS[0..15]
U2A
U2
Q
5
Q
6
GND
DS0
DS1
DS2
DS3
DS4
DS5
DS6
DS7
CLK
74LS74
U?
U2
WRF
1
1
DS[0..15]
2
1
LDN
2
CLKINH
LDN
1
SHTCNTN
10
11
12
13
14
3
4
5
6
SER
A
B
C
D
E
F
G
H
2
15
1
CLK
INH
SH/LD
U2
3
OR5
NAND2
3
STRB-
D
QH
9
QH
7
QH
9
QH
7
74165
OR2
CLK
RS-
RSGND
3
CLK
OR2
2
3
4
1
5
D
3
CLK
DFF3
3
U?
Q
1
U2
DACWRN
VCC
NOR2
3
4
5
6
7
10
2
9
1
DFF3
4
1
2
CL
2
1
Q
PR
D
CL
2
3
U2
RS-
U2
2
1
U2
U2
5
U2
WRF
4
CLK
RS-
PR
D
DFF
D
PR
1
CL
2
4
U2
SERCK
AND3
1
C
U2
A
B
C
D
QA
QB
QC
QD
RCO
14
13
12
11
15
ENP
ENT
CLK
LOAD
CLR
U2
DS15
2
74161
2
DS8
DS9
DS10
DS11
DS12
DS13
DS14
1
NOT
10
11
12
13
14
3
4
5
6
SER
A
B
C
D
E
F
G
H
2
15
1
CLK
INH
SH/LD
DL
NRL
13
5
DR
NRR
11
VOR
10
VBR
8
LR
B
SERCK
CLK
VO1
D
3
1
GND
G
DACL
SERCK
GND
DLAT
VO2
1
2
3
6
4
5
U2
A2
2
D
3
G
VB2
WRF
Q
A
B
C
G1
G2A
G2B
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
15
14
13
12
11
10
9
7
L1
L2
L3
L4
3
K
L1
L2
L3
L4
Q
7
U2
2
D
3
CLK
74109
VCC
138
1
PR
U2
Q
CL
2
2
J
4
CLK
3
K
Q
1
SDAT
SDAT
U2A
DFF
Q
6
Q
7
DACL
B
74109
AD1866
7
12
4
A1
SHFTCNTN
1
VOL
14
VB1
5
LL
U2
16
3
6
CLK
6
PR
L2
4
Q
1
SDAT
J
CL
1
9
15
VL
VS
VS
2
2
U3
DGND
AGND
L1
U2A
5
5VA
VBL
C
74165
NOT
VCC
SERD
DLAT
GND
ALL LOGIC LABELLED U2 MAY BE IMPLEMENTED IN A CPLD
VCC
5VA
THE MODULE PORTS REPRESENT INPUTS AND OUTPUTS FROM THE CPLD
ALL INPUT SIGNALS ARE COMMON TO THE CP.
VL
VS
VS
1
9
15
U4
16
VB3
VOL
14
VO3
3
DL
NRL
13
5
DR
NRR
11
6
LR
4
CLK
VO1
10K
VOR
10
VO4
VBR
8
VB4
3
+
2
-
-12VA
R2
U4A
DACV1
1
DACV1
A
OP497
PERFORMANCE MOTION DEVICES
55 OLD BEDFORD RD
LINCOLN, MA 01773
R3
VB1
Title
10K
SERIAL DAC OUT
100K
AD1866
7
12
L4
R1
13
A
+12VA
4
VBL
LL
2
DGND
AGND
L3
AXIS 1 AMP SHOWN TYPICAL OF ALL 4 AXIS
Size
B
Document Number
Date:
Thursday, April 11, 2002
Rev
A
GND
8
7
6
5
4
3
2
Sheet
1
of
1
0
7.7
RAM Interface
The following schematic shows an interface circuit between the MC3110 and external ram.
Comments on Schematic
The CP is capable of directly addressing 32K words of 16-bit memory. It will also use a 16 bit
paging register to address up to 32K word pages. The schematic shows the paging and addressing
for 128KB RAM chips, i.e. 4 pages per RAM chip. The page address decoding is shown for only 6 of
the 16 possible paging bits. The decoding time from W/R and DS- to the memory output must not
exceed 18 ns. for a read with no wait states. The writes provide 25 extra ns access time for W/R and
DS- to reverse the CP data bus.
MC3110 Technical Specifications
72
8
7
6
5
4
3
2
1
D[0..15]
A[0..14]
D
D
R?
VCC
U?
VCC
~RS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
35
2
7
13
21
36
40
47
50
52
60
62
93
103
121
22K
9
10
11
12
15
16
17
18
19
22
23
24
25
26
27
28
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
63
64
POSLIM1
NEGLIM1
72
94
AXISIN1
AXISOUT1
67
68
69
70
73
90
91
QUADA1
QUADB1
~INDEX1
~HOME1
HALL1A
HALL1B
HALL1C
B
RS-
41
~RESET
CLK
58
CLOCKIN
U2
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
N/C
~RAMSLCT
~PERIPHSLCT
R/~W
~STROBE
~WRITEENBL
W/~R
110
111
112
114
115
116
117
118
119
122
123
124
125
126
127
128
131
129
130
4
6
1
132
~HOSTINTRPT
98
PWMMAG1
PWMMAG2
PWMMAG3
100
101
102
PWMSIGN1
PWMSIGN2
96
97
SRLRCV
SRLXMT
SRLENABLE
43
44
99
I/OINTRPT
PRLENABLE
SYNCH
53
65
54
ANALOG1
ANALOG2
ANALOG3
ANALOG4
ANALOG5
ANALOG6
ANALOG7
ANALOG8
74
89
75
88
76
83
77
82
ANALOGVCC
ANALOGREFHIGH
ANALOGREFLOW
ANALOGGND
84
85
86
87
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
D0
D1
D2
D3
D4
D5
D6
D7
3
4
7
8
13
14
17
18
D1
D2
D3
D4
D5
D6
D7
D8
W EPGR-
11
1
CLK
G
2
5
6
9
12
15
16
19
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
MPG0
MPG1
U2A
2
3
A
B
1
G
Y0
Y1
Y2
Y3
4
5
6
7
CS1
CS2
CS3
CS4
Y0
Y1
Y2
Y3
12
11
10
9
CS5
CS6
CS7
CS8
POS139
U2B
74LS377
GND
14
13
A
B
15
G
U2
W EW/R
D8
D9
D10
D11
D12
D13
D14
D15
3
4
7
8
13
14
17
18
D1
D2
D3
D4
D5
D6
D7
D8
W EPGR-
11
1
CLK
G
2
5
6
9
12
15
16
19
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
DSCS1
22
30
CE1
CE2
WEW/R
POS139
DSISR/W
12
11
10
9
8
7
6
5
27
26
23
25
4
28
3
31
2
NOTE:THE CRITICAL DECODE AND MEMORY
ACCESS TIME IS DURING READ,
THE REQUIRED ACCESS TIME IS
18 NS. FROM DS- LOW.
AS ILLUSTRATED THERE IS ~ 100NS.
TO ACCOMPLISH THE DECODING
FROM PAGE REG WRITE TO
MEMORY READ OR WRITE.
DECODING WILL HAVE TO BE
CAREFULLY DONE ON MEMORIES
WITH A SINGLE CHIP SELECT.
29
24
U?
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
13
14
15
17
18
19
20
21
D0
D1
D2
D3
D4
D5
D6
D7
WE
OE
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
MPG0
MPG1
12
11
10
9
8
7
6
5
27
26
23
25
4
28
3
31
2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
DSCS1
22
30
CE1
CE2
WEW/R
29
24
WE
OE
MCM6226
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
D8
D9
D10
D11
D12
D13
D14
D15
13
14
15
17
18
19
20
21
C
MCM6226
D[0..15]
A[0..14]
74LS377
PAGE REGISTER UP TO 16 BITS
U?
U2
U2
A13
2
1
ISR/W
2
3
4
1
PGR-
NOT
OR3
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
MPG0
MPG1
12
11
10
9
8
7
6
5
27
26
23
25
4
28
3
31
2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
DSCS2
22
30
CE1
CE2
WEW/R
29
24
U?
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
13
14
15
17
18
19
20
21
D0
D1
D2
D3
D4
D5
D6
D7
WE
OE
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
MPG0
MPG1
12
11
10
9
8
7
6
5
27
26
23
25
4
28
3
31
2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
DSCS2
22
30
CE1
CE2
WEW/R
29
24
WE
OE
MCM6226
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
D8
D9
D10
D11
D12
D13
D14
D15
13
14
15
17
18
19
20
21
B
MCM6226
3
8
14
20
29
37
46
56
59
61
71
92
104
113
120
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
C
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
NOTE: POS139 IS A STANDARD 139 WITH INVERTED
OUTPUTS
U?
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
MPG0
MPG1
CP2N11
GND
A
A
PERFORMANCE MOTION DEVICES
55 OLD BEDFORD RD
LINCOLN, MA 01773
Title
RAM INTERFACE
8
7
6
5
4
3
Size
B
Document Number
Date:
Tuesday, November 19, 2002
2
Rev
B
Sheet
1
of
1
0
7.8
User-defined I/O
The interface between the MC3110 chip and 16 bits of user output and 16 bits of user input is shown
in the following figure.
Comments on Schematic
The schematic implements 1 word of user output registered in the 74LS377’s and 1 word of user
inputs read via the 244’s. The schematic decodes the low 3 bits of the address to 8 possible UIO
addresses UIO0 through UIO7. Registers and buffers are shown for only UIO0, but the
implementation shown may be easily extended. The lower 8 address bits may be decoded to provide
up to 256 user output words and 256 user input words of 16 bits.
MC3110 Technical Specifications
74
8
7
6
5
4
3
2
1
D[0..15]
A[0..14]
R?
D
D
VCC
U2
35
2
7
13
21
36
40
47
50
52
60
62
93
103
121
22K
U2
~RS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
9
10
11
12
15
16
17
18
19
22
23
24
25
26
27
28
63
64
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
POSLIM1
NEGLIM1
72
94
AXISIN1
AXISOUT1
67
68
69
70
QUADA1
QUADB1
~INDEX1
~HOME1
73
90
91
HALL1A
HALL1B
HALL1C
B
41
~RESET
CLK
58
CLOCKIN
110
111
112
114
115
116
117
118
119
122
123
124
125
126
127
128
131
129
130
4
6
1
132
~HOSTINTRPT
98
PWMMAG1
PWMMAG2
PWMMAG3
100
101
102
PWMSIGN1
PWMSIGN2
96
97
SRLRCV
SRLXMT
SRLENABLE
43
44
99
I/OINTRPT
PRLENABLE
SYNCH
53
65
54
ANALOG1
ANALOG2
ANALOG3
ANALOG4
ANALOG5
ANALOG6
ANALOG7
ANALOG8
74
89
75
88
76
83
77
82
ANALOGVCC
ANALOGREFHIGH
ANALOGREFLOW
ANALOGGND
84
85
86
87
3
8
14
20
29
37
46
56
59
61
71
92
104
113
120
RS-
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
N/C
~RAMSLCT
~PERIPHSLCT
R/~W
~STROBE
~WRITEENBL
W/~R
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
D0
D1
D2
D3
D4
D5
D6
D7
3
4
7
8
13
14
17
18
D1
D2
D3
D4
D5
D6
D7
D8
WEUIO0
11
1
CLK
G
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
UO0-0
UO0-1
UO0-2
UO0-3
UO0-4
UO0-5
UO0-6
UO0-7
2
5
6
9
12
15
16
19
UIO
A3
A4
1
2
3
A
B
C
6
4
5
G1
G2A
G2B
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
UIO0
UIO1
UIO2
UIO3
UIO4
UIO5
UIO6
UIO7
15
14
13
12
11
10
9
7
138
USER OUTPUTS
74LS377
U2
U2
ISWEW/R
U2
D8
D9
D10
D11
D12
D13
D14
D15
3
4
7
8
13
14
17
18
D1
D2
D3
D4
D5
D6
D7
D8
WEUIO0
11
1
CLK
G
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
UO0-8
UO0-9
UO0-10
UO0-11
UO0-12
UO0-13
UO0-14
UO0-15
2
5
6
9
12
15
16
19
A12
2
1
A12n
2
IS-
3
1
C
UIO
NOT
NOR2
U2
A12n
2
IS-
3
U2
1
74LS377
UIOn
W/R
UIO0
2
3
4
1
UI0n
OR2
OR3
U2
D0
D1
D2
D3
D4
D5
D6
D7
18
16
14
12
9
7
5
3
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
2
4
6
8
11
13
15
17
UI0-0
UI0-1
UI0-2
UI0-3
UI0-4
UI0-5
UI0-6
UI0-7
1G
2G
1
19
UI0n
UI0n
THE LOGIC LABELED U2 MAY BE IMPLEMENTED IN
A CPLD. THE LOWER 8 ADDRESS BITS, A0-A8, MAY BE
DECODED TO PROVIDE 256 16 BIT USER INPUTS
B
AND 256 USER OUTPUTS.
USER INPUTS
244
U2
D8
D9
D10
D11
D12
D13
D14
D15
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
C
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
A0
A1
A2
U?
18
16
14
12
9
7
5
3
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
CP2N11
GND
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
2
4
6
8
11
13
15
17
1G
2G
1
19
UI0-8
UI0-9
UI0-10
UI0-11
UI0-12
UI0-13
UI0-14
UI0-15
UI0n
UI0n
244
A
A
PERFORMANCE MOTION DEVICES
55 OLD BEDFORD RD
LINCOLN, MA 01773
Title
USER I/O
8
7
6
5
4
3
Size
B
Document Number
Date:
Tuesday, November 19, 2002
2
Rev
D
Sheet
1
of
1
0
7.9
12-bit A/D Interface
The following schematic shows a typical interface circuit between the MC3110 and a quad 12 bit 2’s
complement A/D converter used as a position input device. Any single channel A/D can also be
used provided it meets the interface timing requirements.
Comments on Schematic
The A/D converter samples the 2’s complement digital words. DACRD- is used to perform the
read and is also used to load the counter to FFh. The counter will be reloaded for each read and will
not count significantly between reads. The counter will therefore start counting down after the last
read and will generate the cvt- pulse after 12.75 µsec. The conversions will take approximately 35
µsec, and the data will be available for the next set of reads after 50 µsec. The 12 bit words from the
A/D are extended to 16 bits with the 74LS244.
MC3110 Technical Specifications
76
8
7
6
5
4
3
2
1
R?
VCC
A[0..15]
QUADA1
QUADB1
~INDEX1
~HOME1
73
90
91
HALL1A
HALL1B
HALL1C
B
41
~RESET
58
CLOCKIN
100
101
102
PWMSIGN1
PWMSIGN2
96
97
SRLRCV
SRLXMT
SRLENABLE
43
44
99
I/OINTRPT
PRLENABLE
SYNCH
53
65
54
VIN3
POS4
28
VIN4
CVT-
74
89
75
88
76
83
77
82
ANALOGVCC
ANALOGREFHIGH
ANALOGREFLOW
ANALOGGND
84
85
86
87
9
VDD
VDD
11
DS10
DB9
12
DS9
DB8
13
DS8
DB7
15
DS7
DB6
16
DS6
DACRD-
IS-
2
3
STRB-
1
W/R
DB5
17
DS5
6
RD
DB4
18
DS4
7
CS
DB3
19
DS3
DB2
20
DS2
DB1
21
DS1
DB0
22
DS0
INT
4
24
4
5
U2
CONVST
U2
25
A11
2
1
8
REFIN
REFOUT
CLK
NOT
CLK
DACRDGND
ENCNT-
2
9
1
10
7
A
B
C
D
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
1
19
1G
2G
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
18
16
14
12
9
7
5
3
DS15
DS14
DS13
DS12
D
74LS244
NOTE:SIGN EXTENTION FOR 2'S COMPLEMENT
AD7874
C
AGND
U2
3
4
5
6
DACRD-
2
4
6
8
11
13
15
17
GND
VCC
VCC
U2
DS11
5
-5VA
ANALOG1
ANALOG2
ANALOG3
ANALOG4
ANALOG5
ANALOG6
ANALOG7
ANALOG8
3
8
14
20
29
37
46
56
59
61
71
92
104
113
120
RSCLK
PWMMAG1
PWMMAG2
PWMMAG3
10
DB10
VIN2
27
OR4
98
DB11
NOTE:FS INPUTS ARE +- 10V
POS3
DS11
U2
QA
QB
QC
QD
RCO
CLK
LOAD
U/D
ENT
ENP
14
13
12
11
15
3
4
5
6
CLK
DACRDGND
2
9
1
10
7
74ALS169
A
B
C
D
QA
QB
QC
QD
RCO
14
13
12
11
15
U2
CVT-
2
U2
DFF2
1
CLK
LOAD
U/D
ENT
ENP
NOT
2
D
3
CLK
Q
ENCNT-
1
CL
67
68
69
70
~HOSTINTRPT
VIN1
DGND
AXISIN1
AXISOUT1
2
AGND
72
94
1
POS2
DS[0..15]
U?
CLK
74ALS169
4
C
POSLIM1
NEGLIM1
POS1
VSS
63
64
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
23
9
10
11
12
15
16
17
18
19
22
23
24
25
26
27
28
110
111
112
114
115
116
117
118
119
122
123
124
125
126
127
128
131
129
130
4
6
1
132
DACRD- WILL LOAD THE COUNTER TO 255.
12.8 USEC. AFTER THE LAST DACRDTHE COUNTER WILL REACH 0 AND START THE
NEXT CONVERSION. THE INPUT WILL
BE CONVERTED IN 35 USEC. READY FOR
THE NEXT READ 50 USEC LATER.
DACRDB
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
D
DS0
DS1
DS2
DS3
DS4
DS5
DS6
DS7
DS8
DS9
DS10
DS11
DS12
DS13
DS14
DS15
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
N/C
~RAMSLCT
~PERIPHSLCT
R/~W
~STROBE
~WRITEENBL
W/~R
26
~RS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
3
U1
14
22K
DS[0..15]
35
2
7
13
21
36
40
47
50
52
60
62
93
103
121
VCC
CP2N11
NOTE:THE LOGIC LABELED U2 MAY
BE IMPLEMENTEDIN A PLD.
GND
A
A
PERFORMANCE MOTION DEVICES
55 OLD BEDFORD RD
LINCOLN, MA 01773
Title
12 BIT A/D IN
8
7
6
5
4
3
Size
B
Document Number
Date:
Tuesday, November 19, 2002
2
Rev
A
Sheet
1
of
1
0
7.10 16-bit A/D Input
The interface between the MC3110 chip and a 16 bit A/D converter as a parallel input position
device is shown in the following figure.
Comments on Schematic
The schematic shows a 16 bit A/D used to provide parallel position input. The 374 registers are
required on the output of the A/D converters to make the 68-nanosecond access time of the CP.
The worst-case timing of the A/D’s specify 83 nanoseconds for data on the bus and 83 nanoseconds
from data to tri-state on the bus. Each time the data is read the 169 counter is set to 703 decimal.
This provides a 35.2-microsecond delay before the next conversion. With a 10-microsecond
conversion time the data will be available for the next set of reads after 50 microseconds. The delay
is used to provide a position sample close to the actual position.
MC3110 Technical Specifications
78
8
7
6
5
4
3
2
1
R?
VCC
DS[0..15]
+5A
63
64
POSLIM1
NEGLIM1
72
94
C
AXISIN1
AXISOUT1
67
68
69
70
QUADA1
QUADB1
~INDEX1
~HOME1
73
90
91
HALL1A
HALL1B
HALL1C
41
~RESET
CLK
58
CLOCKIN
VIN
R2
33.2
3
REF
4
CVTGND
IS-
2
3
1
W/R
R/C
23
BYTE
DACRD-
4
5
A11n
CS
24
U2
STRB-
CAP
25
C1
2.2UF
C1
2.2UF
PWMSIGN1
PWMSIGN2
96
97
SRLRCV
SRLXMT
SRLENABLE
43
44
99
I/OINTRPT
PRLENABLE
SYNCH
53
65
54
ANALOG1
ANALOG2
ANALOG3
ANALOG4
ANALOG5
ANALOG6
ANALOG7
ANALOG8
74
89
75
88
76
83
77
82
ANALOGVCC
ANALOGREFHIGH
ANALOGREFLOW
ANALOGGND
84
85
86
87
A11
U3
28
27
1
200
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
6
7
8
9
10
11
12
13
15
16
17
18
19
20
21
22
BUSY
26
D0
D1
D2
D3
D4
D5
D6
D7
1
11
OC
CLK
3
4
7
8
13
14
17
18
D0
D1
D2
D3
D4
D5
D6
D7
1
11
OC
CLK
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
D
374
U2
AD976
DACRD-
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
374
GND
U2
100
101
102
VCC
R1
AIN1
OR4
PWMMAG1
PWMMAG2
PWMMAG3
3
8
14
20
29
37
46
56
59
61
71
92
104
113
120
RS-
98
NOTE:FS INPUTS ARE +- 10V
3
4
7
8
13
14
17
18
2
A11n
1
AGND
C
NOTE:THE LOGIC LABELED U2 MAY
NOT
BE IMPLEMENTEDIN A PLD.
SEE ANALOG DEVICES SPECIFICATIONS FOR
ADITIONAL INFORMATION AND POWER BYPASSING.
B
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
B
~HOSTINTRPT
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
VANA
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
110
111
112
114
115
116
117
118
119
122
123
124
125
126
127
128
131
129
130
4
6
1
132
AGND1
AGND2
DGND
9
10
11
12
15
16
17
18
19
22
23
24
25
26
27
28
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
N/C
~RAMSLCT
~PERIPHSLCT
R/~W
~STROBE
~WRITEENBL
W/~R
2
5
14
DS0
DS1
DS2
DS3
DS4
DS5
DS6
DS7
DS8
DS9
DS10
DS11
DS12
DS13
DS14
DS15
U2
U1
~RS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
D
VCC
A[0..15]
35
2
7
13
21
36
40
47
50
52
60
62
93
103
121
22K
DS[0..15]
CP2N11
GND
VCC
VCC
A
CLK
DACRDGND
ENCNT-
2
9
1
10
7
A
B
C
D
CLK
LOAD
U/D
ENT
ENP
14
13
12
11
15
3
4
5
6
CLK
DACRDGND
2
9
1
10
7
74ALS169
8
U2
U2
QA
QB
QC
QD
RCO
A
B
C
D
CLK
LOAD
U/D
ENT
ENP
14
13
12
11
15
3
4
5
6
GND
CLK
DACRDGND
2
9
1
10
7
74ALS169
7
U2
DFF2
U2
QA
QB
QC
QD
RCO
A
B
C
D
QA
QB
QC
QD
RCO
CLK
LOAD
U/D
ENT
ENP
14
13
12
11
15
CVT-
2
1
NOT
D
3
CLK
Q
1
ENCNTA
PERFORMANCE MOTION DEVICES
55 OLD BEDFORD RD
LINCOLN, MA 01773
CLK
DACRD-
74ALS169
6
2
CL
U2
3
4
5
6
4
VCC
5
DACRD- WILL LOAD THE COUNTER TO 700.
38.4 USEC. AFTER THE DACRDTHE COUNTER WILL REACH 0 AND START THE
NEXT CONVERSION. THE INPUT WILL
BE CONVERTED IN 10 USEC. READY FOR
THE NEXT READ AFTER 50 USEC.
4
Title
16 BIT A/D INPUT
3
Size
B
Document Number
Date:
Tuesday, November 19, 2002
2
Rev
A
Sheet
1
of
1
1
7.11 External Gating Logic Index
A typical circuit for gating the Index signal with the encoder A & B channels is shown in the
following schematic.
Comments on Schematic
In order for proper operation of the Index signal when used for position capture, the signal must be
gated with the A & B encoder channels to ensure that this signal is only active when all three signals
are LOW. The motion processor does not perform this gating internally.
MC3110 Technical Specifications
80
5
4
3
2
1
D
D
R?
~RS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
22K
35
2
7
13
21
36
40
47
50
52
60
62
93
103
121
VCC
QUADA1
QUADB1
HOME1
QUADA1
QUADB1
INDEX1
B
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
63
64
POSLIM1
NEGLIM1
72
94
AXISIN1
AXISOUT1
67
68
69
70
QUADA1
QUADB1
~INDEX1
~HOME1
73
90
91
HALL1A
HALL1B
HALL1C
U3
2
3
4
1
INDX1
OR3
~RESET
58
CLOCKIN
~HOSTINTRPT
98
PWMMAG1
PWMMAG2
PWMMAG3
100
101
102
PWMSIGN1
PWMSIGN2
96
97
SRLRCV
SRLXMT
SRLENABLE
43
44
99
I/OINTRPT
PRLENABLE
SYNCH
53
65
54
ANALOG1
ANALOG2
ANALOG3
ANALOG4
ANALOG5
ANALOG6
ANALOG7
ANALOG8
74
89
75
88
76
83
77
82
ANALOGVCC
ANALOGREFHIGH
ANALOGREFLOW
ANALOGGND
84
85
86
87
3
8
14
20
29
37
46
56
59
61
71
92
104
113
120
41
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
N/C
~RAMSLCT
~PERIPHSLCT
R/~W
~STROBE
~WRITEENBL
W/~R
C
B
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
C
9
10
11
12
15
16
17
18
19
22
23
24
25
26
27
28
U1
110
111
112
114
115
116
117
118
119
122
123
124
125
126
127
128
131
129
130
4
6
1
132
CP24N11
GND
A
A
PERFORMANCE MOTION DEVICES
55 OLD BEDFORD RD
LINCOLN, MA 01773
Title
EXTERNAL GATING LOGIC INDEX
5
4
3
2
Size
B
Document Number
Date:
Tuesday, November 19, 2002
Rev
A
Sheet
1
1
of
1
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