Freescale MC68HC908AT32FU Microcontroller Datasheet

MC68HC908AT32
Advance Information Data Sheet
M68HC08
Microcontrollers
MC68HC908AT32
Rev. 3.1
09/2005
freescale.com
This document contains certain information on a new product.Specifications and information herein are subject to change without notice.
MC68HC908AT32
Advance Information Data Sheet
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be
the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://www.freescale.com
The following revision history table summarizes changes contained in this document. For your
convenience, the page number designators have been linked to the appropriate location.
Revision History
Date
June,
2001
September,
2005
Revision
Level
3.0
3.1
Description
Page
Number(s)
General reformat to bring document up to current publication standards
All
First bulleted paragraph under the subsection 18.5 Interrupts reworded
for clarity
290
First bulleted paragraph under the subsection 19.5 Interrupts reworded
for clarity
316
First bulleted paragraph under the subsection 25.5 Interrupts reworded
for clarity
446
Updated to meet Freescale identity guidelines.
Throughout
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
This product incorporates SuperFlash® technology licensed from SST.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
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Revision History
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List of Chapters
Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Chapter 2 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Chapter 3 Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Chapter 4 FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Chapter 5 Electrically Erasable Programmable ROM (EEPROM) . . . . . . . . . . . . . . . . . . . . 57
Chapter 6 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Chapter 7 System Integration Module (SIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Chapter 8 Clock Generator Module (CGM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Chapter 9 Configuration Register (CONFIG-1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Chapter 10 Configuration Register (CONFIG-2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Chapter 11 Break Module (BRK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Chapter 12 Monitor ROM (MON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Chapter 13 Computer Operating Properly Module (COP) . . . . . . . . . . . . . . . . . . . . . . . . . 125
Chapter 14 Low-Voltage Inhibit (LVI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Chapter 15 External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Chapter 16 Serial Communications Interface Module (SCI) . . . . . . . . . . . . . . . . . . . . . . .139
Chapter 17 Serial Peripheral Interface Module (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Chapter 18 Timer Interface (TIMA-4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Chapter 19 Timer Interface (TIMB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Chapter 20 Modulo Timer (TIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Chapter 21 Analog-to-Digital Converter (ADC-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Chapter 22 MC68HC08AZ32 Emulator Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . 233
Chapter 23 MSCAN Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
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List of Chapters
Chapter 24 Keyboard Interrupt Module (KBD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Chapter 25 Timer Interface (TIM-6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Chapter 26 Analog-to-Digital Converter (ADC-15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Chapter 27 MC68HC08AS20 Emulator Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . 315
Chapter 28 Byte Data Link Controller-Digital (BDLC-D) . . . . . . . . . . . . . . . . . . . . . . . . . . 329
Chapter 29 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
Chapter 30 Mechanical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
Chapter 31 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
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Table of Contents
Chapter 1
General Description
1.1
1.2
1.3
1.4
1.4.1
1.4.2
1.4.3
1.4.4
1.4.5
1.4.6
1.4.7
1.4.8
1.4.9
1.4.10
1.4.11
1.4.12
1.4.13
1.4.14
1.4.15
1.4.16
1.4.17
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply Pins (VDD and VSS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Reset Pin (RST). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Interrupt Pin (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Power Supply Pin (VDDA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Ground Pin (VSSA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A Input/Output (I/O) Pins (PTA7–PTA0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port B I/O Pins (PTB7/ATD7–PTB0/ATD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port C I/O Pins (PTC5–PTC0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port D I/O Pins (PTD7/ATD15–PTD0/ATD8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port E I/O Pins (PTE7/SPSCK–PTE0/TxD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port F I/O Pins (PTF6–PTF0/TACH2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port G I/O Pins (PTG2/KBD2–PTG0/KBD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port H I/O Pins (PTH1/KBD4–PTH0/KBD3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CAN Transmit Pin (CANTx)/BDLC Transmit Pin (BDTxD). . . . . . . . . . . . . . . . . . . . . . . . . .
CAN Receive Pin (CANRx)/BDLC Receive Pin (BDRxD) . . . . . . . . . . . . . . . . . . . . . . . . . .
21
21
24
27
29
29
29
29
29
30
30
30
30
30
30
31
31
31
31
31
32
Chapter 2
Memory Map
2.1
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Input/Output (I/O) Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Chapter 3
Random-Access Memory (RAM)
3.1
3.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Chapter 4
FLASH Memory
4.1
4.2
4.3
4.4
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Charge Pump Frequency Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
51
51
51
52
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4.5
4.6
4.7
4.8
FLASH Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FLASH Program/Verify Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FLASH Block Protect Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
53
54
54
55
Chapter 5
Electrically Erasable Programmable ROM (EEPROM)
5.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.1
EEPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.2
EEPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.3
EEPROM Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.4
EEPROM Redundant Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.5
MCU Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.6
MC68HC908AT32 EEPROM Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.7
EEPROM Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.8
EEPROM Non-Volatile Register and EEPROM Array Configuration Register . . . . . . . . . .
5.3.9
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.9.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.9.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
57
57
57
57
58
59
60
60
60
61
62
63
63
63
Chapter 6
Central Processor Unit (CPU)
6.1
6.2
6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.4
6.5
6.5.1
6.5.2
6.6
6.7
6.8
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
65
65
65
66
66
67
67
68
69
69
69
69
69
70
75
Chapter 7
System Integration Module (SIM)
7.1
7.2
7.2.1
7.2.2
7.2.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Startup from POR or LVI Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
77
79
79
79
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7.3
Reset and System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.1
External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.2
Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.2.1
Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.2.2
Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.2.3
Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.2.4
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.2.5
Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4
SIM Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4.1
SIM Counter during Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4.2
SIM Counter during Stop Mode Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4.3
SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5
Program Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5.1
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5.1.1
Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5.1.2
SWI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5.2
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5.3
Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5.4
Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.6
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.6.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.6.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7
SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7.1
SIM Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7.2
SIM Reset Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7.3
SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
80
80
81
81
82
82
82
82
83
83
83
83
83
84
85
86
86
86
87
87
87
88
89
89
90
91
Chapter 8
Clock Generator Module (CGM)
8.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
8.2
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
8.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
8.3.1
Crystal Oscillator Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
8.3.2
Phase-Locked Loop Circuit (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
8.3.2.1
Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
8.3.2.2
Acquisition and Tracking Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
8.3.2.3
Manual and Automatic PLL Bandwidth Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
8.3.2.4
Programming the PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
8.3.2.5
Special Programming Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
8.3.3
Base Clock Selector Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
8.3.4
CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
8.4
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
8.4.1
Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
8.4.2
Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
8.4.3
External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
8.4.4
Analog Power Pin (VDDA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
8.4.5
Oscillator Enable Signal (SIMOSCEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
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Freescale Semiconductor
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Table of Contents
8.4.6
8.4.7
8.4.8
8.5
8.5.1
8.5.2
8.5.3
8.6
8.7
8.7.1
8.7.2
8.8
8.9
8.9.1
8.9.2
8.9.3
8.9.4
Crystal Output Frequency Signal (CGMXCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CGM Base Clock Output (CGMOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CGM CPU Interrupt (CGMINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CGM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Bandwidth Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Programming Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CGM during Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Acquisition/Lock Time Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Acquisition/Lock Time Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parametric Influences on Reaction Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Choosing a Filter Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reaction Time Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
101
101
101
101
101
103
104
105
105
105
105
106
106
106
107
107
108
Chapter 9
Configuration Register (CONFIG-1)
9.1
9.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Chapter 10
Configuration Register (CONFIG-2)
10.1
10.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Chapter 11
Break Module (BRK)
11.1
11.2
11.3
11.3.1
11.3.2
11.3.3
11.3.4
11.4
11.4.1
11.4.2
11.5
11.5.1
11.5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flag Protection during Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU during Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIM during Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COP during Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Break Module Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Break Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
113
113
113
114
114
115
115
115
115
115
115
115
116
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Chapter 12
Monitor ROM (MON)
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.3.1
Entering Monitor Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.3.2
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.3.3
Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.3.4
Break Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.3.5
Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.3.6
Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
117
117
117
119
120
120
120
121
123
Chapter 13
Computer Operating Properly Module (COP)
13.1
13.2
13.3
13.3.1
13.3.2
13.3.3
13.3.4
13.3.5
13.3.6
13.3.7
13.3.8
13.4
13.5
13.6
13.7
13.7.1
13.7.2
13.8
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CGMXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Vector Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COPD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COPRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COP Module during Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
125
125
126
126
126
126
126
126
127
127
127
127
127
127
127
127
128
128
Chapter 14
Low-Voltage Inhibit (LVI)
14.1
14.2
14.3
14.3.1
14.3.2
14.3.3
14.4
14.5
14.6
14.6.1
14.6.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Forced Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
False Reset Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LVI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
129
129
129
129
129
130
130
131
131
131
131
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Table of Contents
Chapter 15
External Interrupt (IRQ)
15.1
15.2
15.3
15.4
15.5
15.6
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IRQ/VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IRQ Module during Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
133
133
133
136
136
137
Chapter 16
Serial Communications Interface Module (SCI)
16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
16.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
16.3 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
16.4.1
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
16.4.2
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
16.4.2.1
Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
16.4.2.2
Character Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
16.4.2.3
Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
16.4.2.4
Idle Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
16.4.2.5
Inversion of Transmitted Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
16.4.2.6
Transmitter Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
16.4.3
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
16.4.3.1
Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
16.4.3.2
Character Reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
16.4.3.3
Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
16.4.3.4
Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
16.4.3.5
Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
16.4.3.6
Receiver Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
16.4.3.7
Receiver Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
16.4.3.8
Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
16.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
16.5.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
16.5.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
16.6 SCI during Break Module Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
16.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
16.7.1
PTE0/SCTxD (Transmit Data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
16.7.2
PTE1/SCRxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
16.8 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
16.8.1
SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
16.8.2
SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
16.8.3
SCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
16.8.4
SCI Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
16.8.5
SCI Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
16.8.6
SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
16.8.7
SCI Baud Rate Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
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Chapter 17
Serial Peripheral Interface Module (SPI)
17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.3 Pin Name and Register Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.4.1
Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.4.2
Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.5 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.5.1
Clock Phase and Polarity Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.5.2
Transmission Format When CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.5.3
Transmission Format When CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.5.4
Transmission Initiation Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.6 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.6.1
Overflow Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.6.2
Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.8 Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.9 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.10 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.10.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.10.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.11 SPI during Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.12 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.12.1
MISO (Master In/Slave Out). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.12.2
MOSI (Master Out/Slave In). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.12.3
SPSCK (Serial Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.12.4
SS (Slave Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.12.5
VSS (Clock Ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.13 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.13.1
SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.13.2
SPI Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.13.3
SPI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
163
163
163
164
164
166
166
167
167
168
168
170
170
171
173
174
175
175
175
175
176
176
176
177
177
177
178
178
178
180
182
Chapter 18
Timer Interface (TIMA-4)
18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.3.1
TIMA Counter Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.3.2
Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.3.3
Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.3.3.1
Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.3.3.2
Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.3.4
Pulse-Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.3.4.1
Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
185
185
185
188
188
189
189
190
190
191
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18.3.4.2
Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.3.4.3
PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.5.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.5.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.6 TIMA during Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.7.1
TIMA Clock Pin (PTD6/ATD14/TCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.7.2
TIMA Channel I/O Pins (PTF1/TACH3–PTF0/TACH2 and PTE3/TACH1–PTE2/TACH0)
18.8 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.8.1
TIMA Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.8.2
TIMA Counter Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.8.3
TIMA Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.8.4
TIMA Channel Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.8.5
TIMA Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
192
192
193
193
193
194
194
194
194
195
195
195
197
197
198
201
Chapter 19
Timer Interface (TIMB)
19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.3.1
TIMB Counter Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.3.2
Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.3.3
Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.3.3.1
Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.3.3.2
Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.3.4
Pulse-Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.3.4.1
Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.3.4.2
Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.3.4.3
PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.5.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.5.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.6 TIMB during Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.7.1
TIMB Clock Pin (PTD4/ATD12/TBCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.7.2
TIMB Channel I/O Pins (PTF5/TBCH1–PTF4/TBCH0) . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.8 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.8.1
TIMB Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.8.2
TIMB Counter Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.8.3
TIMB Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.8.4
TIMB Channel Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.8.5
TIMB Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
203
203
203
205
205
206
206
207
207
208
208
209
210
210
210
210
210
211
211
211
211
211
213
214
214
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Chapter 20
Modulo Timer (TIM)
20.1
20.2
20.3
20.4
20.5
20.5.1
20.5.2
20.6
20.7
20.7.1
20.7.2
20.7.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIM Counter Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIM during Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
219
219
219
220
220
220
221
221
221
221
223
224
Chapter 21
Analog-to-Digital Converter (ADC-8)
21.1
21.2
21.3
21.3.1
21.3.2
21.3.3
21.3.4
21.3.5
21.4
21.5
21.5.1
21.5.2
21.6
21.6.1
21.6.2
21.6.3
21.7
21.7.1
21.7.2
21.7.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Analog Power Pin (VDDAREF)/ADC Voltage Reference Pin (VREFH) . . . . . . . . . . . . .
ADC Analog Ground Pin (AVSS)/ADC Voltage Reference Low Pin (VREFL) . . . . . . . . . . .
ADC Voltage In (ADCVIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Input Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
225
225
225
225
226
226
227
227
227
227
227
227
228
228
228
228
228
228
230
230
Chapter 22
MC68HC08AZ32 Emulator Input/Output Ports
22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.2 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.2.1
Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.2.2
Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
233
235
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22.3
22.3.1
22.3.2
22.4
22.4.1
22.4.2
22.5
22.5.1
22.5.2
22.6
22.6.1
22.6.2
22.7
22.7.1
22.7.2
22.8
22.8.1
22.8.2
22.9
22.9.1
22.9.2
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Direction Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Direction Register C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Direction Register D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Direction Register E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port F Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Direction Register F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port G. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port G Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Direction Register G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port H Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Direction Register H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
237
237
237
239
239
239
241
241
241
243
243
244
245
245
246
247
247
248
249
249
250
Chapter 23
MSCAN Controller
23.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.3 External Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.4 Message Storage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.4.1
Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.4.2
Receive Structures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.4.3
Transmit Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.5 Identifier Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.6.1
Interrupt Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.6.2
Interrupt Vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.7 Protocol Violation Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.8.1
MSCAN08 Internal Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.8.2
CPU Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.8.3
CPU Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.8.4
Programmable Wakeup Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.9 Timer Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.10 Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.11 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.12 Programmer’s Model of Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.12.1
Message Buffer Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
251
251
252
252
252
253
255
255
258
258
259
259
260
260
261
261
261
261
261
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23.12.2
Identifier Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.12.3
Data Length Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.12.4
Data Segment Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.12.5
Transmit Buffer Priority Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.13 Programmer’s Model of Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.13.1
MSCAN08 Module Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.13.2
MSCAN08 Module Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.13.3
MSCAN08 Bus Timing Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.13.4
MSCAN08 Bus Timing Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.13.5
MSCAN08 Receiver Flag Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.13.6
MSCAN08 Receiver Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.13.7
MSCAN08 Transmitter Flag Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.13.8
MSCAN08 Transmitter Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.13.9
MSCAN08 Identifier Acceptance Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.13.10 MSCAN08 Receive Error Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.13.11 MSCAN08 Transmit Error Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.13.12 MSCAN08 Identifier Acceptance Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.13.13 MSCAN08 Identifier Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
266
267
267
267
268
270
271
272
273
274
275
276
277
277
278
278
279
280
Chapter 24
Keyboard Interrupt Module (KBD)
24.1
24.2
24.3
24.4
24.5
24.5.1
24.5.2
24.6
24.7
24.7.1
24.7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Keyboard Module during Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Keyboard Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Keyboard Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
281
281
281
283
284
284
284
284
284
284
285
Chapter 25
Timer Interface (TIM-6)
25.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25.3.1
TIMA Counter Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25.3.2
Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25.3.3
Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25.3.3.1
Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25.3.3.2
Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25.3.4
Pulse-Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25.3.4.1
Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25.3.4.2
Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25.3.4.3
PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
287
287
291
291
291
292
292
292
293
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25.4
25.5
25.5.1
25.5.2
25.6
25.7
25.7.1
25.7.2
25.8
25.8.1
25.8.2
25.8.3
25.8.4
25.8.5
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIMA during Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIMA Clock Pin (PTD6/ATD14/TCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIMA Channel I/O Pins (PTF3/TACH5–PTF0/TACH2 and PTE3/TACH1–PTE2/TACH0)
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIMA Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIMA Counter Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIMA Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIMA Channel Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIMA Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
296
296
296
297
297
297
297
297
298
298
300
300
301
304
Chapter 26
Analog-to-Digital Converter (ADC-15)
26.1
26.2
26.3
26.3.1
26.3.2
26.3.3
26.3.4
26.3.5
26.4
26.5
26.5.1
26.5.2
26.6
26.6.1
26.6.2
26.6.3
26.7
26.7.1
26.7.2
26.7.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Analog Power Pin (VDDAREF)/ADC Voltage Reference Pin (VREFH) . . . . . . . . . . . . .
ADC Analog Ground Pin (VSSA)/ADC Voltage Reference Low Pin (VREFL) . . . . . . . . . . .
ADC Voltage In (ADCVIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Input Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
307
307
307
307
308
308
309
309
309
309
309
309
310
310
310
310
310
310
312
313
Chapter 27
MC68HC08AS20 Emulator Input/Output Ports
27.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27.2 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27.2.1
Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27.2.2
Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27.3 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27.3.1
Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27.3.2
Data Direction Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
315
317
317
317
318
318
319
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27.4
27.4.1
27.4.2
27.5
27.5.1
27.5.2
27.6
27.6.1
27.6.2
27.7
27.7.1
27.7.2
Port C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Direction Register C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Direction Register D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Direction Register E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port F Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Direction Register F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
320
320
321
322
322
323
324
324
325
327
327
327
Chapter 28
Byte Data Link Controller-Digital (BDLC-D)
28.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.3.1
BDLC Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.3.1.1
Power Off Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.3.1.2
Reset Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.3.1.3
Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.3.1.4
BDLC Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.3.1.5
BDLC Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.3.1.6
Digital Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.3.1.7
Analog Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.4 BDLC MUX Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.4.1
Rx Digital Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.4.1.1
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.4.1.2
Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.4.2
J1850 Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.4.3
J1850 VPW Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.4.4
J1850 VPW Valid/Invalid Bits and Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.4.5
Message Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.5 BDLC Protocol Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.5.1
Protocol Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.5.2
Rx and Tx Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.5.3
Rx and Tx Shadow Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.5.4
Digital Loopback Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.5.5
State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.5.5.1
4X Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.5.5.2
Receiving a Message in Block Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.5.5.3
Transmitting a Message in Block Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.5.5.4
J1850 Bus Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.5.5.5
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
329
329
329
331
331
331
332
332
332
332
332
333
333
333
334
334
336
338
341
342
343
343
343
344
344
344
344
344
344
346
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Table of Contents
28.6 BDLC CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.6.1
BDLC Analog and Round-Trip Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.6.2
BDLC Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.6.3
BDLC Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.6.4
BDLC State Vector Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.6.5
BDLC Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.7.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.7.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
346
347
348
349
354
355
356
356
356
Chapter 29
Electrical Specifications
29.1
29.2
29.3
29.4
29.5
29.6
29.7
29.8
29.9
29.10
29.11
29.12
29.13
29.14
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.0-Volt DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.0 Vdc ± 10% Serial Peripheral Interface (SPI) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CGM Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CGM Component Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CGM Acquisition/Lock Time Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BDLC Transmitter VPW Symbol Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BDLC Receiver VPW Symbol Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
359
360
360
361
362
362
363
366
366
367
367
368
368
369
Chapter 30
Mechanical Data
30.1
30.2
30.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
52-Pin Plastic Leaded Chip Carrier Package (Case 778) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
64-Pin Quad Flat Pack (QFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
Chapter 31
Ordering Information
31.1
31.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
MC68HC908AT32 Data Sheet, Rev. 3.1
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Chapter 1
General Description
1.1 Introduction
The MC68HC908AT32 is a member of the low-cost, high-performance M68HC08 Family of 8-bit
microcontroller units (MCUs). The M68HC08 Family is based on the customer-specified integrated circuit
(CSIC) design strategy. All MCUs in the family use the enhanced M68HC08 central processor unit
(CPU08) and are available with a variety of modules, memory sizes and types, and package types.
This part is designed to emulate two separate automotive parts: the MC68HC08AZ32 and the
MC68HC08AS20. This document demonstrates the unique qualities of both parts. In the case of
similarities, these are explained in the beginning sections of the specification.
1.2 Features
Refer to Table 1-1 for an encapsulated feature list comparison between the MC68HC08AZ32 and
MC68HC08AS20.
Table 1-1. Feature Comparisons (Sheet 1 of 3)
MC68HC08AZ32
64-Pin Emulator
Features
MC68HC08AS20
52-Pin Emulator
8-bit 8-channel analog-to-digital converter (ADC-8)
8-bit 15-channel analog-to-digital converter (ADC-15)
J1850 byte data link controller-digital (BDLC)
Break module (BRK)
Controller area network (CAN)
512 bytes electrically erasable programmable read-only memory
(EEPROM)
32-K FLASH
20-K FLASH
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
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General Description
Table 1-1. Feature Comparisons (Sheet 2 of 3)
Features
MC68HC08AZ32
64-Pin Emulator
MC68HC08AS20
52-Pin Emulator
5-bit keyboard interrupt module (KBD)
Low-voltage inhibit (LVI)
1-K random-access memory (RAM)
640 bytes RAM
Monitor read-only memory (ROM)
Serial communications interface (SCI)
Serial peripheral interface (SPI)
2-channel timer (TIMB)
4-channel timer (TIMA-4)
6-channel timer (TIMA-6)
Periodic interrupt timer (TIM)
Port A (PTA)
Port B (PTB)
Port C (PTC)
(PTC5:PTC0)
(PTC4:PTC0)
(PTD7:PTD0)
(PTD6:PTD0)
Port D (PTD)
Port E (PTE)
MC68HC908AT32 Data Sheet, Rev. 3.1
22
Freescale Semiconductor
Features
Table 1-1. Feature Comparisons (Sheet 3 of 3)
MC68HC08AZ32
64-Pin Emulator
Features
MC68HC08AS20
52-Pin Emulator
Port F (PTF)
(PTF6:PTF0)
(PTF3:PTF0)
Port G (PTG)
Port H (PTH)
Features of the MC68HC908AT32 include:
• High-performance M68HC08 architecture
• Fully upward-compatible object code with M6805, M146805, and M68HC05 Families
• 8-MHz internal bus frequency
• 32 Kbytes of FLASH electrically erasable read-only memory (FLASH)
• FLASH data security(1)
• 512 bytes of on-chip electrically erasable programmable read-only memory with security option
(EEPROM)
• 1 Kbyte of on-chip random-access memory (RAM)
• Clock generator module (CGM)
• Serial peripheral interface module (SPI)
• Serial communications interface module (SCI)
• System protection features:
– Computer operating properly (COP) with optional reset
– Low-voltage detection with optional reset
– Illegal opcode detection with optional reset
– Illegal address detection with optional reset
• Low-power design (fully static with stop and wait modes)
• Master reset pin and power-on reset (POR)
Features of the CPU08 include:
• Enhanced HC05 programming model
• Extensive loop control functions
• 16 addressing modes (eight more than the HC05)
• 16-bit index register and stack pointer
• Memory-to-memory data transfers
• Fast 8 × 8 multiply instruction
• Fast 16/8 divide instruction
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for
unauthorized users.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
23
General Description
•
•
•
Binary-coded decimal (BCD) instructions
Optimization for controller applications
C language support
Features of the MC68HC08AZ32 emulator (64-pin QFP) not listed previously include:
• 16-bit, 4-channel timer interface module (TIMA-4)
• 16-bit, 2-channel timer interface module (TIMB)
• Periodic interrupt timer (PIT)
• 5-bit keyboard interrupt module (KBD)
• 8-bit, 8-channel analog-to-digital converter module (ADC-8)
• MSCAN (scalable CAN) controller implements CAN 2.0B protocol as defined in BOSCH
Specification September 1991
Features of the MC68HC08AS20 emulator (52-pin PLCC) not listed previously include:
• 8-bit, 15-channel analog-to-digital converter (ADC-15)
• 16-bit, 6-channel timer interface module (TIMA-6)
• SAE J1850 byte data link controller digital module (BDLC-D)
1.3 MCU Block Diagram
Figure 1-1 and Figure 1-2 show the structure of the MC68HC908AT32.
MC68HC908AT32 Data Sheet, Rev. 3.1
24
Freescale Semiconductor
DDRA
PTA
ANALOG-TO-DIGITAL
MODULE
PTB
ARITHMETIC/LOGIC
UNIT (ALU)
PTA7–PTA0
DDRB
CPU
REGISTERS
VREFH
PTB7/ATD7–PTB0/ATD0
PTC
Freescale Semiconductor
M68HC08 CPU
PTC5–PTC3
PTC2/MCLK
PTC1–PTC0
BREAK MODULE
USER FLASH — 32,768 BYTES
OSC1
OSC2
CGMXFC
CLOCK GENERATOR
MODULE
RST
SYSTEM INTEGRATION
MODULE
SERIAL PERIPHERAL
INTERFACE MODULE
IRQ MODULE
KEYBOARD INTERRUPT
MODULE
POWER-ON RESET
MODULE
PERIODIC INTERRUPT
TIMER MODULE
POWER
AVSS/VREFL
VDDAREF
DDRG
PTG
SERIAL COMMUNICATIONS
INTERFACE MODULE
PTH
VSS
VDD
VDDA
VSSA
PTD
TIMER B INTERFACE
MODULE
PTE
USER FLASH VECTOR SPACE — 48 BYTES
DDRE
TIMER A 4-CHANNEL
INTERFACE MODULE
PTF
MONITOR ROM — 224 BYTES
PTD7
PTD6/TACLK
PTD5
PTD4/TBCLK
PTD3–PTD0
DDRF
COMPUTER OPERATING
PROPERLY MODULE
DDRH
MC68HC908AT32 Data Sheet, Rev. 3.1
USER EEPROM — 512 BYTES
DDRD
LOW-VOLTAGE INHIBIT
MODULE
USER RAM — 1024 BYTES
IRQ
DDRC
CONTROL AND STATUS REGISTERS — 62 BYTES
PTE7/SPSCK
PTE6/MOSI
PTE5/MISO
PTE4/SS
PTE3/TACH1
PTE2/TACH0
PTE1/RxD
PTE0/TxD
PTF6
PTF5/TBCH1–PTF4/TBCH0
PTF3-PTF2
PTF1/TACH3
PTF0/TACH2
PTG2/KBD2–PTG0/KBD0
PTH1/KBD4–PTH0/KBD3
MSCAN MODULE
25
MCU Block Diagram
Figure 1-1. MCU Block Diagram for the MC68HC08AZ32 Emulator (64-Pin QFP)
CANRx
CANTx
DDRA
PTA
SERIAL COMMUNICATIONS
INTERFACE MODULE
RST
SYSTEM INTEGRATION
MODULE
SERIAL PERIPHERAL INTERFACE
MODULE
IRQ MODULE
BYTE DATA LINK CONTROLLER
Freescale Semiconductor
VSS
VDD
VDDAREF/ VDDA
VSSA/VREFL
PTB
CLOCK GENERATOR
MODULE
PTF3/TACH5
PTF2 /TACH4
PTF1/TACH3
PTF0/TACH2
DDRD
BDTxD
OSC1
OSC2
CGMXFC
POWER-ON RESET
MODULE
PTE7/SPSCK
PTE6/MOSI
PTE5/MISO
PTE4/SS
PTE3/TACH1
PTE2/TACH0
PTE1/RxD
PTE0/TxD
TIMER A 6 CHANNEL
INTERFACE MODULE
USER FLASH VECTOR SPACE — 36 BYTES
IRQ
DDRB
MONITOR ROM — 224 BYTES
COMPUTER OPERATING
PROPERLY MODULE
BDRxD
MC68HC908AT32 Data Sheet, Rev. 3.1
USER EEPROM — 512 BYTES
PTD6/ATD14/TACLK
PTD5/ATD13
PTD4/ATD12
PTD3/ATD11
PTD2/ATD10
PTD1/ATD9–PTD0/ATD8
LOW-VOLTAGE INHIBIT
MODULE
DDRE
USER RAM — 640 BYTES
PTC
USER FLASH — 20,480 BYTES
PTC5–PTC3
PTC2/MCLK
PTC1–PTC0
DDRC
BREAK MODULE
PTD
CONTROL AND STATUS REGISTERS — 62 BYTES
PTB7/ATD7–PTB0/ATD0
PTE
ANALOG-TO-DIGITAL
MODULE
PTF
ARITHMETIC/LOGIC
UNIT (ALU)
PTA7–PTA0
DDRF
CPU
REGISTERS
VREFH
POWER
Figure 1-2. MCU Block Diagram for the MC68HC08AS20 Emulator (52-Pin PLCC)
General Description
26
M68HC08 CPU
Pin Assignments
1.4 Pin Assignments
PTC2/MCLK
PTC1
PTC0
OSC1
OSC2
CGMXFC
VSSA
VDDA
VREFH
PTD7
PTD6/TACLK
PTD5
PTD4/ TBCLK
62
61
60
59
58
57
56
55
54
53
52
51
50
PTC4
1
49
PTH1/KBD4
PTC3
63
64
PTC5
Figure 1-3 shows the MC68HC08AZ32 emulator assignments.
48
PTH0/KBD3
CANRx
9
40
PTB6/ATD6
CANTx
10
39
PTB5/ATD5
PTF5/TBCH1
11
38
PTB4/ATD4
PTF6
12
37
PTB3/ATD3
PTE0/TxD
13
36
PTB2/ATD2
PTE1/RxD
14
35
PTB1/ATD1
PTE2/TACH0
15
34
PTB0/ATD0
33
PTA7
PTA6 32
16
PTE4/SS 17
PTE3/TACH1
31
PTB7/ATD7
PTA5
41
30
8
PTA4
PTF4/TBCH0
29
PTD0
PTA3
42
28
7
PTA2
PTF3
27
PTD1
PTA1
43
26
6
PTA0
PTF2
25
VDDAREF
PTG2/KBD2
44
24
5
PTG1/KBD1
PTF1/TACH3
23
AVSS /VREFL
PTG0/KBD0
45
22
4
VDD
PTF0/TACH2
21
PTD2
VSS
46
20
3
PTE7/SPSCK
RST
19
PTD3
PTE6/MOSI
47
18
2
PTE5/MISO
IRQ
Figure 1-3. MC68HC08AZ32 Emulator (64-Pin QFP)
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
27
General Description
PTD6/ATD14/TACLK
PTD5/ATD13
49
48
PTC4
PTD4/ATD12
VREFH
50
47
VDDA/VDDAREF
OSC2
2
51
OSC1
3
VSSA/VREFL
PTC0
4
52
PTC1
5
CGMXFC
PTC2/MCLK
6
1
PTC3
7
Figure 1-4 shows MC68HC08AS20 emulator assignments.
8
PTD3/ATD11
46
IRQ
9
45
PTD2/ATD10
RST
10
44
PTD1/ATD9
PTF0/TACH2
11
43
PTD0/ATD8
PTF1/TACH3
12
42
PTB7/ATD7
PTF2/TACH4
13
41
PTB6/ATD6
PTF3/TACH5
14
40
PTB5/ATD5
BDRxD
15
39
PTB4/ATD4
BDTxD
16
38
PTB3/ATD3
PTE0/TxD
17
37
PTB2/ATD2
PTE1/RxD
18
36
PTB1/ATD1
PTE2/TACH0
19
35
PTB0/ATD0
20
PTA7
25
26
27
28
29
30
31
32
33
VSS
VDD
PTA0
PTA1
PTA2
PTA3
PTA4
PTA5
PTA6
23
PTE6/MOSI
24
22
PTE5/MISO
PTE7/SPSCK
21
34
PTE4/SS
PTE3/TACH1
Figure 1-4. MC68HC08AS20 Emulator (52-Pin PLCC)
NOTE
The following pin descriptions are just a quick reference. For a more
detailed representation, see Chapter 22 MC68HC08AZ32 Emulator
Input/Output Ports and Chapter 27 MC68HC08AS20 Emulator
Input/Output Ports.
MC68HC908AT32 Data Sheet, Rev. 3.1
28
Freescale Semiconductor
Pin Assignments
1.4.1 Power Supply Pins (VDD and VSS)
VDD and VSS are the power supply and ground pins. The MCU operates from a single power supply.
Fast signal transitions on MCU pins place high, short-duration current demands on the power supply. To
prevent noise problems, take special care to provide power supply bypassing at the MCU as shown. Place
the C1 bypass capacitor as close to the MCU as possible. Use a high-frequency response ceramic
capacitor for C1. C2 is an optional bulk current bypass capacitor for use in applications that require the
port pins to source high current levels.
MCU
VDD
VSS
C1
0.1 µF
+
C2
VDD
Note: Component values shown represent typical applications.
Figure 1-5. Power Supply Bypassing
VSS is also the ground for the port output buffers and the ground return for the serial clock in the serial
peripheral interface module (SPI). See Chapter 17 Serial Peripheral Interface Module (SPI).
NOTE
VSS must be grounded for proper MCU operation.
1.4.2 Oscillator Pins (OSC1 and OSC2)
The OSC1 and OSC2 pins are the connections for the on-chip oscillator circuit. See Chapter 8 Clock
Generator Module (CGM).
1.4.3 External Reset Pin (RST)
A logic 0 on the RST pin forces the MCU to a known startup state. RST is bidirectional, allowing a reset
of the entire system. It is driven low when any internal reset source is asserted. See Chapter 7 System
Integration Module (SIM) for more information.
1.4.4 External Interrupt Pin (IRQ)
IRQ is an asynchronous external interrupt pin. See Chapter 15 External Interrupt (IRQ).
1.4.5 Analog Power Supply Pin (VDDA)
VDDA is the power supply pin for the analog portion of the chip. For the MC68HC08AZ32 emulator
protocol, this pin will supply the clock generator module (CGM). However, for the MC68HC08AS20
emulator protocol this pin will supply both the clock generator module and the analog-to-digital converter
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
29
General Description
(ADC). See Chapter 8 Clock Generator Module (CGM) and Chapter 26 Analog-to-Digital Converter
(ADC-15).
1.4.6 Analog Ground Pin (VSSA)
The VSSA analog ground pin is used only for the ground connections for the analog sections of the circuit
and should be decoupled as per the VSS digital ground pin. This will only supply the clock generator
module on the MC68HC08AZ32 emulator part. The analog sections consist of a clock generator module
(CGM) and an analog-to-digital converter (ADC) for the MC68HC08AS20 emulator part. See Chapter 8
Clock Generator Module (CGM) and Chapter 26 Analog-to-Digital Converter (ADC-15).
1.4.7 External Filter Capacitor Pin (CGMXFC)
CGMXFC is an external filter capacitor connection for the CGM. See Chapter 8 Clock Generator Module
(CGM).
1.4.8 Port A Input/Output (I/O) Pins (PTA7–PTA0)
PTA7–PTA0 are general-purpose bidirectional I/O port pins. See Chapter 22 MC68HC08AZ32 Emulator
Input/Output Ports or Chapter 27 MC68HC08AS20 Emulator Input/Output Ports depending on the
configuration.
1.4.9 Port B I/O Pins (PTB7/ATD7–PTB0/ATD0)
Port B is an 8-bit special function port that shares all eight pins with the analog-to-digital converter (ADC).
See Chapter 26 Analog-to-Digital Converter (ADC-15) and See Chapter 22 MC68HC08AZ32 Emulator
Input/Output Ports or Chapter 27 MC68HC08AS20 Emulator Input/Output Ports depending on the
configuration.
1.4.10 Port C I/O Pins (PTC5–PTC0)
PTC5–PTC3 and PTC1–PTC0 are general-purpose bidirectional I/O port pins. PTC2/MCLK is a special
function port that shares its pin with the system clock. See See Chapter 22 MC68HC08AZ32 Emulator
Input/Output Ports or Chapter 27 MC68HC08AS20 Emulator Input/Output Ports depending on the
configuration.
NOTE
PTC5 is available only in 64-pin packages.
1.4.11 Port D I/O Pins (PTD7/ATD15–PTD0/ATD8)
Port D is an 8-bit special-function port that shares all of its pins with the analog-to-digital converter module
(ADC-15), and one of its pins with the timer interface module (TIMA) if the part is configured as
MC68HC08AS20. If the part is configured as MC68HC08AZ32, then port D shares one of its pins with the
4-channel interface module (TIMA) and one of its pins with the 2-channel interface module (TIMB).
See Chapter 25 Timer Interface (TIM-6) and Chapter 26 Analog-to-Digital Converter (ADC-15) or Chapter
18 Timer Interface (TIMA-4), Chapter 19 Timer Interface (TIMB), and Chapter 21 Analog-to-Digital
Converter (ADC-8) depending on the configuration.
MC68HC908AT32 Data Sheet, Rev. 3.1
30
Freescale Semiconductor
Pin Assignments
1.4.12 Port E I/O Pins (PTE7/SPSCK–PTE0/TxD)
Port E is an 8-bit special function port that shares two of its pins with the timer interface module (TIMA),
four of its pins with the serial peripheral interface module (SPI), and two of its pins with the serial
communication interface module (SCI). See Chapter 16 Serial Communications Interface Module (SCI),
Chapter 17 Serial Peripheral Interface Module (SPI), Chapter 18 Timer Interface (TIMA-4) or Chapter 25
Timer Interface (TIM-6), and Chapter 22 MC68HC08AZ32 Emulator Input/Output Ports or Chapter 27
MC68HC08AS20 Emulator Input/Output Ports depending on the configuration.
1.4.13 Port F I/O Pins (PTF6–PTF0/TACH2)
Port F is a 7-bit special function port that shares its pins with the timer interface module (TIMB) if the part
is configured as MC68HC08AZ32 emulator protocol. If the part is configured as MC68HC08AS20
emulator protocol, four of its pins will be shared with the timer interface module (TIMA-6). See Chapter
18 Timer Interface (TIMA-4) or Chapter 25 Timer Interface (TIM-6), Chapter 19 Timer Interface (TIMB),
and Chapter 22 MC68HC08AZ32 Emulator Input/Output Ports or Chapter 27 MC68HC08AS20 Emulator
Input/Output Ports depending on the configuration.
NOTE
PTF4–PTF6 is available only in 64-pin packages.
1.4.14 Port G I/O Pins (PTG2/KBD2–PTG0/KBD0)
NOTE
This port is available only in the MC68HC08AZ32 emulator.
Port G is a 3-bit special function port that shares all of its pins with the keyboard interrupt module (KBD)
only if the part is configured as MC68HC08AZ32 emulator (64-pin QFP) protocol. If port G is available
and MC68HC08AS20 emulation is selected, this port will be general I/O only. See Chapter 24 Keyboard
Interrupt Module (KBD) and Chapter 22 MC68HC08AZ32 Emulator Input/Output Ports.
1.4.15 Port H I/O Pins (PTH1/KBD4–PTH0/KBD3)
NOTE
This port is available only in the MC68HC08AZ32 emulator.
Port H is a 2-bit special-function port that shares all of its pins with the keyboard interrupt module (KBD)
only if the part is configured as MC68HC08AZ32 emulator protocol. If port H is available and
MC68HC08AS20 emulation is selected, this port will be general I/O only. See Chapter 24 Keyboard
Interrupt Module (KBD) and Chapter 22 MC68HC08AZ32 Emulator Input/Output Ports.
1.4.16 CAN Transmit Pin (CANTx)/BDLC Transmit Pin (BDTxD)
If the part is configured as MC68HC08AZ32 emulator protocol, this pin is the digital output from the CAN
module (CANTx). Otherwise, if the part is configured as MC68HC08AS20 emulator protocol this pin is the
serial digital output from the BDLC module (BDTxD). See Chapter 23 MSCAN Controller or Chapter 28
Byte Data Link Controller-Digital (BDLC-D).
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
31
General Description
1.4.17 CAN Receive Pin (CANRx)/BDLC Receive Pin (BDRxD)
If the part is configured as MC68HC08AZ32 emulator protocol, this pin is the digital input to the CAN
module (CANRx). Otherwise, if the part is configured as MC68HC08AS20 emulator protocol, this pin is
the serial digital input to the BDLC module (BDRxD). See Chapter 23 MSCAN Controller or Chapter 28
Byte Data Link Controller-Digital (BDLC-D).
Table 1-2. External Pins Summary
Pin Name
Function
Driver Type
Hysteresis
Reset
State
PTA7–PTA0
General-purpose I/O
Dual state
No
Input Hi-Z
PTB7/ATD7–PTB0/ATD0
General-purpose I/O
ADC channel
Dual state
No
Input Hi-Z
PTC5–PTC0 ** PTC5 available
in 64-pin package only
General-purpose I/O
Dual state
No
Input Hi-Z
PTD7/ATD15 ** ADC channel for
MC68HC08AS20 emulation only
General-purpose I/O/
ADC channel
Dual state
No
Input Hi-Z
PTD6/ATD14/TACLK ** ADC channel
for MC68HC08AS20 emulation only
General-purpose I/O
ADC channel/timer
external input clock
Dual state
No
Input Hi-Z
PTD5/ATD13 ** ADC channel
for MC68HC08AS20 emulation only
General-purpose I/O
ADC channel
Dual state
No
Input Hi-Z
PTD4/ATD12/TBCLK ** ADC channel
for MC68HC08AS20 emulation only
TBCLK for MC68HC08AZ32
emulation only
General-purpose I/O
ADC channel/timer
external input clock
Dual state
No
Input Hi-Z
PTD3/ATD11–PTD0/ATD8 ** ADC channels for
MC68HC08AS20 emulation only
General-purpose I/O
ADC channel
Dual state
No
Input Hi-Z
PTE7/SPSCK
General-purpose I/O
SPI clock
Dual state
open drain
Yes
Input Hi-Z
PTE6/MOSI
General-purpose I/O
SPI data path
Dual state
open drain
Yes
Input Hi-Z
PTE5/MISO
General-purpose I/O
SPI data path
Dual state
open drain
Yes
Input Hi-Z
PTE4/SS
General-purpose I/O
SPI slave select
Dual state
Yes
Input Hi-Z
PTE3/TACH1
General-purpose I/O
Timer channel 1
Dual state
Yes
Input Hi-Z
PTE2/TACH0
General-purpose I/O
Timer channel 0
Dual state
Yes
Input Hi-Z
PTE1/RxD
General-purpose I/O
SCI receive data
Dual state
Yes
Input Hi-Z
PTE0/TxD
General-purpose I/O
SCI transmit data
Dual state
Yes
Input Hi-Z
PTF6 **available in 64-pin package only
General-purpose I/O
Dual state
No
Input Hi-Z
MC68HC908AT32 Data Sheet, Rev. 3.1
32
Freescale Semiconductor
Pin Assignments
Table 1-2. External Pins Summary (Continued)
Pin Name
Function
Driver Type
Hysteresis
Reset
State
PTF5/TBCH1–PTF4/TBCH0 ** available in
MC68HC08AZ32 emulation only
General-purpose
I/O/timer B channel
Dual state
Yes
Input Hi-Z
PTF3/TACH5 ** timer channel available only in
MC68HC08AS20 emulation
General-purpose I/O
timer A channel 5
Dual state
Yes
Input Hi-Z
PTF2/TACH4** TACH4 available
only in MC68HC08AS20 emulation
General-purpose I/O
timer A channel 4
Dual state
Yes
Input Hi-Z
PTF1/TACH3
General-purpose I/O
timer A channel 3
Dual state
Yes
Input Hi-Z
PTF0/TACH2
General-purpose I/O
timer A channel 2
Dual state
Yes
Input Hi-Z
PTG2/KBD2–PTG0/KBD0** keyboard pins
available only in MC68HC08AZ32 emulation
General-purpose I/O/
keyboard wakeup pin
Dual state
Yes
Input Hi-Z
PTH1/KBD4 –PTH0/KBD3 **available only in
MC68HC08AZ32 emulation
General-purpose I/O/
keyboard wakeup pin
Dual state
Yes
Input Hi-Z
VDD
Chip power supply
N/A
N/A
N/A
VSS
Chip ground
N/A
N/A
N/A
VDDA/VDDAREF ** VDDAREF available
in MC68HC08AS20 emulation only
Analog power supply
N/A
N/A
N/A
VSSA/VREFL ** VREFL available only
in MC68HC08AS20 emulation
Analog ground/ ADC
reference voltage
N/A
N/A
N/A
AVDD/VDDAREF ** available only
in MC68HC08AZ32 emulation
ADC power supply/ ADC
reference voltage
N/A
N/A
N/A
AVSS/VREFL ** available only
in MC68HC08AZ32 emulation
ADC ground/ADC
reference voltage
N/A
N/A
N/A
VREFH
A/D reference voltage
N/A
N/A
N/A
OSC1
External clock in
N/A
N/A
Input Hi-Z
OSC2
External clock out
N/A
N/A
Output
CGMXFC
PLL loop filter cap
N/A
N/A
N/A
IRQ
External interrupt request
N/A
N/A
Input Hi-Z
RST
Reset
N/A
N/A
Output low
CANRx
CAN serial input
N/A
Yes
Input Hi-Z
CANTx
CAN serial output
Output
No
Output
BDRxD
BDLC-D serial input
N/A
No
Input Hi-Z
BDTxD
BDLC-D serial output
Output
No
Output low
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
33
General Description
Table 1-3. Clock Source Summary
Module
Clock Source
ADC
CGMXCLK or bus clock
BDLC
CGMXCLK
CAN
CGMXCLK or CGMOUT
COP
CGMXCLK
CPU
Bus clock
EEPROM
CGMXCLK or bus clock
SPI
Bus clock/SPSCK
SCI
CGMXCLK
TIMA-4
Bus clock or PTD6/TACLK
TIMA-6
Bus clock or PTD6/ATD14/TACLK
TIMB
Bus clock or PTD4/TBCLK
PIT
Bus clock
SIM
CGMOUT and CGMXCLK
IRQ
Bus clock
BRK
Bus clock
LVI
Bus clock
CGM
OSC1 and OSC2
MC68HC908AT32 Data Sheet, Rev. 3.1
34
Freescale Semiconductor
Chapter 2
Memory Map
2.1 Introduction
The CPU08 can address 64 Kbytes of memory space. The memory map, shown in Figure 2-1, includes:
• 32 Kbytes of FLASH on-chip electrically erasable programmable read-only memory (EEPROM) for
the MC68HC08AZ32 emulator (64-pin QFP) or the MC68HC08AS20 emulator (52-pin PLCC) with
memory extentsion
• 20 Kbytes of FLASH EEPROM for the MC68HC08AS20 emulator (52-pin PLCC)
• 1024 bytes of random-access memory (RAM) for the MC68HC08AZ32 emulator (64-pin QFP) or
the MC68HC08AS20 emulator (52-pin PLCC) with memory extentsion
• 640 bytes of RAM for the MC68HC08AS20 emulator (52-pin PLCC)
• 512 bytes of EEPROM with security option
• 48 bytes of user-defined vectors for the MC68HC08AZ32 emulator (64-pin QFP)
• 36 bytes of user-defined vectors for the MC68HC08AS20 emulator (52-pin PLCC)
• 224 bytes of monitor read-only memory (ROM)
• 128 bytes of CAN control and message buffers
NOTE
The memory extension bit in the CONFIG-2 register must be set to enable
1 K of RAM memory space and 32 K of FLASH memory space in the
MC68HC08AS20 emulator configuration. (See Chapter 10 Configuration
Register (CONFIG-2).)
The following definitions apply to the memory map (Figure 2-1) representation of reserved and
unimplemented locations.
• Reserved — Accessing a reserved location can have unpredictable effects on MCU operation.
• Unimplemented — Accessing an unimplemented location causes an illegal address reset if illegal
address resets are enabled.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
35
Memory Map
MC68HC08AZ32 Emulator
(64-Pin)
MC68HC08AS20 Emulator
(52-Pin)
$0000
$0000
↓
↓
I/O REGISTERS (64 BYTES)
$003F
$003F
$0040
$0040
↓
I/O REGISTERS, 16 BYTES
TIMB AND PIT REGISTERS
UNIMPLEMENTED, 16 BYTES
↓
$004F
$004F
$0050
$0050
↓
RAM, 640 BYTES
RAM, 1024 BYTES
Ø
$02CF
$044F
$02D0
$0450
↓
UNIMPLEMENTED, 176 BYTES
$04FF
$0500
↓
UNIMPLEMENTED, 1328 BYTES
CAN CONTROL AND MESSAGE
BUFFERS, 128 BYTES
↓
$057F
$0580
↓
UNIMPLEMENTED, 640 BYTES
$07FF
$07FF
$0800
$0800
↓
↓
EEPROM, 512 BYTES
$09FF
$09FF
$0A00
$0A00
↓
UNIMPLEMENTED, 30,208 BYTES
UNIMPLEMENTED, 41,984 BYTES
$7FFF
$8000
↓
↓
$ADFF
$AE00
FLASH, 32,256 BYTES
FLASH, 20,480 BYTES
$FDFF
↓
$FDFF
$FE00
SIM BREAK STATUS REGISTER (SBSR)
$FE00
$FE01
SIM RESET STATUS REGISTER (SRSR)
$FE01
$FE02
RESERVED
$FE02
$FE03
SIM BREAK FLAG CONTROL REGISTER (SBFCR)
$FE03
$FE04
RESERVED
$FE04
Figure 2-1. Memory Map
MC68HC908AT32 Data Sheet, Rev. 3.1
36
Freescale Semiconductor
Introduction
MC68HC08AZ32 Emulator
(64-Pin)
MC68HC08AS20 Emulator
(52-Pin)
$FE05
RESERVED
$FE05
$FE06
RESERVED
$FE06
$FE07
RESERVED
$FE07
$FE08
RESERVED
$FE08
$FE09
CONFIGURATION WRITE-ONCE REGISTER (CONFIG-2)
$FE09
$FE0A
RESERVED
$FE0A
$FE0B
FLASH CONTROL REGISTER (FLCR)
$FE0B
$FE0C
BREAK ADDRESS REGISTER HIGH (BRKH)
$FE0C
$FE0D
BREAK ADDRESS REGISTER LOW (BRKL)
$FE0D
$FE0E
BREAK STATUS AND CONTROL REGISTER (BRKSCR)
$FE0E
$FE0F
LVI STATUS REGISTER (LVISR)
$FE0F
$FE10
$FE10
↓
↓
UNIMPLEMENTED, 12 BYTES
$FE1B
$FE1B
$FE1C
EEPROM NON-VOLATILE REGISTER (EENVR)
$FE1C
$FE1D
EEPROM CONTROL REGISTER (EECR)
$FE1D
$FE1E
RESERVED
$FE1E
$FE1F
EEPROM ARRAY CONFIGURATION (EEACR)
$FE1F
$FE20
$FE20
↓
↓
MONITOR ROM, 224 BYTES
$FEFF
$FEFF
$FF00
↓
$FF7F
UNIMPLEMENTED, 128 BYTES
$FF00
↓
$FF7F
$FF80
FLASH BLOCK PROTECT REGISTER (FLBPR)
$FF80
$FF81
$FF81
↓
↓
RESERVED, 79 BYTES
$FFCF
$FFCF
$FFD0
$FFD0
RESERVED, 12 BYTES
↓
↓
$FFDB
VECTORS, 48 BYTES
$FFDC
VECTORS, 36 BYTES
$FFFF
↓
$FFFF
Figure 2-1. Memory Map (Continued)
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
37
Memory Map
2.2 Input/Output (I/O) Section
Addresses $0000–$003F, shown in Figure 2-2, contain most of the control, status, and data registers.
Additional I/O registers have these addresses:
• $FE00 (SIM break status register, SBSR)
• $FE01 (SIM reset status register, SRSR)
• $FE03 (SIM break flag control register, SBFCR)
• $FE09 (configuration write-once register, CONFIG-2)
• $FE0B (FLASH control register, FLCR)
• $FE0C and $FE0D (break address registers, BRKH and BRKL)
• $FE0E (break status and control register, BRKSCR)
• $FE0F (LVI status register, LVISR)
• $FE1C (EEPROM non-volatile register, EENVR)
• $FE1D (EEPROM control register, EECR)
• $FE1F (EEPROM array configuration register, EEACR)
• $FF80 (FLASH block protect register, FLBPR)
• $FFFF (COP control register, COPCTL)
Table 2-1 is a list of vector locations.
In Table 2-1, all MC68HC08AZ32 emulator specific register bits will be in bold face type. All
MC68HC08AS20 emulator specific registers will be in italic face type. Those in regular type are common
to both parts.
Addr.
$0000
$0001
Register Name
Port A Data Register Read:
(PTA) Write:
See page 235. Reset:
Port B Data Register Read:
(PTB) Write:
See page 237. Reset:
$0002
Port C Data Register Read:
(PTC) Write:
See page 239. Reset:
$0003
Port D Data Register Read:
(PTD) Write:
See page 241. Reset:
$0004
Data Direction Register A Read:
(DDRA) Write:
See page 235. Reset:
Bit 7
6
5
4
3
2
1
Bit 0
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
PTB2
PTB1
PTB0
PTC2
PTC1
PTC0
PTD2
PTD1
PTD0
Unaffected by reset
PTB7
PTB6
PTB5
PTB4
PTB3
Unaffected by reset
0
0
R
R
PTC5
PTC4
PTC3
Unaffected by reset
PTD7
PTD6
PTD5
PTD4
PTD3
Unaffected by reset
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
0
0
0
0
0
0
0
0
Italic Type = MC68HC08AS20 Specific
Boldface Type = MC68HC08AZ32 Specific
U = Unaffected
= Unimplemented
R
= Reserved
X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 9)
MC68HC908AT32 Data Sheet, Rev. 3.1
38
Freescale Semiconductor
Input/Output (I/O) Section
Addr.
$0005
$0006
$0007
Register Name
Data Direction Register B Read:
(DDRB) Write:
See page 237. Reset:
Bit 7
6
5
4
3
2
1
Bit 0
DDRB7
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
0
0
0
0
0
0
0
0
DDRC5
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
0
0
0
0
0
0
0
DDRD6
DDRD5
DDRD4
DDRD3
DDR2
DDRD1
DDRD0
0
0
0
0
0
0
0
PTE6
PTE5
PTE4
PTE3
PTE2
PTE1
PTE0
PTF2
PTF1
PTF0
PTG2
PTG1
PTG0
PTH1
PTH0
Data Direction Register C Read: MCLKEN
(DDRC) Write:
See page 239. Reset:
0
Data Direction Register D Read: DDRD7
(DDRD) Write:
See page 241. Reset:
0
0
R
$0008
Port E Data Register Read:
(PTE) Write:
See page 243. Reset:
$0009
Port F Data Register Read:
(PTF) Write:
See page 245. Reset:
R
Port G Data Register Read:
(PTG) Write:
See page 247. Reset:
0
0
0
0
0
R
R
R
R
R
$000A
$000B
Port H Data Register Read:
(PTH) Write:
See page 249. Reset:
PTE7
Unaffected by reset
0
PTF6
PTF5
PTF4
PTF3
Unaffected by reset
Unaffected by reset
0
0
0
0
0
0
R
R
R
R
R
R
Unaffected by reset
$000C
Data Direction Register E Read:
(DDRE) Write:
See page 244. Reset:
$000D
Data Direction Register F Read:
(DDRF) Write:
See page 246. Reset:
R
Data Direction Register G Read:
(DDRG) Write:
See page 248. Reset:
0
0
0
0
0
R
R
R
R
R
0
0
0
0
0
0
0
R
R
0
$000E
$000F
$0010
Data Direction Register H Read:
(DDRH) Write:
See page 250. Reset:
SPI Control Register Read:
(SPCR) Write:
See page 178. Reset:
DDRE7
DDRE6
DDRE5
DDRE4
DDRE3
DDRE2
DDRE1
DDRE0
0
0
0
0
0
0
0
0
DDRF6
DDRF5
DDRF4
DDRF3
DDRF2
DDRF1
DDRF0
0
0
0
0
0
0
0
DDRG2
DDRG1
DDRG0
0
0
0
0
0
0
0
R
R
R
R
DDRH1
DDRH0
0
0
0
0
0
0
0
SPRIE
R
SPMSTR
CPOL
CPHA
SPWOM
SPE
SPTIE
0
0
1
0
1
0
0
0
0
0
Italic Type = MC68HC08AS20 Specific
Boldface Type = MC68HC08AZ32 Specific
U = Unaffected
= Unimplemented
R
= Reserved
X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 9)
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
39
Memory Map
Addr.
$0011
$0012
$0013
Register Name
Bit 7
SPI Status and Control Read:
Register (SPSCR) Write:
See page 180. Reset:
SPI Data Register Read:
(SPDR) Write:
See page 182. Reset:
SPRF
R
6
ERRIE
5
4
3
OVRF
MODF
SPTE
R
R
R
2
1
Bit 0
MODFEN
SPR1
SPR0
0
0
0
0
1
0
0
0
R7
R6
R5
R4
R3
R2
R1
R0
T7
T6
T5
T4
T3
T2
T1
T0
Unaffected by reset
SCI Control Register 1 Read: LOOPS
(SCC1) Write:
See page 152. Reset:
0
ENSCI
TXINV
M
WAKE
ILTY
PEN
PTY
0
0
0
0
0
0
0
SCTIE
TCIE
SCRIE
ILIE
TE
RE
RWU
SBK
0
0
0
0
0
0
0
0
T8
R
R
ORIE
NEIE
FEIE
PEIE
$0014
SCI Control Register 2 Read:
(SCC2) Write:
See page 154. Reset:
R8
$0015
SCI Control Register 3 Read:
(SCC3) Write:
See page 156. Reset:
U
U
0
0
0
0
0
0
SCI Status Register 1 Read:
(SCS1) Write:
See page 157. Reset:
SCTE
TC
SCRF
IDLE
OR
NF
FE
PE
1
1
0
0
0
0
0
0
BKF
RPF
$0016
$0017
SCI Status Register 2 Read:
(SCS2) Write:
See page 159. Reset:
$0018
SCI Data Register Read:
(SCDR) Write:
See page 160. Reset:
$0019
SCI Baud Rate Register Read:
(SCBR) Write:
See page 160. Reset:
$001A
$001B
$001C
IRQ Status and Control Read:
Register (ISCR) Write:
See page 137. Reset:
Keyboard Status and Control Read:
Register (KBSCR) Write:
See page 285. Reset:
PLL Control Register Read:
(PCTL) Write:
See page 101. Reset:
0
0
0
0
0
0
0
0
R7
R6
R5
R4
R3
R2
R1
R0
T7
T6
T5
T4
T3
T2
T1
T0
Unaffected by reset
0
0
SCP1
SCP0
R
SCR2
SCR1
SCR0
0
0
0
0
0
0
IMASK1
MODE1
0
0
IMASKK
MODEK
0
0
0
0
IRQF1
0
R
R
R
R
R
ACK1
0
0
0
0
0
0
0
0
0
0
KEYF
0
ACKK
0
PLLIE
0
0
PLLF
0
0
0
PLLON
BCS
1
0
0
0
0
0
1
1
1
1
1
1
1
1
Italic Type = MC68HC08AS20 Specific
Boldface Type = MC68HC08AZ32 Specific
U = Unaffected
= Unimplemented
R
= Reserved
X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 9)
MC68HC908AT32 Data Sheet, Rev. 3.1
40
Freescale Semiconductor
Input/Output (I/O) Section
Addr.
$001D
$001E
$001F
Register Name
Bit 7
PLL Bandwidth Control Read:
Register Write:
(PBWC)
See page 103. Reset:
PLL Programming Register Read:
(PPG) Write:
See page 104. Reset:
AUTO
6
LOCK
5
4
ACQ
XLD
3
2
1
Bit 0
0
0
0
0
0
0
0
0
0
0
0
0
MUL7
MUL6
MUL5
MUL4
VRS7
VRS6
VRS5
VRS4
0
1
1
0
0
1
1
0
R
LVIRST
LVIPWR
SSREC
COPRS
STOP
COPD
1
1
1
0
0
0
0
TOIE
TSTOP
0
0
TRST
R
PS2
PS1
PS0
0
0
0
0
0
KBIE4
KBIE3
KBIE2
KBIE1
KBIE0
Configuration Write-Once Read: LVISTOP
Register (CONFIG-1) Write:
See page 109. Reset:
0
Timer A Status and Control Register Read:
(TASC) Write:
See page 195. Reset:
TOF
0
0
1
0
0
0
$0021
Keyboard Interrupt Enable Register Read:
(KBIER) Write:
See page 285. Reset:
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
$0022
Timer A Counter Register Read:
High (TACNTH) Write:
See page 197. Reset:
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
Timer A Counter Register Read:
Low (TACNTL) Write:
See page 197. Reset:
Bit 7
6
5
4
3
2
1
Bit 0
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
1
1
1
1
1
1
1
1
Bit 7
6
5
4
3
2
1
Bit 0
1
1
1
1
1
1
1
1
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
$0020
$0023
$0024
$0025
Timer A Modulo Register Read:
High (TAMODH) Write:
See page 197. Reset:
Timer A Modulo Register Read:
Low (TAMODL) Write:
See page 197. Reset:
Timer A Channel 0 Status and Control Read:
$0026
Register (TASC0) Write:
See 198 and 301. Reset:
$0027
$0028
Timer A Channel 0 Register Read:
High (TACH0H) Write:
See 201 and 304. Reset:
Timer A Channel 0 Register Read:
Low (TACH0L) Write:
See 201 and 304. Reset:
0
CH0F
0
Indeterminate after reset
Bit 7
6
5
4
3
Indeterminate after reset
Italic Type = MC68HC08AS20 Specific
Boldface Type = MC68HC08AZ32 Specific
U = Unaffected
= Unimplemented
R
= Reserved
X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 9)
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
41
Memory Map
Addr.
Register Name
Bit 7
Timer A Channel 1 Status and Control Read:
$0029
Register (TASC1) Write:
See 198 and 301. Reset:
CH1F
$002A
$002B
Timer A Channel 1 Register Read:
High (TACH1H) Write:
See 201 and 304. Reset:
Timer A Channel 1 Register Read:
Low (TACH1L) Write:
See 201 and 304. Reset:
Timer A Channel 2 Status and Control Read:
$002C
Register (TASC2) Write:
See 198 and 301. Reset:
$002D
$002E
Timer A Channel 2 Register Read:
High (TACH2H) Write:
See 201 and 304. Reset:
Timer A Channel 2 Register Read:
Low (TACH2L) Write:
See 201 and 304. Reset:
Timer A Channel 3 Status and Control Read:
$002F
Register (TASC3) Write:
See 198 and 301. Reset:
$0030
Timer A Channel 3 Register Read:
High (TACH3H) Write:
See 201 and 304. Reset:
$0031
Timer A Channel 3 Register Read:
Low (TACH3L) Write:
See 201 and 304. Reset:
$0032
$0033
$0034
Timer A Channel 4 Status and Control Read:
Register (TASC4) Write:
See page 301. Reset:
Timer A Channel 4 Register High Read:
(TACH4H) Write:
See page 304. Reset:
Timer A Channel 4 Register Low Read:
(TACH4L) Write:
See page 304. Reset:
0
6
CH1IE
5
0
R
4
3
2
1
Bit 0
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
Indeterminate after reset
Bit 7
6
5
4
3
Indeterminate after reset
CH2F
CH2IE
MS2B
MS2A
ELS2B
ELS2A
TOV2
CH2MAX
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
0
Indeterminate after reset
Bit 7
6
5
4
3
Indeterminate after reset
CH3F
0
CH3IE
0
R
MS3A
ELS3B
ELS3A
TOV3
CH3MAX
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
Indeterminate after reset
Bit 7
6
5
4
3
Indeterminate after reset
CH4F
CH4IE
MS4B
MS4A
ELS4B
ELS4A
TOV4
CH4MAX
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
0
Indeterminate after reset
Bit 7
6
5
4
3
Indeterminate after reset
Italic Type = MC68HC08AS20 Specific
Boldface Type = MC68HC08AZ32 Specific
U = Unaffected
= Unimplemented
R
= Reserved
X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 9)
MC68HC908AT32 Data Sheet, Rev. 3.1
42
Freescale Semiconductor
Input/Output (I/O) Section
Addr.
Register Name
Bit 7
Timer A Channel 5 Status and Control Read:
$0035
Register (TASC5) Write:
See page 301. Reset:
CH5F
$0036
$0037
$0038
Timer A Channel 5 Register Read:
High (TACH5H) Write:
See page 304. Reset:
Timer A Channel 5 Register Read:
Low (TACH5L) Write:
See page 304. Reset:
Analog-to-Digital Status and Control Read:
Register (ADSCR) Write:
See page 228. Reset:
Read:
$0039
$003A
$003B
Analog-to-Digital Data Register (ADR)
Write:
See page 230.
Reset:
Analog-to-Digital Input Clock Register Read:
(ADCLK) Write:
See page 230. Reset:
BDLC Analog and Roundtrip Read:
Delay Register (BARD) Write:
See page 347. Reset:
0
$0040
Timer B Status and Control Read:
Register (TBSCR) Write:
See page 212. Reset:
2
1
Bit 0
MS5A
ELS5B
ELS5A
TOV5
CH5MAX
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
ADCH2
ADCH1
ADCH0
Indeterminate after reset
Bit 7
6
5
4
3
Indeterminate after reset
COCO
R
AIEN
ADCO
ADCH4
ADCH3
0
0
0
1
1
1
1
1
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
R
R
R
R
R
R
R
R
Indeterminate after reset
0
0
0
0
R
R
R
R
0
0
0
0
BO3
BO2
BO1
BO0
0
1
1
1
0
0
R
R
IE
WCM
0
0
0
0
0
RX4XE
NBFS
TEOD
TSIFR
TMIFR1
TMIFR0
1
0
0
0
0
0
0
ADIV2
ADIV1
ADIV0
ADICLK
0
0
0
0
ATE
RXPOL
0
0
1
1
0
0
IMSG
CLKS
R1
R0
1
1
1
DLOOP
$003D
BDLC Data Register Read:
(BDR) Write:
See page 355. Reset:
3
0
BDLC Control Register 2 Read: ALOOP
(BCR2) Write:
See page 349. Reset:
1
$003F
R
4
0
$003C
Read:
BDLC State Vecto Register (BSVR)
Write:
See page 354.
Reset:
CH5IE
5
0
0
BDLC Control Register 1 Read:
(BCR1) Write:
See page 348. Reset:
$003E
6
0
0
I3
I2
I1
I0
0
0
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
BD7
BD6
BD5
BD4
BD3
BD2
BD1
BD0
PS2
PS1
PS0
0
0
Indeterminate after reset
TOF
0
0
TOIE
TSTOP
0
1
0
0
TRST
R
0
0
0
Italic Type = MC68HC08AS20 Specific
Boldface Type = MC68HC08AZ32 Specific
U = Unaffected
= Unimplemented
R
= Reserved
X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 9)
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
43
Memory Map
Addr.
$0041
$0042
$0043
$0044
$0045
$0046
$0047
$0048
$0049
$004A
$004B
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Timer B Counter Register High Read:
(TBCNTH) Write:
See page 213. Reset:
Bit 15
14
13
12
11
10
9
Bit 8
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
Timer B Counter Register Low Read:
(TBCNTL) Write:
See page 213. Reset:
Bit 7
6
5
4
3
2
1
Bit 0
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
1
1
1
1
1
1
1
1
Bit 7
6
5
4
3
2
1
Bit 0
1
1
1
1
1
1
1
1
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
Timer B Modulo Register High Read:
(TBMODH) Write:
See page 214. Reset:
Timer B Modulo Register Low Read:
(TBMODL) Write:
See page 214. Reset:
Timer B CH0 Status and Control Read:
Register (TBSC0) Write:
See page 215. Reset:
Timer B CH0 Register High Read:
(TBCH0H) Write:
See page 218. Reset:
Timer B CH0 Register Low Read:
(TBCH0L) Write:
See page 218. Reset:
Timer B CH1 Status and Control Read:
Register (TBSC1) Write:
See page 215. Reset:
Timer B CH1 Register High Read:
(TBCH1H) Write:
See page 218. Reset:
Timer B CH1 Register Low Read:
(TBCH1L) Write:
See page 218. Reset:
TIM Status and Control Register Read:
(TSC) Write:
See page 222. Reset:
Read:
$004C TIM Counter Register High (TCNTH)
Write:
See page 223.
Reset:
CH0F
0
Indeterminate after reset
Bit 7
6
5
4
3
Indeterminate after reset
CH1F
0
CH1IE
0
R
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
PS2
PS1
PS0
Indeterminate after reset
Bit 7
6
5
4
3
Indeterminate after reset
TOF
0
0
TOIE
TSTOP
0
0
1
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
0
0
0
0
0
0
0
0
0
TRST
Italic Type = MC68HC08AS20 Specific
Boldface Type = MC68HC08AZ32 Specific
U = Unaffected
= Unimplemented
R
= Reserved
X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 9)
MC68HC908AT32 Data Sheet, Rev. 3.1
44
Freescale Semiconductor
Input/Output (I/O) Section
Addr.
$004D
Register Name
Read:
TIM Counter Register Low (TCNTL)
Write:
See page 223.
Reset:
Read:
$004E TIM Modulo Register High (TMODH)
Write:
See page 224.
Reset:
$004F
$FE00
Read:
TIM Modulo Register Low (TMODL)
Write:
See page 224.
Reset:
SIM Break Status Register Read:
(SBSR) Write:
See page 89. Reset:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
1
1
1
1
1
1
1
1
Bit 7
6
5
4
3
2
1
Bit 0
1
1
1
1
1
1
1
1
R
R
R
R
R
R
SBSW
R
See Note
0
Note: Writing a logic 0 clears SBSW.
$FE01
$FE03
$FE09
$FE0B
$FE0C
$FE0D
$FE0E
$FE0F
Read:
SIM Reset Status Register (SRSR)
Write:
See page 90.
Reset:
SIM Break Flag Control Register Read:
(SBFCR) Write:
See page 91. Reset:
Configuration Write-Once Register Read:
(CONFIG-2) Write:
See page 111. Reset:
FLASH Control Register Read:
(FLCR) Write:
See page 51. Reset:
Read:
Break Address Register High (BRKH)
Write:
See page 116.
Reset:
Read:
Break Address Register Low (BRKL)
Write:
See page 116.
Reset:
Break Status and Control Read:
Register (BRKSCR) Write:
See page 115. Reset:
POR
PIN
COP
ILOP
ILAD
0
LVI
0
1
X
0
0
0
0
X
0
BCFE
R
R
R
R
R
R
R
0
0
0
0
0
MSCAND
0
0
MEMEXT
AZ32
0
0
0
1
0
0
1
0
FDIV1
FDIV0
BLKI
BLKO
HVEN
VERF
ERASE
PGM
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
0
0
0
0
0
0
0
0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
BRKE
BRKA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LVI Status Register Read: LVIOUT
(LVISR) Write:
See page 130. Reset:
0
Italic Type = MC68HC08AS20 Specific
Boldface Type = MC68HC08AZ32 Specific
U = Unaffected
= Unimplemented
R
= Reserved
X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 8 of 9)
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
45
Memory Map
Addr.
$FE1C
$FE1D
Register Name
EEPROM Nonvolatile Register Read:
(EENVR) Write:
See page 62. Reset:
$FF80
6
5
4
3
2
1
Bit 0
EERA
CON2
CON1
CON0
EEBP3
EEBP2
EEBP1
EEBP0
Programmed value or 1 in the erased state
Read:
EEBCLK
EEPROM Control Register (EECR)
Write:
See page 61.
Reset:
0
$FE1E
$FE1F
Bit 7
0
EEOFF
0
EERAS1
EERAS0
1
0
0
0
0
0
0
EEBP3
EEBP2
EEBP1
EEBP0
0
Reserved
0
EEPGM
Reserved
EEPROM Array Control Register Read:
(EEACR) Write:
See page 62. Reset:
FLASH Block Protect Register Read:
(FLBPR) Write:
See page 55. Reset:
EERA
CON2
CON1
CON0
Reset loads bits from EENVR to EEACR
0
0
0
0
0
0
0
0
COP Control Register Read:
(COPCTL) Write:
See page 127. Reset:
$FFFF
EELAT
BPR3
BPR2
BPR1
BPR0
0
0
0
0
LOW BYTE OF RESET VECTOR
WRITING TO $FFFF CLEARS COP COUNTER
Unaffected by reset
Italic Type = MC68HC08AS20 Specific
U = Unaffected
= Unimplemented
Boldface Type = MC68HC08AZ32 Specific
R
= Reserved
X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 9 of 9)
Table 2-1. Vector Addresses
Address
Priority
Low
MC68HC08AZ32 Emulation
MC68HC08AS20 Emulation
$FFD0
ADC Vector (High)
$FFD1
ADC Vector (Low)
$FFD2
Keyboard Vector (High)
$FFD3
Keyboard Vector (Low)
$FFD4
SCI Transmit Vector (High)
$FFD5
SCI Transmit Vector (Low)
$FFD6
SCI Receive Vector (High)
$FFD7
SCI Receive Vector (Low)
$FFD8
SCI Error Vector (High)
$FFD9
SCI Error Vector (Low)
$FFDA
CAN Transmit Vector (High)
$FFDB
CAN Transmit Vector (Low)
$FFDC
CAN Receive Vector (High)
BDLC Vector (High)
$FFDD
CAN Receive Vector (Low)
BDLC Vector (Low)
MC68HC908AT32 Data Sheet, Rev. 3.1
46
Freescale Semiconductor
Input/Output (I/O) Section
Table 2-1. Vector Addresses (Continued)
Priority
Address
High
MC68HC08AZ32 Emulation
MC68HC08AS20 Emulation
$FFDE
CAN Error Vector (High)
ADC Vector (High)
$FFDF
CAN Error Vector (Low)
ADC Vector (Low)
$FFE0
CAN Wakeup Vector (High)
SCI Transmit Vector (High)
$FFE1
CAN Wakeup Vector (Low)
SCI Transmit Vector (Low)
$FFE2
SPI Transmit Vector (High)
SCI Receive Vector (High)
$FFE3
SPI Transmit Vector (Low)
SCI Receive Vector (Low)
$FFE4
SPI Receive Vector (High)
SCI Error Vector (High)
$FFE5
SPI Receive Vector (Low)
SCI Error Vector (Low)
$FFE6
TIMB Overflow Vector (High)
SPI Transmit Vector (High)
$FFE7
TIMB Overflow Vector (Low)
SPI Transmit Vector (Low)
$FFE8
TIMB CH1 Vector (High)
SPI Receive Vector (High)
$FFE9
TIMB CH1 Vector (Low)
SPI Receive Vector (Low)
$FFEA
TIMB CH0 Vector (High)
TIM Overflow Vector (High)
$FFEB
TIMB CH0 Vector (Low)
TIM Overflow Vector (Low)
$FFEC
TIMA Overflow Vector (High)
TIM Channel 5 Vector (High)
$FFED
TIMA Overflow Vector (Low)
TIM Channel 5 Vector (Low)
$FFEE
TIMA CH3 Vector (High)
TIM Channel 4 Vector (High)
$FFEF
TIMA CH3 Vector (Low)
TIM Channel 4 Vector (Low)
$FFF0
TIMA CH2 Vector (High)
TIM Channel 3 Vector (High)
$FFF1
TIMA CH2 Vector (Low)
TIM Channel 3 Vector (Low)
$FFF2
TIMA CH1 Vector (High)
TIM Channel 2 Vector (High)
$FFF3
TIMA CH1 Vector (Low)
TIM Channel 2 Vector (Low)
$FFF4
TIMA CH0 Vector (High)
TIM Channel 1 Vector (High)
$FFF5
TIMA CH0 Vector (Low)
TIM Channel 1 Vector (Low)
$FFF6
PIT Vector (High)
TIM Channel 0 Vector (High)
$FFF7
PIT Vector (Low)
TIM Channel 0 Vector (Low)
$FFF8
PLL Vector (High)
$FFF9
PLL Vector (Low)
$FFFA
IRQ1 Vector (High)
$FFFB
IRQ1 Vector (Low)
$FFFC
SWI Vector (High)
$FFFD
SWI Vector (Low)
$FFFE
Reset Vector (High)
$FFFF
Reset Vector (Low)
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
47
Memory Map
MC68HC908AT32 Data Sheet, Rev. 3.1
48
Freescale Semiconductor
Chapter 3
Random-Access Memory (RAM)
3.1 Introduction
This section describes the 1024 bytes of random-access memory (RAM).
3.2 Functional Description
Addresses $0050–$044F are RAM locations. The location of the stack RAM is programmable. The 16-bit
stack pointer allows the stack to be anywhere in the 1024-byte memory space.
NOTE
For correct operation, the stack pointer must point only to RAM locations.
Within page zero are 176 bytes of RAM. Because the location of the stack RAM is programmable, all page
zero RAM locations can be used for input/output (I/O) control and user data or code. When the stack
pointer is moved from its reset location at $00FF, direct addressing mode instructions can access all page
zero RAM locations efficiently. Page zero RAM, therefore, provides ideal locations for frequently
accessed global variables.
Before processing an interrupt, the central processor unit (CPU) uses five bytes of the stack to save the
contents of the CPU registers.
NOTE
For M68HC05, M6805, and M146805 compatibility, the H register is not
stacked.
During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack
pointer decrements during pushes and increments during pulls.
NOTE
Be careful when using nested subroutines. The CPU could overwrite data
in the RAM during a subroutine or during the interrupt stacking operation.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
49
Random-Access Memory (RAM)
MC68HC908AT32 Data Sheet, Rev. 3.1
50
Freescale Semiconductor
Chapter 4
FLASH Memory
4.1 Introduction
This section describes the operation of the embedded FLASH memory. This memory can be read,
programmed, and erased from a single external supply through the use of on-board charge pumps for
program and erase.
4.2 Functional Description
The FLASH memory is an array of 32,256 bytes with an additional 48 bytes of user vectors and one byte
of block protection. An erased bit reads as a logic 0 and a programmed bit reads as a logic 1. Program
and erase operations are facilitated through control bits in a memory mapped register. Details for these
operations appear later in this section. The address ranges for the user memory and vectors are:
• $8000–$FDFF
• $FF80 (block protect register)
• $FFD0–$FFFF (These locations are reserved for user-defined interrupt and reset vectors.)
Programming tools are available from Freescale. Contact your local Freescale representative for more
information.
NOTE
A security feature prevents viewing of the FLASH contents.(1)
4.3 FLASH Control Register
The FLASH control register (FLCR) controls FLASH program, erase, and verify operations.
Address: $FE0B
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
FDIV1
FDIV0
BLK1
BLK0
HVEN
VERF
ERASE
PGM
0
0
0
0
0
0
0
0
Figure 4-1. FLASH Control Register (FLCR)
FDIV1 — Frequency Divide Control Bit
This read/write bit together with FDIV0 selects the factor by which the charge pump clock is divided
from the system clock. See 4.4 Charge Pump Frequency Control.
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for
unauthorized users.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
51
FLASH Memory
FDIV0 — Frequency Divide Control Bit
This read/write bit together with FDIV1 selects the factor by which the charge pump clock is divided
from the system clock. See 4.4 Charge Pump Frequency Control.
BLK1— Block Erase Control Bit
This read/write bit together with BLK0 allows erasing of blocks of varying size. See 4.5 FLASH Erase
Operation for a description of available block sizes.
BLK0 — Block Erase Control Bit
This read/write bit together with BLK1 allows erasing of blocks of varying size. See 4.5 FLASH Erase
Operation for a description of available block sizes.
HVEN — High-Voltage Enable Bit
This read/write bit enables high voltage from the charge pump to the memory for either program or
erase operation. It can be set only if either PGM or ERASE is high and the sequence for erase or
program/verify is followed.
1 = High voltage enabled to array and charge pump on
0 = High voltage disabled to array and charge pump off
VERF — Verify Control Bit
This read/write bit configures the memory for verify operation. It cannot be set if the HVEN bit is high,
and if it is high when HVEN is set, it will automatically return to 0.
1 = Verify operation selected
0 = Verify operation unselected
ERASE — Erase Control Bit
This read/write bit configures the memory for erase operation. It is interlocked with the PGM bit such
that both bits cannot be equal to 1 or set to 1 at the same time.
1 = Erase operation selected
0 = Erase operation unselected
PGM — Program Control Bit
This read/write bit configures the memory for program operation. It is interlocked with the ERASE bit
such that both bits cannot be equal to 1 or set to 1 at the same time.
1 = Program operation selected
0 = Program operation unselected
4.4 Charge Pump Frequency Control
The internal charge pump is designed to operate at greatest efficiency at a frequency of 2 MHz. Table 4-1
shows how the FDIV bits are used to select a charge pump frequency and the recommended bus
frequency ranges for each configuration. Program and erase operations cannot be performed if the pump
clock frequency is below 2 MHz.
Table 4-1. Charge Pump Clock Frequency
FDIV1
FDIV0
Pump Clock Frequency
Bus Frequency
0
0
Bus frequency ÷ 1
2 MHz ± 10%
0
1
Bus frequency ÷ 2
4 MHz ± 10%
1
0
Bus frequency ÷ 2
4 MHz ± 10%
1
1
Bus frequency ÷ 4
8 MHz ± 10%
MC68HC908AT32 Data Sheet, Rev. 3.1
52
Freescale Semiconductor
FLASH Erase Operation
4.5 FLASH Erase Operation
Use the following procedure to erase a block of FLASH memory:
1. Set the ERASE bit and the BLK0 and BLK1 bits in the FLASH control register. See Table 4-2 for
block sizes.
2. Read from the block protect register: address $FF80.
3. Write to any FLASH address with any data within the block address range desired.
4. Set the HVEN bit.
5. Wait for a time, tErase.
6. Clear the HVEN bit.
7. Wait for a time, t Kill for the high voltages to dissipate.
8. Clear the ERASE bit.
9. After time, tHVD, the memory can be accessed in read mode again.
NOTE
While these operations must be performed in the order shown, other
unrelated operations may occur between the steps.
Table 4-2 shows the various block sizes which can be erased in one erase operation.
Table 4-2. Erase Block Sizes
BLK1
BLK0
Block Size, Addresses Cared
0
0
Full array: 32 Kbytes (A15)
0
1
One-half array: 16 Kbytes (A15 and A14)
1
0
Eight rows: 512 Bytes (A15–A9)
1
1
Single row: 64 Bytes (A15–A6)
In step 2 of the erase operation, the cared addresses are latched and used to determine the location of
the block to be erased. For the full array, the only requirement is that A15 be high. Writing to any address
in the range $8000 to $FFFF will enable the full-array erase.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
53
FLASH Memory
4.6 FLASH Program/Verify Operation
Programming of the FLASH memory is done on a page basis. A page consists of eight consecutive bytes
starting from address $XXX0 or $XXX8. The purpose of the verify mode is to ensure that data has been
programmed with sufficient margin for long-term data retention. During verify, the control gates of the
selected memory bits are held at a slightly negative voltage by an internal charge pump. Reading the data
is the same as for ordinary read mode except that a built-in counter stretches the data access for an
additional eight cycles to allow sensing of the lower cell current. A verify can only follow a program
operation. To program and verify the FLASH memory:
1. Set the PGM bit. This configures the memory for program operation and enables the latching of
address and data for programming.
2. Read from the block protect register.
3. Write data to the eight bytes of the page being programmed. This requires eight separate write
operations.
4. Set the HVEN bit.
5. Wait for time, tPROG.
6. Clear the HVEN bit.
7. Wait for time, tHVTV.
8. Set the VERF bit.
9. Wait for time, tVTP.
10. Clear the PGM bit.
11. Wait for time, tHVD.
12. Read back data in verify mode. This is done in eight separate read operations which are each
stretched by eight cycles.
13. Clear the VERF bit.
NOTE
While these operations must be performed in the order shown, other
unrelated operations may occur between the steps.
This program/verify sequence is repeated throughout the memory until all data is programmed. For
minimum overall programming time and least program disturb effect, the sequence should be part of an
intelligent operation which iterates per page (See 4.5 FLASH Erase Operation).
4.7 Block Protection
Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target
application, provision is made for protecting blocks of memory from unintentional erase or program
operations due to system malfunction. This protection is done by reserving a location in the memory for
block protect information and requiring that this location be read from to enable setting of the HVEN bit.
When the block protect register is read, its contents are latched by the FLASH control logic. If the address
range for an erase or program operation includes a protected block, the PGM or ERASE bit is cleared
which prevents the HVEN bit in the FLASH control register from being set so that no high voltage is
allowed in the array.
When the block protect register is erased (all 0s), the entire memory is accessible for program and erase.
When bits within the register are programmed, they lock blocks of memory address ranges as shown in
4.8 FLASH Block Protect Register. The block protect register itself can be erased or programmed only
MC68HC908AT32 Data Sheet, Rev. 3.1
54
Freescale Semiconductor
FLASH Block Protect Register
with an external voltage VDD + VHI present on the IRQ pin. This voltage also allows entry from reset into
the monitor mode.
4.8 FLASH Block Protect Register
The block protect register is implemented as a byte within the FLASH memory. Each bit, when
programmed, protects a range of addresses in the FLASH.
Address:
Read:
$FF80
Bit 7
6
5
4
0
0
0
0
0
0
0
0
Write:
Reset:
3
2
1
Bit 0
BPR3
BPR2
BPR1
BPR0
0
0
0
0
= Unimplemented
Figure 4-2. FLASH Block Protect Register (FLBPR)
BPR3 — Block Protect Register Bit 3
This bit protects the memory contents in the address range $C000 to $FFFF.
1 = Address range protected from erase or program
0 = Address range open to erase or program
BPR2 — Block Protect Register Bit 2
This bit protects the memory contents in the address range $A000 to $FFFF.
1 = Address range protected from erase or program
0 = Address range open to erase or program
BPR1 — Block Protect Register Bit 1
This bit protects the memory contents in the address range $9000 to $FFFF.
1 = Address range protected from erase or program
0 = Address range open to erase or program
BPR0 — Block Protect Register Bit 0
This bit protects the memory contents in the address range $8000 to $FFFF.
1 = Address range protected from erase or program
0 = Address range open to erase or program
By programming the block protect bits, a portion of the memory will be locked so that no further erase or
program operations may be performed. Programming more than one bit at a time is redundant. If both
bit 3 and bit 2 are set, for instance, the address range $A000 through $FFFF is locked. If all bits are
erased, then all of the memory is available for erase and program. The presence of a voltage VDD + VHI
on the IRQ pin will bypass the block protection so that all of the memory, including the block protect
register, is open for program and erase operations.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
55
FLASH Memory
MC68HC908AT32 Data Sheet, Rev. 3.1
56
Freescale Semiconductor
Chapter 5
Electrically Erasable Programmable ROM (EEPROM)
5.1 Introduction
This section describes the electrically erasable programmable read-only memory (EEPROM).
5.2 Features
EEPROM features include:
• Modular architecture expandable in 128 bytes
• Byte, block, or bulk erasable
• Non-volatile redundant array option
• Non-volatile block protection option
• Non-volatile microcontroller unit (MCU) configuration bits
• On-chip charge pump for programming/erasing
• Security option
5.3 Functional Description
The 512 bytes of EEPROM can be programmed or erased without an external voltage supply. The
EEPROM has a lifetime of 10,000 write-erase cycles in the non-redundant mode. Reliability (data
retention) is further extended if the redundancy option is selected. EEPROM cells are protected with a
non-volatile block protection option. These options are stored in the EEPROM non-volatile register
(EENVR) and are loaded into the EEPROM array configuration register after reset (EEACR) or a read of
EENVR. Hardware interlocks are provided to protect stored data corruption from accidental
programming/erasing.
5.3.1 EEPROM Programming
The unprogrammed state is a logic 1. Programming changes the state to a logic 0. Only valid EEPROM
bytes in the non-protected blocks and EENVR can be programmed. When the array is configured in the
redundant mode, programming the first 256 bytes also will program the last 256 bytes with the same data.
Programming the EEPROM in the non-redundant mode is recommended. Program the data to both
locations before entering redundant mode.
Follow this procedure to program a byte of EEPROM:
1. Clear EERAS1 and EERAS0 and set EELAT in the EECTL. Set value of tEEPGM. (See notes a
and b.)
2. Write the desired data to any user EEPROM address.
3. Set the EEPGM bit. (See note c.)
4. Wait for a time, tEEPGM, to program the byte.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
57
Electrically Erasable Programmable ROM (EEPROM)
5. Clear EEPGM bit.
6. Wait for the programming voltage time, tEEFPV, to fall.
7. Clear EELAT bits. (See note d.)
8. Repeat steps 1 to 7 for more EEPROM programming.
Notes:
a. EERAS1 and EERAS0 must be cleared for programming. Otherwise, the part will be in erase
mode.
b. Setting EELAT bit configures the address and data buses to latch data for programming the
array. Only data a with valid EEPROM address will be latched. If another consecutive valid
EEPROM write occurs, this address and data will override the previous address and data.
Any attempts to read other EEPROM data will read the latched data. If EELAT is set, other
writes to the EECR will be allowed after a valid EEPROM write.
c. To ensure proper programming sequence, the EEPGM bit cannot be set if the EELAT bit is
cleared and a non-EEPROM write has occurred. When EEPGM is set, the onboard charge
pump generates the program voltage and applies it to the user EEPROM array. When the
EEPGM bit is cleared, the program voltage is removed from the array and the internal charge
pump is turned off.
d. Any attempt to clear both EEPGM and EELAT bits with a single instruction will only clear
EEPGM. This is to allow time for removal of high voltage from the EEPROM array.
5.3.2 EEPROM Erasing
The unprogrammed state is a logic 1. Only the valid EEPROM bytes in the non-protected blocks and
EENVR can be erased. When the array is configured in the redundant mode, erasing the first 256 bytes
also will erase the last 256 bytes.
Using this procedure erases EEPROM:
1. Clear/set EERAS1 and EERAS0 to select byte/block/bulk erase, and set EELAT in EECTL. Set
value of tEEBYT/tEEBLOCK/tEEBULK. (See note a.)
2. Write any data to the desired address for byte erase, to any address in the desired block for block
erase, or to any array address for bulk erase.
3. Set the EEPGM bit. (See note b.)
4. Wait for a time, tEEPGM, to program the byte.
5. Clear EEPGM bit.
6. Wait for the erasing voltage time, tEEFPV, to fall.
7. Clear EELAT bits. (See note c.)
8. Repeat steps 1 to 7 for more EEPROM byte/block erasing.
EEBPx bit must be cleared to erase EEPROM data in the corresponding block. If any EEBPx is set, the
corresponding block can not be erased and bulk erase mode does not apply.
Notes:
a. Setting EELAT bit configures the address and data buses to latch data for erasing the array.
Only valid EEPROM addresses with their data will be latched. If another consecutive valid
EEPROM write occurs, this address and data will override the previous address and data. In
block erase mode, any EEPROM address in the block may be used in step 2. All locations
within this block will be erased. In bulk erase mode, any EEPROM address may be used to
MC68HC908AT32 Data Sheet, Rev. 3.1
58
Freescale Semiconductor
Functional Description
erase the whole EEPROM. EENVR is not affected with block or bulk erase. Any attempts to
read other EEPROM data will read the latched data. If EELAT is set, other writes to the EECR
will be allowed after a valid EEPROM write.
b. The EEPGM bit cannot be set if the EELAT bit is cleared and a non-EEPROM write has
occurred. This is to ensure proper erasing sequence. Once EEPGM is set, the type of erase
mode cannot be modified. If EEPGM is set, the onboard charge pump generates the erase
voltage and applies it to the user EEPROM array. When the EEPGM bit is cleared, the erase
voltage is removed from the array and the internal charge pump is turned off.
c. Any attempt to clear both EEPGM and EELAT bits with a single instruction will only clear
EEPGM. This is to allow time for removal of high voltage from the EEPROM array.
In general, all bits should be erased before being programmed. However, if program/erase cycling is of
concern, minimize bit cycling in each EEPROM byte. If any bit in a byte requires change from a 0 to a 1,
the byte needs be erased before programming. Table 5-1 summarizes the conditions for erasing before
programming.
Table 5-1. EEPROM Program/Erase Cycling Reduction
EEPROM Data
to be Programmed
EEPROM Data
before Programming
Erase
before Programming?
0
0
No
0
1
No
1
0
Yes
1
1
No
5.3.3 EEPROM Block Protection
The 512 bytes of EEPROM are divided into four 128-byte blocks. Each of these blocks can be separately
protected by EEBPx bit. Any attempt to program or erase memory locations within the protected block will
not allow the program/erase voltage to be applied to the array. Table 5-2 shows the address ranges within
the blocks.
Table 5-2. EEPROM Array Address Blocks
Block Number (EEBPx)
Address Range
EEBP0
$0800–$087F
EEBP1
$0880–$08FF
EEBP2
$0900–$097F
EEBP3
$0980–$09FF
If EEBPx bit is set, that corresponding address block is protected. These bits are effective after a reset or
a read to EENVR register. The block protect configuration can be modified by erasing/programming the
corresponding bits in the EENVR register and then reading the EENVR register.
In redundant mode, EEBP3 and EEBP2 will have no meaning.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
59
Electrically Erasable Programmable ROM (EEPROM)
5.3.4 EEPROM Redundant Mode
To extend the EEPROM data retention, the array can be placed in redundant mode. In this mode, the first
256 bytes of user EEPROM array are mapped to the last 256 bytes. Reading, programming and erasing
of the first 256 EEPROM bytes will physically affect two bytes of EEPROM. Addressing the last 256 bytes
will not be recognized. Block protection still applies but EEBP3 and EEBP2 are meaningless.
NOTE
Programming the EEPROM in non-redundant mode and programming the
data to its corresponding location before entering redundant mode is
recommended.
The EEPROM non-volatile register (EENVR) contains configurations concerning block protection and
redundancy. EENVR is physically located on the bottom of the EEPROM array. The contents are
non-volatile and are not modified by reset. On reset, this special register loads the EEPROM configuration
into a corresponding volatile EEPROM array configuration register (EEACR). Thereafter, all reads to the
EENVR will reload EEACR.
The EEPROM configuration can be changed by programming/erasing the EENVR like a normal EEPROM
byte. The new array configuration will take effect with a system reset or a read of the EENVR.
5.3.5 MCU Configuration
The EEPROM non-volatile register (EENVR) also contains general-purpose bits which can be used to
enable/disable functions within the MCU which, for safety reasons, need to be controlled from non-volatile
memory. On reset, this special register loads the MCU configuration into the volatile EEPROM array
configuration register (EEACR). Thereafter, all reads to the EENVR will reload EEACR.
The MCU configuration can be changed by programming/erasing the EENVR like a normal EEPROM
byte. The new array configuration will take affect with a system reset or a read of the EENVR.
5.3.6 MC68HC908AT32 EEPROM Security
The MC68HC908AT32 has a special security option which prevents program/erase access to memory
locations $08F0 to $08FF. This security function is enabled by programming the CON0 bit in the EENVR
to 0.
NOTE
Once armed, the security is permanently enabled. As a consequence, all
functions in the EENVR will remain in the state they were in immediately
before the security was enabled.
Once the security is armed, bulk and block erase modes are disabled for all EEPROM locations.
Byte erasing can be used for all locations except $08F0 to $08FF. These protected locations can be read
as normal.
MC68HC908AT32 Data Sheet, Rev. 3.1
60
Freescale Semiconductor
Functional Description
5.3.7 EEPROM Control Register
This read/write register controls programming/erasing of the array.
Address:
$FE1D
Bit 7
Read:
Write:
Reset:
6
0
EEBCLK
0
5
EEOFF
0
0
4
3
EERAS1
EERAS0
1
0
0
0
2
1
0
EELAT
0
Bit 0
EEPGM
0
0
= Unimplemented
Figure 5-1. EEPROM Control Register (EECR)
EEBCLK — EEPROM Bus Clock Enable Bit
This read/write bit determines which clock will be used to drive the internal charge pump for
programming/erasing. Reset clears this bit.
1 = Bus clock drives charge pump
0 = Internal RC oscillator drives charge pump
NOTE
Using the internal RC oscillator for applications in the 3- to 5-V range is
recommended.
EEOFF — EEPROM Power Down Bit
This read/write bit disables the EEPROM module for lower power consumption. Any attempts to
access the array will give unpredictable results. Reset clears this bit.
1 = Disable EEPROM array
0 = Enable EEPROM array
NOTE
The EEPROM requires a recovery time, tEEOFF, to stabilize after clearing
the EEOFF bit.
EERAS1 and EERAS0 — Erase Bits
These read/write bits set the erase modes. Reset clears these bits. See Table 5-3.
Table 5-3. EEPROM Program/Erase Mode Select
EEBPx
EERAS1
EERA0
MODE
0
0
0
Byte program
0
0
1
Byte erase
0
1
0
Block erase
0
1
1
Bulk erase
1
X
X
No erase/program
X = don’t care
EELAT — EEPROM Latch Control Bit
This read/write bit latches the address and data buses for programming the EEPROM array. EELAT
cannot be cleared if EEPGM is still set. Reset clears this bit.
1 = Buses configured for EEPROM programming
0 = Buses configured for normal read operation
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
61
Electrically Erasable Programmable ROM (EEPROM)
EEPGM — EEPROM Program/Erase Enable Bit
This read/write bit enables the internal charge pump and applies the programming/erasing voltage to
the EEPROM array if the EELAT bit is set and a write to a valid EEPROM location has occurred. Reset
clears the EEPGM bit.
1 = EEPROM programming/erasing power switched on
0 = EEPROM programming/erasing power switched off
NOTE
Writing logic 0s to both the EELAT and EEPGM bits with a single instruction
will clear EEPGM only to allow time for the removal of high voltage.
5.3.8 EEPROM Non-Volatile Register and EEPROM Array Configuration Register
The EEPROM non-volatile register (EENVR) and array configuration register (EEACR) are shown in
Figure 5-3 and Figure 5-2.
Address:
Read:
Write:
$FE1C
Bit 7
6
5
4
3
2
1
Bit 0
EERA
CON2
CON1
CON0
EEBP3
EEBP2
EEBP1
EEBP0
Reset:
PV
PV = Programmed value or 1 in the erased state.
Figure 5-2. EEPROM Non-Volatile Register (EENVR)
Address:
Read:
$FE1F
Bit 7
6
5
4
3
2
1
Bit 0
EERA
CON2
CON1
CON0
EEBP3
EEBP2
EEBP1
EEBP0
Write:
Reset:
Reset loads bits from EENVR to EEACR
= Unimplemented
Figure 5-3. EEPROM Array Control Register (EEACR)
EERA — EEPROM Redundant Array Bit
This programmable/erasable/read bit in EENVR and read-only bit in EEACR configures the array in
redundant mode. Reset loads EERA from EENVR to EEACR.
1 = EEPROM array is in redundant mode configuration.
0 = EEPROM array is in normal mode configuration.
CONx — MCU Configuration Bits
These read/write bits can be used to enable/disable functions within the MCU. Reset loads CONx from
EENVR to EEACR.
CON2 — Unused
CON1 — Unused
CON0 — EEPROM Security Bit
1 = EEPROM security disabled
0 = EEPROM security enabled
MC68HC908AT32 Data Sheet, Rev. 3.1
62
Freescale Semiconductor
Functional Description
EEBP3–EEBP0 — EEPROM Block Protection Bits
These read/write bits select blocks of EEPROM array from being programmed or erased. Reset loads
EEBP[3:0] from EENVR to EEACR.
1 = EEPROM array block is protected.
0 = EEPROM array block is unprotected.
5.3.9 Low-Power Modes
The WAIT and STOP instructions can put the MCU in low-power standby modes.
5.3.9.1 Wait Mode
The WAIT instruction does not affect the EEPROM. It is possible to program the EEPROM and put the
MCU in wait mode. However, if the EEPROM is inactive, power can be reduced by setting the EEOFF bit
before executing the WAIT instruction.
5.3.9.2 Stop Mode
The STOP instruction reduces the EEPROM power consumption to a minimum. The STOP instruction
should not be executed while the high voltage is turned on (EEPGM = 1).
If stop mode is entered while program/erase is in progress, high voltage will be automatically turned off.
However, the EEPGM bit will remain set. When stop mode is terminated, and if EEPGM is still set, the
high voltage will be automatically turned back on. Program/erase time will need to be extended if
program/erase is interrupted by entering stop mode.
The module requires a recovery time, tEESTOP, to stabilize after leaving stop mode. Attempts to access
the array during the recovery time will result in unpredictable behavior.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
63
Electrically Erasable Programmable ROM (EEPROM)
MC68HC908AT32 Data Sheet, Rev. 3.1
64
Freescale Semiconductor
Chapter 6
Central Processor Unit (CPU)
6.1 Introduction
The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of
the M68HC05 CPU. The CPU08 Reference Manual (document order number CPU08RM/AD) contains a
description of the CPU instruction set, addressing modes, and architecture.
6.2 Features
Features of the CPU include:
• Object code fully upward-compatible with M68HC05 Family
• 16-bit stack pointer with stack manipulation instructions
• 16-bit index register with x-register manipulation instructions
• 8-MHz CPU internal bus frequency
• 64-Kbyte program/data memory space
• 16 addressing modes
• Memory-to-memory data moves without using accumulator
• Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions
• Enhanced binary-coded decimal (BCD) data handling
• Modular architecture with expandable internal bus definition for extension of addressing range
beyond 64 Kbytes
• Low-power stop and wait modes
6.3 CPU Registers
Figure 6-1 shows the five CPU registers. CPU registers are not part of the memory map.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
65
Central Processor Unit (CPU)
0
7
ACCUMULATOR (A)
0
15
H
X
INDEX REGISTER (H:X)
15
0
STACK POINTER (SP)
15
0
PROGRAM COUNTER (PC)
7
0
V 1 1 H I N Z C
CONDITION CODE REGISTER (CCR)
CARRY/BORROW FLAG
ZERO FLAG
NEGATIVE FLAG
INTERRUPT MASK
HALF-CARRY FLAG
TWO’S COMPLEMENT OVERFLOW FLAG
Figure 6-1. CPU Registers
6.3.1 Accumulator
The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and
the results of arithmetic/logic operations.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Unaffected by reset
Figure 6-2. Accumulator (A)
6.3.2 Index Register
The 16-bit index register allows indexed addressing of a 64-Kbyte memory space. H is the upper byte of
the index register, and X is the lower byte. H:X is the concatenated 16-bit index register.
In the indexed addressing modes, the CPU uses the contents of the index register to determine the
conditional address of the operand.
The index register can serve also as a temporary data storage location.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Bit
0
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
Read:
Write:
Reset:
X = Indeterminate
Figure 6-3. Index Register (H:X)
MC68HC908AT32 Data Sheet, Rev. 3.1
66
Freescale Semiconductor
CPU Registers
6.3.3 Stack Pointer
The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a
reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least
significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data
is pushed onto the stack and increments as data is pulled from the stack.
In the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an
index register to access data on the stack. The CPU uses the contents of the stack pointer to determine
the conditional address of the operand.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Bit
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Read:
Write:
Reset:
Figure 6-4. Stack Pointer (SP)
NOTE
The location of the stack is arbitrary and may be relocated anywhere in
random-access memory (RAM). Moving the SP out of page 0 ($0000 to
$00FF) frees direct address (page 0) space. For correct operation, the
stack pointer must point only to RAM locations.
6.3.4 Program Counter
The program counter is a 16-bit register that contains the address of the next instruction or operand to be
fetched.
Normally, the program counter automatically increments to the next sequential memory location every
time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program
counter with an address other than that of the next sequential location.
During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF.
The vector address is the address of the first instruction to be executed after exiting the reset state.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Bit
0
Read:
Write:
Reset:
Loaded with vector from $FFFE and $FFFF
Figure 6-5. Program Counter (PC)
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
67
Central Processor Unit (CPU)
6.3.5 Condition Code Register
The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the
instruction just executed. Bits 6 and 5 are set permanently to 1. The following paragraphs describe the
functions of the condition code register.
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
V
1
1
H
I
N
Z
C
X
1
1
X
1
X
X
X
X = Indeterminate
Figure 6-6. Condition Code Register (CCR)
V — Overflow Flag
The CPU sets the overflow flag when a two's complement overflow occurs. The signed branch
instructions BGT, BGE, BLE, and BLT use the overflow flag.
1 = Overflow
0 = No overflow
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an
add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is required for
binary-coded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and
C flags to determine the appropriate correction factor.
1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4
I — Interrupt Mask
When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled
when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but before the interrupt vector is fetched.
1 = Interrupts disabled
0 = Interrupts enabled
NOTE
To maintain M6805 Family compatibility, the upper byte of the index
register (H) is not stacked automatically. If the interrupt service routine
modifies H, then the user must stack and unstack H using the PSHH and
PULH instructions.
After the I bit is cleared, the highest-priority interrupt request is serviced first.
A return-from-interrupt (RTI) instruction pulls the CPU registers from the stack and restores the
interrupt mask from the stack. After any reset, the interrupt mask is set and can be cleared only by the
clear interrupt mask software instruction (CLI).
N — Negative Flag
The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation
produces a negative result, setting bit 7 of the result.
1 = Negative result
0 = Non-negative result
MC68HC908AT32 Data Sheet, Rev. 3.1
68
Freescale Semiconductor
Arithmetic/Logic Unit (ALU)
Z — Zero Flag
The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation
produces a result of $00.
1 = Zero result
0 = Non-zero result
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the
accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test
and branch, shift, and rotate — also clear or set the carry/borrow flag.
1 = Carry out of bit 7
0 = No carry out of bit 7
6.4 Arithmetic/Logic Unit (ALU)
The ALU performs the arithmetic and logic operations defined by the instruction set.
Refer to the CPU08 Reference Manual (document order number CPU08RM/AD) for a description of the
instructions and addressing modes and more detail about the architecture of the CPU.
6.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
6.5.1 Wait Mode
The WAIT instruction:
• Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from
wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
6.5.2 Stop Mode
The STOP instruction:
• Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After
exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay.
6.6 CPU During Break Interrupts
If a break module is present on the MCU, the CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC:$FFFD or with $FEFC:$FEFD in monitor mode
The break interrupt begins after completion of the CPU instruction in progress. If the break address
register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.
A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU
to normal operation if the break interrupt has been deasserted.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
69
Central Processor Unit (CPU)
6.7 Instruction Set Summary
Table 6-1 provides a summary of the M68HC08 instruction set.
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
ADC opr,SP
ADC opr,SP
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
ADD opr,SP
ADD opr,SP
V H I N Z C
A ← (A) + (M) + (C)
Add with Carry
A ← (A) + (M)
Add without Carry
IMM
DIR
EXT
IX2
– IX1
IX
SP1
SP2
A9
B9
C9
D9
E9
F9
9EE9
9ED9
ii
dd
hh ll
ee ff
ff
IMM
DIR
EXT
– IX2
IX1
IX
SP1
SP2
AB
BB
CB
DB
EB
FB
9EEB
9EDB
ii
dd
hh ll
ee ff
ff
ff
ee ff
ff
ee ff
Cycles
Effect
on CCR
Description
Operand
Operation
Opcode
Source
Form
Address
Mode
Table 6-1. Instruction Set Summary (Sheet 1 of 6)
2
3
4
4
3
2
4
5
2
3
4
4
3
2
4
5
AIS #opr
Add Immediate Value (Signed) to SP
SP ← (SP) + (16 « M)
– – – – – – IMM
A7
ii
2
AIX #opr
Add Immediate Value (Signed) to H:X
H:X ← (H:X) + (16 « M)
– – – – – – IMM
AF
ii
2
A ← (A) & (M)
IMM
DIR
EXT
IX2
0 – – – IX1
IX
SP1
SP2
A4
B4
C4
D4
E4
F4
9EE4
9ED4
ii
dd
hh ll
ee ff
ff
2
3
4
4
3
2
4
5
0
DIR
INH
INH
– – IX1
IX
SP1
38 dd
48
58
68 ff
78
9E68 ff
4
1
1
4
3
5
C
DIR
INH
– – INH
IX1
IX
SP1
37 dd
47
57
67 ff
77
9E67 ff
4
1
1
4
3
5
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
AND opr,SP
AND opr,SP
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
ASL opr,SP
Logical AND
Arithmetic Shift Left
(Same as LSL)
C
b7
ASR opr
ASRA
ASRX
ASR opr,X
ASR opr,X
ASR opr,SP
Arithmetic Shift Right
BCC rel
Branch if Carry Bit Clear
b0
b7
BCLR n, opr
Clear Bit n in M
b0
PC ← (PC) + 2 + rel ? (C) = 0
Mn ← 0
ff
ee ff
– – – – – – REL
24
rr
3
DIR (b0)
DIR (b1)
DIR (b2)
– – – – – – DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
4
4
4
4
4
4
4
4
BCS rel
Branch if Carry Bit Set (Same as BLO)
PC ← (PC) + 2 + rel ? (C) = 1
– – – – – – REL
25
rr
3
BEQ rel
Branch if Equal
PC ← (PC) + 2 + rel ? (Z) = 1
– – – – – – REL
27
rr
3
BGE opr
Branch if Greater Than or Equal To
(Signed Operands)
PC ← (PC) + 2 + rel ? (N ⊕ V) = 0
– – – – – – REL
90
rr
3
BGT opr
Branch if Greater Than (Signed
Operands)
PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V) = 0 – – – – – – REL
92
rr
3
BHCC rel
Branch if Half Carry Bit Clear
PC ← (PC) + 2 + rel ? (H) = 0
– – – – – – REL
28
rr
BHCS rel
Branch if Half Carry Bit Set
PC ← (PC) + 2 + rel ? (H) = 1
– – – – – – REL
29
rr
BHI rel
Branch if Higher
PC ← (PC) + 2 + rel ? (C) | (Z) = 0
– – – – – – REL
22
rr
3
3
3
MC68HC908AT32 Data Sheet, Rev. 3.1
70
Freescale Semiconductor
Instruction Set Summary
Effect
on CCR
V H I N Z C
Cycles
Description
Operand
Operation
Opcode
Source
Form
Address
Mode
Table 6-1. Instruction Set Summary (Sheet 2 of 6)
BHS rel
Branch if Higher or Same
(Same as BCC)
PC ← (PC) + 2 + rel ? (C) = 0
– – – – – – REL
BIH rel
Branch if IRQ Pin High
PC ← (PC) + 2 + rel ? IRQ = 1
– – – – – – REL
2F
rr
3
BIL rel
Branch if IRQ Pin Low
PC ← (PC) + 2 + rel ? IRQ = 0
– – – – – – REL
2E
rr
3
(A) & (M)
IMM
DIR
EXT
0 – – – IX2
IX1
IX
SP1
SP2
A5
B5
C5
D5
E5
F5
9EE5
9ED5
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
rr
3
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
BIT opr,SP
BIT opr,SP
Bit Test
BLE opr
Branch if Less Than or Equal To
(Signed Operands)
PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V) = 1 – – – – – – REL
24
93
rr
3
BLO rel
Branch if Lower (Same as BCS)
PC ← (PC) + 2 + rel ? (C) = 1
– – – – – – REL
25
rr
3
BLS rel
Branch if Lower or Same
PC ← (PC) + 2 + rel ? (C) | (Z) = 1
– – – – – – REL
23
rr
3
BLT opr
Branch if Less Than (Signed Operands)
PC ← (PC) + 2 + rel ? (N ⊕ V) =1
– – – – – – REL
91
rr
3
BMC rel
Branch if Interrupt Mask Clear
PC ← (PC) + 2 + rel ? (I) = 0
– – – – – – REL
2C
rr
3
BMI rel
Branch if Minus
PC ← (PC) + 2 + rel ? (N) = 1
– – – – – – REL
2B
rr
3
BMS rel
Branch if Interrupt Mask Set
PC ← (PC) + 2 + rel ? (I) = 1
– – – – – – REL
2D
rr
3
BNE rel
Branch if Not Equal
PC ← (PC) + 2 + rel ? (Z) = 0
– – – – – – REL
26
rr
3
BPL rel
Branch if Plus
PC ← (PC) + 2 + rel ? (N) = 0
– – – – – – REL
2A
rr
3
BRA rel
Branch Always
PC ← (PC) + 2 + rel
– – – – – – REL
20
rr
3
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
– – – – – DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
– – – – – – REL
21
rr
3
PC ← (PC) + 3 + rel ? (Mn) = 1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
– – – – – DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
Mn ← 1
DIR (b0)
DIR (b1)
DIR (b2)
– – – – – – DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
4
4
4
4
4
4
4
4
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
PC ← (PC) + rel
– – – – – – REL
AD
rr
4
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (X) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 2 + rel ? (A) – (M) = $00
PC ← (PC) + 4 + rel ? (A) – (M) = $00
DIR
IMM
– – – – – – IMM
IX1+
IX+
SP1
31
41
51
61
71
9E61
dd rr
ii rr
ii rr
ff rr
rr
ff rr
5
4
4
5
4
6
BRCLR n,opr,rel Branch if Bit n in M Clear
BRN rel
Branch Never
BRSET n,opr,rel Branch if Bit n in M Set
BSET n,opr
Set Bit n in M
BSR rel
Branch to Subroutine
CBEQ opr,rel
CBEQA #opr,rel
CBEQX #opr,rel Compare and Branch if Equal
CBEQ opr,X+,rel
CBEQ X+,rel
CBEQ opr,SP,rel
PC ← (PC) + 3 + rel ? (Mn) = 0
PC ← (PC) + 2
CLC
Clear Carry Bit
C←0
– – – – – 0 INH
98
1
CLI
Clear Interrupt Mask
I←0
– – 0 – – – INH
9A
2
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
71
Central Processor Unit (CPU)
CLR opr
CLRA
CLRX
CLRH
CLR opr,X
CLR ,X
CLR opr,SP
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
CMP opr,SP
CMP opr,SP
V H I N Z C
Clear
Compare A with M
COM opr
COMA
COMX
COM opr,X
COM ,X
COM opr,SP
Complement (One’s Complement)
CPHX #opr
CPHX opr
Compare H:X with M
CPX #opr
CPX opr
CPX opr
CPX ,X
CPX opr,X
CPX opr,X
CPX opr,SP
CPX opr,SP
Compare X with M
DAA
Decimal Adjust A
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
DEC opr,SP
Decrement
DIV
Divide
INC opr
INCA
INCX
INC opr,X
INC ,X
INC opr,SP
Exclusive OR M with A
Increment
M ← $00
A ← $00
X ← $00
H ← $00
M ← $00
M ← $00
M ← $00
DIR
INH
INH
0 – – 0 1 – INH
IX1
IX
SP1
3F dd
4F
5F
8C
6F ff
7F
9E6F ff
(A) – (M)
IMM
DIR
EXT
IX2
– – IX1
IX
SP1
SP2
A1
B1
C1
D1
E1
F1
9EE1
9ED1
DIR
INH
INH
0 – – 1
IX1
IX
SP1
33 dd
43
53
63 ff
73
9E63 ff
M ← (M) = $FF – (M)
A ← (A) = $FF – (M)
X ← (X) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
(H:X) – (M:M + 1)
(X) – (M)
(A)10
DBNZ opr,rel
DBNZA rel
DBNZX rel
Decrement and Branch if Not Zero
DBNZ opr,X,rel
DBNZ X,rel
DBNZ opr,SP,rel
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
EOR opr,SP
EOR opr,SP
Effect
on CCR
ff
ee ff
2
3
4
4
3
2
4
5
4
1
1
4
3
5
ii ii+1
dd
3
4
IMM
DIR
EXT
IX2
– – IX1
IX
SP1
SP2
A3
B3
C3
D3
E3
F3
9EE3
9ED3
ii
dd
hh ll
ee ff
ff
2
3
4
4
3
2
4
5
U – – INH
72
A ← (A) – 1 or M ← (M) – 1 or X ← (X) – 1
PC ← (PC) + 3 + rel ? (result) ≠ 0
DIR
PC ← (PC) + 2 + rel ? (result) ≠ 0
INH
PC ← (PC) + 2 + rel ? (result) ≠ 0
– – – – – – INH
PC ← (PC) + 3 + rel ? (result) ≠ 0
IX1
PC ← (PC) + 2 + rel ? (result) ≠ 0
IX
PC ← (PC) + 4 + rel ? (result) ≠ 0
SP1
3B
4B
5B
6B
7B
9E6B
ff
ee ff
2
dd rr
rr
rr
ff rr
rr
ff rr
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
M ← (M) – 1
DIR
INH
INH
– – –
IX1
IX
SP1
A ← (H:A)/(X)
H ← Remainder
– – – – INH
52
A ← (A ⊕ M)
IMM
DIR
EXT
0 – – – IX2
IX1
IX
SP1
SP2
A8
B8
C8
D8
E8
F8
9EE8
9ED8
DIR
INH
– – – INH
IX1
IX
SP1
3C dd
4C
5C
6C ff
7C
9E6C ff
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
M ← (M) + 1
3
1
1
1
3
2
4
65
75
– – IMM
DIR
ii
dd
hh ll
ee ff
ff
Cycles
Description
Operand
Operation
Opcode
Source
Form
Address
Mode
Table 6-1. Instruction Set Summary (Sheet 3 of 6)
3A dd
4A
5A
6A ff
7A
9E6A ff
5
3
3
5
4
6
4
1
1
4
3
5
7
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
4
1
1
4
3
5
MC68HC908AT32 Data Sheet, Rev. 3.1
72
Freescale Semiconductor
Instruction Set Summary
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
Jump to Subroutine
LDHX #opr
LDHX opr
Load H:X from M
2
3
4
3
2
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Unconditional Address
DIR
EXT
– – – – – – IX2
IX1
IX
BD
CD
DD
ED
FD
dd
hh ll
ee ff
ff
4
5
6
5
4
A ← (M)
IMM
DIR
EXT
IX2
0 – – – IX1
IX
SP1
SP2
A6
B6
C6
D6
E6
F6
9EE6
9ED6
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
ii jj
dd
3
4
ii
dd
hh ll
ee ff
ff
2
3
4
4
3
2
4
5
H:X ← (M:M + 1)
Logical Shift Left
(Same as ASL)
Logical Shift Right
MOV opr,opr
MOV opr,X+
MOV #opr,opr
MOV X+,opr
Move
MUL
Unsigned multiply
C
b7
45
55
AE
BE
CE
DE
EE
FE
9EEE
9EDE
0
DIR
INH
INH
– – IX1
IX
SP1
38 dd
48
58
68 ff
78
9E68 ff
4
1
1
4
3
5
C
DIR
INH
– – 0 INH
IX1
IX
SP1
34 dd
44
54
64 ff
74
9E64 ff
4
1
1
4
3
5
b0
0
IMM
DIR
IMM
DIR
EXT
IX2
0 – – – IX1
IX
SP1
SP2
X ← (M)
b7
Negate (Two’s Complement)
0 – – –
b0
H:X ← (H:X) + 1 (IX+D, DIX+)
DD
DIX+
0 – – – IMD
IX+D
X:A ← (X) × (A)
– 0 – – – 0 INH
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
DIR
INH
INH
– – IX1
IX
SP1
(M)Destination ← (M)Source
4E
5E
6E
7E
dd dd
dd
ii dd
dd
42
No Operation
None
– – – – – – INH
9D
NSA
Nibble Swap A
A ← (A[3:0]:A[7:4])
– – – – – – INH
62
A ← (A) | (M)
IMM
DIR
EXT
IX2
0 – – –
IX1
IX
SP1
SP2
AA
BA
CA
DA
EA
FA
9EEA
9EDA
Inclusive OR A and M
ff
ee ff
5
4
4
4
5
30 dd
40
50
60 ff
70
9E60 ff
NOP
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
ORA opr,SP
ORA opr,SP
Cycles
dd
hh ll
ee ff
ff
Load X from M
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
LSR opr,SP
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
NEG opr,SP
BC
CC
DC
EC
FC
Jump
Load A from M
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
LSL opr,SP
PC ← Jump Address
DIR
EXT
– – – – – – IX2
IX1
IX
Effect
on CCR
Description
V H I N Z C
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDA opr,SP
LDA opr,SP
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LDX opr,SP
LDX opr,SP
Operand
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
Operation
Address
Mode
Source
Form
Opcode
Table 6-1. Instruction Set Summary (Sheet 4 of 6)
4
1
1
4
3
5
1
3
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
PSHA
Push A onto Stack
Push (A); SP ← (SP) – 1
– – – – – – INH
87
2
PSHH
Push H onto Stack
Push (H); SP ← (SP) – 1
– – – – – – INH
8B
2
PSHX
Push X onto Stack
Push (X); SP ← (SP) – 1
– – – – – – INH
89
2
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
73
Central Processor Unit (CPU)
V H I N Z C
Cycles
Effect
on CCR
Description
Operand
Operation
Opcode
Source
Form
Address
Mode
Table 6-1. Instruction Set Summary (Sheet 5 of 6)
PULA
Pull A from Stack
SP ← (SP + 1); Pull (A)
– – – – – – INH
86
2
PULH
Pull H from Stack
SP ← (SP + 1); Pull (H)
– – – – – – INH
8A
2
PULX
Pull X from Stack
SP ← (SP + 1); Pull (X)
– – – – – – INH
C
DIR
INH
INH
– – IX1
IX
SP1
39 dd
49
59
69 ff
79
9E69 ff
4
1
1
4
3
5
DIR
INH
– – INH
IX1
IX
SP1
36 dd
46
56
66 ff
76
9E66 ff
4
1
1
4
3
5
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
ROL opr,SP
Rotate Left through Carry
b7
b0
88
2
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
ROR opr,SP
Rotate Right through Carry
RSP
Reset Stack Pointer
SP ← $FF
– – – – – – INH
9C
1
RTI
Return from Interrupt
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
INH
80
7
RTS
Return from Subroutine
SP ← SP + 1; Pull (PCH)
SP ← SP + 1; Pull (PCL)
– – – – – – INH
81
4
A ← (A) – (M) – (C)
IMM
DIR
EXT
– – IX2
IX1
IX
SP1
SP2
A2
B2
C2
D2
E2
F2
9EE2
9ED2
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
SBC opr,SP
SBC opr,SP
C
b7
Subtract with Carry
b0
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
SEC
Set Carry Bit
C←1
– – – – – 1 INH
99
1
SEI
Set Interrupt Mask
I←1
– – 1 – – – INH
9B
2
M ← (A)
DIR
EXT
IX2
0 – – – IX1
IX
SP1
SP2
B7
C7
D7
E7
F7
9EE7
9ED7
(M:M + 1) ← (H:X)
0 – – – DIR
35
I ← 0; Stop Processing
– – 0 – – – INH
8E
M ← (X)
DIR
EXT
IX2
0 – – – IX1
IX
SP1
SP2
BF
CF
DF
EF
FF
9EEF
9EDF
dd
hh ll
ee ff
ff
IMM
DIR
EXT
– – IX2
IX1
IX
SP1
SP2
A0
B0
C0
D0
E0
F0
9EE0
9ED0
ii
dd
hh ll
ee ff
ff
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
STA opr,SP
STA opr,SP
Store A in M
STHX opr
Store H:X in M
STOP
Enable Interrupts, Stop Processing,
Refer to MCU Documentation
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
STX opr,SP
STX opr,SP
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
SUB opr,SP
SUB opr,SP
Store X in M
Subtract
A ← (A) – (M)
dd
hh ll
ee ff
ff
ff
ee ff
3
4
4
3
2
4
5
dd
4
1
ff
ee ff
ff
ee ff
3
4
4
3
2
4
5
2
3
4
4
3
2
4
5
MC68HC908AT32 Data Sheet, Rev. 3.1
74
Freescale Semiconductor
Opcode Map
V H I N Z C
Cycles
Effect
on CCR
Description
Operand
Operation
Opcode
Source
Form
Address
Mode
Table 6-1. Instruction Set Summary (Sheet 6 of 6)
SWI
Software Interrupt
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
CCR ← (A)
INH
84
2
X ← (A)
– – – – – – INH
97
1
A ← (CCR)
– – – – – – INH
(A) – $00 or (X) – $00 or (M) – $00
DIR
INH
INH
0 – – –
IX1
IX
SP1
TAP
Transfer A to CCR
TAX
Transfer A to X
TPA
Transfer CCR to A
TST opr
TSTA
TSTX
TST opr,X
TST ,X
TST opr,SP
Test for Negative or Zero
TSX
Transfer SP to H:X
TXA
Transfer X to A
TXS
Transfer H:X to SP
WAIT
A
C
CCR
dd
dd rr
DD
DIR
DIX+
ee ff
EXT
ff
H
H
hh ll
I
ii
IMD
IMM
INH
IX
IX+
IX+D
IX1
IX1+
IX2
M
N
Enable Interrupts; Wait for Interrupt
– – 1 – – – INH
83
85
3D dd
4D
5D
6D ff
7D
9E6D ff
9
1
3
1
1
3
2
4
H:X ← (SP) + 1
– – – – – – INH
95
2
A ← (X)
– – – – – – INH
9F
1
(SP) ← (H:X) – 1
– – – – – – INH
94
2
I bit ← 0; Inhibit CPU clocking
until interrupted
– – 0 – – – INH
8F
1
Accumulator
Carry/borrow bit
Condition code register
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct to direct addressing mode
Direct addressing mode
Direct to indexed with post increment addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
Offset byte in indexed, 8-bit offset addressing
Half-carry bit
Index register high byte
High and low bytes of operand address in extended addressing
Interrupt mask
Immediate operand byte
Immediate source to direct destination addressing mode
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, no offset, post increment addressing mode
Indexed with post increment to direct addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 8-bit offset, post increment addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Negative bit
n
opr
PC
PCH
PCL
REL
rel
rr
SP1
SP2
SP
U
V
X
Z
&
|
⊕
()
–( )
#
«
←
?
:
—
Any bit
Operand (one or two bytes)
Program counter
Program counter high byte
Program counter low byte
Relative addressing mode
Relative program counter offset byte
Relative program counter offset byte
Stack pointer, 8-bit offset addressing mode
Stack pointer 16-bit offset addressing mode
Stack pointer
Undefined
Overflow bit
Index register low byte
Zero bit
Logical AND
Logical OR
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Immediate value
Sign extend
Loaded with
If
Concatenated with
Set or cleared
Not affected
6.8 Opcode Map
See Table 6-2.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
75
MSB
Branch
REL
DIR
INH
3
4
0
1
2
5
BRSET0
3 DIR
5
BRCLR0
3 DIR
5
BRSET1
3 DIR
5
BRCLR1
3 DIR
5
BRSET2
3 DIR
5
BRCLR2
3 DIR
5
BRSET3
3 DIR
5
BRCLR3
3 DIR
5
BRSET4
3 DIR
5
BRCLR4
3 DIR
5
BRSET5
3 DIR
5
BRCLR5
3 DIR
5
BRSET6
3 DIR
5
BRCLR6
3 DIR
5
BRSET7
3 DIR
5
BRCLR7
3 DIR
4
BSET0
2 DIR
4
BCLR0
2 DIR
4
BSET1
2 DIR
4
BCLR1
2 DIR
4
BSET2
2 DIR
4
BCLR2
2 DIR
4
BSET3
2 DIR
4
BCLR3
2 DIR
4
BSET4
2 DIR
4
BCLR4
2 DIR
4
BSET5
2 DIR
4
BCLR5
2 DIR
4
BSET6
2 DIR
4
BCLR6
2 DIR
4
BSET7
2 DIR
4
BCLR7
2 DIR
3
BRA
2 REL
3
BRN
2 REL
3
BHI
2 REL
3
BLS
2 REL
3
BCC
2 REL
3
BCS
2 REL
3
BNE
2 REL
3
BEQ
2 REL
3
BHCC
2 REL
3
BHCS
2 REL
3
BPL
2 REL
3
BMI
2 REL
3
BMC
2 REL
3
BMS
2 REL
3
BIL
2 REL
3
BIH
2 REL
Read-Modify-Write
INH
IX1
5
6
1
NEGX
1 INH
4
CBEQX
3 IMM
7
DIV
1 INH
1
COMX
1 INH
1
LSRX
1 INH
4
LDHX
2 DIR
1
RORX
1 INH
1
ASRX
1 INH
1
LSLX
1 INH
1
ROLX
1 INH
1
DECX
1 INH
3
DBNZX
2 INH
1
INCX
1 INH
1
TSTX
1 INH
4
MOV
2 DIX+
1
CLRX
1 INH
4
NEG
2
IX1
5
CBEQ
3 IX1+
3
NSA
1 INH
4
COM
2 IX1
4
LSR
2 IX1
3
CPHX
3 IMM
4
ROR
2 IX1
4
ASR
2 IX1
4
LSL
2 IX1
4
ROL
2 IX1
4
DEC
2 IX1
5
DBNZ
3 IX1
4
INC
2 IX1
3
TST
2 IX1
4
MOV
3 IMD
3
CLR
2 IX1
SP1
IX
9E6
7
Control
INH
INH
8
9
Register/Memory
IX2
SP2
IMM
DIR
EXT
A
B
C
D
9ED
4
SUB
3 EXT
4
CMP
3 EXT
4
SBC
3 EXT
4
CPX
3 EXT
4
AND
3 EXT
4
BIT
3 EXT
4
LDA
3 EXT
4
STA
3 EXT
4
EOR
3 EXT
4
ADC
3 EXT
4
ORA
3 EXT
4
ADD
3 EXT
3
JMP
3 EXT
5
JSR
3 EXT
4
LDX
3 EXT
4
STX
3 EXT
4
SUB
3 IX2
4
CMP
3 IX2
4
SBC
3 IX2
4
CPX
3 IX2
4
AND
3 IX2
4
BIT
3 IX2
4
LDA
3 IX2
4
STA
3 IX2
4
EOR
3 IX2
4
ADC
3 IX2
4
ORA
3 IX2
4
ADD
3 IX2
4
JMP
3 IX2
6
JSR
3 IX2
4
LDX
3 IX2
4
STX
3 IX2
5
SUB
4 SP2
5
CMP
4 SP2
5
SBC
4 SP2
5
CPX
4 SP2
5
AND
4 SP2
5
BIT
4 SP2
5
LDA
4 SP2
5
STA
4 SP2
5
EOR
4 SP2
5
ADC
4 SP2
5
ORA
4 SP2
5
ADD
4 SP2
IX1
SP1
IX
E
9EE
F
LSB
0
1
2
3
4
MC68HC908AT32 Data Sheet, Rev. 3.1
5
6
7
8
9
A
B
C
D
E
Freescale Semiconductor
F
4
1
NEG
NEGA
2 DIR 1 INH
5
4
CBEQ CBEQA
3 DIR 3 IMM
5
MUL
1 INH
4
1
COM
COMA
2 DIR 1 INH
4
1
LSR
LSRA
2 DIR 1 INH
4
3
STHX
LDHX
2 DIR 3 IMM
4
1
ROR
RORA
2 DIR 1 INH
4
1
ASR
ASRA
2 DIR 1 INH
4
1
LSL
LSLA
2 DIR 1 INH
4
1
ROL
ROLA
2 DIR 1 INH
4
1
DEC
DECA
2 DIR 1 INH
5
3
DBNZ DBNZA
3 DIR 2 INH
4
1
INC
INCA
2 DIR 1 INH
3
1
TST
TSTA
2 DIR 1 INH
5
MOV
3 DD
3
1
CLR
CLRA
2 DIR 1 INH
INH Inherent
REL Relative
IMM Immediate
IX
Indexed, No Offset
DIR Direct
IX1 Indexed, 8-Bit Offset
EXT Extended
IX2 Indexed, 16-Bit Offset
DD Direct-Direct
IMD Immediate-Direct
IX+D Indexed-Direct DIX+ Direct-Indexed
*Pre-byte for stack pointer indexed instructions
5
3
NEG
NEG
3 SP1 1 IX
6
4
CBEQ
CBEQ
4 SP1 2 IX+
2
DAA
1 INH
5
3
COM
COM
3 SP1 1 IX
5
3
LSR
LSR
3 SP1 1 IX
4
CPHX
2 DIR
5
3
ROR
ROR
3 SP1 1 IX
5
3
ASR
ASR
3 SP1 1 IX
5
3
LSL
LSL
3 SP1 1 IX
5
3
ROL
ROL
3 SP1 1 IX
5
3
DEC
DEC
3 SP1 1 IX
6
4
DBNZ
DBNZ
4 SP1 2 IX
5
3
INC
INC
3 SP1 1 IX
4
2
TST
TST
3 SP1 1 IX
4
MOV
2 IX+D
4
2
CLR
CLR
3 SP1 1 IX
SP1 Stack Pointer, 8-Bit Offset
SP2 Stack Pointer, 16-Bit Offset
IX+ Indexed, No Offset with
Post Increment
IX1+ Indexed, 1-Byte Offset with
Post Increment
7
3
RTI
BGE
1 INH 2 REL
4
3
RTS
BLT
1 INH 2 REL
3
BGT
2 REL
9
3
SWI
BLE
1 INH 2 REL
2
2
TAP
TXS
1 INH 1 INH
1
2
TPA
TSX
1 INH 1 INH
2
PULA
1 INH
2
1
PSHA
TAX
1 INH 1 INH
2
1
PULX
CLC
1 INH 1 INH
2
1
PSHX
SEC
1 INH 1 INH
2
2
PULH
CLI
1 INH 1 INH
2
2
PSHH
SEI
1 INH 1 INH
1
1
CLRH
RSP
1 INH 1 INH
1
NOP
1 INH
1
STOP
*
1 INH
1
1
WAIT
TXA
1 INH 1 INH
2
SUB
2 IMM
2
CMP
2 IMM
2
SBC
2 IMM
2
CPX
2 IMM
2
AND
2 IMM
2
BIT
2 IMM
2
LDA
2 IMM
2
AIS
2 IMM
2
EOR
2 IMM
2
ADC
2 IMM
2
ORA
2 IMM
2
ADD
2 IMM
3
SUB
2 DIR
3
CMP
2 DIR
3
SBC
2 DIR
3
CPX
2 DIR
3
AND
2 DIR
3
BIT
2 DIR
3
LDA
2 DIR
3
STA
2 DIR
3
EOR
2 DIR
3
ADC
2 DIR
3
ORA
2 DIR
3
ADD
2 DIR
2
JMP
2 DIR
4
4
BSR
JSR
2 REL 2 DIR
2
3
LDX
LDX
2 IMM 2 DIR
2
3
AIX
STX
2 IMM 2 DIR
MSB
0
3
SUB
2 IX1
3
CMP
2 IX1
3
SBC
2 IX1
3
CPX
2 IX1
3
AND
2 IX1
3
BIT
2 IX1
3
LDA
2 IX1
3
STA
2 IX1
3
EOR
2 IX1
3
ADC
2 IX1
3
ORA
2 IX1
3
ADD
2 IX1
3
JMP
2 IX1
5
JSR
2 IX1
5
3
LDX
LDX
4 SP2 2 IX1
5
3
STX
STX
4 SP2 2 IX1
4
SUB
3 SP1
4
CMP
3 SP1
4
SBC
3 SP1
4
CPX
3 SP1
4
AND
3 SP1
4
BIT
3 SP1
4
LDA
3 SP1
4
STA
3 SP1
4
EOR
3 SP1
4
ADC
3 SP1
4
ORA
3 SP1
4
ADD
3 SP1
2
SUB
1 IX
2
CMP
1 IX
2
SBC
1 IX
2
CPX
1 IX
2
AND
1 IX
2
BIT
1 IX
2
LDA
1 IX
2
STA
1 IX
2
EOR
1 IX
2
ADC
1 IX
2
ORA
1 IX
2
ADD
1 IX
2
JMP
1 IX
4
JSR
1 IX
4
2
LDX
LDX
3 SP1 1 IX
4
2
STX
STX
3 SP1 1 IX
High Byte of Opcode in Hexadecimal
LSB
Low Byte of Opcode in Hexadecimal
0
5
Cycles
BRSET0 Opcode Mnemonic
3 DIR Number of Bytes / Addressing Mode
Central Processor Unit (CPU)
76
Table 6-2. Opcode Map
Bit Manipulation
DIR
DIR
Chapter 7
System Integration Module (SIM)
7.1 Introduction
This section describes the system integration module (SIM), which supports up to 24 external and/or
internal interrupts. Together with the central processor unit (CPU), the SIM controls all MCU activities. A
block diagram of the SIM is shown in Figure 7-2. Figure 7-1 is a summary of the SIM input/output (I/O)
registers. The SIM is a system state controller that coordinates CPU and exception timing. The SIM is
responsible for:
• Bus clock generation and control for CPU and peripherals:
– Stop/wait/reset/break entry and recovery
– Internal clock control
• Master reset control, including power-on reset (POR) and computer operating properly (COP)
timeout
• Interrupt control:
– Acknowledge timing
– Arbitration control timing
– Vector address generation
• CPU enable/disable timing
• Modular architecture expandable to 128 interrupt sources
Addr.
$FE00
$FE01
Register Name
SIM Break Status Register Read:
(SBSR) Write:
See page 89. Reset:
Read:
SIM Reset Status Register (SRSR)
See page 90.
6
5
4
3
2
1
R
R
R
R
R
R
POR
PIN
COP
ILOP
ILAD
0
LVI
0
1
X
0
0
0
0
X
0
BCFE
R
R
R
R
R
R
R
SBSW
See note
Bit 0
R
0
Write:
Reset:
$FE03
Bit 7
SIM Break Flag Control Register Read:
(SBFCR) Write:
See page 91. Reset:
0
Note: Writing a logic 0 clears SBSW
0
= Unimplemented
R
= Reserved
X = Indeterminate
Figure 7-1. SIM I/O Register Summary
Table 7-1. I/O Register Address Summary
Register
SBSR
SRSR
SBFCR
Address
$FE00
$FE01
$FE03
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
77
System Integration Module (SIM)
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
STOP/WAIT
CONTROL
SIMOSCEN (TO CGM)
SIM
COUNTER
COP CLOCK
CGMXCLK (FROM CGM)
CGMOUT (FROM CGM)
÷2
CLOCK
CONTROL
RESET
PIN LOGIC
CLOCK GENERATORS
INTERNAL CLOCKS
LVI (FROM LVI MODULE)
POR CONTROL
MASTER
RESET
CONTROL
RESET PIN CONTROL
SIM RESET STATUS REGISTER
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP (FROM COP MODULE)
RESET
INTERRUPT SOURCES
INTERRUPT CONTROL
AND PRIORITY DECODE
CPU INTERFACE
Figure 7-2. SIM Block Diagram
Table 7-2 shows the internal signal names used in this section.
Table 7-2. Signal Name Conventions
Signal Name
Description
CGMXCLK
Buffered version of OSC1 from clock generator module (CGM)
CGMVCLK
PLL output
CGMOUT
PLL-based or OSC1-based clock output from CGM module
(Bus clock = CGMOUT divided by two)
IAB
Internal address bus
IDB
Internal data bus
PORRST
Signal from the power-on reset module to the SIM
IRST
Internal reset signal
R/W
Read/write signal
MC68HC908AT32 Data Sheet, Rev. 3.1
78
Freescale Semiconductor
SIM Bus Clock Control and Generation
7.2 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The
system clocks are generated from an incoming clock, CGMOUT, as shown in Figure 7-3. This clock can
come from either an external oscillator or from the on-chip phase-locked loop (PLL). See Chapter 8 Clock
Generator Module (CGM).
7.2.1 Bus Timing
In user mode, the internal bus frequency is either the crystal oscillator output (CGMXCLK) divided by four
or the PLL output (CGMVCLK) divided by four. See Chapter 8 Clock Generator Module (CGM).
7.2.2 Clock Startup from POR or LVI Reset
When the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the
CPU and peripherals are inactive and held in an inactive phase until after 4096 CGMXCLK cycles. The
RST pin is driven low by the SIM during this entire period. The bus clocks start upon completion of the
timeout.
CGMXCLK
OSC1
CGMVCLK
PLL
CLOCK
SELECT
CIRCUIT
÷2
A
CGMOUT
B S*
*When S = 1,
CGMOUT = B
SIM COUNTER
÷2
BUS CLOCK
GENERATORS
SIM
BCS
PTC3
MONITOR MODE
USER MODE
CGM
Figure 7-3. CGM Clock Signals
7.2.3 Clocks in Stop Mode and Wait Mode
Upon exit from stop mode by an interrupt, break, or reset, the SIM allows CGMXCLK to clock the SIM
counter. The CPU and peripheral clocks do not become active until after the stop delay timeout. This
timeout is selectable as 4096 or 32 CGMXCLK cycles. See 7.6.2 Stop Mode.
In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the
module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
79
System Integration Module (SIM)
7.3 Reset and System Initialization
The MCU has these reset sources:
• Power-on reset module (POR)
• External reset pin (RST)
• Computer operating properly module (COP)
• Low-voltage inhibit module (LVI)
• Illegal opcode
• Illegal address
All of these resets produce the vector $FFFE–FFFF ($FEFE–FEFF in monitor mode) and assert the
internal reset signal (IRST). IRST causes all registers to be returned to their default values and all
modules to be returned to their reset states.
An internal reset clears the SIM counter (see 7.4 SIM Counter), but an external reset does not. Each of
the resets sets a corresponding bit in the SIM reset status register (SRSR). See 7.7 SIM Registers.
7.3.1 External Pin Reset
Pulling the asynchronous RST pin low halts all processing. The PIN bit of the SIM reset status register
(SRSR) is set as long as RST is held low for a minimum of 67 CGMXCLK cycles, assuming that neither
the POR nor the LVI was the source of the reset. See Table 7-3 for details.
Figure 7-4 shows the relative timing.
Table 7-3. PIN Bit Set Timing
Reset Type
Number of Cycles Required to Set PIN
POR/LVI
4163 (4096 + 64 + 3)
All others
67 (64 + 3)
CGMOUT
RST
IAB
PC
VECT H
VECT L
Figure 7-4. External Reset Timing
MC68HC908AT32 Data Sheet, Rev. 3.1
80
Freescale Semiconductor
Reset and System Initialization
7.3.2 Active Resets from Internal Sources
All internal reset sources actively pull the RST pin low for 32 CGMXCLK cycles to allow resetting of
external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles.
See Figure 7-5. An internal reset can be caused by an illegal address, illegal opcode, COP timeout, LVI,
or POR. (See Figure 7-6.) Note that for LVI or POR resets, the SIM cycles through 4096 CGMXCLK
cycles during which the SIM forces the RST pin low. The internal reset signal then follows the sequence
from the falling edge of RST shown in Figure 7-5.
The COP reset is asynchronous to the bus clock.
The active reset feature allows the part to issue a reset to peripherals and other chips within a system
built around the MCU.
IRST
RST PULLED LOW BY MCU
RST
32 CYCLES
32 CYCLES
CGMXCLK
IAB
VECTOR HIGH
Figure 7-5. Internal Reset Timing
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
LVI
POR
INTERNAL RESET
Figure 7-6. Sources of Internal Reset
7.3.2.1 Power-On Reset (POR)
When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate
that power-on has occurred. The external reset pin (RST) is held low while the SIM counter counts out
4096 CGMXCLK cycles. Another sixty-four CGMXCLK cycles later, the CPU and memories are released
from reset to allow the reset vector sequence to occur. See Figure 7-7.
At power-on, the following events occur:
• A POR pulse is generated.
• The internal reset signal is asserted.
• The SIM enables CGMOUT.
• Internal clocks to the CPU and modules are held inactive for 4096 CGMXCLK cycles to allow
stabilization of the oscillator.
• The RST pin is driven low during the oscillator stabilization time.
• The POR bit of the SIM reset status register (SRSR) is set and all other bits in the register are
cleared.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
81
System Integration Module (SIM)
OSC1
PORRST
4096
CYCLES
32
CYCLES
32
CYCLES
CGMXCLK
CGMOUT
RST
$FFFE
IAB
$FFFF
Figure 7-7. POR Recovery
7.3.2.2 Computer Operating Properly (COP) Reset
The overflow of the COP counter causes an internal reset and sets the COP bit in the SIM reset status
register (SRSR) if the COPD bit in the CONFIG-1 register is at logic 0. See Chapter 13 Computer
Operating Properly Module (COP).
7.3.2.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP
bit in the SIM reset status register (SRSR) and causes a reset.
If the stop enable bit, STOP, in the CONFIG-1 register is logic 0, the SIM treats the STOP instruction as
an illegal opcode and causes an illegal opcode reset.
7.3.2.4 Illegal Address Reset
An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the
CPU is fetching an opcode prior to asserting the ILAD bit in the SIM reset status register (SRSR) and
resetting the MCU. A data fetch from an unmapped address does not generate a reset.
7.3.2.5 Low-Voltage Inhibit (LVI) Reset
The low-voltage inhibit module (LVI) asserts its output to the SIM when the VDD voltage falls to the VLVII
voltage. The LVI bit in the SIM reset status register (SRSR) is set and a chip reset is asserted if the
LVIPWRD and LVIRSTD bits in the CONFIG-1 register are at logic 0. The RST pin will be held low until
the SIM counts 4096 CGMXCLK cycles after VDD rises above VLVIR. Another 64 CGMXCLK cycles later,
the CPU is released from reset to allow the reset vector sequence to occur. See Chapter 14 Low-Voltage
Inhibit (LVI).
MC68HC908AT32 Data Sheet, Rev. 3.1
82
Freescale Semiconductor
SIM Counter
7.4 SIM Counter
The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the
oscillator time to stabilize before enabling the internal bus (IBUS) clocks. The SIM counter also serves as
a prescaler for the computer operating properly module (COP). The SIM counter overflow supplies the
clock for the COP module. The SIM counter is 12 bits long and is clocked by the falling edge of
CGMXCLK.
7.4.1 SIM Counter during Power-On Reset
The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit
asserts the signal PORRST. Once the SIM is initialized, it enables the clock generation module (CGM) to
drive the bus clock state machine.
7.4.2 SIM Counter during Stop Mode Recovery
The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After
an interrupt, break, or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the
CONFIG-1 register. If the SSREC bit is a logic 1, then the stop recovery is reduced from the normal delay
of 4096 CGMXCLK cycles down to 32 CGMXCLK cycles. This is ideal for applications using canned
oscillators that do not require long start-up times from stop mode. External crystal applications should use
the full stop recovery time, that is, with SSREC cleared.
7.4.3 SIM Counter and Reset States
External reset has no effect on the SIM counter. (See 7.6.2 Stop Mode for details.) The SIM counter is
free-running after all reset states. (See 7.3.2 Active Resets from Internal Sources for counter control and
internal reset recovery sequences.)
7.5 Program Exception Control
Normal, sequential program execution can be changed in three different ways:
• Interrupts:
– Maskable hardware CPU interrupts
– Non-maskable software interrupt instruction (SWI)
• Reset
• Break interrupts
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
83
System Integration Module (SIM)
7.5.1 Interrupts
At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the
interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers
the CPU register contents from the stack so that normal processing can resume. Figure 7-8 shows
interrupt entry timing. Figure 7-9 shows interrupt recovery timing.
Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The
arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is
latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched
interrupt is serviced (or the I bit is cleared). See Figure 7-10.
MODULE
INTERRUPT
IAB
IDB
LAST
ADDRESS
SP
SP – 1
SP – 2
PC – 1
END OF
PC – 1
LAST INSTR. LOW BYTE HIGH BYTE
SP – 3
X
VECTOR
VECTOR
ADDR. HIGH ADDR. LOW
SP – 4
A
VECTOR
HIGH
CCR
NEW PC
VECTOR
LOW
NEW PC
+1
OPCODE
R/W
Figure 7-8. Interrupt Entry Timing
MODULE
INTERRUPT
IAB
IDB
RTI
ADDRESS
RTI
ADDR. + 1
RTI
OPCODE
SP – 4
IRRELEVANT
DATA
SP – 3
CCR
SP – 2
A
SP – 1
X
SP
PC – 1
PC – 1
HIGH BYTE LOW BYTE
PC
PC + 1
OPCODE
OPERAND
R/W
Figure 7-9. Interrupt Recovery Timing
MC68HC908AT32 Data Sheet, Rev. 3.1
84
Freescale Semiconductor
Program Exception Control
FROM RESET
BREAK
INTERRUPT?
I BIT
SET?
YES
NO
YES
I BIT SET?
NO
HARDWARE
INTERRUPT?
YES
NO
STACK CPU REGISTERS
SET I BIT
LOAD PC WITH INTERRUPT VECTOR
FETCH NEXT
INSTRUCTION
SWI
INSTRUCTION?
YES
NO
RTI
INSTRUCTION?
YES
UNSTACK CPU REGISTERS
NO
EXECUTE INSTRUCTION
Figure 7-10. Interrupt Processing
7.5.1.1 Hardware Interrupts
A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after
completion of the current instruction. When the current instruction is complete, the SIM checks all pending
hardware interrupts. If interrupts are not masked (I bit clear in the condition code register), and if the
corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next
instruction is fetched and executed.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
85
System Integration Module (SIM)
If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is
serviced first. Figure 7-11 demonstrates what happens when two interrupts are pending. If an interrupt is
pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the
LDA instruction is executed.
CLI
BACKGROUND
ROUTINE
LDA #$FF
INT1
PSHH
INT1 INTERRUPT SERVICE ROUTINE
PULH
RTI
INT2
PSHH
INT2 INTERRUPT SERVICE ROUTINE
PULH
RTI
Figure 7-11. Interrupt Recognition Example
The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the
INT1 RTI prefetch, this is a redundant operation.
NOTE
To maintain compatibility with the M68HC05, M6805 and M146805
Families, the H register is not pushed on the stack during interrupt entry. If
the interrupt service routine modifies the H register or uses the indexed
addressing mode, software should save the H register and then restore it
prior to exiting the routine.
7.5.1.2 SWI Instruction
The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the
interrupt mask (I bit) in the condition code register.
NOTE
A software interrupt pushes PC onto the stack. A software interrupt does
not push PC – 1, as a hardware interrupt does.
7.5.2 Reset
All reset sources always have higher priority than interrupts and cannot be arbitrated.
7.5.3 Break Interrupts
The break module can stop normal program flow at a software-programmable break point by asserting its
break interrupt output. (See Chapter 11 Break Module (BRK).) The SIM puts the CPU into the break state
MC68HC908AT32 Data Sheet, Rev. 3.1
86
Freescale Semiconductor
Low-Power Modes
by forcing it to the SWI vector location. Refer to the break interrupt subsection of each module to see how
each module is affected by the break state.
7.5.4 Status Flag Protection in Break Mode
The SIM controls whether status flags contained in other modules can be cleared during break mode. The
user can select whether flags are protected from being cleared by properly initializing the break clear flag
enable bit (BCFE) in the SIM break flag control register (SBFCR).
Protecting flags in break mode ensures that set flags will not be cleared while in break mode. This
protection allows registers to be freely read and written during break mode without losing status flag
information.
Setting the BCFE bit enables the clearing mechanisms. Once cleared in break mode, a flag remains
cleared even when break mode is exited. Status flags with a two-step clearing mechanism — for example,
a read of one register followed by the read or write of another — are protected, even when the first step
is accomplished prior to entering break mode. Upon leaving break mode, execution of the second step
will clear the flag as normal.
7.6 Low-Power Modes
Executing the WAIT or STOP instruction puts the MCU in a low-power mode for standby situations. The
SIM holds the CPU in a non-clocked state. The operation of each of these modes is described here. Both
STOP and WAIT clear the interrupt mask (I) in the condition code register, allowing interrupts to occur.
7.6.1 Wait Mode
In wait mode, the CPU clocks are inactive while one set of peripheral clocks continues to run. Figure 7-12
shows the timing for wait mode entry.
A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled.
Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred.
Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode.
Some modules can be programmed to be active in wait mode.
Wait mode can also be exited by a reset or break. A break interrupt during wait mode sets the SIM break
stop/wait bit, SBSW, in the SIM break status register (SBSR). If the COP disable bit, COPD, in the
configuration register is logic 0, then the computer operating properly module (COP) is enabled and
remains active in wait mode.
IAB
IDB
WAIT ADDR
WAIT ADDR + 1
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
SAME
SAME
R/W
NOTE: Previous data can be operand data or the WAIT opcode, depending on the last instruction.
Figure 7-12. Wait Mode Entry Timing
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
87
System Integration Module (SIM)
Figure 7-13 and Figure 7-14 show the timing for WAIT recovery.
IAB
$6E0B
IDB
$A6
$A6
$6E0C
$A6
$01
$00FF
$00FE
$0B
$00FD
$00FC
$6E
EXITSTOPWAIT
NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt OR break interrupt
Figure 7-13. Wait Recovery from Interrupt or Break
32
CYCLES
IAB
IDB
$6E0B
$A6
$A6
32
CYCLES
RSTVCTH
RST VCTL
$A6
RST
CGMXCLK
Figure 7-14. Wait Recovery from Internal Reset
7.6.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a
module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset or break also causes an exit from stop mode.
The SIM disables the clock generator module outputs (CGMOUT and CGMXCLK) in stop mode, stopping
the CPU and peripherals. Stop recovery time is selectable using the SSREC bit in the configuration
register (CONFIG-1). If SSREC is set, stop recovery is reduced from the normal delay of 4096 CGMXCLK
cycles down to 32. This is ideal for applications using canned oscillators that do not require long startup
times from stop mode.
NOTE
External crystal applications should use the full stop recovery time by
clearing the SSREC bit.
A break interrupt during stop mode sets the SIM break stop/wait bit (SBSW) in the SIM break status
register (SBSR).
The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop
recovery. It is then used to time the recovery period. Figure 7-15 shows stop mode entry timing.
MC68HC908AT32 Data Sheet, Rev. 3.1
88
Freescale Semiconductor
SIM Registers
CPUSTOP
IAB
STOP ADDR
IDB
STOP ADDR + 1
PREVIOUS DATA
SAME
NEXT OPCODE
SAME
SAME
SAME
R/W
NOTE: Previous data can be operand data or the STOP opcode, depending on the last
instruction.
Figure 7-15. Stop Mode Entry Timing
STOP RECOVERY PERIOD
CGMXCLK
INT/BREAK
IAB
STOP + 2
STOP +1
STOP + 2
SP
SP – 1
SP – 2
SP – 3
Figure 7-16. Stop Mode Recovery from Interrupt or Break
7.7 SIM Registers
The SIM has three memory mapped registers.
7.7.1 SIM Break Status Register
The SIM break status register contains a flag to indicate that a break caused an exit from stop or wait
mode.
Address:
$FE00
Bit 7
Read:
Write:
R
6
5
R
R
4
R
3
R
2
R
1
SBSW
See Note
Reset:
Bit 0
R
0
R
= Reserved
NOTE: Writing a logic 0 clears SBSW.
Figure 7-17. SIM Break Status Register (SBSR)
SBSW — SIM Break Stop/Wait Bit
This status bit is useful in applications requiring a return to wait or stop mode after exiting from a break
interrupt. Clear SBSW by writing a logic 0 to it. Reset clears SBSW.
1 = Stop mode or wait mode was exited by break interrupt.
0 = Stop mode or wait mode was not exited by break interrupt.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
89
System Integration Module (SIM)
SBSW can be read within the break state SWI routine. The user can modify the return address on the
stack by subtracting one from it. The following code is an example of this. Writing 0 to the SBSW bit
clears it.
; This code works if the H register has been pushed onto the stack in the break
; service routine software. This code should be executed at the end of the
; break service routine software.
HIBYTE
EQU
5
LOBYTE
EQU
6
;
If not SBSW, do RTI
BRCLR
SBSW,SBSR, RETURN ; See if wait mode or stop mode was exited
; by break.
TST
LOBYTE,SP
; If RETURNLO is not zero,
BNE
DOLO
; then just decrement low byte.
DEC
HIBYTE,SP
; Else deal with high byte, too.
DOLO
DEC
LOBYTE,SP
; Point to WAIT/STOP opcode.
RETURN
PULH
RTI
; Restore H register.
7.7.2 SIM Reset Status Register
This read-only register contains flags to show reset sources. A power-on reset sets the POR flag and
clears all other flags. Reset sources other than power-on reset do not clear all other flags.
Reading the reset status register clears all reset flags. Reset service can read the reset status register to
clear the register after power-on reset and to determine the source of any subsequent reset.
NOTE
Only a read of the reset status register clears all reset flags. After multiple
resets from different sources without reading the register, multiple flags
remain set.
Address:
Read:
$FE01
Bit 7
6
5
4
3
2
1
Bit 0
POR
PIN
COP
ILOP
ILAD
0
LVI
0
1
X
0
0
0
0
X
0
Write:
Reset:
= Unimplemented
X = Indeterminate
Figure 7-18. SIM Reset Status Register (SRSR)
POR — Power-On Reset Flag
1 = Power-on reset since last read of RSR
0 = Read of RSR since last power-on reset
PIN — External Reset Flag
1 = External reset since last read of RSR
0 = Power-on reset or read of RSR since last external reset
MC68HC908AT32 Data Sheet, Rev. 3.1
90
Freescale Semiconductor
SIM Registers
COP — COP Reset Flag
1 = COP reset since last read of RSR
0 = Power-on reset or read of RSR since last COP reset
ILOP — Illegal Opcode Reset Flag
1 = Illegal opcode reset since last read of RSR
0 = Power-on reset or read of RSR since last illegal opcode reset
ILAD — Illegal Address Reset Flag
1 = Illegal address reset since last read of RSR
0 = Power-on reset or read of RSR since last illegal address reset
LVI — Low-Voltage Inhibit Reset Flag
1 = LVI reset since last read of RSR
0 = Power-on reset or read of RSR since last LVI reset
7.7.3 SIM Break Flag Control Register
The SIM break control register contains a bit that enables software to clear status bits while the MCU is
in a break state.
Address:
Read:
Write:
Reset:
$FE03
Bit 7
6
5
4
3
2
1
Bit 0
BCFE
R
R
R
R
R
R
R
0
R
0
= Reserved
Figure 7-19. SIM Break Flag Control Register (SBFCR)
BCFE — Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by accessing status registers while the MCU is
in a break state. To clear status bits during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
91
System Integration Module (SIM)
MC68HC908AT32 Data Sheet, Rev. 3.1
92
Freescale Semiconductor
Chapter 8
Clock Generator Module (CGM)
8.1 Introduction
The clock generator module (CGM) generates the crystal clock signal, CGMXCLK, which operates at the
frequency of the crystal. The CGM also generates the base clock signal, CGMOUT, from which the
system clocks are derived. CGMOUT is based on either the crystal clock divided by two or the
phase-locked loop (PLL) clock, CGMVCLK, divided by two. The PLL is a frequency generator designed
for use with 1-MHz to 16-MHz crystals or ceramic resonators. The PLL can generate an 8-MHz bus
frequency without using a 32-MHz crystal.
8.2 Features
Features of the CGM include:
• Phase-locked loop with output frequency in integer multiples of the crystal reference
• Programmable hardware voltage-controlled oscillator (VCO) for low-jitter operation
• Automatic bandwidth control mode for low-jitter operation
• Automatic frequency lock detector
• CPU interrupt on entry or exit from locked condition
8.3 Functional Description
The CGM consists of three major submodules:
• Crystal oscillator circuit — The crystal oscillator circuit generates the constant crystal frequency
clock, CGMXCLK.
• Phase-locked loop (PLL) — The PLL generates the programmable VCO frequency clock
CGMVCLK.
• Base clock selector circuit — This software-controlled circuit selects either CGMXCLK divided by
two or the VCO clock, CGMVCLK, divided by two as the base clock, CGMOUT. The system clocks
are derived from CGMOUT.
Figure 8-1 shows the structure of the CGM.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
93
Clock Generator Module (CGM)
CRYSTAL OSCILLATOR
OSC2
STOP RECOVERY COUNTER,
COP PRESCALER,
RESET COUNTER,
SCI BAUD RATE GENERATOR
CGMXCLK
OSC1
SIMOSCEN
÷2
CLOCK
SELECT
CIRCUIT
CGMRDV
÷2
A
CGMOUT
B S
CPU CLOCK,
BUS CLOCK
WHEN S = 0, CGMOUT = B
CGMRCLK
BCS
USER MODE
VDDA
CGMXFC
VSS
PC3 PIN
VRS7–VRS4
MONITOR MODE
PHASE
DETECTOR
VOLTAGE
CONTROLLED
OSCILLATOR
LOOP
FILTER
PLL ANALOG
LOCK
DETECTOR
LOCK
BANDWIDTH
CONTROL
AUTO
ACQ
INTERRUPT
CONTROL
PLLIE
CGMINT
PLLF
MUL7–MUL4
CGMVDV
FREQUENCY
DIVIDER
CGMVCLK
Figure 8-1. CGM Block Diagram
MC68HC908AT32 Data Sheet, Rev. 3.1
94
Freescale Semiconductor
Functional Description
Addr.
Register Name
$001C
PLL Bandwidth Control Read:
Register (PBWC) Write:
See page 103. Reset:
$001D
$001E
Bit 7
PLL Control Register Read:
(PCTL) Write:
See page 101. Reset:
PLL Programming Register Read:
(PPG) Write:
See page 104. Reset:
PLLIE
0
AUTO
6
PLLF
0
LOCK
5
4
PLLON
BCS
1
0
ACQ
XLD
3
2
1
Bit 0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
MUL7
MUL6
MUL5
MUL4
VRS7
VRS6
VRS5
VRS4
0
1
1
0
0
1
1
0
= Unimplemented
Figure 8-2. I/O Register Summary
Table 8-1. I/O Register Address Summary
Register
PCTL
PBWC
PPG
Address
$001C
$001D
$001E
8.3.1 Crystal Oscillator Circuit
The crystal oscillator circuit consists of an inverting amplifier and an external crystal. The OSC1 pin is the
input to the amplifier and the OSC2 pin is the output. The SIMOSCEN signal enables the crystal oscillator
circuit.
The CGMXCLK signal is the output of the crystal oscillator circuit and runs at a rate equal to the crystal
frequency. CGMXCLK is then buffered to produce CGMRCLK, the PLL reference clock.
CGMXCLK can be used by other modules which require precise timing for operation. The duty cycle of
CGMXCLK is not guaranteed to be 50 percent and depends on external factors, including the crystal and
related external components.
An externally generated clock also can feed the OSC1 pin of the crystal oscillator circuit. Connect the
external clock to the OSC1 pin and let the OSC2 pin float.
8.3.2 Phase-Locked Loop Circuit (PLL)
The PLL is a frequency generator that can operate in either acquisition mode or tracking mode, depending
on the accuracy of the output frequency. The PLL can change between acquisition and tracking modes
either automatically or manually.
8.3.2.1 Circuits
The PLL consists of these circuits:
• Voltage-controlled oscillator (VCO)
• Modulo VCO frequency divider
• Phase detector
• Loop filter
• Lock detector
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
95
Clock Generator Module (CGM)
The operating range of the VCO is programmable for a wide range of frequencies and for maximum
immunity to external noise, including supply and CGMXFC noise. The VCO frequency is bound to a range
from roughly one-half to twice the center-of-range frequency, fVRS. Modulating the voltage on the
CGMXFC pin changes the frequency within this range. By design, fVRS is equal to the nominal
center-of-range frequency, fNOM, (4.9152 MHz) times a linear factor L or (L)fNOM.
CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK. CGMRCLK runs at a frequency,
fRCLK, and is fed to the PLL through a buffer. The buffer output is the final reference clock, CGMRDV,
running at a frequency fRDV = fRCLK.
The VCO’s output clock, CGMVCLK, running at a frequency fVCLK, is fed back through a programmable
modulo divider. The modulo divider reduces the VCO clock by a factor, N. The divider’s output is the VCO
feedback clock, CGMVDV, running at a frequency fVDV = fVCLK/N. See 8.3.2.4 Programming the PLL for
more information.
The phase detector then compares the VCO feedback clock, CGMVDV, with the final reference clock,
CGMRDV. A correction pulse is generated based on the phase difference between the two signals. The
loop filter then slightly alters the dc voltage on the external capacitor connected to CGMXFC based on
the width and direction of the correction pulse. The filter can make fast or slow corrections depending on
its mode, described in 8.3.2.2 Acquisition and Tracking Modes. The value of the external capacitor and
the reference frequency determine the speed of the corrections and the stability of the PLL.
The lock detector compares the frequencies of the VCO feedback clock, CGMVDV, and the final
reference clock, CGMRDV. Therefore, the speed of the lock detector is directly proportional to the final
reference frequency, fRDV. The circuit determines the mode of the PLL and the lock condition based on
this comparison.
8.3.2.2 Acquisition and Tracking Modes
The PLL filter is manually or automatically configurable into one of two operating modes:
• Acquisition mode — In acquisition mode, the filter can make large frequency corrections to the
VCO. This mode is used at PLL startup or when the PLL has suffered a severe noise hit and the
VCO frequency is far off the desired frequency. When in acquisition mode, the ACQ bit is clear in
the PLL bandwidth control register. (See 8.5.2 PLL Bandwidth Control Register.)
• Tracking mode — In tracking mode, the filter makes only small corrections to the frequency of the
VCO. PLL jitter is much lower in tracking mode, but the response to noise is also slower. The PLL
enters tracking mode when the VCO frequency is nearly correct, such as when the PLL is selected
as the base clock source. (See 8.3.3 Base Clock Selector Circuit.) The PLL is automatically in
tracking mode when it’s not in acquisition mode or when the ACQ bit is set.
8.3.2.3 Manual and Automatic PLL Bandwidth Modes
The PLL can change the bandwidth or operational mode of the loop filter manually or automatically.
In automatic bandwidth control mode (AUTO = 1), the lock detector automatically switches between
acquisition and tracking modes. Automatic bandwidth control mode also is used to determine when the
VCO clock, CGMVCLK, is safe to use as the source for the base clock, CGMOUT. (See 8.5.2 PLL
Bandwidth Control Register.) If PLL CPU interrupt requests are enabled, the software can wait for a PLL
CPU interrupt request and then check the LOCK bit. If CPU interrupts are disabled, software can poll the
LOCK bit continuously (during PLL startup, usually) or at periodic intervals. In either case, when the LOCK
bit is set, the VCO clock is safe to use as the source for the base clock. (See 8.3.3 Base Clock Selector
Circuit.) If the VCO is selected as the source for the base clock and the LOCK bit is clear, the PLL has
MC68HC908AT32 Data Sheet, Rev. 3.1
96
Freescale Semiconductor
Functional Description
suffered a severe noise hit and the software must take appropriate action, depending on the application.
See 8.6 Interrupts.
These conditions apply when the PLL is in automatic bandwidth control mode:
• The ACQ bit (see 8.5.2 PLL Bandwidth Control Register) is a read-only indicator of the mode of the
filter. See 8.3.2.2 Acquisition and Tracking Modes.
• The ACQ bit is set when the VCO frequency is within a certain tolerance, ∆TRK, and is cleared when
the VCO frequency is out of a certain tolerance, ∆UNT. See Chapter 29 Electrical Specifications.
• The LOCK bit is a read-only indicator of the locked state of the PLL.
• The LOCK bit is set when the VCO frequency is within a certain tolerance, ∆Lock, and is cleared
when the VCO frequency is out of a certain tolerance, ∆UNL. See Chapter 29 Electrical
Specifications.
• CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s lock condition changes, toggling
the LOCK bit. (See 8.5.1 PLL Control Register.)
The PLL also can operate in manual mode (AUTO = 0). Manual mode is used by systems that do not
require an indicator of the lock condition for proper operation. Such systems typically operate well below
fBUSMAX and require fast startup. The following conditions apply when in manual mode:
• ACQ is a writable control bit that controls the mode of the filter. Before turning on the PLL in manual
mode, the ACQ bit must be clear.
• Before entering tracking mode (ACQ = 1), software must wait a given time, tACQ (See Chapter 29
Electrical Specifications), after turning on the PLL by setting PLLON in the PLL control register
(PCTL).
• Software must wait a given time, tAL, after entering tracking mode before selecting the PLL as the
clock source to CGMOUT (BCS = 1).
• The LOCK bit is disabled.
• CPU interrupts from the CGM are disabled.
8.3.2.4 Programming the PLL
Use this 3-step procedure to program the PLL.
1. Choose the desired bus frequency, fBUSDES.
Example: fBUSDES = 8 MHz
2. Calculate the desired VCO frequency, fVCLKDES.
fVCLKDES = 4 × fBUSDES
Example: fVCLKDES = 4 × 8 MHz = 32 MHz
3. Using a reference frequency, fRCLK, equal to the crystal frequency, calculate the VCO frequency
multiplier, N. Round the result to the nearest integer.
f VCLKDES
N = ----------------------------f RCLK
32 MHz
4 MHz
Example: N = -------------------- = 8
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
97
Clock Generator Module (CGM)
4. Calculate the VCO frequency, fVCLK.
f VCLK = N × f RCLK
Example: fVCLK = 8 × 4 MHz = 32 MHz
5. Calculate the bus frequency, fBus, and compare fBus with fBUSDES.
f
fBus = VCLK
4
Example: fBus =
32 MHz
= 8 MHZ
4
6. If the calculated fBus is not within the tolerance limits of the application, select another fBUSDEs or
another fRCLK.
7. Using the value 4.9152 MHz for fNOM, calculate the VCO linear range multiplier, L. The linear range
multiplier controls the frequency range of the PLL.
⎛ f VCLK⎞
L = Round ⎜ -----------------⎟
⎝ f NOM ⎠
Example:
32 MHz
L = -------------------------------- = 7
4.9152 MHz
8. Calculate the VCO center-of-range frequency, fVRS. The center-of-range frequency is the midpoint
between the minimum and maximum frequencies attainable by the PLL.
fVRS = L × fNOM
Example: fVRS = 7 × 4.9152 MHz = 34.4 MHz
NOTE
For proper operation,
f NOM
f VRS – f VCLK ≤ -------------2
.
Exceeding the recommended maximum bus frequency or VCO frequency
can crash the MCU.
9. Program the PLL registers accordingly:
a. In the upper four bits of the PLL programming register (PPG), program the binary equivalent
of N.
b. In the lower four bits of the PLL programming register (PPG), program the binary equivalent
of L.
MC68HC908AT32 Data Sheet, Rev. 3.1
98
Freescale Semiconductor
Functional Description
8.3.2.5 Special Programming Exceptions
The programming method described in 8.3.2.4 Programming the PLL does not account for two possible
exceptions. A value of 0 for N or L is meaningless when used in the equations given. To account for these
exceptions:
• A 0 value for N is interpreted the same as a value of 1.
• A 0 value for L disables the PLL and prevents its selection as the source for the base clock. See
8.3.3 Base Clock Selector Circuit.
8.3.3 Base Clock Selector Circuit
This circuit is used to select either the crystal clock, CGMXCLK, or the VCO clock, CGMVCLK, as the
source of the base clock, CGMOUT. The two input clocks go through a transition control circuit that waits
up to three CGMXCLK cycles and three CGMVCLK cycles to change from one clock source to the other.
During this time, CGMOUT is held in stasis. The output of the transition control circuit is then divided by
two to correct the duty cycle. Therefore, the bus clock frequency, which is one-half of the base clock
frequency, is one-fourth the frequency of the selected clock (CGMXCLK or CGMVCLK).
The BCS bit in the PLL control register (PCTL) selects which clock drives CGMOUT. The VCO clock
cannot be selected as the base clock source if the PLL is not turned on. The PLL cannot be turned off if
the VCO clock is selected. The PLL cannot be turned on or off simultaneously with the selection or
deselection of the VCO clock. The VCO clock also cannot be selected as the base clock source if the
factor L is programmed to a 0. This value would set up a condition inconsistent with the operation of the
PLL, so that the PLL would be disabled and the crystal clock would be forced as the source of the base
clock.
8.3.4 CGM External Connections
In its typical configuration, the CGM requires seven external components. Five of these are for the crystal
oscillator and two are for the PLL.
The crystal oscillator is normally connected in a Pierce oscillator configuration, as shown in Figure 8-3.
Figure 8-3 shows only the logical representation of the internal components and may not represent actual
circuitry. The oscillator configuration uses five components:
• Crystal, X1
• Fixed capacitor, C1
• Tuning capacitor, C2 (can also be a fixed capacitor)
• Feedback resistor, RB
• Series resistor, RS (optional)
The series resistor (RS) may not be required for all ranges of operation, especially with high-frequency
crystals. Refer to the crystal manufacturer’s data for more information.
Figure 8-3 also shows the external components for the PLL:
• Bypass capacitor, CBYP
• Filter capacitor, CF
Routing should be done with great care to minimize signal cross talk and noise. See 8.9 Acquisition/Lock
Time Specifications for routing information and more information on the filter capacitor’s value and its
effects on PLL performance.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
99
Clock Generator Module (CGM)
SIMOSCEN
VDDA
CGMXFC
VSS
OSC2
OSC1
CGMXCLK
RS*
VDD
CF
CBYP
RB
X1
C1
C2
*RS can be 0 (shorted) when used with higher-frequency crystals. Refer to manufacturer’s data.
Figure 8-3. CGM External Connections
8.4 I/O Signals
The following paragraphs describe the CGM input/output (I/O) signals.
8.4.1 Crystal Amplifier Input Pin (OSC1)
The OSC1 pin is an input to the crystal oscillator amplifier.
8.4.2 Crystal Amplifier Output Pin (OSC2)
The OSC2 pin is the output of the crystal oscillator inverting amplifier.
8.4.3 External Filter Capacitor Pin (CGMXFC)
The CGMXFC pin is required by the loop filter to filter out phase corrections. A small external capacitor is
connected to this pin.
NOTE
To prevent noise problems, CF should be placed as close to the CGMXFC
pin as possible with minimum routing distances and no routing of other
signals across the CF connection.
8.4.4 Analog Power Pin (VDDA)
VDDA is a power pin used by the analog portions of the PLL. Connect the VDDA pin to the same voltage
potential as the VDD pin.
NOTE
Route VDDA carefully for maximum noise immunity and place bypass
capacitors as close as possible to the package.
MC68HC908AT32 Data Sheet, Rev. 3.1
100
Freescale Semiconductor
CGM Registers
8.4.5 Oscillator Enable Signal (SIMOSCEN)
The SIMOSCEN signal enables the oscillator and PLL.
8.4.6 Crystal Output Frequency Signal (CGMXCLK)
CGMXCLK is the crystal oscillator output signal. It runs at the full speed of the crystal (fXCLK) and comes
directly from the crystal oscillator circuit. Figure 8-3 shows only the logical relation of CGMXCLK to OSC1
and OSC2 and may not represent the actual circuitry. The duty cycle of CGMXCLK is unknown and may
depend on the crystal and other external factors. Also, the frequency and amplitude of CGMXCLK can be
unstable at startup.
8.4.7 CGM Base Clock Output (CGMOUT)
CGMOUT is the clock output of the CGM. This signal is used to generate the MCU clocks. CGMOUT is
a 50 percent duty cycle clock running at twice the bus frequency. CGMOUT is software programmable to
be either the oscillator output, CGMXCLK, divided by two or the VCO clock, CGMVCLK, divided by two.
8.4.8 CGM CPU Interrupt (CGMINT)
CGMINT is the CPU interrupt signal generated by the PLL lock detector.
8.5 CGM Registers
Three registers control and monitor operation of the CGM:
• PLL control register (PCTL)
• PLL bandwidth control register (PBWC)
• PLL programming register (PPG)
8.5.1 PLL Control Register
The PLL control register contains the interrupt enable and flag bits, the on/off switch, and the base clock
selector bit.
Address:
$001C
Bit 7
Read:
Write:
Reset:
PLLIE
0
6
PLLF
0
5
4
PLLON
BCS
1
0
3
2
1
Bit 0
1
1
1
1
1
1
1
1
= Unimplemented
Figure 8-4. PLL Control Register (PCTL)
PLLIE — PLL Interrupt Enable Bit
This read/write bit enables the PLL to generate a CPU interrupt request when the LOCK bit toggles,
setting the PLL flag, PLLF. When the AUTO bit in the PLL bandwidth control register (PBWC) is clear,
PLLIE cannot be written and reads as logic 0. Reset clears the PLLIE bit.
1 = PLL CPU interrupt requests enabled
0 = PLL CPU interrupt requests disabled
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
101
Clock Generator Module (CGM)
PLLF — PLL Flag Bit
This read-only bit is set whenever the LOCK bit toggles. PLLF generates a CPU interrupt request if the
PLLIE bit also is set. PLLF always reads as logic 0 when the AUTO bit in the PLL bandwidth control
register (PBWC) is clear. Clear the PLLF bit by reading the PLL control register. Reset clears the PLLF
bit.
1 = Change in lock condition
0 = No change in lock condition
NOTE
Do not inadvertently clear the PLLF bit. Be aware that any read or
read-modify-write operation on the PLL control register clears the PLLF bit.
PLLON — PLL On Bit
This read/write bit activates the PLL and enables the VCO clock, CGMVCLK. PLLON cannot be
cleared if the VCO clock is driving the base clock, CGMOUT (BCS = 1). (See 8.3.3 Base Clock Selector
Circuit.) Reset sets this bit so that the loop can stabilize as the MCU is powering up.
1 = PLL on
0 = PLL off
BCS — Base Clock Select Bit
This read/write bit selects either the crystal oscillator output, CGMXCLK, or the VCO clock,
CGMVCLK, as the source of the CGM output, CGMOUT. CGMOUT frequency is one-half the
frequency of the selected clock. BCS cannot be set while the PLLON bit is clear. After toggling BCS,
it may take up to three CGMXCLK and three CGMVCLK cycles to complete the transition from one
source clock to the other. During the transition, CGMOUT is held in stasis. (See 8.3.3 Base Clock
Selector Circuit.) Reset and the STOP instruction clear the BCS bit.
1 = CGMVCLK divided by two drives CGMOUT
0 = CGMXCLK divided by two drives CGMOUT
NOTE
PLLON and BCS have built-in protection that prevents the base clock
selector circuit from selecting the VCO clock as the source of the base clock
if the PLL is off. Therefore, PLLON cannot be cleared when BCS is set, and
BCS cannot be set when PLLON is clear. If the PLL is off (PLLON = 0),
selecting CGMVCLK requires two writes to the PLL control register. See
8.3.3 Base Clock Selector Circuit.
PCTL3–PCTL — Unimplemented
These bits provide no function and always read as logic 1s.
MC68HC908AT32 Data Sheet, Rev. 3.1
102
Freescale Semiconductor
CGM Registers
8.5.2 PLL Bandwidth Control Register
The PLL bandwidth control register:
• Selects automatic or manual (software-controlled) bandwidth control mode
• Indicates when the PLL is locked
• In automatic bandwidth control mode, indicates when the PLL is in acquisition or tracking mode
• In manual operation, forces the PLL into acquisition or tracking mode
Address:
$001D
Bit 7
Read:
Write:
Reset:
AUTO
0
6
5
LOCK
0
4
ACQ
XLD
0
0
3
2
1
Bit 0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 8-5. PLL Bandwidth Control Register (PBWC)
AUTO — Automatic Bandwidth Control Bit
This read/write bit selects automatic or manual bandwidth control. When initializing the PLL for manual
operation (AUTO = 0), clear the ACQ bit before turning on the PLL. Reset clears the AUTO bit.
1 = Automatic bandwidth control
0 = Manual bandwidth control
LOCK — Lock Indicator Bit
When the AUTO bit is set, LOCK is a read-only bit that becomes set when the VCO clock, CGMVCLK,
is locked (running at the programmed frequency). When the AUTO bit is clear, LOCK reads as logic 0
and has no meaning. Reset clears the LOCK bit.
1 = VCO frequency correct or locked
0 = VCO frequency incorrect or unlocked
ACQ — Acquisition Mode Bit
When the AUTO bit is set, ACQ is a read-only bit that indicates whether the PLL is in acquisition mode
or tracking mode. When the AUTO bit is clear, ACQ is a read/write bit that controls whether the PLL is
in acquisition or tracking mode.
In automatic bandwidth control mode (AUTO = 1), the last-written value from manual operation is
stored in a temporary location and is recovered when manual operation resumes. Reset clears this bit,
enabling acquisition mode.
1 = Tracking mode
0 = Acquisition mode
XLD — Crystal Loss Detect Bit
When the VCO output, CGMVCLK, is driving CGMOUT, this read/write bit can indicate whether the
crystal reference frequency is active or not.
1 = Crystal reference not active
0 = Crystal reference active
To check the status of the crystal reference, do the following:
1. Write a logic 1 to XLD.
2. Wait N × 4 cycles. N is the VCO frequency multiplier.
3. Read XLD.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
103
Clock Generator Module (CGM)
The crystal loss detect function works only when the BCS bit is set, selecting CGMVCLK to drive
CGMOUT. When BCS is clear, XLD always reads as logic 0.
Bits 3–0 — Reserved for Test
These bits enable test functions not available in user mode. To ensure software portability from
development systems to user applications, software should write 0s to bits 3–0 when writing to PBWC.
8.5.3 PLL Programming Register
The PLL programming register contains the programming information for the modulo feedback divider
and the programming information for the hardware configuration of the VCO.
Address:
Read:
Write:
Reset:
$001E
Bit 7
6
5
4
3
2
1
Bit 0
MUL7
MUL6
MUL5
MUL4
VRS7
VRS6
VRS5
VRS4
0
1
1
0
0
1
1
0
Figure 8-6. PLL Programming Register (PPG)
MUL7–MUL4 — Multiplier Select Bits
These read/write bits control the modulo feedback divider that selects the VCO frequency multiplier,
N. (See 8.3.2.1 Circuits and 8.3.2.4 Programming the PLL.) A value of $0 in the multiplier select bits
configures the modulo feedback divider the same as a value of $1. Reset initializes these bits to $6 to
give a default multiply value of 6. See Table 8-2.
NOTE
The multiplier select bits have built-in protection that prevents them from
being written when the PLL is on (PLLON = 1).
Table 8-2. VCO Frequency Multiplier (N) Selection
MUL7:MUL6:MUL5:MUL4
VCO Frequency Multiplier (N)
0000
1
0001
1
0010
2
0011
3
1101
13
1110
14
1111
15
VRS7–VRS4 — VCO Range Select Bits
These read/write bits control the hardware center-of-range linear multiplier L, which controls the
hardware center-of-range frequency, fVRS. (See 8.3.2.1 Circuits, 8.3.2.4 Programming the PLL, and
8.5.1 PLL Control Register.) VRS7–VRS4 cannot be written when the PLLON bit in the PLL control
register (PCTL) is set. See 8.3.2.5 Special Programming Exceptions. A value of $0 in the VCO range
MC68HC908AT32 Data Sheet, Rev. 3.1
104
Freescale Semiconductor
Interrupts
select bits disables the PLL and clears the BCS bit in the PCTL. (See 8.3.3 Base Clock Selector Circuit
and 8.3.2.5 Special Programming Exceptions for more information.) Reset initializes the bits to $6 to
give a default range multiply value of 6.
NOTE
The VCO range select bits have built-in protection that prevents them from
being written when the PLL is on (PLLON = 1) and prevents selection of the
VCO clock as the source of the base clock (BCS = 1) if the VCO range
select bits are all clear.
The VCO range select bits must be programmed correctly. Incorrect
programming can result in failure of the PLL to achieve lock.
8.6 Interrupts
When the AUTO bit is set in the PLL bandwidth control register (PBWC), the PLL can generate a CPU
interrupt request every time the LOCK bit changes state. The PLLIE bit in the PLL control register (PCTL)
enables CPU interrupt requests from the PLL. PLLF, the interrupt flag in the PCTL, becomes set whether
CPU interrupt requests are enabled or not. When the AUTO bit is clear, CPU interrupt requests from the
PLL are disabled and PLLF reads as logic 0.
Software should read the LOCK bit after a PLL CPU interrupt request to see if the request was due to an
entry into lock or an exit from lock. When the PLL enters lock, the VCO clock, CGMVCLK, divided by two
can be selected as the CGMOUT source by setting BCS in the PCTL. When the PLL exits lock, the VCO
clock frequency is corrupt, and appropriate precautions should be taken. If the application is not frequency
sensitive, CPU interrupt requests should be disabled to prevent PLL interrupt service routines from
impeding software performance or from exceeding stack limitations.
NOTE
Software can select the CGMVCLK divided by two as the CGMOUT source
even if the PLL is not locked (LOCK = 0). Therefore, software should make
sure the PLL is locked before setting the BCS bit.
8.7 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power standby modes.
8.7.1 Wait Mode
The CGM remains active in wait mode. Before entering wait mode, software can disengage and turn off
the PLL by clearing the BCS and PLLON bits in the PLL control register (PCTL). Less power-sensitive
applications can disengage the PLL without turning it off. Applications that require the PLL to wake the
MCU from wait mode also can deselect the PLL output without turning off the PLL.
8.7.2 Stop Mode
The STOP instruction disables the CGM and holds low all CGM outputs (CGMXCLK, CGMOUT, and
CGMINT).
If CGMOUT is being driven by CGMVCLK and a STOP instruction is executed, the PLL will clear the BCS
bit in the PLL control register, causing CGMOUT to be driven by CGMXCLK. When the MCU recovers
from STOP, the crystal clock divided by two drives CGMOUT and BCS remains clear.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
105
Clock Generator Module (CGM)
8.8 CGM during Break Interrupts
The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the
break state. See Chapter 11 Break Module (BRK).
To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status
bit is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect the PLLF bit during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its
default state), software can read and write the PLL control register during the break state without affecting
the PLLF bit.
8.9 Acquisition/Lock Time Specifications
The acquisition and lock times of the PLL are, in many applications, the most critical PLL design
parameters. Proper design and use of the PLL ensures the highest stability and lowest acquisition/lock
times.
8.9.1 Acquisition/Lock Time Definitions
Typical control systems refer to the acquisition time or lock time as the reaction time, within specified
tolerances, of the system to a step input. In a PLL, the step input occurs when the PLL is turned on or
when it suffers a noise hit. The tolerance is usually specified as a percent of the step input or when the
output settles to the desired value plus or minus a percent of the frequency change. Therefore, the
reaction time is constant in this definition, regardless of the size of the step input. For example, consider
a system with a 5 percent acquisition time tolerance. If a command instructs the system to change from
0 Hz to 1 MHz, the acquisition time is the time taken for the frequency to reach 1 MHz ±50 kHz.
Fifty kHz = 5% of the 1-MHz step input. If the system is operating at 1 MHz and suffers a –100 kHz noise
hit, the acquisition time is the time taken to return from 900 kHz to 1 MHz ±5 kHz. Five kHz = 5% of the
100-kHz step input.
Other systems refer to acquisition and lock times as the time the system takes to reduce the error between
the actual output and the desired output to within specified tolerances. Therefore, the acquisition or lock
time varies according to the original error in the output. Minor errors may not even be registered. Typical
PLL applications prefer to use this definition because the system requires the output frequency to be
within a certain tolerance of the desired frequency regardless of the size of the initial error.
The discrepancy in these definitions makes it difficult to specify an acquisition or lock time for a typical
PLL. Therefore, the definitions for acquisition and lock times for this module are:
• Acquisition time, tACQ, is the time the PLL takes to reduce the error between the actual output
frequency and the desired output frequency to less than the tracking mode entry tolerance, ∆TRK.
Acquisition time is based on an initial frequency error, (fDES – fORIG)/fDES, of not more than ±100
percent. In automatic bandwidth control mode (see 8.3.2.3 Manual and Automatic PLL Bandwidth
Modes), acquisition time expires when the ACQ bit becomes set in the PLL bandwidth control
register (PBWC).
• Lock time, tLock, is the time the PLL takes to reduce the error between the actual output frequency
and the desired output frequency to less than the lock mode entry tolerance, ∆Lock. Lock time is
based on an initial frequency error, (fDES – fORIG)/fDES, of not more than ±100 percent. In automatic
bandwidth control mode, lock time expires when the LOCK bit becomes set in the PLL bandwidth
control register (PBWC). See 8.3.2.3 Manual and Automatic PLL Bandwidth Modes.
MC68HC908AT32 Data Sheet, Rev. 3.1
106
Freescale Semiconductor
Acquisition/Lock Time Specifications
Obviously, the acquisition and lock times can vary according to how large the frequency error is and may
be shorter or longer in many cases.
8.9.2 Parametric Influences on Reaction Time
Acquisition and lock times are designed to be as short as possible while still providing the highest possible
stability. These reaction times are not constant, however. Many factors directly and indirectly affect the
acquisition time.
The most critical parameter which affects the reaction times of the PLL is the reference frequency, fRDV.
This frequency is the input to the phase detector and controls how often the PLL makes corrections. For
stability, the corrections must be small compared to the desired frequency, so several corrections are
required to reduce the frequency error. Therefore, the slower the reference the longer it takes to make
these corrections. This parameter is also under user control via the choice of crystal frequency fXCLK.
Another critical parameter is the external filter capacitor. The PLL modifies the voltage on the VCO by
adding or subtracting charge from this capacitor. Therefore, the rate at which the voltage changes for a
given frequency error (thus a change in charge) is proportional to the capacitor size. The size of the
capacitor also is related to the stability of the PLL. If the capacitor is too small, the PLL cannot make small
enough adjustments to the voltage and the system cannot lock. If the capacitor is too large, the PLL may
not be able to adjust the voltage in a reasonable time. See 8.9.3 Choosing a Filter Capacitor.
Also important is the operating voltage potential applied to VDDA. The power supply potential alters the
characteristics of the PLL. A fixed value is best. Variable supplies, such as batteries, are acceptable if
they vary within a known range at very slow speeds. Noise on the power supply is not acceptable,
because it causes small frequency errors which continually change the acquisition time of the PLL.
Temperature and processing also can affect acquisition time because the electrical characteristics of the
PLL change. The part operates as specified as long as these influences stay within the specified limits.
External factors, however, can cause drastic changes in the operation of the PLL. These factors include
noise injected into the PLL through the filter capacitor, filter capacitor leakage, stray impedances on the
circuit board, and even humidity or circuit board contamination.
8.9.3 Choosing a Filter Capacitor
As described in 8.9.2 Parametric Influences on Reaction Time, the external filter capacitor, CF, is critical
to the stability and reaction time of the PLL. The PLL is also dependent on reference frequency and supply
voltage. The value of the capacitor must, therefore, be chosen with supply potential and reference
frequency in mind. For proper operation, the external filter capacitor must be chosen according to this
equation:
C
F
= C
⎛ V DDA⎞
-----------------⎟
Fact ⎜⎝ f
RDV ⎠
For acceptable values of CFact, see Chapter 29 Electrical Specifications. For the value of VDDA, choose
the voltage potential at which the MCU is operating. If the power supply is variable, choose a value near
the middle of the range of possible supply values.
This equation does not always yield a commonly available capacitor size, so round to the nearest
available size. If the value is between two different sizes, choose the higher value for better stability.
Choosing the lower size may seem attractive for acquisition time improvement, but the PLL may become
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
107
Clock Generator Module (CGM)
unstable. Also, always choose a capacitor with a tight tolerance (±20 percent or better) and low
dissipation.
8.9.4 Reaction Time Calculation
The actual acquisition and lock times can be calculated using the equations below. These equations yield
nominal values under the following conditions:
• Correct selection of filter capacitor, CF. See 8.9.3 Choosing a Filter Capacitor.
• Room temperature operation
• Negligible external leakage on CGMXFC
• Negligible noise
The K factor in the equations is derived from internal PLL parameters. KACQ is the K factor when the PLL
is configured in acquisition mode, and KTRK is the K factor when the PLL is configured in tracking mode.
See 8.3.2.2 Acquisition and Tracking Modes.
t
⎛ V DDA⎞
8
= ⎜ -----------------⎟ ⎛ -----------------⎞
ACQ
⎝ f RDV ⎠ ⎝ K ACQ⎠
t
⎛ V DDA⎞
4
= ⎜ -----------------⎟ ⎛ ----------------⎞
⎝
AL
K
f
⎝ RDV ⎠ TRK⎠
t
Lock
= t
ACQ
+t
AL
Note the inverse proportionality between the lock time and the reference frequency.
In automatic bandwidth control mode, the acquisition and lock times are quantized into units based on the
reference frequency. (See 8.3.2.3 Manual and Automatic PLL Bandwidth Modes.) A certain number of
clock cycles, nACQ, is required to ascertain that the PLL is within the tracking mode entry tolerance, ∆TRK,
before exiting acquisition mode. A certain number of clock cycles, nTRK, is required to ascertain that the
PLL is within the lock mode entry tolerance, ∆Lock. Therefore, the acquisition time, tACQ, is an integer
multiple of nACQ/fRDV, and the acquisition to lock time, tAL, is an integer multiple of nTRK/fRDV.
Also, since the average frequency over the entire measurement period must be within the specified
tolerance, the total time usually is longer than tLock as calculated previously.
In manual mode, it is usually necessary to wait considerably longer than tLock before selecting the PLL
clock (see 8.3.3 Base Clock Selector Circuit) because the factors described in 8.9.2 Parametric
Influences on Reaction Time may slow the lock time considerably.
MC68HC908AT32 Data Sheet, Rev. 3.1
108
Freescale Semiconductor
Chapter 9
Configuration Register (CONFIG-1)
9.1 Introduction
This section describes the configuration register (CONFIG-1), which contains bits that configure these
options:
• Resets caused by the low-voltage inhibit (LVI) module
• Power to the LVI module
• LVI enabled during stop mode
• Stop mode recovery time (32 CGMXCLK cycles or 4096 CGMXCLK cycles)
• Computer operating properly module (COP)
• FLASH security feature(1)
9.2 Functional Description
The configuration register is a write-once register. Out of reset, the configuration register will read the
default value. Once the register is written, further writes will have no effect until a reset occurs.
NOTE
If the LVI module and the LVI reset signal are enabled, a reset occurs when
VDD falls to a voltage, LVITRIPF, and remains at or below that level for at
least nine consecutive CPU cycles. Once an LVI reset occurs, the MCU
remains in reset until VDD rises to a voltage, LVITRIPR.
Address:
Read:
Write:
Reset:
$001F
Bit 7
6
5
4
3
2
1
Bit 0
LVISTOP
R
LVIRST
LVIPWR
SSREC
COPRS
STOP
COPD
0
1
1
1
0
0
0
0
R
= Reserved
Figure 9-1. Configuration Register (CONFIG-1)
LVISTOP — LVI Stop Mode Enable Bit
LVISTOP enables the LVI module in stop mode. See Chapter 14 Low-Voltage Inhibit (LVI).
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for
unauthorized users.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
109
Configuration Register (CONFIG-1)
NOTE
To have the LVI enabled in stop mode, the LVIPWR must be at a logic 0
and the LVISTOP bit must be at a logic 1. Take note that by enabling the
LVI in stop mode, the stop IDD current will be higher and for compatibility
when using a MC68HC08AS20 a register bit will have to be written. See the
LVI section of the MC68HC08AS20 Advance Information.
LVIRST — LVI Reset Enable Bit
LVIRST enables the reset signal from the LVI module. See Chapter 14 Low-Voltage Inhibit (LVI).
1 = LVI module resets enabled
0 = LVI module resets disabled
LVIPWR — LVI Power Enable Bit
LVIPWR enables the LVI module. See Chapter 14 Low-Voltage Inhibit (LVI).
1 = LVI module power enabled
0 = LVI module power disabled
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of 32 CGMXCLK cycles instead of a
4096-CGMXCLK cycle delay. (See 7.6.2 Stop Mode.)
1 = Stop mode recovery after 32 CGMXCLK cycles
0 = Stop mode recovery after 4096 CGMXCLK cycles
NOTE
If using an external crystal oscillator, do not set the SSREC bit.
COPRS — COP Rate Select Bit
COPRS selects either the short COP timeout period or the long COP timeout period. See Chapter 13
Computer Operating Properly Module (COP).
1 = COP timeout period is 8,176 CGMXCLK cycles.
0 = COP timeout period is 262,128 CGMXCLK cycles.
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module. See Chapter 13 Computer Operating Properly Module (COP).
1 = COP module disabled
0 = COP module enabled
MC68HC908AT32 Data Sheet, Rev. 3.1
110
Freescale Semiconductor
Chapter 10
Configuration Register (CONFIG-2)
10.1 Introduction
This section describes the configuration register (CONFIG-2). This register contains bits that configure
these options:
• Configures the MC68HC908AT32 to either the MC68HC08AZ32 emulator or the MC68HC08AS20
emulator
• Enables the memory extenion for the MC68HC08AS20 emulator
• Disables the CAN module
NOTE
The MEMEXT bit comes up enabled. If you are planning or emulating an
MC68HC08AS20, be aware that this extra memory is not available.
10.2 Functional Description
The configuration register is a write-once register. Out of reset, the configuration register will read the
default. Once the register is written, further writes will have no effect until a reset occurs.
Address:
$FE09
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
MSCAND
0
0
MEMEXT
AZ32
0
0
0
1
0
0
1
0
Read:
Write:
Reset:
Figure 10-1. Configuration Register (CONFIG-2)
MSCAND — MSCAN Disable Bit
MSCAND disables the MSCAN module. See Chapter 23 MSCAN Controller.
1 = MSCAN module disabled
0 = MSCAN Module enabled
MEMEXT — Memory Extention Enable Bit
MEMEXT enables the extra memory locations in the RAM and the FLASH modules. See Chapter 2
Memory Map.
1 = Extra RAM and FLASH enabled
0 = Extra RAM and FLASH disabled
NOTE
This function comes up enabled. Be careful when emulating the
MC68HC08AS20 since this is not an option on the MC68HC08AS20.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
111
Configuration Register (CONFIG-2)
This function is primarily for the MC68HC08AS20 emulator. If this bit is
enabled in the MC68HC08AZ32 emulator configuration, there will be no
effect on the memory map, considering these memory sections already
exist.
AZ32 — AZ32 Emulator Enable Bit
AZ32 enables the MC68HC08AZ32 emulator configuration. This bit will be 0 out of reset.
1 = MC68HC08AZ32 emulator protocol enabled
0 = MC68HC08AS20 emulator protocol enabled
MC68HC908AT32 Data Sheet, Rev. 3.1
112
Freescale Semiconductor
Chapter 11
Break Module (BRK)
11.1 Introduction
The break module can generate a break interrupt that stops normal program flow at a defined address to
enter a background program.
11.2 Features
Features of the break module include:
• Accessible I/O registers during break interrupts
• Central processor unit (CPU) generated break interrupts
• Software-generated break interrupts
• COP disabling during break interrupts
11.3 Functional Description
When the internal address bus matches the value written in the break address registers, the break module
issues a breakpoint signal to the CPU. The CPU then loads the instruction register with a software
interrupt instruction (SWI) after completion of the current CPU instruction. The program counter vectors
to $FFFC and $FFFD ($FEFC and $FEFD in monitor mode).
The following events can cause a break interrupt to occur:
• A CPU-generated address (the address in the program counter) matches the contents of the break
address registers.
• Software writes a logic 1 to the BRKA bit in the break status and control register.
When a CPU-generated address matches the contents of the break address registers, the break interrupt
begins after the CPU completes its current instruction. A return-from-interrupt instruction (RTI) in the
break routine ends the break interrupt and returns the MCU to normal operation. Figure 11-1 shows the
structure of the break module.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
113
Break Module (BRK)
IAB[15:8]
BREAK ADDRESS REGISTER HIGH
8-BIT COMPARATOR
IAB[15:0]
BREAK
CONTROL
8-BIT COMPARATOR
BREAK ADDRESS REGISTER LOW
IAB[7:0]
Figure 11-1. Break Module Block Diagram
Addr.
$FE0C
$FE0D
$FE0E
Register Name
Read:
Break Address Register High (BRKH)
Write:
See page 116.
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
0
0
0
0
0
0
0
0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
BRKE
BRKA
0
0
0
0
0
0
0
0
0
0
0
0
Read:
Break Address Register Low (BRKL)
Write:
See page 116.
Reset:
Break Status and Control Read:
Register (BRKSCR) Write:
See page 115. Reset:
0
0
= Unimplemented
Figure 11-2. I/O Register Summary
Table 11-1. I/O Register Address Summary
Register
BRKH
BRKL
BSCR
Address
$FE0C
$FE0D
$FE0E
11.3.1 Flag Protection during Break Interrupts
The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the
break state.
11.3.2 CPU during Break Interrupts
The CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC:$FFFD ($FEFC:$FEFD in monitor mode)
The break interrupt begins after completion of the CPU instruction in progress. If the break address
register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.
MC68HC908AT32 Data Sheet, Rev. 3.1
114
Freescale Semiconductor
Low-Power Modes
11.3.3 TIM during Break Interrupts
A break interrupt stops the timer counter.
11.3.4 COP during Break Interrupts
The COP is disabled during a break interrupt when VDD + VHi is present on the RST pin.
11.4 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power standby modes.
11.4.1 Wait Mode
If enabled, the break module is active in wait mode. The SIM break stop/wait bit (SBSW) in the SIM break
status register indicates whether wait was exited by a break interrupt. If so, the user can modify the return
address on the stack by subtracting one from it. See 7.7.1 SIM Break Status Register.
11.4.2 Stop Mode
The break module is inactive in stop mode. The STOP instruction does not affect break module register
states. A break interrupt will cause an exit from stop mode and sets the SBSW bit in the SIM break status
register.
11.5 Break Module Registers
These registers control and monitor operation of the break module:
• Break status and control register (BRKSCR)
• Break address register high (BRKH)
• Break address register low (BRKL)
11.5.1 Break Status and Control Register
The break status and control register contains break module enable and status bits.
Address:
$FE0E
Read:
Write:
Reset:
Bit 7
6
BRKE
BRKA
0
0
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 11-3. Break Status and Control Register (BRKSCR)
BRKE — Break Enable Bit
This read/write bit enables breaks on break address register matches. Clear BRKE by writing a logic
0 to bit 7. Reset clears the BRKE bit.
1 = Breaks enabled on 16-bit address match
0 = Breaks disabled on 16-bit address match
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
115
Break Module (BRK)
BRKA — Break Active Bit
This read/write status and control bit is set when a break address match occurs. Writing a logic 1 to
BRKA generates a break interrupt. Clear BRKA by writing a logic 0 to it before exiting the break routine.
Reset clears the BRKA bit.
1 = (When read) Break address match
0 = (When read) No break address match
11.5.2 Break Address Registers
The break address registers contain the high and low bytes of the desired breakpoint address. Reset
clears the break address registers.
Register Name and Address: BRKH — $FE0C
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
0
0
0
0
0
0
0
0
Register Name and Address: BRKHL — $FE0D
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
Figure 11-4. Break Address Registers (BRKH and BRKL)
MC68HC908AT32 Data Sheet, Rev. 3.1
116
Freescale Semiconductor
Chapter 12
Monitor ROM (MON)
12.1 Introduction
This section describes the monitor ROM (MON). The monitor ROM allows complete testing of the
microcontroller unit (MCU) through a single-wire interface with a host computer.
12.2 Features
Features of the MON include:
• Normal user-mode pin functionality
• One pin dedicated to serial communication between MON and a host computer
• Standard mark/space non-return-to-zero (NRZ) communication with host computer
• 4800 baud–28.8 Kbaud communication with host computer
• Execution of code in random-access memory (RAM) or read-only memory (ROM)
12.3 Functional Description
Monitor ROM receives and executes commands from a host computer. Figure 12-1 shows a sample
circuit used to enter monitor mode and communicate with a host computer via a standard RS232
interface.
While simple monitor commands can access any memory address, the MC68HC908AT32 has a FLASH
security feature to prevent external viewing of the contents of FLASH. Proper procedures must be
followed to verify FLASH content. Access to the FLASH is denied to unauthorized users of customer
specified software.
In monitor mode, the MCU can execute host-computer code in RAM while all MCU pins except PTA0
retain normal operating mode functions. All communication between the host computer and the MCU is
through the PTA0 pin. A level-shifting and multiplexing interface is required between PTA0 and the host
computer. PTA0 is used in a wired-OR configuration and requires a pullup resistor.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
117
Monitor ROM (MON)
VDD
68HC08
10 kΩ
RST
0.1 µF
VDD + VHI
10 Ω
IRQ1/VPP
VDDA
VDDA/VDDAREF
CGMXFC
1
10 µF
+
3
4
10 µF
MC145407
0.1 µF
20
+
10 µF
OSC1
18
20 pF
17
+
+
2
19
DB-25
2
5
16
3
6
15
10 µF
X1
4.9152 MHz
10 MΩ
OSC2
VDD
20 pF
VSS
VDD
VDD
0.1 µF
7
VDD
1
MC74HC125
2
3
6
5
4
7
NOTE: Position A — Bus clock = CGMXCLK ÷ 4 or CGMVCLK ÷ 4
Position B — Bus clock = CGMXCLK ÷ 2
VDD
14
10 kΩ
PTA0
PTC3
VDD
VDD
10 kΩ
A
(SEE
NOTE.)
10 kΩ
B
PTC0
PTC1
Figure 12-1. Monitor Mode Circuit
MC68HC908AT32 Data Sheet, Rev. 3.1
118
Freescale Semiconductor
Functional Description
12.3.1 Entering Monitor Mode
Table 12-1 shows the pin conditions for entering monitor mode.
VHi(1)
PTC3 Pin
VDD +
PTA0 Pin
VHi(1)
PTC1 Pin
VDD +
PTC0 Pin
IRQ Pin
Table 12-1. Mode Selection
Mode
1
0
1
1
Monitor
CGMXCLK
CGMVCLK
----------------------------- or ----------------------------2
2
CGMOUT
-------------------------2
1
0
1
0
Monitor
CGMXCLK
CGMOUT
-------------------------2
CGMOUT
Bus
Frequency
1. For VHi, see 29.4 5.0-Volt DC Electrical Characteristics and 29.1 Maximum Ratings.
Enter monitor mode by either:
• Executing a software interrupt instruction (SWI) or
• Applying a logic 0 and then a logic 1 to the RST pin.
The MCU sends a break signal (10 consecutive logic 0s) to the host computer, indicating that it is ready
to receive a command. The break signal also provides a timing reference to allow the host to determine
the necessary baud rate.
Monitor mode uses alternate vectors for reset, SWI, and break interrupt. The alternate vectors are in the
$FE page instead of the $FF page and allow code execution from the internal monitor firmware instead
of user code. The COP module is disabled in monitor mode as long as VDD + VHi (see 29.4 5.0-Volt DC
Electrical Characteristics) is applied to either the IRQ pin or the VDD pin. See Chapter 7 System
Integration Module (SIM) for more information on modes of operation.
NOTE
Holding the PTC3 pin low when entering monitor mode causes a bypass of
a divide-by-two stage at the oscillator. The CGMOUT frequency is equal to
the CGMXCLK frequency, and the OSC1 input directly generates internal
bus clocks. In this case, the OSC1 signal must have a 50 percent duty cycle
at maximum bus frequency.
Table 12-2 is a summary of the differences between user mode and monitor mode.
Table 12-2. User and Monitor Mode Differences
Functions
COP
Reset
Vector
High
Reset
Vector
Low
Break
Vector
High
Break
Vector
Low
SWI
Vector
High
SWI
Vector
Low
User
Enabled
$FFFE
$FFFF
$FFFC
$FFFD
$FFFC
$FFFD
Monitor
Disabled(1)
$FEFE
$FEFF
$FEFC
$FEFD
$FEFC
$FEFD
Modes
1. If the high voltage (VDD + VHi) is removed from the IRQ1/VPP pin while in monitor mode,
the SIM asserts its COP enable output. The COP is a mask option enabled or disabled by
the COPD bit in the configuration register. (See 29.4 5.0-Volt DC Electrical
Characteristics.)
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
119
Monitor ROM (MON)
12.3.2 Data Format
Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format.
See Figure 12-2 and Figure 12-3.
The data transmit and receive rate can be anywhere from 4800 baud to 28.8 Kbaud. Transmit and receive
baud rates must be identical.
START
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
STOP
BIT
BIT 7
NEXT
START
BIT
Figure 12-2. Monitor Data Format
$A5
START
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BREAK
START
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
NEXT
START
BIT
STOP
BIT
STOP
BIT
NEXT
START
BIT
Figure 12-3. Sample Monitor Waveforms
12.3.3 Echoing
As shown in Figure 12-4, the monitor ROM immediately echoes each received byte back to the PTA0 pin
for error checking.
Any result of a command appears after the echo of the last byte of the command.
SENT TO
MONITOR
READ
READ
ADDR. HIGH
ADDR. HIGH
ADDR. LOW
ADDR. LOW
DATA
ECHO
RESULT
Figure 12-4. Read Transaction
12.3.4 Break Signal
A start bit followed by nine low bits is a break signal. (See Figure 12-5.) When the monitor receives a break
signal, it drives the PTA0 pin high for the duration of two bits before echoing the break signal.
MISSING STOP BIT
TWO-STOP-BIT DELAY BEFORE ZERO ECHO
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Figure 12-5. Break Transaction
MC68HC908AT32 Data Sheet, Rev. 3.1
120
Freescale Semiconductor
Functional Description
12.3.5 Commands
The monitor ROM uses these commands:
• READ, read memory
• WRITE, write memory
• IREAD, indexed read
• IWRITE, indexed write
• READSP, read stack pointer
• RUN, run user program
A sequence of IREAD or IWRITE commands can access a block of memory sequentially over the full
64-Kbyte memory map.
Table 12-3. READ (Read Memory) Command
Description
Read byte from memory
Operand
Specifies 2-byte address in high byte:low byte order
Data Returned
Returns contents of specified address
Opcode
$4A
Command Sequence
SENT TO
MONITOR
READ
READ
ADDR. HIGH
ADDR. HIGH
ADDR. LOW
ADDR. LOW
ECHO
DATA
RESULT
Table 12-4. WRITE (Write Memory) Command
Description
Write byte to memory
Operand
Specifies 2-byte address in high byte:low byte order; low byte followed by data byte
Data Returned
None
Opcode
$49
Command Sequence
SENT TO
MONITOR
WRITE
WRITE
ADDR. HIGH
ADDR. HIGH
ADDR. LOW
ADDR. LOW
DATA
DATA
ECHO
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
121
Monitor ROM (MON)
Table 12-5. IREAD (Indexed Read) Command
Description
Read next 2 bytes in memory from last address accessed
Operand
Specifies 2-byte address in high byte:low byte order
Data Returned
Returns contents of next two addresses
Opcode
$1A
Command Sequence
SENT TO
MONITOR
IREAD
IREAD
DATA
DATA
RESULT
ECHO
Table 12-6. IWRITE (Indexed Write) Command
Description
Write to last address accessed + 1
Operand
Specifies single data byte
Data Returned
None
Opcode
$19
Command Sequence
SENT TO
MONITOR
IWRITE
IWRITE
DATA
DATA
ECHO
Table 12-7. READSP (Read Stack Pointer) Command
Description
Reads stack pointer
Operand
None
Data Returned
Returns stack pointer in high byte:low byte order
Opcode
$0C
Command Sequence
SENT TO
MONITOR
READSP
READSP
SP HIGH
SP LOW
RESULT
ECHO
MC68HC908AT32 Data Sheet, Rev. 3.1
122
Freescale Semiconductor
Functional Description
Table 12-8. RUN (Run User Program) Command
Description
Executes RTI instruction
Operand
None
Data Returned
None
Opcode
$28
Command Sequence
SENT TO
MONITOR
RUN
RUN
ECHO
12.3.6 Baud Rate
With a 4.9152-MHz crystal and the PTC3 pin at logic 1 during reset, data is transferred between the
monitor and host at 4800 baud. If the PTC3 pin is at logic 0 during reset, the monitor baud rate is 9600.
When the CGM output, CGMOUT, is driven by the PLL, the baud rate is determined by the MUL[7:4] bits
in the PLL programming register (PPG). See Chapter 8 Clock Generator Module (CGM).
Table 12-9. Monitor Baud Rate Selection
VCO Frequency Multiplier (N)
Monitor
Baud Rate
1
2
3
4
5
6
4.9152 MHz
4800
9600
14,400
19,200
24,000
28,800
4.194 MHz
4096
8192
12,288
16,384
20,480
24,576
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
123
Monitor ROM (MON)
MC68HC908AT32 Data Sheet, Rev. 3.1
124
Freescale Semiconductor
Chapter 13
Computer Operating Properly Module (COP)
13.1 Introduction
The computer operating properly (COP) module contains a free-running counter that generates a reset if
allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset
by periodically clearing the COP counter.
13.2 Functional Description
12-BIT COP PRESCALER
CLEAR STAGES 4–12
STOP INSTRUCTION
NTERNAL RESET SOURCES
RESET VECTOR FETCH
CLEAR ALL STAGES
CGMXCLK
COPCTL WRITE
RESET
RESET STATUS
REGISTER
6-BIT COP COUNTER
COPD FROM CONFIG
RESET
COPCTL WRITE
CLEAR COP
COUNTER
COPRS FROM CONFIG
Figure 13-1. COP Block Diagram
The COP counter is a free-running 6-bit counter preceded by the 12-bit system integration module (SIM)
counter. COP timeouts are determined strictly by the CGM crystal oscillator clock signal (CGMXCLK), not
the CGMOUT signal (see Figure 13-1).
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
125
Computer Operating Properly Module (COP)
If not cleared by software, the COP counter overflows and generates an asynchronous reset after 8,176
or 262,128 CGMXCLK cycles divided by the crystal frequency, depending upon COPRS bit in the
configuration register ($001F). See Chapter 9 Configuration Register (CONFIG-1).
COP timeout period = 8,176 or 262,128 / fosc
When COPRS = 0, a 4.9152-MHz crystal gives a COP timeout period of 53.3 ms. Writing any value to
location $FFFF before an overflow occurs prevents a COP reset by clearing the COP counter and stages
4–12 of the SIM counter.
NOTE
Service the COP immediately after reset and before entering or after exiting
stop mode to guarantee the maximum time before the first COP counter
overflow.
A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the COP bit in the reset status
register (RSR).
In monitor mode, the COP is disabled if the RST pin or the IRQ pin is held at VDD + VHi. During the break
state, VDD + VHi on the RST pin disables the COP.
NOTE
Place COP clearing instructions in the main program and not in an interrupt
subroutine. Such an interrupt subroutine could keep the COP from
generating a reset even while the main program is not working properly.
13.3 I/O Signals
The following paragraphs describe the signals shown in Figure 13-1.
13.3.1 CGMXCLK
CGMXCLK is the crystal oscillator output signal. CGMXCLK frequency is equal to the crystal frequency.
13.3.2 STOP Instruction
The STOP instruction clears the COP prescaler.
13.3.3 COPCTL Write
Writing any value to the COP control register (COPCTL) (see 13.4 COP Control Register) clears the COP
counter and clears stages 12 through 4 of the COP prescaler. Reading the COP control register returns
the reset vector.
13.3.4 Power-On Reset
The power-on reset (POR) circuit clears the COP prescaler 4096 CGMXCLK cycles after power-up.
13.3.5 Internal Reset
An internal reset clears the COP prescaler and the COP counter.
MC68HC908AT32 Data Sheet, Rev. 3.1
126
Freescale Semiconductor
COP Control Register
13.3.6 Reset Vector Fetch
A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears
the COP prescaler.
13.3.7 COPD
The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register. See
Chapter 10 Configuration Register (CONFIG-2).
13.3.8 COPRS
The COPRS bit selects the state of the COP rate select timeout bit (COPRS) in the configuration register
($001F). Timeout periods can be 262,128 or 8,176 CGMXCLK cycles. See Chapter 10 Configuration
Register (CONFIG-2).
13.4 COP Control Register
The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to
$FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
Address:
$FFFF
Bit 7
6
5
4
3
Read:
Low byte of reset vector
Write:
Clear COP counter
Reset:
Unaffected by reset
2
1
Bit 0
Figure 13-2. COP Control Register (COPCTL)
13.5 Interrupts
The COP does not generate CPU interrupt requests or DMA service requests.
13.6 Monitor Mode
The COP is disabled in monitor mode when VDD + VHi is present on the IRQ1/VPP pin or on the RST pin.
13.7 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power standby modes.
13.7.1 Wait Mode
The COP remains active in wait mode. To prevent a COP reset during wait mode, periodically clear the
COP counter in a CPU interrupt routine or a DMA service routine.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
127
Computer Operating Properly Module (COP)
13.7.2 Stop Mode
Stop mode turns off the CGMXCLK input to the COP and clears the COP prescaler. Service the COP
immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering
or exiting stop mode.
The STOP bit in the configuration register (CONFIG) enables the STOP instruction. To prevent
inadvertently turning off the COP with a STOP instruction, disable the STOP instruction by clearing the
STOP bit.
13.8 COP Module during Break Interrupts
The COP is disabled during a break interrupt when VDD + VHi is present on the RST pin.
MC68HC908AT32 Data Sheet, Rev. 3.1
128
Freescale Semiconductor
Chapter 14
Low-Voltage Inhibit (LVI)
14.1 Introduction
This section describes the low-voltage inhibit (LVI) module (LVI47, Version A), which monitors the voltage
on the VDD pin and can force a reset when the VDD voltage falls to the LVI trip voltage.
14.2 Features
Features of the LVI module include:
• Programmable LVI reset
• Programmable power consumption
• Digital filtering of VDD pin level
14.3 Functional Description
Figure 14-1 shows the structure of the LVI module. The LVI is enabled out of reset. The LVI module
contains a bandgap reference circuit and comparator. The LVI power bit, LVIPWR, enables the LVI to
monitor VDD voltage. The LVI reset bit, LVIRST, enables the LVI module to generate a reset when VDD
falls below a voltage, LVITRIPF, and remains at or below that level for nine or more consecutive CPU
cycles. LVISTOP, enables the LVI module during stop mode. This will ensure when the STOP instruction
is implemented, the LVI will continue to monitor the voltage level on VDD. LVIPWR, LVISTOP, and
LVIRST are in the configuration register (CONFIGA). (See Chapter 9 Configuration Register
(CONFIG-1).) Once an LVI reset occurs, the MCU remains in reset until VDD rises above a voltage,
LVITRIPR. VDD must be above LVITRIPR for only one CPU cycle to bring the MCU out of reset. (See 14.3.2
Forced Reset Operation.) The output of the comparator controls the state of the LVIOUT flag in the LVI
status register (LVISR).
An LVI reset also drives the RST pin low to provide low-voltage protection to external peripheral devices.
14.3.1 Polled LVI Operation
In applications that can operate at VDD levels below the LVITRIPF level, software can monitor VDD by
polling the LVIOUT bit. In the configuration register, the LVIPWR bit must be at logic 0 to enable the LVI
module, and the LVIRST bit must be at logic 1 to disable LVI resets.
14.3.2 Forced Reset Operation
In applications that require VDD to remain above the LVITRIPF level, enabling LVI resets allows the LVI
module to reset the MCU when VDD falls to the LVITRIPF level and remains at or below that level for nine
or more consecutive CPU cycles. In the configuration register, the LVIPWR and LVIRST bits must be at
logic 0 to enable the LVI module and to enable LVI resets.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
129
Low-Voltage Inhibit (LVI)
VDD
LVIPWR
FROM CONFIG
FROM CONFIG
CPU CLOCK
LVIRST
VDD
DIGITAL FILTER
VDD > LVITRIP = 0
LOW VDD
DETECTOR
LVI RESET
VDD < LVITRIP = 1
Stop Mode
Filter Bypass
ANLGTRIP
LVIOUT
LVISTOP
FROM CONFIG
Figure 14-1. LVI Module Block Diagram
Addr.
$FE0F
Register Name
Bit 7
Read: LVIOUT
LVI Status Register
(LVISR) Write:
See page 130.
Reset:
0
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 14-2. LVI I/O Register Summary
14.3.3 False Reset Protection
The VDD pin level is digitally filtered to reduce false resets due to power supply noise. In order for the LVI
module to reset the MCU,VDD must remain at or below the LVITRIPF level for nine or more consecutive
CPU cycles. VDD must be above LVITRIPR for only one CPU cycle to bring the MCU out of reset.
14.4 LVI Status Register
The LVI status register flags VDD voltages below the LVITRIPF level.
Address:
$FE0F
Bit 7
6
5
4
3
2
1
Bit 0
Read:
LVIOUT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Write:
Reset:
= Unimplemented
Figure 14-3. LVI Status Register (LVISR)
MC68HC908AT32 Data Sheet, Rev. 3.1
130
Freescale Semiconductor
LVI Interrupts
LVIOUT — LVI Output Bit
This read-only flag becomes set when the VDD voltage falls below the LVITRIPF voltage for 32 to 40
CGMXCLK cycles. (See Table 14-1.) Reset clears the LVIOUT bit.
Table 14-1. LVIOUT Bit Indication
VDD
At Level:
For Number of
CGMXCLK Cycles:
LVIOUT
VDD > LVITRIPR
Any
0
VDD < LVITRIPF
< 32 CGMXCLK cycles
0
VDD < LVITRIPF
Between 32 and 40
CGMXCLK cycles
0 or 1
VDD < LVITRIPF
> 40 CGMXCLK cycles
1
LVITRIPF < VDD < LVITRIPR
Any
Previous value
14.5 LVI Interrupts
The LVI module does not generate interrupt requests.
14.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power standby modes.
14.6.1 Wait Mode
With the LVIPWR bit in the configuration register programmed to logic 0, the LVI module is active after a
WAIT instruction.
With the LVIRST bit in the configuration register programmed to logic 0, the LVI module can generate a
reset and bring the MCU out of wait mode.
14.6.2 Stop Mode
With the LVISTOP and LVIPWR bits in the configuration register programmed to a logic 0, the LVI module
will be active after a STOP instruction. Because CPU clocks are disabled during stop mode, the LVI trip
must bypass the digital filter to generate a reset and bring the MCU out of stop.
With the LVIPWR bit in the configuration register programmed to logic 0 and the LVISTOP bit at a logic
1, the LVI module will be inactive after a STOP instruction.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
131
Low-Voltage Inhibit (LVI)
MC68HC908AT32 Data Sheet, Rev. 3.1
132
Freescale Semiconductor
Chapter 15
External Interrupt (IRQ)
15.1 Introduction
This section describes the non-maskable external interrupt (IRQ) input.
15.2 Features
Features include:
• Dedicated external interrupt pin (IRQ1/VPP)
• Hysteresis buffer
• Programmable edge-only or edge- and level-interrupt sensitivity
• Automatic interrupt acknowledge
15.3 Functional Description
A logic 0 applied to the external interrupt pin can latch a CPU interrupt request. Figure 15-1 shows the
structure of the IRQ module.
Interrupt signals on the IRQ1/VPP pin are latched into the IRQ1 latch. An interrupt latch remains set until
one of the following actions occurs:
• Vector fetch — A vector fetch automatically generates an interrupt acknowledge signal that clears
the latch that caused the vector fetch.
• Software clear — Software can clear an interrupt latch by writing to the appropriate acknowledge
bit in the interrupt status and control register (ISCR). Writing a logic 1 to the ACK1 bit clears the
IRQ1 latch.
• Reset — A reset automatically clears both interrupt latches.
The external interrupt pin is falling-edge triggered and is software- configurable to be both falling-edge
and low-level triggered. The MODE1 bit in the ISCR controls the triggering sensitivity of the IRQ1/VPP pin.
When an interrupt pin is edge-triggered only, the interrupt latch remains set until a vector fetch, software
clear, or reset occurs.
When an interrupt pin is both falling-edge and low-level-triggered, the interrupt latch remains set until both
of the following occur:
• Vector fetch or software clear
• Return of the interrupt pin to logic 1
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
133
External Interrupt (IRQ)
INTERNAL ADDRESS BUS
ACK1
TO CPU FOR
BIL/BIH
INSTRUCTIONS
VECTOR
FETCH
DECODER
VDD
IRQ1F
D
CLR
Q
SYNCHRONIZER
CK
IRQ1/VPP
IRQ1
INTERRUPT
REQUEST
IRQ1
LATCH
IMASK1
MODE1
HIGH
VOLTAGE
DETECT
TO MODE
SELECT
LOGIC
Figure 15-1. IRQ Block Diagram
Addr.
$001A
Register Name
IRQ Status and Control Register Read:
(ISCR) Write:
See page 137. Reset:
Bit 7
6
5
4
3
2
0
0
0
0
IRQF1
0
R
R
R
R
R
ACK1
0
0
0
0
0
0
R
1
Bit 0
IMASK1
MODE1
0
0
= Reserved
Figure 15-2. IRQ I/O Register Summary
The vector fetch or software clear may occur before or after the interrupt pin returns to logic 1. As long as
the pin is low, the interrupt request remains pending. A reset will clear the latch and the MODE1 control
bit, thereby clearing the interrupt even if the pin stays low.
When set, the IMASK1 bit in the ISCR masks all external interrupt requests. A latched interrupt request
is not presented to the interrupt priority logic unless the corresponding IMASK bit is clear.
NOTE
The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests.
(See Figure 15-3.)
MC68HC908AT32 Data Sheet, Rev. 3.1
134
Freescale Semiconductor
Functional Description
FROM RESET
YES
I BIT SET?
NO
INTERRUPT?
YES
NO
STACK CPU REGISTERS
SET I BIT
LOAD PC WITH INTERRUPT VECTOR
FETCH NEXT
INSTRUCTION
SWI
INSTRUCTION?
YES
NO
RTI
INSTRUCTION?
YES
UNSTACK CPU REGISTERS
NO
EXECUTE INSTRUCTION
Figure 15-3. IRQ Interrupt Flowchart
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
135
External Interrupt (IRQ)
15.4 IRQ/VPP Pin
A logic 0 on the IRQ1/VPP pin can latch an interrupt request into the IRQ1 latch. A vector fetch, software
clear, or reset clears the IRQ1 latch.
If the MODE1 bit is set, the IRQ1/VPP pin is both falling-edge sensitive and low-level sensitive. With
MODE1 set, both of these actions must occur to clear the IRQ1 latch:
• Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear
the latch. Software may generate the interrupt acknowledge signal by writing a logic 1 to the ACK1
bit in the interrupt status and control register (ISCR). The ACK1 bit is useful in applications that poll
the IRQ1/VPP pin and require software to clear the IRQ1 latch. Writing to the ACK1 bit can also
prevent spurious interrupts due to noise. Setting ACK1 does not affect subsequent transitions on
the IRQ1/VPP pin. A falling edge on IRQ1/VPP that occurs after writing to the ACK1 bit latches
another interrupt request. If the IRQ1 mask bit, IMASK1, is clear, the CPU loads the program
counter with the vector address at locations $FFFA and $FFFB.
• Return of the IRQ1/VPP pin to logic 1 — As long as the IRQ1/VPP pin is at logic 0, the IRQ1 latch
remains set.
The vector fetch or software clear and the return of the IRQ1/VPP pin to logic 1 can occur in any order.
The interrupt request remains pending as long as the IRQ1/VPP pin is at logic 0. A reset will clear the latch
and the MODE1 control bit, thereby clearing the interrupt even if the pin stays low.
If the MODE1 bit is clear, the IRQ1/VPP pin is falling-edge sensitive only. With MODE1 clear, a vector
fetch or software clear immediately clears the IRQ1 latch.
The IRQF1 bit in the ISCR register can be used to check for pending interrupts. The IRQF1 bit is not
affected by the IMASK1 bit, which makes it useful in applications where polling is preferred.
Use the BIH or BIL instruction to read the logic level on the IRQ1/VPP pin.
NOTE
When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine.
15.5 IRQ Module during Break Interrupts
The system integration module (SIM) controls whether the IRQ1 interrupt latch can be cleared during the
break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear the
latches during the break state. See 7.7.3 SIM Break Flag Control Register.
To allow software to clear the IRQ1 latch during a break interrupt, write a logic 1 to the BCFE bit. If a latch
is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect the latch during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default
state), writing to the ACK1 bit in the IRQ status and control register during the break state has no effect
on the IRQ latch.
MC68HC908AT32 Data Sheet, Rev. 3.1
136
Freescale Semiconductor
IRQ Status and Control Register
15.6 IRQ Status and Control Register
The IRQ status and control register (ISCR) controls and monitors operation of the IRQ module. The ISCR
has these functions:
• Shows the state of the IRQ1 interrupt flag
• Clears the IRQ1 interrupt latch
• Masks IRQ1 interrupt request
• Controls triggering sensitivity of the IRQ1/VPP interrupt pin
Address:
$001A
Bit 7
6
5
4
3
2
Read:
0
0
0
0
IRQF1
0
Write:
R
R
R
R
R
ACK1
Reset:
0
0
0
0
0
0
R
= Reserved
1
Bit 0
IMASK1
MODE1
0
0
Figure 15-4. IRQ Status and Control Register (ISCR)
IRQ1F — IRQ1 Flag Bit
This read-only status bit is high when the IRQ1 interrupt is pending.
1 = IRQ1 interrupt pending
0 = IRQ1 interrupt not pending
ACK1 — IRQ1 Interrupt Request Acknowledge Bit
Writing a logic 1 to this write-only bit clears the IRQ1 latch. ACK1 always reads as logic 0. Reset clears
ACK1.
IMASK1 — IRQ1 Interrupt Mask Bit
Writing a logic 1 to this read/write bit disables IRQ1 interrupt requests. Reset clears IMASK1.
1 = IRQ1 interrupt requests disabled
0 = IRQ1 interrupt requests enabled
MODE1 — IRQ1 Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ1/VPP pin. Reset clears MODE1.
1 = IRQ1/VPP interrupt requests on falling edges and low levels
0 = IRQ1/VPP interrupt requests on falling edges only
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
137
External Interrupt (IRQ)
MC68HC908AT32 Data Sheet, Rev. 3.1
138
Freescale Semiconductor
Chapter 16
Serial Communications Interface Module (SCI)
16.1 Introduction
The serial communications interface (SCI) allows asynchronous communications with peripheral devices
and other microcontroller units (MCU).
16.2 Features
The SCI module’s features include:
• Full-duplex operation
• Standard mark/space non-return-to-zero (NRZ) format
• 32 programmable baud rates
• Programmable 8-bit or 9-bit character length
• Separately enabled transmitter and receiver
• Separate receiver and transmitter central processor unit (CPU) interrupt requests
• Programmable transmitter output polarity
• Two receiver wakeup methods:
– Idle line wakeup
– Address mark wakeup
• Interrupt-driven operation with eight interrupt flags:
– Transmitter empty
– Transmission complete
– Receiver full
– Idle receiver input
– Receiver overrun
– Noise error
– Framing error
– Parity error
• Receiver framing error detection
• Hardware parity checking
• 1/16 bit-time noise detection
16.3 Pin Name Conventions
The generic names of the SCI input/output (I/O) pins are:
• RxD (receive data)
• TxD (transmit data)
SCI I/O lines are implemented by sharing parallel I/O port pins. The full name of an SCI input or output
reflects the name of the shared port pin. Table 16-1 shows the full names and the generic names of the
SCI I/O pins.The generic pin names appear in the text of this section.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
139
Serial Communications Interface Module (SCI)
Table 16-1. Pin Name Conventions
SCI Generic Pin Name
RxD
TxD
Full SCI Pin Name
PTE1/SCRxD
PTE0/SCTxD
16.4 Functional Description
Figure 16-1 shows the structure of the SCI module. The SCI allows full-duplex, asynchronous, NRZ serial
communication between the MCU and remote devices, including other MCUs. The transmitter and
receiver of the SCI operate independently, although they use the same baud rate generator. During
normal operation, the CPU monitors the status of the SCI, writes the data to be transmitted, and
processes received data.
INTERNAL BUS
ERROR
INTERRUPT
CONTROL
RECEIVE
SHIFT REGISTER
RxD
SCI DATA
REGISTER
RECEIVER
INTERRUPT
CONTROL
TRANSMITTER
INTERRUPT
CONTROL
SCI DATA
REGISTER
TRANSMIT
SHIFT REGISTER
TxD
TXINV
SCTIE
R8
TCIE
T8
SCRIE
ILIE
TE
SCTE
RE
TC
RWU
SBK
SCRF
OR
ORIE
IDLE
NF
NEIE
FE
FEIE
PE
PEIE
LOOPS
LOOPS
RECEIVE
CONTROL
WAKEUP
CONTROL
ENSCI
ENSCI
TRANSMIT
CONTROL
FLAG
CONTROL
BKF
M
RPF
WAKE
ILTY
CGMXCLK
÷4
PRESCALER
BAUD RATE
GENERATOR
÷ 16
PEN
PTY
DATA SELECTION
CONTROL
Figure 16-1. SCI Module Block Diagram
MC68HC908AT32 Data Sheet, Rev. 3.1
140
Freescale Semiconductor
Functional Description
Address
$0013
$0014
Register Name
SCI Control Register 1 Read:
(SCC1) Write:
See page 152. Reset:
SCI Control Register 2 Read:
(SCC2) Write:
See page 154. Reset:
Bit 7
6
5
4
3
2
1
Bit 0
LOOPS
ENSCI
TXINV
M
WAKE
ILTY
PEN
PTY
0
0
0
0
0
0
0
0
SCTIE
TCIE
SCRIE
ILIE
TE
RE
RWU
SBK
0
0
0
0
0
0
0
0
T8
R
R
ORIE
NEIE
FEIE
PEIE
SCI Control Register 3 Read:
(SCC3) Write:
See page 156. Reset:
R8
U
U
0
0
0
0
0
0
SCTE
TC
SCRF
IDLE
OR
NF
FE
PE
$0016
SCI Status Register 1 Read:
(SCS1) Write:
See page 157. Reset:
1
1
0
0
0
0
$0017
SCI Status Register 2 Read:
(SCS2) Write:
See page 159. Reset:
$0015
$0018
$0019
SCI Data Register Read:
(SCDR) Write:
See page 160. Reset:
SCI Baud Rate Register Read:
(SCBR) Write:
See page 160. Reset:
0
0
BKF
RPF
0
0
0
0
0
0
0
0
R7
R6
R5
R4
R3
R2
R1
R0
T7
T6
T5
T4
T3
T2
T1
T0
Unaffected by Reset
0
SCP1
SCP0
R
SCR2
SCR1
SCR0
0
0
0
0
0
0
R
= Reserved
0
= Unimplemented
U = Unaffected
Figure 16-2. SCI I/O Register Summary
16.4.1 Data Format
The SCI uses the standard non-return-to-zero mark/space data format illustrated in Figure 16-3.
8-BIT DATA FORMAT
(BIT M IN SCC1 CLEAR)
START
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
PARITY
OR DATA
BIT
BIT 6
9-BIT DATA FORMAT
(BIT M IN SCC1 SET)
START
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
STOP
BIT
NEXT
START
BIT
PARITY
OR DATA
BIT
BIT 7
BIT 8 STOP
BIT
NEXT
START
BIT
Figure 16-3. SCI Data Formats
16.4.2 Transmitter
Figure 16-4 shows the structure of the SCI transmitter.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
141
Serial Communications Interface Module (SCI)
INTERNAL BUS
÷ 16
SCI DATA REGISTER
SCP1
11-BIT
TRANSMIT
SHIFT REGISTER
STOP
CGMXCLK
BAUD
DIVIDER
SCP0
SCR1
H
SCR2
8
7
6
5
4
3
2
START
PRESCALER
÷4
1
0
L
TxD
MSB
TXINV
T8
BREAK
(ALL 0S)
PTY
PARITY
GENERATION
PREAMBLE
(ALL 1S)
PEN
SHIFT ENABLE
M
LOAD FROM SCDR
TRANSMITTER CPU INTERRUPT REQUEST
SCR0
TRANSMITTER
CONTROL LOGIC
SCTE
SCTE
SCTIE
TC
TCIE
SBK
LOOPS
SCTIE
ENSCI
TC
TE
TCIE
Figure 16-4. SCI Transmitter
16.4.2.1 Character Length
The transmitter can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1
(SCC1) determines character length. When transmitting 9-bit data, bit T8 in SCI control register 3 (SCC3)
is the ninth bit (bit 8).
16.4.2.2 Character Transmission
During an SCI transmission, the transmit shift register shifts a character out to the TxD pin. The SCI data
register (SCDR) is the write-only buffer between the internal data bus and the transmit shift register. To
initiate an SCI transmission:
1. Enable the SCI by writing a logic 1 to the enable SCI bit (ENSCI) in SCI control register 1 (SCC1).
2. Enable the transmitter by writing a logic 1 to the transmitter enable bit (TE) in SCI control register
2 (SCC2).
3. Clear the SCI transmitter empty bit (SCTE) by first reading SCI status register 1 (SCS1) and then
writing to the SCDR.
4. Repeat step 3 for each subsequent transmission.
MC68HC908AT32 Data Sheet, Rev. 3.1
142
Freescale Semiconductor
Functional Description
At the start of a transmission, transmitter control logic automatically loads the transmit shift register with
a preamble of logic 1s. After the preamble shifts out, control logic transfers the SCDR data into the
transmit shift register. A logic 0 start bit automatically goes into the least significant bit position of the
transmit shift register. A logic 1 stop bit goes into the most significant bit position.
The SCI transmitter empty bit, SCTE, in SCS1 becomes set when the SCDR transfers a byte to the
transmit shift register. The SCTE bit indicates that the SCDR can accept new data from the internal data
bus. If the SCI transmit interrupt enable bit, SCTIE, in SCC2 is also set, the SCTE bit generates a
transmitter CPU interrupt request.
When the transmit shift register is not transmitting a character, the TxD pin goes to the idle condition,
logic 1. If at any time software clears the ENSCI bit in SCI control register 1 (SCC1), the transmitter and
receiver relinquish control of the port E pins.
16.4.2.3 Break Characters
Writing a logic 1 to the send break bit, SBK, in SCC2 loads the transmit shift register with a break
character. A break character contains all logic 0s and has no start, stop, or parity bit. Break character
length depends on the M bit in SCC1. As long as SBK is at logic 1, transmitter logic continuously loads
break characters into the transmit shift register. After software clears the SBK bit, the shift register finishes
transmitting the last break character and then transmits at least one logic 1. The automatic logic 1 at the
end of a break character guarantees the recognition of the start bit of the next character.
The SCI recognizes a break character when a start bit is followed by eight or nine logic 0 data bits and a
logic 0 where the stop bit should be. Receiving a break character has the following effects on SCI
registers:
• Sets the framing error bit (FE) in SCS1
• Sets the SCI receiver full bit (SCRF) in SCS1
• Clears the SCI data register (SCDR)
• Clears the R8 bit in SCC3
• Sets the break flag bit (BKF) in SCS2
• May set the overrun (OR), noise flag (NF), parity error (PE), or reception in progress flag (RPF) bits
16.4.2.4 Idle Characters
An idle character contains all logic 1s and has no start, stop, or parity bit. Idle character length depends
on the M bit in SCC1. The preamble is a synchronizing idle character that begins every transmission.
If the TE bit is cleared during a transmission, the TxD pin becomes idle after completion of the
transmission in progress. Clearing and then setting the TE bit during a transmission queues an idle
character to be sent after the character currently being transmitted.
NOTE
When queueing an idle character, return the TE bit to logic 1 before the stop
bit of the current character shifts out to the TxD pin. Setting TE after the stop
bit appears on TxD causes data previously written to the SCDR to be lost.
A good time to toggle the TE bit for a queued idle character is when the
SCTE bit becomes set and just before writing the next byte to the SCDR.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
143
Serial Communications Interface Module (SCI)
16.4.2.5 Inversion of Transmitted Output
The transmit inversion bit (TXINV) in SCI control register 1 (SCC1) reverses the polarity of transmitted
data. All transmitted values, including idle, break, start, and stop bits, are inverted when TXINV is at
logic 1. See 16.8.1 SCI Control Register 1.
16.4.2.6 Transmitter Interrupts
These conditions can generate CPU interrupt requests from the SCI transmitter:
• SCI transmitter empty (SCTE) — The SCTE bit in SCS1 indicates that the SCDR has transferred
a character to the transmit shift register. SCTE can generate a transmitter CPU interrupt request.
Setting the SCI transmit interrupt enable bit, SCTIE, in SCC2 enables the SCTE bit to generate
transmitter CPU interrupt requests.
• Transmission complete (TC) — The TC bit in SCS1 indicates that the transmit shift register and the
SCDR are empty and that no break or idle character has been generated. The transmission
complete interrupt enable bit, TCIE, in SCC2 enables the TC bit to generate transmitter CPU
interrupt requests.
16.4.3 Receiver
Figure 16-5 shows the structure of the SCI receiver.
16.4.3.1 Character Length
The receiver can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1
(SCC1) determines character length. When receiving 9-bit data, bit R8 in SCI control register 2 (SCC2)
is the ninth bit (bit 8). When receiving 8-bit data, bit R8 is a copy of the eighth bit (bit 7).
16.4.3.2 Character Reception
During an SCI reception, the receive shift register shifts characters in from the RxD pin. The SCI data
register (SCDR) is the read-only buffer between the internal data bus and the receive shift register.
After a complete character shifts into the receive shift register, the data portion of the character transfers
to the SCDR. The SCI receiver full bit, SCRF, in SCI status register 1 (SCS1) becomes set, indicating that
the received byte can be read. If the SCI receive interrupt enable bit, SCRIE, in SCC2 is also set, the
SCRF bit generates a receiver CPU interrupt request.
MC68HC908AT32 Data Sheet, Rev. 3.1
144
Freescale Semiconductor
Functional Description
INTERNAL BUS
SCR1
SCR2
SCP0
SCR0
BAUD
DIVIDER
÷ 16
CGMXCLK
DATA
RECOVERY
RxD
CPU INTERRUPT REQUEST
11-BIT
RECEIVE SHIFT REGISTER
8
7
M
WAKE
ILTY
PEN
PTY
6
5
4
3
2
1
0
L
ALL ZEROS
RPF
ERROR CPU INTERRUPT REQUEST
H
ALL 1S
BKF
STOP
PRESCALER
MSB
÷4
SCI DATA REGISTER
START
SCP1
SCRF
WAKEUP
LOGIC
IDLE
R8
PARITY
CHECKING
IDLE
ILIE
SCRF
SCRIE
RWU
ILIE
SCRIE
OR
ORIE
NF
NEIE
FE
FEIE
PE
PEIE
OR
ORIE
NF
NEIE
FE
FEIE
PE
PEIE
Figure 16-5. SCI Receiver Block Diagram
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
145
Serial Communications Interface Module (SCI)
16.4.3.3 Data Sampling
The receiver samples the RxD pin at the RT clock rate. The RT clock is an internal signal with a frequency
16 times the baud rate. To adjust for baud rate mismatch, the RT clock is resynchronized at the following
times (see Figure 16-6):
• After every start bit
• After the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit
samples at RT8, RT9, and RT10 returns a valid logic 1 and the majority of the next RT8, RT9, and
RT10 samples returns a valid logic 0)
To locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three
logic 1s. When the falling edge of a possible start bit occurs, the RT clock begins to count to 16.
START BIT
RxD
START BIT
QUALIFICATION
SAMPLES
LSB
START BIT
DATA
VERIFICATION SAMPLING
RT CLOCK
STATE
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT2
RT3
RT4
RT5
RT6
RT7
RT8
RT9
RT10
RT11
RT12
RT13
RT14
RT15
RT16
RT1
RT2
RT3
RT4
RT
CLOCK
RT CLOCK
RESET
Figure 16-6. Receiver Data Sampling
To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7.
Table 16-2 summarizes the results of the start bit verification samples.
Table 16-2. Start Bit Verification
RT3, RT5, and RT7 Samples
Start Bit Verification
Noise Flag
000
Yes
0
001
Yes
1
010
Yes
1
011
No
0
100
Yes
1
101
No
0
110
No
0
111
No
0
If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins.
MC68HC908AT32 Data Sheet, Rev. 3.1
146
Freescale Semiconductor
Functional Description
To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and
RT10. Table 16-3 summarizes the results of the data bit samples.
Table 16-3. Data Bit Recovery
RT8, RT9, and RT10 Samples
Data Bit Determination
Noise Flag
000
0
0
001
0
1
010
0
1
011
1
1
100
0
1
101
1
1
110
1
1
111
1
0
NOTE
The RT8, RT9, and RT10 samples do not affect start bit verification. If any
or all of the RT8, RT9, and RT10 start bit samples are logic 1s following a
successful start bit verification, the noise flag (NF) is set and the receiver
assumes that the bit is a start bit.
To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 16-4
summarizes the results of the stop bit samples.
Table 16-4. Stop Bit Recovery
RT8, RT9, and RT10 Samples
Framing Error Flag
Noise Flag
000
1
0
001
1
1
010
1
1
011
0
1
100
1
1
101
0
1
110
0
1
111
0
0
16.4.3.4 Framing Errors
If the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming character,
it sets the framing error bit, FE, in SCS1. A break character also sets the FE bit because a break character
has no stop bit. The FE bit is set at the same time that the SCRF bit is set.
16.4.3.5 Baud Rate Tolerance
A transmitting device may be operating at a baud rate below or above the receiver baud rate.
Accumulated bit time misalignment can cause one of the three stop bit data samples to fall outside the
actual stop bit. Then a noise error occurs. If more than one of the samples is outside the stop bit, a framing
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
147
Serial Communications Interface Module (SCI)
error occurs. In most applications, the baud rate tolerance is much more than the degree of misalignment
that is likely to occur.
As the receiver samples an incoming character, it resynchronizes the RT clock on any valid falling edge
within the character. Resynchronization within characters corrects misalignments between transmitter bit
times and receiver bit times.
Slow Data Tolerance
Figure 16-7 shows how much a slow received character can be misaligned without causing a noise
error or a framing error. The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop
bit data samples at RT8, RT9, and RT10.
MSB
STOP
RT16
RT15
RT14
RT13
RT12
RT11
RT10
RT9
RT8
RT7
RT6
RT5
RT4
RT3
RT2
RT1
RECEIVER
RT CLOCK
DATA
SAMPLES
Figure 16-7. Slow Data
For an 8-bit character, data sampling of the stop bit takes the receiver
9 bit times × 16 RT cycles + 10 RT cycles = 154 RT cycles.
With the misaligned character shown in Figure 16-7, the receiver counts 154 RT cycles at the point
when the count of the transmitting device is 9 bit times × 16 RT cycles + 3 RT cycles = 147 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit
character with no errors is
154 – 147
-------------------------- × 100 = 4.54%
154
For a 9-bit character, data sampling of the stop bit takes the receiver
10 bit times × 16 RT cycles + 10 RT cycles = 170 RT cycles.
With the misaligned character shown in Figure 16-7, the receiver counts 170 RT cycles at the point
when the count of the transmitting device is
10 bit times × 16 RT cycles + 3 RT cycles = 163 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit
character with no errors is
170 – 163
-------------------------- × 100 = 4.12%
170
MC68HC908AT32 Data Sheet, Rev. 3.1
148
Freescale Semiconductor
Functional Description
Fast Data Tolerance
Figure 16-8 shows how much a fast received character can be misaligned without causing a noise
error or a framing error. The fast stop bit ends at RT10 instead of RT16 but is still there for the stop bit
data samples at RT8, RT9, and RT10.
STOP
IDLE OR NEXT CHARACTER
RT16
RT15
RT14
RT13
RT12
RT11
RT10
RT9
RT8
RT7
RT6
RT5
RT4
RT3
RT2
RT1
RECEIVER
RT CLOCK
DATA
SAMPLES
Figure 16-8. Fast Data
For an 8-bit character, data sampling of the stop bit takes the receiver
9 bit times × 16 RT cycles + 10 RT cycles = 154 RT cycles.
With the misaligned character shown in Figure 16-8, the receiver counts 154 RT cycles at the point
when the count of the transmitting device is 10 bit times × 16 RT cycles = 160 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of a fast 8-bit
character with no errors is
154 – 160 × 100 = 3.90%.
-------------------------154
For a 9-bit character, data sampling of the stop bit takes the receiver
10 bit times × 16 RT cycles + 10 RT cycles = 170 RT cycles.
With the misaligned character shown in Figure 16-8, the receiver counts 170 RT cycles at the point
when the count of the transmitting device is 11 bit times × 16 RT cycles = 176 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit
character with no errors is
170 – 176 × 100 = 3.53%.
-------------------------170
16.4.3.6 Receiver Wakeup
So that the MCU can ignore transmissions intended only for other receivers in multiple-receiver systems,
the receiver can be put into a standby state. Setting the receiver wakeup bit, RWU, in SCC2 puts the
receiver into a standby state during which receiver interrupts are disabled.
Depending on the state of the WAKE bit in SCC1, either of two conditions on the RxD pin can bring the
receiver out of the standby state:
• Address mark — An address mark is a logic 1 in the most significant bit position of a received
character. When the WAKE bit is set, an address mark wakes the receiver from the standby state
by clearing the RWU bit. The address mark also sets the SCI receiver full bit, SCRF. Software can
then compare the character containing the address mark to the user-defined address of the
receiver. If they are the same, the receiver remains awake and processes the characters that
follow. If they are not the same, software can set the RWU bit and put the receiver back into the
standby state.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
149
Serial Communications Interface Module (SCI)
•
Idle input line condition — When the WAKE bit is clear, an idle character on the RxD pin wakes the
receiver from the standby state by clearing the RWU bit. The idle character that wakes the receiver
does not set the receiver idle bit, IDLE, or the SCI receiver full bit, SCRF. The idle line type bit,
ILTY, determines whether the receiver begins counting logic 1s as idle character bits after the start
bit or after the stop bit.
NOTE
With the WAKE bit clear, setting the RWU bit after the RxD pin has been
idle may cause the receiver to wake up immediately.
16.4.3.7 Receiver Interrupts
These sources can generate CPU interrupt requests from the SCI receiver:
• SCI receiver full (SCRF) — The SCRF bit in SCS1 indicates that the receive shift register has
transferred a character to the SCDR. SCRF can generate a receiver CPU interrupt request. Setting
the SCI receive interrupt enable bit, SCRIE, in SCC2 enables the SCRF bit to generate receiver
CPU interrupts.
• Idle input (IDLE) — The IDLE bit in SCS1 indicates that 10 or 11 consecutive logic 1s shifted in
from the RxD pin. The idle line interrupt enable bit, ILIE, in SCC2 enables the IDLE bit to generate
CPU interrupt requests.
16.4.3.8 Error Interrupts
These receiver error flags in SCS1 can generate CPU interrupt requests:
• Receiver overrun (OR) — The OR bit indicates that the receive shift register shifted in a new
character before the previous character was read from the SCDR. The previous character remains
in the SCDR, and the new character is lost. The overrun interrupt enable bit, ORIE, in SCC3
enables OR to generate SCI error CPU interrupt requests.
• Noise flag (NF) — The NF bit is set when the SCI detects noise on incoming data or break
characters, including start, data, and stop bits. The noise error interrupt enable bit, NEIE, in SCC3
enables NF to generate SCI error CPU interrupt requests.
• Framing error (FE) — The FE bit in SCS1 is set when a logic 0 occurs where the receiver expects
a stop bit. The framing error interrupt enable bit, FEIE, in SCC3 enables FE to generate SCI error
CPU interrupt requests.
• Parity error (PE) — The PE bit in SCS1 is set when the SCI detects a parity error in incoming data.
The parity error interrupt enable bit, PEIE, in SCC3 enables PE to generate SCI error CPU interrupt
requests.
16.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power standby modes.
16.5.1 Wait Mode
The SCI module remains active in wait mode. Any enabled CPU interrupt request from the SCI module
can bring the MCU out of wait mode.
If SCI module functions are not required during wait mode, reduce power consumption by disabling the
module before executing the WAIT instruction.
MC68HC908AT32 Data Sheet, Rev. 3.1
150
Freescale Semiconductor
SCI during Break Module Interrupts
16.5.2 Stop Mode
The SCI module is inactive in stop mode. The STOP instruction does not affect SCI register states. SCI
module operation resumes after the MCU exits stop mode.
Because the internal clock is inactive during stop mode, entering stop mode during an SCI transmission
or reception results in invalid data.
16.6 SCI during Break Module Interrupts
The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the
break state. See Chapter 11 Break Module (BRK).
To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status
bit is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its
default state), software can read and write I/O registers during the break state without affecting status bits.
Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit
before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the
break, doing the second step clears the status bit.
16.7 I/O Signals
Port E shares two of its pins with the SCI module. The two SCI I/O pins are:
• PTE0/SCTxD — Transmit data
• PTE1/SCRxD — Receive data
16.7.1 PTE0/SCTxD (Transmit Data)
The PTE0/SCTxD pin is the serial data output from the SCI transmitter. The SCI shares the PTE0/SCTxD
pin with port E. When the SCI is enabled, the PTE0/SCTxD pin is an output regardless of the state of the
DDRE2 bit in data direction register E (DDRE).
16.7.2 PTE1/SCRxD (Receive Data)
The PTE1/SCRxD pin is the serial data input to the SCI receiver. The SCI shares the PTE1/SCRxD pin
with port E. When the SCI is enabled, the PTE1/SCRxD pin is an input regardless of the state of the
DDRE1 bit in data direction register E (DDRE).
16.8 I/O Registers
These I/O registers control and monitor SCI operation:
• SCI control register 1 (SCC1)
• SCI control register 2 (SCC2)
• SCI control register 3 (SCC3)
• SCI status register 1 (SCS1)
• SCI status register 2 (SCS2)
• SCI data register (SCDR)
• SCI baud rate register (SCBR)
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
151
Serial Communications Interface Module (SCI)
16.8.1 SCI Control Register 1
SCI control register 1:
• Enables loop mode operation
• Enables the SCI
• Controls output polarity
• Controls character length
• Controls SCI wakeup method
• Controls idle character detection
• Enables parity function
• Controls parity type
Address:
$0013
Bit 7
6
5
4
3
2
1
Bit 0
LOOPS
ENSCI
TXINV
M
WAKE
ILTY
PEN
PTY
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 16-9. SCI Control Register 1 (SCC1)
LOOPS — Loop Mode Select Bit
This read/write bit enables loop mode operation. In loop mode the RxD pin is disconnected from the
SCI, and the transmitter output goes into the receiver input. Both the transmitter and the receiver must
be enabled to use loop mode. Reset clears the LOOPS bit.
1 = Loop mode enabled
0 = Normal operation enabled
ENSCI — Enable SCI Bit
This read/write bit enables the SCI and the SCI baud rate generator. Clearing ENSCI sets the SCTE
and TC bits in SCI status register 1 and disables transmitter interrupts. Reset clears the ENSCI bit.
1 = SCI enabled
0 = SCI disabled
TXINV — Transmit Inversion Bit
This read/write bit reverses the polarity of transmitted data. Reset clears the TXINV bit.
1 = Transmitter output inverted
0 = Transmitter output not inverted
NOTE
Setting the TXINV bit inverts all transmitted values, including idle, break,
start, and stop bits.
M — Mode (Character Length) Bit
This read/write bit determines whether SCI characters are eight or nine bits long. (See Table 16-5.)
The ninth bit can serve as an extra stop bit, as a receiver wakeup signal, or as a parity bit. Reset clears
the M bit.
1 = 9-bit SCI characters
0 = 8-bit SCI characters
MC68HC908AT32 Data Sheet, Rev. 3.1
152
Freescale Semiconductor
I/O Registers
WAKE — Wakeup Condition Bit
This read/write bit determines which condition wakes up the SCI: a logic 1 (address mark) in the most
significant bit position of a received character or an idle condition on the RxD pin. Reset clears the
WAKE bit.
1 = Address mark wakeup
0 = Idle line wakeup
ILTY — Idle Line Type Bit
This read/write bit determines when the SCI starts counting logic 1s as idle character bits. The counting
begins either after the start bit or after the stop bit. If the count begins after the start bit, then a string
of logic 1s preceding the stop bit may cause false recognition of an idle character. Beginning the count
after the stop bit avoids false idle character recognition, but requires properly synchronized
transmissions. Reset clears the ILTY bit.
1 = Idle character bit count begins after stop bit
0 = Idle character bit count begins after start bit
PEN — Parity Enable Bit
This read/write bit enables the SCI parity function. (See Table 16-5.) When enabled, the parity function
inserts a parity bit in the most significant bit position. (See Figure 16-3.) Reset clears the PEN bit.
1 = Parity function enabled
0 = Parity function disabled
PTY — Parity Bit
This read/write bit determines whether the SCI generates and checks for odd parity or even parity.
(See Table 16-5.) Reset clears the PTY bit.
1 = Odd parity
0 = Even parity
NOTE
Changing the PTY bit in the middle of a transmission or reception can
generate a parity error.
Table 16-5. Character Format Selection
Control Bits
Character Format
M
PEN:PTY
Start
Bits
Data
Bits
Parity
Stop
Bits
Character
Length
0
0X
1
8
None
1
10 bits
1
0X
1
9
None
1
11 bits
0
10
1
7
Even
1
10 bits
0
11
1
7
Odd
1
10 bits
1
10
1
8
Even
1
11 bits
1
11
1
8
Odd
1
11 bits
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
153
Serial Communications Interface Module (SCI)
16.8.2 SCI Control Register 2
SCI control register 2:
• Enables these CPU interrupt requests:
– Enables the SCTE bit to generate transmitter CPU interrupt requests
– Enables the TC bit to generate transmitter CPU interrupt requests
– Enables the SCRF bit to generate receiver CPU interrupt requests
– Enables the IDLE bit to generate receiver CPU interrupt requests
• Enables the transmitter
• Enables the receiver
• Enables SCI wakeup
• Transmits SCI break characters
Address:
$0014
Bit 7
6
5
4
3
2
1
Bit 0
SCTIE
TCIE
SCRIE
ILIE
TE
RE
RWU
SBK
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 16-10. SCI Control Register 2 (SCC2)
SCTIE — SCI Transmit Interrupt Enable Bit
This read/write bit enables the SCTE bit to generate SCI transmitter CPU interrupt requests. Setting
the SCTIE bit in SCC3 enables the SCTE bit to generate CPU interrupt requests. Reset clears the
SCTIE bit.
1 = SCTE enabled to generate CPU interrupt
0 = SCTE not enabled to generate CPU interrupt
TCIE — Transmission Complete Interrupt Enable Bit
This read/write bit enables the TC bit to generate SCI transmitter CPU interrupt requests. Reset clears
the TCIE bit.
1 = TC enabled to generate CPU interrupt requests
0 = TC not enabled to generate CPU interrupt requests
SCRIE — SCI Receive Interrupt Enable Bit
This read/write bit enables the SCRF bit to generate SCI receiver CPU interrupt requests. Setting the
SCRIE bit in SCC3 enables the SCRF bit to generate CPU interrupt requests. Reset clears the SCRIE
bit.
1 = SCRF enabled to generate CPU interrupt
0 = SCRF not enabled to generate CPU interrupt
ILIE — Idle Line Interrupt Enable Bit
This read/write bit enables the IDLE bit to generate SCI receiver CPU interrupt requests. Reset clears
the ILIE bit.
1 = IDLE enabled to generate CPU interrupt requests
0 = IDLE not enabled to generate CPU interrupt requests
MC68HC908AT32 Data Sheet, Rev. 3.1
154
Freescale Semiconductor
I/O Registers
TE — Transmitter Enable Bit
Setting this read/write bit begins the transmission by sending a preamble of 10 or 11 logic 1s from the
transmit shift register to the TxD pin. If software clears the TE bit, the transmitter completes any
transmission in progress before the TxD returns to the idle condition (logic 1). Clearing and then setting
TE during a transmission queues an idle character to be sent after the character currently being
transmitted. Reset clears the TE bit.
1 = Transmitter enabled
0 = Transmitter disabled
NOTE
Writing to the TE bit is not allowed when the enable SCI bit (ENSCI) is clear.
ENSCI is in SCI control register 1.
RE — Receiver Enable Bit
Setting this read/write bit enables the receiver. Clearing the RE bit disables the receiver but does not
affect receiver interrupt flag bits. Reset clears the RE bit.
1 = Receiver enabled
0 = Receiver disabled
NOTE
Writing to the RE bit is not allowed when the enable SCI bit (ENSCI) is
clear. ENSCI is in SCI control register 1.
RWU — Receiver Wakeup Bit
This read/write bit puts the receiver in a standby state during which receiver interrupts are disabled.
The WAKE bit in SCC1 determines whether an idle input or an address mark brings the receiver out
of the standby state and clears the RWU bit. Reset clears the RWU bit.
1 = Standby state
0 = Normal operation
SBK — Send Break Bit
Setting and then clearing this read/write bit transmits a break character followed by a logic 1. The
logic 1 after the break character guarantees recognition of a valid start bit. If SBK remains set, the
transmitter continuously transmits break characters with no logic 1s between them. Reset clears the
SBK bit.
1 = Transmit break characters
0 = No break characters being transmitted
NOTE
Do not toggle the SBK bit immediately after setting the SCTE bit. Toggling
SBK before the preamble begins causes the SCI to send a break character
instead of a preamble.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
155
Serial Communications Interface Module (SCI)
16.8.3 SCI Control Register 3
•
•
•
SCI control register 3:
Stores the ninth SCI data bit received and the ninth SCI data bit to be transmitted.
Enables these interrupts:
– Receiver overrun interrupts
– Noise error interrupts
– Framing error interrupts
– Parity error interrupts
Address:
$0015
Bit 7
Read:
R8
Write:
Reset:
U
6
5
4
3
2
1
Bit 0
T8
R
R
ORIE
NEIE
FEIE
PEIE
U
0
0
0
0
0
0
R
= Reserved
= Unimplemented
U = Unaffected
Figure 16-11. SCI Control Register 3 (SCC3)
R8 — Received Bit 8
When the SCI is receiving 9-bit characters, R8 is the read-only ninth bit (bit 8) of the received character.
R8 is received at the same time that the SCDR receives the other 8 bits.
When the SCI is receiving 8-bit characters, R8 is a copy of the eighth bit (bit 7). Reset has no effect on
the R8 bit.
T8 — Transmitted Bit 8
When the SCI is transmitting 9-bit characters, T8 is the read/write ninth bit (bit 8) of the transmitted
character. T8 is loaded into the transmit shift register at the same time that the SCDR is loaded into
the transmit shift register. Reset has no effect on the T8 bit.
ORIE — Receiver Overrun Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt requests generated by the receiver overrun bit, OR.
1 = SCI error CPU interrupt requests from OR bit enabled
0 = SCI error CPU interrupt requests from OR bit disabled
NEIE — Receiver Noise Error Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt requests generated by the noise error bit, NE.
Reset clears NEIE.
1 = SCI error CPU interrupt requests from NE bit enabled
0 = SCI error CPU interrupt requests from NE bit disabled
FEIE — Receiver Framing Error Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt requests generated by the framing error bit, FE.
Reset clears FEIE.
1 = SCI error CPU interrupt requests from FE bit enabled
0 = SCI error CPU interrupt requests from FE bit disabled
PEIE — Receiver Parity Error Interrupt Enable Bit
This read/write bit enables SCI receiver CPU interrupt requests generated by the parity error bit, PE.
Reset clears PEIE.
1 = SCI error CPU interrupt requests from PE bit enabled
0 = SCI error CPU interrupt requests from PE bit disabled
MC68HC908AT32 Data Sheet, Rev. 3.1
156
Freescale Semiconductor
I/O Registers
16.8.4 SCI Status Register 1
SCI status register 1 contains flags to signal these conditions:
• Transfer of SCDR data to transmit shift register complete
• Transmission complete
• Transfer of receive shift register data to SCDR complete
• Receiver input idle
• Receiver overrun
• Noisy data
• Framing error
• Parity error
Address:
Read:
$0016
Bit 7
6
5
4
3
2
1
Bit 0
SCTE
TC
SCRF
IDLE
OR
NF
FE
PE
1
1
0
0
0
0
0
0
Write:
Reset:
= Unimplemented
Figure 16-12. SCI Status Register 1 (SCS1)
SCTE — SCI Transmitter Empty Bit
This clearable, read-only bit is set when the SCDR transfers a character to the transmit shift register.
SCTE can generate an SCI transmitter CPU interrupt request. When the SCTIE bit in SCC2 is set,
SCTE generates an SCI transmitter CPU interrupt request. In normal operation, clear the SCTE bit by
reading SCS1 with SCTE set and then writing to SCDR. Reset sets the SCTE bit.
1 = SCDR data transferred to transmit shift register
0 = SCDR data not transferred to transmit shift register
TC — Transmission Complete Bit
This read-only bit is set when the SCTE bit is set, and no data, preamble, or break character is being
transmitted. TC generates an SCI transmitter CPU interrupt request if the TCIE bit in SCC2 is also set.
TC is cleared automatically when data, preamble, or break is queued and ready to be sent. There may
be up to 1.5 transmitter clocks of latency between queueing data, preamble, and break and the
transmission actually starting. Reset sets the TC bit.
1 = No transmission in progress
0 = Transmission in progress
SCRF — SCI Receiver Full Bit
This clearable, read-only bit is set when the data in the receive shift register transfers to the SCI data
register. SCRF can generate an SCI receiver CPU interrupt request. When the SCRIE bit in SCC2 is
set the SCRF generates a CPU interrupt request. In normal operation, clear the SCRF bit by reading
SCS1 with SCRF set and then reading the SCDR. Reset clears SCRF.
1 = Received data available in SCDR
0 = Data not available in SCDR
IDLE — Receiver Idle Bit
This clearable, read-only bit is set when 10 or 11 consecutive logic 1s appear on the receiver input.
IDLE generates an SCI error CPU interrupt request if the ILIE bit in SCC2 is also set. Clear the IDLE
bit by reading SCS1 with IDLE set and then reading the SCDR. After the receiver is enabled, it must
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
157
Serial Communications Interface Module (SCI)
receive a valid character that sets the SCRF bit before an idle condition can set the IDLE bit. Also, after
the IDLE bit has been cleared, a valid character must again set the SCRF bit before an idle condition
can set the IDLE bit. Reset clears the IDLE bit.
1 = Receiver input idle
0 = Receiver input active (or idle since the IDLE bit was cleared)
OR — Receiver Overrun Bit
This clearable, read-only bit is set when software fails to read the SCDR before the receive shift
register receives the next character. The OR bit generates an SCI error CPU interrupt request if the
ORIE bit in SCC3 is also set. The data in the shift register is lost, but the data already in the SCDR is
not affected. Clear the OR bit by reading SCS1 with OR set and then reading the SCDR. Reset clears
the OR bit.
1 = Receive shift register full and SCRF = 1
0 = No receiver overrun
Software latency may allow an overrun to occur between reads of SCS1 and SCDR in the flag-clearing
sequence. Figure 16-13 shows the normal flag-clearing sequence and an example of an overrun caused
by a delayed flag-clearing sequence. The delayed read of SCDR does not clear the OR bit because OR
was not set when SCS1 was read. Byte 2 caused the overrun and is lost. The next flag-clearing sequence
reads byte 3 in the SCDR instead of byte 2.
In applications that are subject to software latency or in which it is important to know which byte is lost
due to an overrun, the flag-clearing routine can check the OR bit in a second read of SCS1 after reading
the data register.
BYTE 1
BYTE 2
BYTE 3
SCRF = 0
SCRF = 1
SCRF = 0
SCRF = 1
SCRF = 0
SCRF = 1
NORMAL FLAG CLEARING SEQUENCE
BYTE 4
READ SCS1
SCRF = 1
OR = 0
READ SCS1
SCRF = 1
OR = 0
READ SCS1
SCRF = 1
OR = 0
READ SCDR
BYTE 1
READ SCDR
BYTE 2
READ SCDR
BYTE 3
BYTE 1
BYTE 2
BYTE 3
SCRF = 0
OR = 0
SCRF = 1
OR = 1
SCRF = 0
OR = 1
SCRF = 1
SCRF = 1
OR = 1
DELAYED FLAG CLEARING SEQUENCE
BYTE 4
READ SCS1
SCRF = 1
OR = 0
READ SCS1
SCRF = 1
OR = 1
READ SCDR
BYTE 1
READ SCDR
BYTE 3
Figure 16-13. Flag Clearing Sequence
MC68HC908AT32 Data Sheet, Rev. 3.1
158
Freescale Semiconductor
I/O Registers
NF — Receiver Noise Flag Bit
This clearable, read-only bit is set when the SCI detects noise on the RxD pin. NF generates an NF
CPU interrupt request if the NEIE bit in SCC3 is also set. Clear the NF bit by reading SCS1 and then
reading the SCDR. Reset clears the NF bit.
1 = Noise detected
0 = No noise detected
FE — Receiver Framing Error Bit
This clearable, read-only bit is set when a logic 0 is accepted as the stop bit. FE generates an SCI error
CPU interrupt request if the FEIE bit in SCC3 also is set. Clear the FE bit by reading SCS1 with FE set
and then reading the SCDR. Reset clears the FE bit.
1 = Framing error detected
0 = No framing error detected
PE — Receiver Parity Error Bit
This clearable, read-only bit is set when the SCI detects a parity error in incoming data. PE generates
a PE CPU interrupt request if the PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1 with
PE set and then reading the SCDR. Reset clears the PE bit.
1 = Parity error detected
0 = No parity error detected
16.8.5 SCI Status Register 2
SCI status register 2 contains flags to signal these conditions:
• Break character detected
• Incoming data
Address:
$0017
Bit 7
6
5
4
3
2
Read:
1
Bit 0
BKF
RPF
0
0
Write:
Reset:
0
0
0
0
0
0
= Unimplemented
Figure 16-14. SCI Status Register 2 (SCS2)
BKF — Break Flag Bit
This clearable, read-only bit is set when the SCI detects a break character on the RxD pin. In SCS1,
the FE and SCRF bits are also set. In 9-bit character transmissions, the R8 bit in SCC3 is cleared. BKF
does not generate a CPU interrupt request. Clear BKF by reading SCS2 with BKF set and then reading
the SCDR. Once cleared, BKF can become set again only after logic 1s again appear on the RxD pin
followed by another break character. Reset clears the BKF bit.
1 = Break character detected
0 = No break character detected
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
159
Serial Communications Interface Module (SCI)
RPF — Reception in Progress Flag Bit
This read-only bit is set when the receiver detects a logic 0 during the RT1 time period of the start bit
search. RPF does not generate an interrupt request. RPF is reset after the receiver detects false start
bits (usually from noise or a baud rate mismatch), or when the receiver detects an idle character.
Polling RPF before disabling the SCI module or entering stop mode can show whether a reception is
in progress.
1 = Reception in progress
0 = No reception in progress
16.8.6 SCI Data Register
The SCI data register is the buffer between the internal data bus and the receive and transmit shift
registers. Reset has no effect on data in the SCI data register.
Address:
$0018
Bit 7
6
5
4
3
2
1
Bit 0
Read:
R7
R6
R5
R4
R3
R2
R1
R0
Write:
T7
T6
T5
T4
T3
T2
T1
T0
Reset:
Unaffected by reset
Figure 16-15. SCI Data Register (SCDR)
R7/T7:R0/T0 — Receive/Transmit Data Bits
Reading address $0018 accesses the read-only received data bits, R7:R0. Writing to address $0018
writes the data to be transmitted, T7:T0. Reset has no effect on the SCI data register.
NOTE
Do not use read-modify-write instructions on the SCI data register.
16.8.7 SCI Baud Rate Register
The baud rate register selects the baud rate for both the receiver and the transmitter.
Address:
$0019
Bit 7
6
Read:
Write:
Reset:
0
0
5
4
3
2
1
Bit 0
SCP1
SCP0
R
SCR2
SCR1
SCR0
0
0
0
0
0
R
= Reserved
0
= Unimplemented
Figure 16-16. SCI Baud Rate Register (SCBR)
MC68HC908AT32 Data Sheet, Rev. 3.1
160
Freescale Semiconductor
I/O Registers
SCP1 and SCP0 — SCI Baud Rate Prescaler Bits
These read/write bits select the baud rate prescaler divisor as shown in Table 16-6. Reset clears SCP1
and SCP0.
Table 16-6. SCI Baud Rate Prescaling
SCP[1:0]
Prescaler Divisor (PD)
00
1
01
3
10
4
11
13
SCR2 – SCR0 — SCI Baud Rate Select Bits
These read/write bits select the SCI baud rate divisor as shown in Table 16-7. Reset clears
SCR2–SCR0.
Table 16-7. SCI Baud Rate Selection
SCR[2:1:0]
Baud Rate Divisor (BD)
000
1
001
2
010
4
011
8
100
16
101
32
110
64
111
128
Use the following formula to calculate the SCI baud rate:
f Crystal
Baud rate = -----------------------------------64 × PD × BD
where:
fCrystal = crystal frequency
PD = prescaler divisor
BD = baud rate divisor
Table 16-8 shows the SCI baud rates that can be generated with a 4.194-MHz crystal.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
161
Serial Communications Interface Module (SCI)
Table 16-8. SCI Baud Rate Selection Examples
SCP[1:0]
Prescaler
Divisor
(PD)
SCR[2:1:0]
Baud Rate
Divisor
(BD)
Baud Rate
(fCrystal = 4.9152 MHz)
00
1
000
1
76,800
00
1
001
2
38,400
00
1
010
4
19,200
00
1
011
8
9600
00
1
100
16
4800
00
1
101
32
2400
00
1
110
64
1200
00
1
111
128
600
01
3
000
1
25,600
01
3
001
2
12,800
01
3
010
4
6400
01
3
011
8
3200
01
3
100
16
1600
01
3
101
32
800
01
3
110
64
400
01
3
111
128
200
10
4
000
1
19,200
10
4
001
2
9600
10
4
010
4
4800
10
4
011
8
2400
10
4
100
16
1200
10
4
101
32
600
10
4
110
64
300
10
4
111
128
150
11
13
000
1
5908
11
13
001
2
2954
11
13
010
4
1477
11
13
011
8
739
11
13
100
16
369
11
13
101
32
185
11
13
110
64
92
11
13
111
128
46
MC68HC908AT32 Data Sheet, Rev. 3.1
162
Freescale Semiconductor
Chapter 17
Serial Peripheral Interface Module (SPI)
17.1 Introduction
This section describes the serial peripheral interface (SPI) module, which allows full-duplex, synchronous,
serial communications with peripheral devices.
17.2 Features
Features of the SPI module include:
• Full-duplex operation
• Master and slave modes
• Double-buffered operation with separate transmit and receive registers
• Four master mode frequencies (maximum = bus frequency ÷ 2)
• Maximum slave mode frequency = bus frequency
• Serial clock with programmable polarity and phase
• Two separately enabled interrupts with central processor unit (CPU) service:
– SPRF (SPI receiver full)
– SPTE (SPI transmitter empty)
• Mode fault error flag with cpu interrupt capability
• Overflow error flag with cpu interrupt capability
• Programmable wired-OR mode
• I2C (inter-integrated circuit) compatibility
17.3 Pin Name and Register Name Conventions
The generic names of the SPI input/output (I/O) pins are:
• SS (slave select)
• SPSCK (SPI serial clock)
• MOSI (master out slave in)
• MISO (master in slave out)
The SPI shares four I/O pins with a parallel I/O port. The full name of an SPI pin reflects the name of the
shared port pin. Table 17-1 shows the full names of the SPI I/O pins. The generic pin names appear in
the text that follows.
Table 17-1. Pin Name Conventions
SPI Generic Pin Name
Full SPI Pin Name
MISO
MOSI
SS
SPSCK
PTE5/MISO
PTE6/MOSI
PTE4/SS
PTE7/SPSCK
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
163
Serial Peripheral Interface Module (SPI)
The generic names of the SPI I/O registers are:
• SPI control register (SPCR)
• SPI status and control register (SPSCR)
• SPI data register (SPDR)
17.4 Functional Description
Figure 17-1 summarizes the SPI I/O registers and Figure 17-2 shows the structure of the SPI module.
Addr.
$0010
$0011
$0012
Register Name
SPI Control Register Read:
(SPCR) Write:
See page 178. Reset:
SPI Status and Control Register Read:
(SPSCR) Write:
See page 180. Reset:
SPI Data Register Read:
(SPDR) Write:
See page 182. Reset:
Bit 7
6
5
4
3
2
1
Bit 0
SPRIE
R
SPMSTR
CPOL
CPHA
SPWOM
SPE
SPTIE
0
0
1
0
1
0
0
0
OVRF
MODF
SPTE
R
R
R
MODFEN
SPR1
SPR0
SPRF
R
ERRIE
0
0
0
0
1
0
0
0
R7
R6
R5
R4
R3
R2
R1
R0
T7
T6
T5
T4
T3
T2
T1
T0
Unaffected by reset
R
= Reserved
Figure 17-1. SPI I/O Register Summary
The SPI module allows full-duplex, synchronous, serial communication among the MCU and peripheral
devices, including other MCUs. Software can poll the SPI status flags or SPI operation can be interrupt
driven. All SPI interrupts can be serviced by the CPU.
The following paragraphs describe the operation of the SPI module.
17.4.1 Master Mode
The SPI operates in master mode when the SPI master bit, SPMSTR (SPCR $0010), is set.
NOTE
Configure the SPI modules as master and slave before enabling them.
Enable the master SPI before enabling the slave SPI. Disable the slave SPI
before disabling the master SPI. See 17.13.1 SPI Control Register.
Only a master SPI module can initiate transmissions. Software begins the transmission from a master SPI
module by writing to the SPI data register. If the shift register is empty, the byte immediately transfers to
the shift register, setting the SPI transmitter empty bit, SPTE (SPSCR $0011). The byte begins shifting
out on the MOSI pin under the control of the serial clock. See Figure 17-3.
The SPR1 and SPR0 bits control the baud rate generator and determine the speed of the shift register.
(See 17.13.2 SPI Status and Control Register.) Through the SPSCK pin, the baud rate generator of the
master also controls the shift register of the slave peripheral.
MC68HC908AT32 Data Sheet, Rev. 3.1
164
Freescale Semiconductor
Functional Description
INTERNAL BUS
TRANSMIT DATA REGISTER
SHIFT REGISTER
BUS CLOCK
7
6
5
4
3
2
1
MISO
0
÷2
CLOCK
DIVIDER
MOSI
÷8
RECEIVE DATA REGISTER
÷ 32
PIN
CONTROL
LOGIC
÷ 128
SPMSTR
CLOCK
SELECT
SPE
SPR1
SPSCK
M
CLOCK
LOGIC
S
SS
SPR0
SPMSTR
TRANSMITTER CPU INTERRUPT REQUEST
CPHA
CPOL
SPWOM
MODFEN
ERRIE
SPI
CONTROL
SPTIE
RECEIVER/ERROR CPU INTERRUPT REQUEST
SPRIE
SPE
SPRF
SPTE
OVRF
MODF
Figure 17-2. SPI Module Block Diagram
MASTER MCU
SHIFT REGISTER
SLAVE MCU
MISO
MISO
MOSI
MOSI
SPSCK
BAUD RATE
GENERATOR
SS
SHIFT REGISTER
SPSCK
VDD
SS
Figure 17-3. Full-Duplex Master-Slave Connections
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
165
Serial Peripheral Interface Module (SPI)
As the byte shifts out on the MOSI pin of the master, another byte shifts in from the slave on the master’s
MISO pin. The transmission ends when the receiver full bit, SPRF (SPSCR), becomes set. At the same
time that SPRF becomes set, the byte from the slave transfers to the receive data register. In normal
operation, SPRF signals the end of a transmission. Software clears SPRF by reading the SPI status and
control register and then reading the SPI data register. Writing to the SPI data register clears the SPTIE
bit.
17.4.2 Slave Mode
The SPI operates in slave mode when the SPMSTR bit (SPCR, $0010) is clear. In slave mode the SPSCK
pin is the input for the serial clock from the master MCU. Before a data transmission occurs, the SS pin
of the slave MCU must be at logic 0. SS must remain low until the transmission is complete. See 17.6.2
Mode Fault Error.
In a slave SPI module, data enters the shift register under the control of the serial clock from the master
SPI module. After a byte enters the shift register of a slave SPI, it is transferred to the receive data
register, and the SPRF bit (SPSCR) is set. To prevent an overflow condition, slave software then must
read the SPI data register before another byte enters the shift register.
The maximum frequency of the SPSCK for an SPI configured as a slave is the bus clock speed, which is
twice as fast as the fastest master SPSCK clock that can be generated. The frequency of the SPSCK for
an SPI configured as a slave does not have to correspond to any SPI baud rate. The baud rate only
controls the speed of the SPSCK generated by an SPI configured as a master. Therefore, the frequency
of the SPSCK for an SPI configured as a slave can be any frequency less than or equal to the bus speed.
When the master SPI starts a transmission, the data in the slave shift register begins shifting out on the
MISO pin. The slave can load its shift register with a new byte for the next transmission by writing to its
transmit data register. The slave must write to its transmit data register at least one bus cycle before the
master starts the next transmission. Otherwise the byte already in the slave shift register shifts out on the
MISO pin. Data written to the slave shift register during a a transmission remains in a buffer until the end
of the transmission.
When the clock phase bit (CPHA) is set, the first edge of SPSCK starts a transmission. When CPHA is
clear, the falling edge of SS starts a transmission. See 17.5 Transmission Formats.
If the write to the data register is late, the SPI transmits the data already in the shift register from the
previous transmission.
NOTE
To prevent SPSCK from appearing as a clock edge, SPSCK must be in the
proper idle state before the slave is enabled.
17.5 Transmission Formats
During an SPI transmission, data is simultaneously transmitted (shifted out serially) and received (shifted
in serially). A serial clock line synchronizes shifting and sampling on the two serial data lines. A slave
select line allows individual selection of a slave SPI device; slave devices that are not selected do not
interfere with SPI bus activities. On a master SPI device, the slave select line can be used optionally to
indicate a multiple-master bus contention.
MC68HC908AT32 Data Sheet, Rev. 3.1
166
Freescale Semiconductor
Transmission Formats
17.5.1 Clock Phase and Polarity Controls
Software can select any of four combinations of serial clock (SCK) phase and polarity using two bits in
the SPI control register (SPCR). The clock polarity is specified by the CPOL control bit, which selects an
active high or low clock and has no significant effect on the transmission format.
The clock phase (CPHA) control bit (SPCR) selects one of two fundamentally different transmission
formats. The clock phase and polarity should be identical for the master SPI device and the
communicating slave device. In some cases, the phase and polarity are changed between transmissions
to allow a master device to communicate with peripheral slaves having different requirements.
NOTE
Before writing to the CPOL bit or the CPHA bit (SPCR), disable the SPI by
clearing the SPI enable bit (SPE).
17.5.2 Transmission Format When CPHA = 0
Figure 17-4 shows an SPI transmission in which CPHA (SPCR) is logic 0. The figure should not be used
as a replacement for data sheet parametric information. Two waveforms are shown for SCK: one for
CPOL = 0 and another for CPOL = 1. The diagram may be interpreted as a master or slave timing
diagram since the serial clock (SCK), master in/slave out (MISO), and master out/slave in (MOSI) pins
are directly connected between the master and the slave. The MISO signal is the output from the slave,
and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The
slave SPI drives its MISO output only when its slave select input (SS) is at logic 0, so that only the selected
slave drives to the master. The SS pin of the master is not shown but is assumed to be inactive. The SS
pin of the master must be high or must be reconfigured as general-purpose I/O not affecting the SPI. (See
17.6.2 Mode Fault Error.) When CPHA = 0, the first SPSCK edge is the MSB capture strobe. Therefore,
the slave must begin driving its data before the first SPSCK edge, and a falling edge on the SS pin is used
to start the transmission. The SS pin must be toggled high and then low again between each byte
transmitted.
SCK CYCLE #
FOR REFERENCE
1
2
3
4
5
6
7
8
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
SCK CPOL = 0
SCK CPOL = 1
MOSI
FROM MASTER
MISO
FROM SLAVE
MSB
SS TO SLAVE
CAPTURE STROBE
Figure 17-4. Transmission Format (CPHA = 0)
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
167
Serial Peripheral Interface Module (SPI)
17.5.3 Transmission Format When CPHA = 1
Figure 17-5 shows an SPI transmission in which CPHA (SPCR) is logic 1. The figure should not be used
as a replacement for data sheet parametric information. Two waveforms are shown for SCK: one for
CPOL = 0 and another for CPOL = 1. The diagram may be interpreted as a master or slave timing
diagram since the serial clock (SCK), master in/slave out (MISO), and master out/slave in (MOSI) pins
are directly connected between the master and the slave. The MISO signal is the output from the slave,
and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The
slave SPI drives its MISO output only when its slave select input (SS) is at logic 0, so that only the selected
slave drives to the master. The SS pin of the master is not shown but is assumed to be inactive. The SS
pin of the master must be high or must be reconfigured as general-purpose I/O not affecting the SPI. (See
17.6.2 Mode Fault Error.) When CPHA = 1, the master begins driving its MOSI pin on the first SPSCK
edge. Therefore, the slave uses the first SPSCK edge as a start transmission signal. The SS pin can
remain low between transmissions. This format may be preferable in systems having only one master and
only one slave driving the MISO data line.
SCK CYCLE #
FOR REFERENCE
1
2
3
4
5
6
7
8
MOSI
FROM MASTER
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
MISO
FROM SLAVE
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
SCK CPOL = 0
SCK CPOL =1
LSB
SS TO SLAVE
CAPTURE STROBE
Figure 17-5. Transmission Format (CPHA = 1)
17.5.4 Transmission Initiation Latency
When the SPI is configured as a master (SPMSTR = 1), transmissions are started by a software write to
the SPDR ($0012). CPHA has no effect on the delay to the start of the transmission, but it does affect the
initial state of the SCK signal. When CPHA = 0, the SCK signal remains inactive for the first half of the
first SCK cycle. When CPHA = 1, the first SCK cycle begins with an edge on the SCK line from its inactive
to its active level. The SPI clock rate (selected by SPR1–SPR0) affects the delay from the write to SPDR
and the start of the SPI transmission. (See Figure 17-6.) The internal SPI clock in the master is a
free-running derivative of the internal MCU clock. It is only enabled when both the SPE and SPMSTR bits
(SPCR) are set to conserve power. SCK edges occur half way through the low time of the internal MCU
clock. Since the SPI clock is free-running, it is uncertain where the write to the SPDR will occur relative
to the slower SCK. This uncertainty causes the variation in the initiation delay shown in Figure 17-6. This
MC68HC908AT32 Data Sheet, Rev. 3.1
168
Freescale Semiconductor
Transmission Formats
delay will be no longer than a single SPI bit time. That is, the maximum delay between the write to SPDR
and the start of the SPI transmission is two MCU bus cycles for DIV2, eight MCU bus cycles for DIV8, 32
MCU bus cycles for DIV32, and 128 MCU bus cycles for DIV128.
WRITE
TO SPDR
INITIATION DELAY
BUS
CLOCK
MOSI
MSB
BIT 5
BIT 6
SCK
CPHA = 1
SCK
CPHA = 0
SCK CYCLE
NUMBER
1
3
2
INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN
⎧
⎨
⎮
⎮
⎩
⎮
⎮
⎮
WRITE
TO SPDR
BUS
CLOCK
EARLIEST LATEST
SCK = INTERNAL CLOCK ÷ 2;
2 POSSIBLE START POINTS
WRITE
TO SPDR
BUS
CLOCK
EARLIEST
WRITE
TO SPDR
SCK = INTERNAL CLOCK ÷ 8;
8 POSSIBLE START POINTS
LATEST
SCK = INTERNAL CLOCK ÷ 32;
32 POSSIBLE START POINTS
LATEST
SCK = INTERNAL CLOCK ÷ 128;
128 POSSIBLE START POINTS
LATEST
BUS
CLOCK
EARLIEST
WRITE
TO SPDR
BUS
CLOCK
EARLIEST
Figure 17-6. Transmission Start Delay (Master)
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
169
Serial Peripheral Interface Module (SPI)
17.6 Error Conditions
Two flags signal SPI error conditions:
1. Overflow (OVRFin SPSCR) — Failing to read the SPI data register before the next byte enters the
shift register sets the OVRF bit. The new byte does not transfer to the receive data register, and
the unread byte still can be read by accessing the SPI data register. OVRF is in the SPI status and
control register.
2. Mode fault error (MODF in SPSCR) — The MODF bit indicates that the voltage on the slave select
pin (SS) is inconsistent with the mode of the SPI. MODF is in the SPI status and control register.
17.6.1 Overflow Error
The overflow flag (OVRF in SPSCR) becomes set if the SPI receive data register still has unread data
from a previous transmission when the capture strobe of bit 1 of the next transmission occurs. (See Figure
17-4 and Figure 17-5.) If an overflow occurs, the data being received is not transferred to the receive data
register so that the unread data can still be read. Therefore, an overflow error always indicates the loss
of data.
OVRF generates a receiver/error CPU interrupt request if the error interrupt enable bit (ERRIE in SPSCR)
is also set. MODF and OVRF can generate a receiver/error CPU interrupt request. (See Figure 17-9.) It
is not possible to enable only MODF or OVRF to generate a receiver/error CPU interrupt request.
However, leaving MODFEN low prevents MODF from being set.
If an end-of-block transmission interrupt was meant to pull the MCU out of wait, having an overflow
condition without overflow interrupts enabled causes the MCU to hang in wait mode. If the OVRF is
enabled to generate an interrupt, it can pull the MCU out of wait mode instead.
If the CPU SPRF interrupt is enabled and the OVRF interrupt is not, watch for an overflow condition.
Figure 17-7 shows how it is possible to miss an overflow.
BYTE 1
1
BYTE 2
4
BYTE 3
6
BYTE 4
8
SPRF
OVRF
READ SPSCR
READ SPDR
2
5
3
1
BYTE 1 SETS SPRF BIT.
2
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
CPU READS BYTE 1 IN SPDR,
CLEARING SPRF BIT.
BYTE 2 SETS SPRF BIT.
3
4
7
5
6
7
8
CPU READS SPSCRW WITH SPRF BIT SET
AND OVRF BIT CLEAR.
BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT,
BUT NOT OVRF BIT.
BYTE 4 FAILS TO SET SPRF BIT BECAUSE
OVRF BIT IS SET. BYTE 4 IS LOST.
Figure 17-7. Missed Read of Overflow Condition
MC68HC908AT32 Data Sheet, Rev. 3.1
170
Freescale Semiconductor
Error Conditions
The first part of Figure 17-7 shows how to read the SPSCR and SPDR to clear the SPRF without
problems. However, as illustrated by the second transmission example, the OVRF flag can be set in
between the time that SPSCR and SPDR are read.
In this case, an overflow can be easily missed. Since no more SPRF interrupts can be generated until this
OVRF is serviced, it will not be obvious that bytes are being lost as more transmissions are completed.
To prevent this, either enable the OVRF interrupt or do another read of the SPSCR after the read of the
SPDR. This ensures that the OVRF was not set before the SPRF was cleared and that future
transmissions will complete with an SPRF interrupt. Figure 17-8 illustrates this process. Generally, to
avoid this second SPSCR read, enable the OVRF to the CPU by setting the ERRIE bit (SPSCR).
BYTE 1
BYTE 2
BYTE 3
BYTE 4
1
5
7
11
SPI RECEIVE
COMPLETE
SPRF
OVRF
2
READ SPSCR
4
6
9
3
READ SPDR
1
BYTE 1 SETS SPRF BIT.
2
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
CPU READS BYTE 1 IN SPDR,
CLEARING SPRF BIT.
3
8
12
10
8
CPU READS BYTE 2 IN SPDR,
CLEARING SPRF BIT.
9
CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
14
13
10 CPU READS BYTE 2 SPDR,
CLEARING OVRF BIT.
4
CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
11 BYTE 4 SETS SPRF BIT.
5
BYTE 2 SETS SPRF BIT.
12 CPU READS SPSCR.
6
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
13 CPU READS BYTE 4 IN SPDR,
CLEARING SPRF BIT.
7
BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
14 CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
Figure 17-8. Clearing SPRF When OVRF Interrupt Is Not Enabled
17.6.2 Mode Fault Error
For the MODF flag (in SPSCR) to be set, the mode fault error enable bit (MODFEN in SPSCR) must be
set. Clearing the MODFEN bit does not clear the MODF flag but does prevent MODF from being set again
after MODF is cleared.
MODF generates a receiver/error CPU interrupt request if the error interrupt enable bit (ERRIE in SPSCR)
is also set. The SPRF, MODF, and OVRF interrupts share the same CPU interrupt vector. MODF
and OVRF can generate a receiver/error CPU interrupt request. (See Figure 17-9.) It is not possible to
enable only MODF or OVRF to generate a receiver/error CPU interrupt request. However, leaving
MODFEN low prevents MODF from being set.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
171
Serial Peripheral Interface Module (SPI)
In a master SPI with the mode fault enable bit (MODFEN) set, the mode fault flag (MODF) is set if SS
goes to logic 0. A mode fault in a master SPI causes the following events to occur:
• If ERRIE = 1, the SPI generates an SPI receiver/error CPU interrupt request.
• The SPE bit is cleared.
• The SPTE bit is set.
• The SPI state counter is cleared.
• The data direction register of the shared I/O port regains control of port drivers.
NOTE
To prevent bus contention with another master SPI after a mode fault error,
clear all data direction register (DDR) bits associated with the SPI shared
port pins.
NOTE
Setting the MODF flag (SPSCR) does not clear the SPMSTR bit. Reading
SPMSTR when MODF = 1 will indicate a MODE fault error occurred in
either master mode or slave mode.
When configured as a slave (SPMSTR = 0), the MODF flag is set if SS goes high during a transmission.
When CPHA = 0, a transmission begins when SS goes low and ends once the incoming SPSCK returns
to its idle level after the shift of the eighth data bit. When CPHA = 1, the transmission begins when the
SPSCK leaves its idle level and SS is already low. The transmission continues until the SPSCK returns
to its IDLE level after the shift of the last data bit. See 17.5 Transmission Formats.
NOTE
When CPHA = 0, a MODF occurs if a slave is selected (SS is at logic 0) and
later unselected (SS is at logic 1) even if no SPSCK is sent to that slave.
This happens because SS at logic 0 indicates the start of the transmission
(MISO driven out with the value of MSB) for CPHA = 0. When CPHA = 1, a
slave can be selected and then later unselected with no transmission
occurring. Therefore, MODF does not occur since a transmission was
never begun.
In a slave SPI (MSTR = 0), the MODF bit generates an SPI receiver/error CPU interrupt request if the
ERRIE bit is set. The MODF bit does not clear the SPE bit or reset the SPI in any way. Software can abort
the SPI transmission by toggling the SPE bit of the slave.
NOTE
A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high
impedance state. Also, the slave SPI ignores all incoming SPSCK clocks,
even if a transmission has begun.
To clear the MODF flag, read the SPSCR and then write to the SPCR register. This entire clearing
procedure must occur with no MODF condition existing or else the flag will not be cleared.
MC68HC908AT32 Data Sheet, Rev. 3.1
172
Freescale Semiconductor
Interrupts
17.7 Interrupts
Four SPI status flags can be enabled to generate CPU interrupt requests:
Table 17-2. SPI Interrupts
Flag
Request
SPTE (transmitter empty)
SPI transmitter CPU interrupt request (SPTIE = 1)
SPRF (receiver full)
SPI receiver CPU interrupt request (SPRIE = 1)
OVRF (overflow)
SPI receiver/error interrupt request
(SPRIE = 1, ERRIE = 1)
MODF (mode fault)
SPI receiver/error interrupt request
(SPRIE = 1, ERRIE = 1, MODFEN = 1)
The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag to generate transmitter CPU
interrupt requests.
The SPI receiver interrupt enable bit (SPRIE) enables the SPRF bit to generate receiver CPU interrupt,
provided that the SPI is enabled (SPE = 1).
The error interrupt enable bit (ERRIE) enables both the MODF and OVRF flags to generate a
receiver/error CPU interrupt request.
The mode fault enable bit (MODFEN) can prevent the MODF flag from being set so that only the OVRF
flag is enabled to generate receiver/error CPU interrupt requests.
SPTE
SPTIE
SPE
SPI TRANSMITTER
CPU INTERRUPT REQUEST
SPRIE
ERRIE
SPRF
SPI RECEIVER/ERROR
CPU INTERRUPT REQUEST
MODF
OVRF
Figure 17-9. SPI Interrupt Request Generation
Two sources in the SPI status and control register can generate CPU interrupt requests:
1. SPI receiver full bit (SPRF) — The SPRF bit becomes set every time a byte transfers from the shift
register to the receive data register. If the SPI receiver interrupt enable bit, SPRIE, is also set,
SPRF can generate an SPI receiver/error CPU interrupt request.
2. SPI transmitter empty (SPTE) — The SPTE bit becomes set every time a byte transfers from the
transmit data register to the shift register. If the SPI transmit interrupt enable bit, SPTIE, is also set,
SPTE can generate an SPTE CPU interrupt request.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
173
Serial Peripheral Interface Module (SPI)
17.8 Queuing Transmission Data
The double-buffered transmit data register allows a data byte to be queued and transmitted. For an SPI
configured as a master, a queued data byte is transmitted immediately after the previous transmission
has completed. The SPI transmitter empty flag (SPTE in SPSCR) indicates when the transmit data buffer
is ready to accept new data. Write to the SPI data register only when the SPTE bit is high. Figure 17-10
shows the timing associated with doing back-to-back transmissions with the SPI (SPSCK has
CPHA:CPOL = 1:0).
For a slave, the transmit data buffer allows back-to-back transmissions to occur without the slave having
to time the write of its data between the transmissions. Also, if no new data is written to the data buffer,
the last value contained in the shift register will be the next data word transmitted.
WRITE TO SPDR
SPTE
1
3
8
5
2
10
SPSCK (CPHA:CPOL = 1:0)
MOSI
MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT
6 5 4 3 2 1
6 5 4 3 2 1
6 5 4
BYTE 1
BYTE 2
BYTE 3
6
READ SPSCR
11
7
READ SPDR
1
9
4
SPRF
CPU WRITES BYTE 1 TO SPDR, CLEARING
SPTE BIT.
2
BYTE 1 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
3
CPU WRITES BYTE 2 TO SPDR, QUEUEING
BYTE 2 AND CLEARING SPTE BIT.
4
FIRST INCOMING BYTE TRANSFERS FROM SHIFT
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
5
BYTE 2 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
6
CPU READS SPSCR WITH SPRF BIT SET.
12
7
CPU READS SPDR, CLEARING SPRF BIT.
8
CPU WRITES BYTE 3 TO SPDR, QUEUEING
BYTE 3 AND CLEARING SPTE BIT.
9
SECOND INCOMING BYTE TRANSFERS FROM SHIFT
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
10 BYTE 3 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
11 CPU READS SPSCR WITH SPRF BIT SET.
12 CPU READS SPDR, CLEARING SPRF BIT.
Figure 17-10. SPRF/SPTE CPU Interrupt Timing
MC68HC908AT32 Data Sheet, Rev. 3.1
174
Freescale Semiconductor
Resetting the SPI
17.9 Resetting the SPI
Any system reset completely resets the SPI. Partial resets occur whenever the SPI enable bit (SPE) is
low. Whenever SPE is low, the following occurs:
• The SPTE flag is set.
• Any transmission currently in progress is aborted.
• The shift register is cleared.
• The SPI state counter is cleared, making it ready for a new complete transmission.
• All the SPI port logic is defaulted back to being general-purpose I/O.
These additional items are reset only by a system reset:
• All control bits in the SPCR register
• All control bits in the SPSCR register (MODFEN, ERRIE, SPR1, and SPR0)
• The status flags SPRF, OVRF, and MODF
By not resetting the control bits when SPE is low, the user can clear SPE between transmissions without
having to reset all control bits when SPE is set back to high for the next transmission.
By not resetting the SPRF, OVRF, and MODF flags, the user can still service these interrupts after the
SPI has been disabled. The user can disable the SPI by writing 0 to the SPE bit. The SPI also can be
disabled by a mode fault occurring in an SPI that was configured as a master with the MODFEN bit set.
17.10 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power standby modes.
17.10.1 Wait Mode
The SPI module remains active after the execution of a WAIT instruction. In wait mode, the SPI module
registers are not accessible by the CPU. Any enabled CPU interrupt request from the SPI module can
bring the MCU out of wait mode.
If SPI module functions are not required during wait mode, reduce power consumption by disabling the
SPI module before executing the WAIT instruction.
To exit wait mode when an overflow condition occurs, enable the OVRF bit to generate CPU interrupt
requests by setting the error interrupt enable bit (ERRIE). See 17.7 Interrupts.
17.10.2 Stop Mode
The SPI module is inactive after the execution of a STOP instruction. The STOP instruction does not
affect register conditions. SPI operation resumes after the MCU exits stop mode. If stop mode is exited
by reset, any transfer in progress is aborted and the SPI is reset.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
175
Serial Peripheral Interface Module (SPI)
17.11 SPI during Break Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the SIM break flag control register (SBFCR, $FE03) enables software to
clear status bits during the break state. See 7.7.3 SIM Break Flag Control Register.
To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status
bit is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its
default state), software can read and write I/O registers during the break state without affecting status bits.
Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit
before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the
break, doing the second step clears the status bit.
Since the SPTE bit cannot be cleared during a break with the BCFE bit cleared, a write to the data register
in break mode will not initiate a transmission nor will this data be transferred into the shift register.
Therefore, a write to the SPDR in break mode with the BCFE bit cleared has no effect.
17.12 I/O Signals
The SPI module has five I/O pins and shares three of them with a parallel I/O port. They are:
• MISO — Data received
• MOSI — Data transmitted
• SPSCK — Serial clock
• SS — Slave select
• VSS — Clock ground
The SPI has limited inter-integrated circuit (I2C) capability (requiring software support) as a master in a
single-master environment. To communicate with I2C peripherals, MOSI becomes an open-drain output
when the SPWOM bit in the SPI control register is set. In I2C communication, the MOSI and MISO pins
are connected to a bidirectional pin from the I2C peripheral and through a pullup resistor to VDD.
17.12.1 MISO (Master In/Slave Out)
MISO is one of the two SPI module pins that transmit serial data. In full duplex operation, the MISO pin
of the master SPI module is connected to the MISO pin of the slave SPI module. The master SPI
simultaneously receives data on its MISO pin and transmits data from its MOSI pin.
Slave output data on the MISO pin is enabled only when the SPI is configured as a slave. The SPI is
configured as a slave when its SPMSTR bit is logic 0 and its SS pin is at logic 0. To support a
multiple-slave system, a logic 1 on the SS pin puts the MISO pin in a high-impedance state.
When enabled, the SPI controls data direction of the MISO pin regardless of the state of the data direction
register of the shared I/O port.
MC68HC908AT32 Data Sheet, Rev. 3.1
176
Freescale Semiconductor
I/O Signals
17.12.2 MOSI (Master Out/Slave In)
MOSI is one of the two SPI module pins that transmit serial data. In full duplex operation, the MOSI pin
of the master SPI module is connected to the MOSI pin of the slave SPI module. The master SPI
simultaneously transmits data from its MOSI pin and receives data on its MISO pin.
When enabled, the SPI controls data direction of the MOSI pin regardless of the state of the data direction
register of the shared I/O port.
17.12.3 SPSCK (Serial Clock)
The serial clock synchronizes data transmission among master and slave devices. In a master MCU, the
SPSCK pin is the clock output. In a slave MCU, the SPSCK pin is the clock input. In full-duplex operation,
the master and slave MCUs exchange a byte of data in eight serial clock cycles.
When enabled, the SPI controls data direction of the SPSCK pin regardless of the state of the data
direction register of the shared I/O port.
17.12.4 SS (Slave Select)
The SS pin has various functions depending on the current state of the SPI. For an SPI configured as a
slave, the SS is used to select a slave. For CPHA = 0, the SS is used to define the start of a transmission.
(See 17.5 Transmission Formats.) Since it is used to indicate the start of a transmission, the SS must be
toggled high and low between each byte transmitted for the CPHA = 0 format. However, it can remain low
throughout the transmission for the CPHA = 1 format. See Figure 17-11.
MISO/MOSI
BYTE 1
BYTE 2
BYTE 3
MASTER SS
SLAVE SS
CPHA = 0
SLAVE SS
CPHA = 1
Figure 17-11. CPHA/SS Timing
When an SPI is configured as a slave, the SS pin is always configured as an input. It cannot be used as
a general-purpose I/O regardless of the state of the MODFEN control bit. However, the MODFEN bit can
still prevent the state of the SS from creating a MODF error. See 17.13.2 SPI Status and Control Register.
NOTE
A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a
high-impedance state. The slave SPI ignores all incoming SPSCK clocks,
even if a transmission already has begun.
When an SPI is configured as a master, the SS input can be used in conjunction with the MODF flag to
prevent multiple masters from driving MOSI and SPSCK. (See 17.6.2 Mode Fault Error.) For the state of
the SS pin to set the MODF flag, the MODFEN bit in the SPSCK register must be set. If the MODFEN bit
is low for an SPI master, the SS pin can be used as a general-purpose I/O under the control of the data
direction register of the shared I/O port. With MODFEN high, it is an input-only pin to the SPI regardless
of the state of the data direction register of the shared I/O port.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
177
Serial Peripheral Interface Module (SPI)
The CPU can always read the state of the SS pin by configuring the appropriate pin as an input and
reading the data register.
See Table 17-3.
Table 17-3. SPI Configuration
SPE
SPMSTR
MODFEN
SPI Configuration
State of SS Logic
0
X
X
Not enabled
General-purpose I/O;
SS ignored by SPI
1
0
X
Slave
Input-only to SPI
1
1
0
Master without MODF
General-purpose I/O;
SS ignored by SPI
1
1
1
Master with MODF
Input-only to SPI
X = don’t care
17.12.5 VSS (Clock Ground)
VSS is the ground return for the serial clock pin, SPSCK, and the ground for the port output buffers. To
reduce the ground return path loop and minimize radio frequency (RF) emissions, connect the ground pin
of the slave to the VSS pin.
17.13 I/O Registers
Three registers control and monitor SPI operation:
• SPI control register (SPCR, $0010)
• SPI status and control register (SPSCR, $0011)
• SPI data register (SPDR, $0012)
17.13.1 SPI Control Register
The SPI control register:
• Enables SPI module interrupt requests
• Selects CPU interrupt requests
• Configures the SPI module as master or slave
• Selects serial clock polarity and phase
• Configures the SPSCK, MOSI, and MISO pins as open-drain outputs
• Enables the SPI module
Address:
Read:
Write:
Reset:
$0010
Bit 7
6
5
4
3
2
1
Bit 0
SPRIE
R
SPMSTR
CPOL
CPHA
SPWOM
SPE
SPTIE
0
0
1
0
1
0
0
0
R
= Reserved
Figure 17-12. SPI Control Register (SPCR)
MC68HC908AT32 Data Sheet, Rev. 3.1
178
Freescale Semiconductor
I/O Registers
SPRIE — SPI Receiver Interrupt Enable Bit
This read/write bit enables CPU interrupt requests generated by the SPRF bit. The SPRF bit is set
when a byte transfers from the shift register to the receive data register. Reset clears the SPRIE bit.
1 = SPRF CPU interrupt requests enabled
0 = SPRF CPU interrupt requests disabled
SPMSTR — SPI Master Bit
This read/write bit selects master mode operation or slave mode operation. Reset sets the SPMSTR
bit.
1 = Master mode
0 = Slave mode
CPOL — Clock Polarity Bit
This read/write bit determines the logic state of the SPSCK pin between transmissions. (See Figure
17-4 and Figure 17-5.) To transmit data between SPI modules, the SPI modules must have identical
CPOL bits. Reset clears the CPOL bit.
CPHA — Clock Phase Bit
This read/write bit controls the timing relationship between the serial clock and SPI data. (See Figure
17-4 and Figure 17-5.) To transmit data between SPI modules, the SPI modules must have identical
CPHA bits. When CPHA = 0, the SS pin of the slave SPI module must be set to logic 1 between bytes.
(See Figure 17-11.) Reset sets the CPHA bit.
When CPHA = 0 for a slave, the falling edge of SS indicates the beginning of the transmission. This
causes the SPI to leave its idle state and begin driving the MISO pin with the MSB of its data. Once
the transmission begins, no new data is allowed into the shift register from the data register. Therefore,
the slave data register must be loaded with the desired transmit data before the falling edge of SS. Any
data written after the falling edge is stored in the data register and transferred to the shift register at
the current transmission.
When CPHA = 1 for a slave, the first edge of the SPSCK indicates the beginning of the transmission.
The same applies when SS is high for a slave. The MISO pin is held in a high-impedance state, and
the incoming SPSCK is ignored. In certain cases, it may also cause the MODF flag to be set. (See
17.6.2 Mode Fault Error.) A logic 1 on the SS pin does not in any way affect the state of the SPI state
machine.
SPWOM — SPI Wired-OR Mode Bit
This read/write bit disables the pullup devices on pins SPSCK, MOSI, and MISO so that those pins
become open-drain outputs.
1 = Wired-OR SPSCK, MOSI, and MISO pins
0 = Normal push-pull SPSCK, MOSI, and MISO pins
SPE — SPI Enable Bit
This read/write bit enables the SPI module. Clearing SPE causes a partial reset of the SPI. (See 17.9
Resetting the SPI.) Reset clears the SPE bit.
1 = SPI module enabled
0 = SPI module disabled
SPTIE — SPI Transmit Interrupt Enable Bit
This read/write bit enables CPU interrupt requests generated by the SPTE bit. SPTE is set when a byte
transfers from the transmit data register to the shift register. Reset clears the SPTIE bit.
1 = SPTE CPU interrupt requests enabled
0 = SPTE CPU interrupt requests disabled
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
179
Serial Peripheral Interface Module (SPI)
17.13.2 SPI Status and Control Register
The SPI status and control register contains flags to signal the following conditions:
• Receive data register full
• Failure to clear SPRF bit before next byte is received (overflow error)
• Inconsistent logic level on SS pin (mode fault error)
• Transmit data register empty
The SPI status and control register also contains bits that perform these functions:
• Enable error interrupts
• Enable mode fault error detection
• Select master SPI baud rate
Address:
$0011
Bit 7
Read:
SPRF
Write:
R
Reset:
6
ERRIE
0
0
R
= Reserved
5
4
3
OVRF
MODF
SPTE
R
R
R
0
0
1
2
1
Bit 0
MODFEN
SPR1
SPR0
0
0
0
Figure 17-13. SPI Status and Control Register (SPSCR)
SPRF — SPI Receiver Full Bit
This clearable, read-only flag is set each time a byte transfers from the shift register to the receive data
register. SPRF generates a CPU interrupt request if the SPRIE bit in the SPI control register is set also.
During an SPRF CPU interrupt, the CPU clears SPRF by reading the SPI status and control register
with SPRF set and then reading the SPI data register. Any read of the SPI data register clears the
SPRF bit.
Reset clears the SPRF bit.
1 = Receive data register full
0 = Receive data register not full
ERRIE — Error Interrupt Enable Bit
This read-only bit enables the MODF and OVRF flags to generate CPU interrupt requests. Reset
clears the ERRIE bit.
1 = MODF and OVRF can generate CPU interrupt requests
0 = MODF and OVRF cannot generate CPU interrupt requests
OVRF — Overflow Bit
This clearable, read-only flag is set if software does not read the byte in the receive data register before
the next byte enters the shift register. In an overflow condition, the byte already in the receive data
register is unaffected, and the byte that shifted in last is lost. Clear the OVRF bit by reading the SPI
status and control register with OVRF set and then reading the SPI data register. Reset clears the
OVRF flag.
1 = Overflow
0 = No overflow
MC68HC908AT32 Data Sheet, Rev. 3.1
180
Freescale Semiconductor
I/O Registers
MODF — Mode Fault Bit
This clearable, read-only flag is set in a slave SPI if the SS pin goes high during a transmission. In a
master SPI, the MODF flag is set if the SS pin goes low at any time. Clear the MODF bit by reading
the SPI status and control register with MODF set and then writing to the SPI data register. Reset
clears the MODF bit.
1 = SS pin at inappropriate logic level
0 = SS pin at appropriate logic level
SPTE — SPI Transmitter Empty Bit
This clearable, read-only flag is set each time the transmit data register transfers a byte into the shift
register. SPTE generates an SPTE CPU interrupt request if the SPTIE bit in the SPI control register is
set also.
NOTE
Do not write to the SPI data register unless the SPTE bit is high.
For an idle master or idle slave that has no data loaded into its transmit buffer, the SPTE will be set
again within two bus cycles since the transmit buffer empties into the shift register. This allows the user
to queue up a 16-bit value to send. For an already active slave, the load of the shift register cannot
occur until the transmission is completed. This implies that a back-to-back write to the transmit data
register is not possible. The SPTE indicates when the next write can occur. Reset sets the SPTE bit.
1 = Transmit data register empty
0 = Transmit data register not empty
MODFEN — Mode Fault Enable Bit
This read/write bit, when set to 1, allows the MODF flag to be set. If the MODF flag is set, clearing the
MODFEN does not clear the MODF flag. If the SPI is enabled as a master and the MODFEN bit is low,
then the SS pin is available as a general-purpose I/O.
If the MODFEN bit is set, then this pin is not available as a general- purpose I/O. When the SPI is
enabled as a slave, the SS pin is not available as a general-purpose I/O regardless of the value of
MODFEN. See 17.12.4 SS (Slave Select).
If the MODFEN bit is low, the level of the SS pin does not affect the operation of an enabled SPI
configured as a master. For an enabled SPI configured as a slave, having MODFEN low only prevents
the MODF flag from being set. It does not affect any other part of SPI operation. See 17.6.2 Mode Fault
Error.
SPR1 and SPR0 — SPI Baud Rate Select Bits
In master mode, these read/write bits select one of four baud rates as shown in Table 17-4. SPR1 and
SPR0 have no effect in slave mode. Reset clears SPR1 and SPR0.
Table 17-4. SPI Master Baud Rate Selection
SPR1:SPR0
Baud Rate Divisor (BD)
00
2
01
8
10
32
11
128
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
181
Serial Peripheral Interface Module (SPI)
Use this formula to calculate the SPI baud rate:
Baud rate =
CGMOUT Bus clock
=
2 x BD
BD
where:
CGMOUT = base clock output of the clock generator module (CGM), see Chapter 8 Clock Generator
Module (CGM).
BD = baud rate divisor
17.13.3 SPI Data Register
The SPI data register is the read/write buffer for the receive data register and the transmit data register.
Writing to the SPI data register writes data into the transmit data register. Reading the SPI data register
reads data from the receive data register. The transmit data and receive data registers are separate
buffers that can contain different values. See Figure 17-2.
Address:
$0012
Bit 7
6
5
4
3
2
1
Bit 0
Read:
R7
R6
R5
R4
R3
R2
R1
R0
Write:
T7
T6
T5
T4
T3
T2
T1
T0
Reset:
Indeterminate after reset
Figure 17-14. SPI Data Register (SPDR)
R7–R0/T7–T0 — Receive/Transmit Data Bits
NOTE
Do not use read-modify-write instructions on the SPI data register since the
buffer read is not the same as the buffer written.
MC68HC908AT32 Data Sheet, Rev. 3.1
182
Freescale Semiconductor
Controller Area Network (CAN)
The following section of modules is MC68HC01AZ32 emulator, 64-pin quad flat pack (QFP), protocol
specific.
References to earlier sections are provided for those modules that are common to both:
• The MC68HC08AZ32 emulator, 64-pin QFP, protocol
• The MC68HC08AS20 emulator, 52-pin plastic-leaded chip carrier (PLCC), protocol
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
183
Controller Area Network (CAN)
MC68HC908AT32 Data Sheet, Rev. 3.1
184
Freescale Semiconductor
Chapter 18
Timer Interface (TIMA-4)
NOTE
This timer is for the MC68HC08AZ32 emulator protocol only.
18.1 Introduction
This section describes the timer interface module (TIMA-4). The TIMA is a 4-channel timer that provides
a timing reference with input capture, output compare, and pulse-width modulation functions. Figure 18-1
is a block diagram of the TIMA.
18.2 Features
Features of the TIMA-4 include:
• Four input capture/output compare channels
– Rising-edge, falling-edge, or any-edge input capture trigger
– Set, clear, or toggle output compare action
• Buffered and unbuffered pulse width-modulation (PWM) signal generation
• Programmable TIMA clock input:
– 7-frequency internal bus clock prescaler selection
– External TIMA clock input (4-MHz maximum frequency)
• Free-running or modulo up-counter operation
• Toggle any channel pin on overflow
• TIMA counter stop and reset bits
18.3 Functional Description
Figure 18-1 shows the TIMA structure. The central component of the TIMA is the 16-bit TIMA counter that
can operate as a free-running counter or a modulo up-counter. The TIMA counter provides the timing
reference for the input capture and output compare functions. The TIMA counter modulo registers,
TAMODH–TAMODL, control the modulo value of the TIMA counter. Software can read the TIMA counter
value at any time without affecting the counting sequence.
The four TIMA channels are programmable independently as input capture or output compare channels.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
185
Timer Interface (TIMA-4)
TCLK
PTD6/ATD14/TACLK
PRESCALER SELECT
INTERNAL
BUS CLOCK
PRESCALER
TSTOP
PS2
TRST
PS1
PS0
16-BIT COUNTER
TOF
TOIE
INTERRUPT
LOGIC
16-BIT COMPARATOR
TMODH:TMODL
CHANNEL 0
ELS0B
ELS0A
TOV0
CH0MAX
16-BIT COMPARATOR
TCH0H:TCH0L
CH0F
16-BIT LATCH
MS0A
CHANNEL 1
ELS1B
MS0B
ELS1A
TOV1
CH1MAX
16-BIT COMPARATOR
TCH1H:TCH1L
CH0IE
CH1F
16-BIT LATCH
CH1IE
MS1A
CHANNEL 2
ELS2B
ELS2A
TOV2
CH2MAX
16-BIT COMPARATOR
TCH2H:TCH2L
CH2F
16-BIT LATCH
MS2A
CHANNEL 3
ELS3B
MS2B
ELS3A
TOV3
CH3MAX
16-BIT COMPARATOR
TCH3H:TCH3L
CH2IE
CH3F
16-BIT LATCH
MS3A
CH3IE
PTE2
LOGIC
PTE2/TACH0
INTERRUPT
LOGIC
PTE3
LOGIC
PTE3/TACH1
INTERRUPT
LOGIC
PTF0
LOGIC
PTF0/TACH2
INTERRUPT
LOGIC
PTF1
LOGIC
PTF1/TACH3
INTERRUPT
LOGIC
Figure 18-1. TIMA Block Diagram
MC68HC908AT32 Data Sheet, Rev. 3.1
186
Freescale Semiconductor
Functional Description
Addr.
$0020
$0021
$0022
$0023
$0024
$0025
Register Name
Bit 7
$0028
TOIE
TSTOP
TOF
0
0
1
Read:
Keyboard Interrupt Enable Register
(KBIER) Write:
See page 285.
Reset:
0
0
0
0
4
3
2
1
Bit 0
0
0
TRST
R
PS2
PS1
PS0
0
0
0
0
0
KBIE4
KBIE3
KBIE2
KBIE1
KBIE0
0
0
0
0
0
0
0
0
Read:
Timer A Counter Register
High (TACNTH) Write:
See page 197.
Reset:
Bit 15
14
13
12
11
10
9
Bit 8
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
Read:
Timer A Counter Register
Low (TACNTL) Write:
See page 197.
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
1
1
1
1
1
1
1
1
Bit 7
6
5
4
3
2
1
Bit 0
1
1
1
1
1
1
1
1
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
Read:
Timer A Modulo Register
High (TAMODH) Write:
See page 197.
Reset:
Read:
Timer A Modulo Register
Low (TAMODL) Write:
See page 197.
Reset:
Read:
Timer A Channel 0 Register
High (TACH0H) Write:
See page 201.
Reset:
Read:
Timer A Channel 0 Register
Low (TACH0L) Write:
See page 201.
Reset:
Read:
Timer A Channel 1 Status and Control
$0029
Register (TASC1) Write:
See page 198.
Reset:
$002A
5
Read:
Timer A Status and Control Register
(TASC) Write:
See page 195.
Reset:
Read:
Timer A Channel 0 Status and Control
$0026
Register (TASC0) Write:
See page 198.
Reset:
$0027
6
Read:
Timer A Channel 1 Register
High (TACH1H) Write:
See page 201.
Reset:
CH0F
0
Indeterminate after reset
Bit 7
6
5
4
3
Indeterminate after reset
CH1F
0
CH1IE
0
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
R
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
Indeterminate after reset
= Unimplemented
R
= Reserved
Figure 18-2. TIM I/O Register Summary
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
187
Timer Interface (TIMA-4)
Addr.
Register Name
$002B
Read:
Timer A Channel 1 Register
Low (TACH1L) Write:
See page 201.
Reset:
Read:
Timer A Channel 2 Status and Control
$002C
Register (TASC2) Write:
See page 198.
Reset:
$002D
$002E
Read:
Timer A Channel 2 Register
High (TACH2H) Write:
See page 201.
Reset:
Read:
Timer A Channel 2 Register
Low (TACH2L) Write:
See page 201.
Reset:
Read:
Timer A Channel 3 Status and Control
$002F
Register (TASC3) Write:
See page 201.
Reset:
$0030
$0031
Read:
Timer A Channel 3 Register
High (TACH3H) Write:
See page 201.
Reset:
Read:
Timer A Channel 3 Register
Low (TACH3L) Write:
See page 201.
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Indeterminate after reset
CH2F
CH2IE
MS2B
MS2A
ELS2B
ELS2A
TOV2
CH2MAX
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
0
Indeterminate after reset
Bit 7
6
5
4
3
Indeterminate after reset
CH3F
0
CH3IE
0
MS3A
ELS3B
ELS3A
TOV3
CH3MAX
R
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
Indeterminate after reset
Bit 7
6
5
4
3
Indeterminate after reset
= Unimplemented
R
= Reserved
Figure 18-2. TIM I/O Register Summary (Continued)
18.3.1 TIMA Counter Prescaler
The TIMA clock source can be one of the seven prescaler outputs or the TIMA clock pin,
PTD6/ATD14/TACLK. The prescaler generates seven clock rates from the internal bus clock. The
prescaler select bits, PS[2:0], in the TIMA status and control register select the TIMA clock source.
18.3.2 Input Capture
An input capture function has three basic parts: edge select logic, an input capture latch, and a 16-bit
counter. Two 8-bit registers, which make up the 16-bit input capture register, are used to latch the value
of the free-running counter after the corresponding input capture edge detector senses a defined
transition. The polarity of the active edge is programmable. The level transition which triggers the counter
transfer is defined by the corresponding input edge bits (ELSxB and ELSxA in TASC0 through TASC3
control registers with x referring to the active channel number). When an active edge occurs on the pin of
an input capture channel, the TIMA latches the contents of the TIMA counter into the TIMA channel
registers, TACHxH–TACHxL. Input captures can generate TIMA CPU interrupt requests. Software can
MC68HC908AT32 Data Sheet, Rev. 3.1
188
Freescale Semiconductor
Functional Description
determine that an input capture event has occurred by enabling input capture interrupts or by polling the
status flag bit.
The result obtained by an input capture will be two more than the value of the free-running counter on the
rising edge of the internal bus clock preceding the external transition. This delay is required for internal
synchronization.
The free-running counter contents are transferred to the TIMA channel status and control register
(TACHxH–TACHxL, see 18.8.5 TIMA Channel Registers) on each proper signal transition regardless of
whether the TIMA channel flag (CH0F–CH5F in TASC0–TASC5 registers) is set or clear. When the status
flag is set, a CPU interrupt is generated if enabled. The value of the count latched or “captured” is the time
of the event. Because this value is stored in the input capture register two bus cycles after the actual event
occurs, user software can respond to this event at a later time and determine the actual time of the event.
However, this must be done prior to another input capture on the same pin; otherwise, the previous time
value will be lost.
By recording the times for successive edges on an incoming signal, software can determine the period
and/or pulse width of the signal. To measure a period, two successive edges of the same polarity are
captured. To measure a pulse width, two alternate polarity edges are captured. Software should track the
overflows at the 16-bit module counter to extend its range.
Another use for the input capture function is to establish a time reference. In this case, an input capture
function is used in conjunction with an output compare function. For example, to activate an output signal
a specified number of clock cycles after detecting an input event (edge), use the input capture function to
record the time at which the edge occurred. A number corresponding to the desired delay is added to this
captured value and stored to an output compare register (see 18.8.5 TIMA Channel Registers). Because
both input captures and output compares are referenced to the same 16-bit modulo counter, the delay
can be controlled to the resolution of the counter independent of software latencies.
Reset does not affect the contents of the input capture channel registers.
18.3.3 Output Compare
With the output compare function, the TIMA can generate a periodic pulse with a programmable polarity,
duration, and frequency. When the counter reaches the value in the registers of an output compare
channel, the TIMA can set, clear, or toggle the channel pin. Output compares can generate TIMA CPU
interrupt requests.
18.3.3.1 Unbuffered Output Compare
Any output compare channel can generate unbuffered output compare pulses as described in 18.3.3
Output Compare. The pulses are unbuffered because changing the output compare value requires writing
the new value over the old value currently in the TIMA channel registers.
An unsynchronized write to the TIMA channel registers to change an output compare value could cause
incorrect operation for up to two counter overflow periods. For example, writing a new value before the
counter reaches the old value but after the counter reaches the new value prevents any compare during
that counter overflow period. Also, using a TIMA overflow interrupt routine to write a new, smaller output
compare value may cause the compare to be missed. The TIMA may pass the new value before it is
written.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
189
Timer Interface (TIMA-4)
Use the following methods to synchronize unbuffered changes in the output compare value on channel x:
• When changing to a smaller value, enable channel x output compare interrupts and write the new
value in the output compare interrupt routine. The output compare interrupt occurs at the end of
the current output compare pulse. The interrupt routine has until the end of the counter overflow
period to write the new value.
• When changing to a larger output compare value, enable channel x TIMA overflow interrupts and
write the new value in the TIMA overflow interrupt routine. The TIMA overflow interrupt occurs at
the end of the current counter overflow period. Writing a larger value in an output compare interrupt
routine (at the end of the current pulse) could cause two output compares to occur in the same
counter overflow period.
18.3.3.2 Buffered Output Compare
Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the
PTE2/TACH0 pin. The TIMA channel registers of the linked pair alternately control the output.
Setting the MS0B bit in TIMA channel 0 status and control register (TASC0) links channel 0 and
channel 1. The output compare value in the TIMA channel 0 registers initially controls the output on the
PTE2/TACH0 pin. Writing to the TIMA channel 1 registers enables the TIMA channel 1 registers to
synchronously control the output after the TIMA overflows. At each subsequent overflow, the TIMA
channel registers (0 or 1) that control the output are the ones written to last. TASC0 controls and monitors
the buffered output compare function, and TIMA channel 1 status and control register (TASC1) is unused.
While the MS0B bit is set, the channel 1 pin, PTE3/TACH1, is available as a general-purpose I/O pin.
Channels 2 and 3 can be linked to form a buffered output compare channel whose output appears on the
PTF0/TACH2 pin. The TIMA channel registers of the linked pair alternately control the output.
Setting the MS2B bit in TIMA channel 2 status and control register (TASC2) links channel 2 and channel
3. The output compare value in the TIMA channel 2 registers initially controls the output on the
PTF0/TACH2 pin. Writing to the TIMA channel 3 registers enables the TIMA channel 3 registers to
synchronously control the output after the TIMA overflows. At each subsequent overflow, the TIMA
channel registers (2 or 3) that control the output are the ones written to last. TASC2 controls and monitors
the buffered output compare function, and TIMA channel 3 status and control register (TASC3) is unused.
While the MS2B bit is set, the channel 3 pin, PTF1/TACH3, is available as a general-purpose I/O pin.
NOTE
In buffered output compare operation, do not write new output compare
values to the currently active channel registers. Writing to the active
channel registers is the same as generating unbuffered output compares.
18.3.4 Pulse-Width Modulation (PWM)
By using the toggle-on-overflow feature with an output compare channel, the TIMA can generate a PWM
signal. The value in the TIMA counter modulo registers determines the period of the PWM signal. The
channel pin toggles when the counter reaches the value in the TIMA counter modulo registers. The time
between overflows is the period of the PWM signal.
As Figure 18-3 shows, the output compare value in the TIMA channel registers determines the pulse width
of the PWM signal. The time between overflow and output compare is the pulse width. Program the TIMA
to clear the channel pin on output compare if the state of the PWM pulse is logic 1. Program the TIMA to
set the pin if the state of the PWM pulse is logic 0.
MC68HC908AT32 Data Sheet, Rev. 3.1
190
Freescale Semiconductor
Functional Description
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
PULSE
WIDTH
PTEx/TCHx
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 18-3. PWM Period and Pulse Width
The value in the TIMA counter modulo registers and the selected prescaler output determines the
frequency of the PWM output. The frequency of an 8-bit PWM signal is variable in 256 increments. Writing
$00FF (255) to the TIMA counter modulo registers produces a PWM period of 256 times the internal bus
clock period if the prescaler select value is $000 (see 18.8.1 TIMA Status and Control Register).
The value in the TIMA channel registers determines the pulse width of the PWM output. The pulse width
of an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIMA channel registers
produces a duty cycle of 128/256 or 50 percent.
18.3.4.1 Unbuffered PWM Signal Generation
Any output compare channel can generate unbuffered PWM pulses as described in 18.3.4 Pulse-Width
Modulation (PWM). The pulses are unbuffered because changing the pulse width requires writing the new
pulse width value over the value currently in the TIMA channel registers.
An unsynchronized write to the TIMA channel registers to change a pulse width value could cause
incorrect operation for up to two PWM periods. For example, writing a new value before the counter
reaches the old value but after the counter reaches the new value prevents any compare during that PWM
period. Also, using a TIMA overflow interrupt routine to write a new, smaller pulse width value may cause
the compare to be missed. The TIMA may pass the new value before it is written to the TIMA channel
registers.
Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x:
• When changing to a shorter pulse width, enable channel x output compare interrupts and write the
new value in the output compare interrupt routine. The output compare interrupt occurs at the end
of the current pulse. The interrupt routine has until the end of the PWM period to write the new
value.
• When changing to a longer pulse width, enable channel x TIMA overflow interrupts and write the
new value in the TIMA overflow interrupt routine. The TIMA overflow interrupt occurs at the end of
the current PWM period. Writing a larger value in an output compare interrupt routine (at the end
of the current pulse) could cause two output compares to occur in the same PWM period.
NOTE
In PWM signal generation, do not program the PWM channel to toggle on
output compare. Toggling on output compare prevents reliable 0 percent
duty cycle generation and removes the ability of the channel to self-correct
in the event of software error or noise. Toggling on output compare also can
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
191
Timer Interface (TIMA-4)
cause incorrect PWM signal generation when changing the PWM pulse
width to a new, much larger value.
18.3.4.2 Buffered PWM Signal Generation
Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the
PTE2/TACH0 pin. The TIMA channel registers of the linked pair alternately control the pulse width of the
output.
Setting the MS0B bit in TIMA channel 0 status and control register (TASC0) links channel 0 and
channel 1. The TIMA channel 0 registers initially control the pulse width on the PTE2/TACH0 pin. Writing
to the TIMA channel 1 registers enables the TIMA channel 1 registers to synchronously control the pulse
width at the beginning of the next PWM period. At each subsequent overflow, the TIMA channel registers
(0 or 1) that control the pulse width are the ones written to last. TASC0 controls and monitors the buffered
PWM function, and TIMA channel 1 status and control register (TASC1) is unused. While the MS0B bit is
set, the channel 1 pin, PTE3/TACH1, is available as a general-purpose I/O pin.
Channels 2 and 3 can be linked to form a buffered PWM channel whose output appears on the
PTF0/TACH2 pin. The TIMA channel registers of the linked pair alternately control the pulse width of the
output.
Setting the MS2B bit in TIMA channel 2 status and control register (TASC2) links channel 2 and channel
3. The TIMA channel 2 registers initially control the pulse width on the PTF0/TACH2 pin. Writing to the
TIMA channel 3 registers enables the TIMA channel 3 registers to synchronously control the pulse width
at the beginning of the next PWM period. At each subsequent overflow, the TIMA channel registers (2 or
3) that control the pulse width are the ones written to last. TASC2 controls and monitors the buffered PWM
function, and TIMA channel 3 status and control register (TASC3) is unused. While the MS2B bit is set,
the channel 3 pin, PTF1/TACH3, is available as a general-purpose I/O pin.
NOTE
In buffered PWM signal generation, do not write new pulse width values to
the currently active channel registers. Writing to the active channel
registers is the same as generating unbuffered PWM signals.
18.3.4.3 PWM Initialization
To ensure correct operation when generating unbuffered or buffered PWM signals, use this initialization
procedure:
1. In the TIMA status and control register (TASC):
a. Stop the TIMA counter by setting the TIMA stop bit, TSTOP.
b. Reset the TIMA counter by setting the TIMA reset bit, TRST.
2. In the TIMA counter modulo registers (TAMODH–TAMODL), write the value for the required PWM
period.
3. In the TIMA channel x registers (TACHxH–TACHxL), write the value for the required pulse width.
4. In TIMA channel x status and control register (TSCx):
a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare
or PWM signals) to the mode select bits, MSxB–MSxA. (See Table 18-2.)
b. Write 1 to the toggle-on-overflow bit, TOVx.
MC68HC908AT32 Data Sheet, Rev. 3.1
192
Freescale Semiconductor
Interrupts
c. Write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level
select bits, ELSxB–ELSxA. The output action on compare must force the output to the
complement of the pulse width level. (See Table 18-2.)
NOTE
In PWM signal generation, do not program the PWM channel to toggle on
output compare. Toggling on output compare prevents reliable 0 percent
duty cycle generation and removes the ability of the channel to self-correct
in the event of software error or noise. Toggling on output compare can also
cause incorrect PWM signal generation when changing the PWM pulse
width to a new, much larger value.
5. In the TIMA status control register (TASC), clear the TIMA stop bit, TSTOP.
Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIMA
channel 0 registers (TACH0H–TACH0L) initially control the buffered PWM output. TIMA status control
register 0 (TASC0) controls and monitors the PWM signal from the linked channels. MS0B takes priority
over MS0A.
Setting MS2B links channels 2 and 3 and configures them for buffered PWM operation. The TIMA
channel 2 registers (TACH2H–TACH2L) initially control the PWM output. TIMA status control register 2
(TASC2) controls and monitors the PWM signal from the linked channels. MS2B takes priority over MS2A.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIMA overflows. Subsequent output
compares try to force the output to a state it is already in and have no effect. The result is a 0 percent duty
cycle output.
Setting the channel x maximum duty cycle bit (CHxMAX) and clearing the TOVx bit generates a
100 percent duty cycle output. (See 18.8.4 TIMA Channel Status and Control Registers.)
18.4 Interrupts
These TIMA sources can generate interrupt requests:
• TIM overflow flag (TOF) — The timer counter value changes on the falling edge of the internal bus
clock. The timer overflow flag (TOF) bit is set on the falling edge of the internal bus clock following
the timer rollover to $0000. The TIM overflow interrupt enable bit, TOIE, enables TIM overflow
interrupt requests. TOF and TOIE are in the TIM status and control registers.
• TIMA channel flags (CH3F–CH0F) — The CHxF bit is set when an input capture or output compare
occurs on channel x. Channel x TIMA CPU interrupt requests are controlled by the channel x
interrupt enable bit, CHxIE.
18.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power standby modes.
18.5.1 Wait Mode
The TIMA remains active after the execution of a WAIT instruction. In wait mode, the TIMA registers are
not accessible by the CPU. Any enabled CPU interrupt request from the TIMA can bring the MCU out of
wait mode.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
193
Timer Interface (TIMA-4)
If TIMA functions are not required during wait mode, reduce power consumption by stopping the TIMA
before executing the WAIT instruction.
18.5.2 Stop Mode
The TIMA is inactive after the execution of a STOP instruction. The STOP instruction does not affect
register conditions or the state of the TIMA counter. TIMA operation resumes when the MCU exits stop
mode.
18.6 TIMA during Break Interrupts
A break interrupt stops the TIMA counter and inhibits input captures.
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. (See 7.7.3 SIM Break Flag Control Register.)
To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status
bit is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its
default state), software can read and write I/O registers during the break state without affecting status bits.
Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit
before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the
break, doing the second step clears the status bit.
18.7 I/O Signals
Port D shares one of its pins with the TIMA. Port E shares two of its pins with the TIMA and port F shares
two of its pins with the TIMA. PTD6/ATD14/TACLK is an external clock input to the TIMA prescaler. The
four TIMA channel I/O pins are PTE2/TACH0, PTE3/TACH1, PTF0/TACH2, and PTF1/TACH3.
18.7.1 TIMA Clock Pin (PTD6/ATD14/TCLK)
PTD6/ATD14/TACLK is an external clock input that can be the clock source for the TIMA counter instead
of the prescaled internal bus clock. Select the PTD6/ATD14/TACLK input by writing logic 1s to the three
prescaler select bits, PS[2:0]. (See 18.8.1 TIMA Status and Control Register.) The minimum TCLK pulse
width, TCLKLMIN or TCLKHMIN, is:
1
------------------------------------- + t
bus frequency SU
The maximum TCLK frequency is the least: 4 MHz or bus frequency ÷ 2.
PTD6/ATD14/TACLK is available as a general-purpose I/O pin or ADC channel when not used as the
TIMA clock input. When the PTD6/ATD14/TACLK pin is the TIMA clock input, it is an input regardless of
the state of the DDRD6 bit in data direction register D.
MC68HC908AT32 Data Sheet, Rev. 3.1
194
Freescale Semiconductor
I/O Registers
18.7.2 TIMA Channel I/O Pins (PTF1/TACH3–PTF0/TACH2 and
PTE3/TACH1–PTE2/TACH0)
Each channel I/O pin is programmable independently as an input capture pin or an output compare pin.
PTE2/TACH0 and PTF0/TACH2 can be configured as buffered output compare or buffered PWM pins.
18.8 I/O Registers
These I/O registers control and monitor TIMA operation:
• TIMA status and control register (TASC)
• TIMA control registers (TACNTH–TACNTL)
• TIMA counter modulo registers (TAMODH–TAMODL)
• TIMA channel status and control registers (TASC0, TASC1, TASC2, and TASC3)
• TIMA channel registers (TACH0H–TACH0L, TACH1H–TACH1L, TACH2H–TACH2L, and
TACH3H–TACH3L)
18.8.1 TIMA Status and Control Register
The TIMA status and control register:
• Enables TIMA overflow interrupts
• Flags TIMA overflows
• Stops the TIMA counter
• Resets the TIMA counter
• Prescales the TIMA counter clock
Address:
$0020
Bit 7
Read:
6
5
TOIE
TSTOP
TOF
Write:
0
Reset:
0
0
R
= Reserved
1
4
3
0
0
TRST
R
0
0
2
1
Bit 0
PS2
PS1
PS0
0
0
0
Figure 18-4. TIMA Status and Control Register (TASC)
TOF — TIMA Overflow Flag
This read/write flag is set when the TIMA counter resets to $0000 after reaching the modulo value
programmed in the TIMA counter modulo registers. Clear TOF by reading the TIMA status and control
register when TOF is set and then writing a logic 0 to TOF. If another TIMA overflow occurs before the
clearing sequence is complete, then writing logic 0 to TOF has no effect. Therefore, a TOF interrupt
request cannot be lost due to inadvertent clearing of TOF. Reset clears the TOF bit. Writing a logic 1
to TOF has no effect.
1 = TIMA counter has reached modulo value.
0 = TIMA counter has not reached modulo value.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
195
Timer Interface (TIMA-4)
TOIE — TIMA Overflow Interrupt Enable Bit
This read/write bit enables TIMA overflow interrupts when the TOF bit becomes set. Reset clears the
TOIE bit.
1 = TIMA overflow interrupts enabled
0 = TIMA overflow interrupts disabled
TSTOP — TIMA Stop Bit
This read/write bit stops the TIMA counter. Counting resumes when TSTOP is cleared. Reset sets the
TSTOP bit, stopping the TIMA counter until software clears the TSTOP bit.
1 = TIMA counter stopped
0 = TIMA counter active
NOTE
Do not set the TSTOP bit before entering wait mode if the TIMA is required
to exit wait mode. Also when the TSTOP bit is set and the timer is
configured for input capture operation, input captures are inhibited until the
TSTOP bit is cleared.
TRST — TIMA Reset Bit
Setting this write-only bit resets the TIMA counter and the TIMA prescaler. Setting TRST has no effect
on any other registers. Counting resumes from $0000. TRST is cleared automatically after the TIMA
counter is reset and always reads as logic 0. Reset clears the TRST bit.
1 = Prescaler and TIMA counter cleared
0 = No effect
NOTE
Setting the TSTOP and TRST bits simultaneously stops the TIMA counter
at a value of $0000.
PS[2:0] — Prescaler Select Bits
These read/write bits select either the PTD6/ATD14/TACLK pin or one of the seven prescaler outputs
as the input to the TIMA counter as Table 18-1 shows. Reset clears the PS[2:0] bits.
Table 18-1. Prescaler Selection
PS[2:0]
TIMA Clock Source
000
Internal bus clock ÷1
001
Internal bus clock ÷ 2
010
Internal bus clock ÷ 4
011
Internal bus clock ÷ 8
100
Internal bus clock ÷ 16
101
Internal bus clock ÷ 32
110
Internal bus clock ÷ 64
111
PTD6/ATD14/TACLK
MC68HC908AT32 Data Sheet, Rev. 3.1
196
Freescale Semiconductor
I/O Registers
18.8.2 TIMA Counter Registers
The two read-only TIMA counter registers contain the high and low bytes of the value in the TIMA counter.
Reading the high byte (TACNTH) latches the contents of the low byte (TACNTL) into a buffer. Subsequent
reads of TACNTH do not affect the latched TACNTL value until TACNTL is read. Reset clears the TIMA
counter registers. Setting the TIMA reset bit (TRST) also clears the TIMA counter registers.
NOTE
If TACNTH is read during a break interrupt, be sure to unlatch TACNTL by
reading TACNTL before exiting the break interrupt. Otherwise, TACNTL
retains the value latched during the break.
Register Name and Address: TACNTH — $0022
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write:
R
R
R
R
R
R
R
R
Reset:
0
0
0
0
0
0
0
0
Register Name and Address: TACNTL — $0023
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
R
R
R
R
R
R
R
R
Reset:
0
0
0
0
0
0
0
0
R
= Reserved
Figure 18-5. TIMA Counter Registers (TACNTH and TACNTL)
18.8.3 TIMA Counter Modulo Registers
The read/write TIMA modulo registers contain the modulo value for the TIMA counter. When the TIMA
counter reaches the modulo value, the overflow flag (TOF) becomes set, and the TIMA counter resumes
counting from $0000 at the next clock. Writing to the high byte (TAMODH) inhibits the TOF bit and
overflow interrupts until the low byte (TAMODL) is written. Reset sets the TIMA counter modulo
registers.
Register Name and Address: TAMODH — $0024
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
1
1
1
1
1
1
1
1
Register Name and Address: TAMODL — $0025
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
1
1
1
1
1
1
1
1
Figure 18-6. TIMA Counter Modulo Registers (TAMODH and TAMODL)
NOTE
Reset the TIMA counter before writing to the TIMA counter modulo registers.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
197
Timer Interface (TIMA-4)
18.8.4 TIMA Channel Status and Control Registers
Each of the TIMA channel status and control registers:
• Flags input captures and output compares
• Enables input capture and output compare interrupts
• Selects input capture, output compare, or PWM operation
• Selects high, low, or toggling output on output compare
• Selects rising edge, falling edge, or any edge as the active input capture trigger
• Selects output toggling on TIMA overflow
• Selects 100 percent PWM duty cycle
• Selects buffered or unbuffered output compare/PWM operation
Register Name and Address: TASC0 — $0026
Bit 7
Read:
CH0F
Write:
0
Reset:
0
6
5
4
3
2
1
Bit 0
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
0
0
0
0
0
0
0
4
3
2
1
Bit 0
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
0
0
0
0
0
Register Name and Address: TASC1 — $0029
Bit 7
Read:
CH1F
Write:
0
Reset:
0
6
5
CH1IE
0
0
R
0
Register Name and Address: TASC2 — $002C
Bit 7
Read:
CH2F
Write:
0
Reset:
0
6
5
4
3
2
1
Bit 0
CH2IE
MS2B
MS2A
ELS2B
ELS2A
TOV2
CH2MAX
0
0
0
0
0
0
0
4
3
2
1
Bit 0
MS3A
ELS3B
ELS3A
TOV3
CH3MAX
0
0
0
0
0
Register Name and Address: TASC3 — $002F
Bit 7
6
5
Read:
CH3F
Write:
0
Reset:
0
0
R
= Reserved
CH3IE
0
R
0
Figure 18-7. TIMA Channel Status
and Control Registers (TASC0–TASC3)
CHxF — Channel x Flag
When channel x is an input capture channel, this read/write bit is set when an active edge occurs on
the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the
TIMA counter registers matches the value in the TIMA channel x registers.
MC68HC908AT32 Data Sheet, Rev. 3.1
198
Freescale Semiconductor
I/O Registers
When CHxIE = 0, clear CHxF by reading TIMA channel x status and control register with CHxF set,
and then writing a logic 0 to CHxF. If another interrupt request occurs before the clearing sequence is
complete, then writing logic 0 to CHxF has no effect. Therefore, an interrupt request cannot be lost due
to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIMA CPU interrupts on channel x.
Reset clears the CHxIE bit.
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
MSxB — Mode Select Bit B
This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIMA
channel 0 and TIMA channel 2 status and control registers.
Setting MS0B disables the channel 1 status and control register and reverts TACH1 pin to
general-purpose I/O.
Setting MS2B disables the channel 3 status and control register and reverts TACH3 pin to
general-purpose I/O.
Reset clears the MSxB bit.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
MSxA — Mode Select Bit A
When ELSxB:A ≠ 00, this read/write bit selects either input capture operation or unbuffered output
compare/PWM operation.
(See Table 18-2.)
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
When ELSxB:A = 00, this read/write bit selects the initial output level of the TCHx pin once PWM, input
capture, or output compare operation is enabled. (See Table 18-2.). Reset clears the MSxA bit.
1 = Initial output level low
0 = Initial output level high
NOTE
Before changing a channel function by writing to the MSxB or MSxA bit, set
the TSTOP and TRST bits in the TIMA status and control register (TASC).
ELSxB and ELSxA — Edge/Level Select Bits
When channel x is an input capture channel, these read/write bits control the active edge-sensing logic
on channel x.
When channel x is an output compare channel, ELSxB and ELSxA control the channel x output
behavior when an output compare occurs.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
199
Timer Interface (TIMA-4)
When ELSxB and ELSxA are both clear, channel x is not connected to port E or port F, and pin
PTEx/TACHx or pin PTFx/TACHx is available as a general-purpose I/O pin. However, channel x is at
a state determined by these bits and becomes transparent to the respective pin when PWM, input
capture, or output compare mode is enabled. Table 18-2 shows how ELSxB and ELSxA work. Reset
clears the ELSxB and ELSxA bits.
Table 18-2. Mode, Edge, and Level Selection
MSxB:MSxA
ELSxB:ELSxA
X0
00
Mode
Output
preset
X1
00
00
01
00
10
00
11
01
01
01
10
01
11
1X
01
1X
10
1X
11
Configuration
Pin under port control;
Initialize timer
Output level high
Pin under port control;
Initialize timer
Output level low
Capture on rising edge only
Input
capture
Capture on falling edge only
Capture on rising or falling edge
Output
compare
or PWM
Toggle output on compare
Clear output on compare
Set output on compare
Toggle output on compare
Buffered
output compare Clear output on compare
or buffered PWM Set output on compare
NOTE
Before enabling a TIMA channel register for input capture operation, make
sure that the PTEx/TACHx pin or PTFx/TACHx pin is stable for at least two
bus clocks.
TOVx — Toggle-On-Overflow Bit
When channel x is an output compare channel, this read/write bit controls the behavior of the channel
x output when the TIMA counter overflows. When channel x is an input capture channel, TOVx has no
effect. Reset clears the TOVx bit.
1 = Channel x pin toggles on TIMA counter overflow.
0 = Channel x pin does not toggle on TIMA counter overflow.
NOTE
When TOVx is set, a TIMA counter overflow takes precedence over a
channel x output compare if both occur at the same time.
CHxMAX — Channel x Maximum Duty Cycle Bit
When the TOVx bit is at logic 0, setting the CHxMAX bit forces the duty cycle of buffered and
unbuffered PWM signals to 100%. As Figure 18-8 shows, the CHxMAX bit takes effect in the cycle after
it is set or cleared. The output stays at the 100 percent duty cycle level until the cycle after CHxMAX
is cleared.
MC68HC908AT32 Data Sheet, Rev. 3.1
200
Freescale Semiconductor
I/O Registers
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
PTEx/TCHx
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
CHxMAX
Figure 18-8. CHxMAX Latency
18.8.5 TIMA Channel Registers
These read/write registers contain the captured TIMA counter value of the input capture function or the
output compare value of the output compare function. The state of the TIMA channel registers after reset
is unknown.
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIMA channel x registers
(TACHxH) inhibits input captures until the low byte (TACHxL) is read.
In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of the TIMA channel x registers
(TACHxH) inhibits output compares until the low byte (TACHxL) is written.
Register Name and Address: TACH0H — $0027
Read:
Write:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Reset:
Indeterminate after reset
Register Name and Address: TACH0L — $0028
Read:
Write:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset:
Indeterminate after reset
Register Name and Address: TACH1H — $002A
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Indeterminate after reset
Figure 18-9. TIMA Channel Registers (TACH0H/L–TACH3H/L)
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
201
Timer Interface (TIMA-4)
Register Name and Address: TACH1L — $002B
Read:
Write:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset:
Indeterminate after reset
Register Name and Address: TACH2H — $002D
Read:
Write:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Reset:
Indeterminate after reset
Register Name and Address: TACH2L — $002E
Read:
Write:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset:
Indeterminate after reset
Register Name and Address: TACH3H — $0030
Read:
Write:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Reset:
Indeterminate after reset
Register Name and Address: TACH3L — $0031
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Indeterminate after reset
Figure 18-9. TIMA Channel Registers (TACH0H/L–TACH3H/L) (Continued)
MC68HC908AT32 Data Sheet, Rev. 3.1
202
Freescale Semiconductor
Chapter 19
Timer Interface (TIMB)
NOTE
This timer is for the MC68HC08AZ32 emulator protocol only.
19.1 Introduction
This section describes the timer interface module (TIMB). The TIMB is a 2-channel timer that provides a
timing reference with input capture, output compare, and pulse-width modulation functions. Figure 19-1
is a block diagram of the TIMB.
19.2 Features
Features of the TIMB include:
• Two input capture/output compare channels:
– Rising-edge, falling-edge, or any-edge input capture trigger
– Set, clear, or toggle output compare action
• Buffered and unbuffered pulse-width modulation (PWM) signal generation
• Programmable TIMB clock input:
– 7-frequency internal bus clock prescaler selection
– External TIMB clock input (4-MHz maximum frequency)
• Free-running or modulo up-counter operation
• Toggle any channel pin on overflow
• TIMB counter stop and reset bits
19.3 Functional Description
Figure 19-1 shows the TIMB structure. The central component of the TIMB is the 16-bit TIMB counter that
can operate as a free-running counter or a modulo up-counter. The TIMB counter provides the timing
reference for the input capture and output compare functions. The TIMB counter modulo registers,
TBMODH–TBMODL, control the modulo value of the TIMB counter. Software can read the TIMB counter
value at any time without affecting the counting sequence.
The two TIMB channels are programmable independently as input capture or output compare channels.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
203
Timer Interface (TIMB)
TCLK
PTD4/ATD12/TBCLK
PRESCALER SELECT
INTERNAL
BUS CLOCK
PRESCALER
TSTOP
PS2
TRST
PS1
PS0
16-BIT COUNTER
INTERRUPT
LOGIC
TOF
TOIE
16-BIT COMPARATOR
TMODH:TMODL
CHANNEL 0
ELS0B
ELS0A
TOV0
CH0MAX
16-BIT COMPARATOR
TCH0H:TCH0L
PTE2
LOGIC
CH0F
INTERRUPT
LOGIC
16-BIT LATCH
MS0A
CHANNEL 1
ELS1B
CH0IE
MS0B
ELS1A
TOV1
CH1MAX
16-BIT COMPARATOR
TCH1H:TCH1L
PTE3
LOGIC
CH1F
PTF5/TBCH1
INTERRUPT
LOGIC
16-BIT LATCH
CH1IE
MS1A
PTF4/TBCH0
Figure 19-1. TIMB Block Diagram
Addr.
$0040
$0041
$0042
$0043
$0044
Register Name
Bit 7
6
5
Timer B Status and Control Read:
Register (TBSCR) Write:
See page 212. Reset:
TOF
TOIE
TSTOP
0
0
Timer B Counter Register High Read:
(TBCNTH) Write:
See page 213. Reset:
Bit 15
Timer B Counter Register Low Read:
(TBCNTL) Write:
See page 213. Reset:
Timer B Modulo Register High Read:
(TBMODH) Write:
See page 214. Reset:
Timer B Modulo Register Low Read:
(TBMODL) Write:
See page 214. Reset:
4
3
2
1
Bit 0
PS2
PS1
PS0
0
0
TRST
R
1
0
0
0
0
0
14
13
12
11
10
9
Bit 8
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
Bit 7
6
5
4
3
2
1
Bit 0
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
1
1
1
1
1
1
1
1
Bit 7
6
5
4
3
2
1
Bit 0
1
1
1
1
1
1
1
1
R
= Reserved
0
Figure 19-2. TIMB I/O Register Summary
MC68HC908AT32 Data Sheet, Rev. 3.1
204
Freescale Semiconductor
Functional Description
Addr.
$0045
Register Name
Bit 7
Timer B CH0 Status and Control Read:
Register (TBSC0) Write:
See page 215. Reset:
Read:
$0046 Timer B CH0 Register High (TBCH0H)
Write:
See page 218.
Reset:
$0047
$0048
Read:
Timer B CH0 Register Low (TBCH0L)
Write:
See page 218.
Reset:
Timer B CH1 Status and Control Read:
Register (TBSC1) Write:
See page 215. Reset:
Read:
$0049 Timer B CH1 Register High (TBCH1H)
Write:
See page 218.
Reset:
$004A
Read:
Timer B CH1 Register Low (TBCH1L)
Write:
See page 218.
Reset:
6
5
4
3
2
1
Bit 0
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
CH0F
0
Indeterminate after reset
Bit 7
6
5
4
3
Indeterminate after reset
CH1F
0
CH1IE
0
R
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
Indeterminate after reset
Bit 7
6
5
4
3
Indeterminate after reset
R
= Reserved
Figure 19-2. TIMB I/O Register Summary (Continued)
19.3.1 TIMB Counter Prescaler
The TIMB clock source can be one of the seven prescaler outputs or the TIMB clock pin,
PTD4/ATD12/TBCLK. The prescaler generates seven clock rates from the internal bus clock. The
prescaler select bits, PS[2:0], in the TIMB status and control register select the TIMB clock source.
19.3.2 Input Capture
An input capture function has three basic parts: edge select logic, an input capture latch, and a 16-bit
counter. Two 8-bit registers, which make up the 16-bit input capture register, are used to latch the value
of the free-running counter after the corresponding input capture edge detector senses a defined
transition. The polarity of the active edge is programmable. The level transition which triggers the counter
transfer is defined by the corresponding input edge bits (ELSxB and ELSxA in TBSC0 through TBSC1
control registers with x referring to the active channel number). When an active edge occurs on the pin of
an input capture channel, the TIMB latches the contents of the TIMB counter into the TIMB channel
registers, TCHxH–TCHxL. Input captures can generate TIMB CPU interrupt requests. Software can
determine that an input capture event has occurred by enabling input capture interrupts or by polling the
status flag bit.
The result obtained by an input capture will be two more than the value of the free-running counter on the
rising edge of the internal bus clock preceding the external transition. This delay is required for internal
synchronization.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
205
Timer Interface (TIMB)
The free-running counter contents are transferred to the TIMB channel status and control register
(TBCHxH–TBCHxL, see 19.8.5 TIMB Channel Registers) on each proper signal transition regardless of
whether the TIMB channel flag (CH0F–CH1F in TBSC0–TBSC1 registers) is set or clear. When the status
flag is set, a CPU interrupt is generated if enabled. The value of the count latched or “captured” is the time
of the event. Because this value is stored in the input capture register two bus cycles after the actual event
occurs, user software can respond to this event at a later time and determine the actual time of the event.
However, this must be done prior to another input capture on the same pin; otherwise, the previous time
value will be lost.
By recording the times for successive edges on an incoming signal, software can determine the period
and/or pulse width of the signal. To measure a period, two successive edges of the same polarity are
captured. To measure a pulse width, two alternate polarity edges are captured. Software should track the
overflows at the 16-bit module counter to extend its range.
Another use for the input capture function is to establish a time reference. In this case, an input capture
function is used in conjunction with an output compare function. For example, to activate an output signal
a specified number of clock cycles after detecting an input event (edge), use the input capture function to
record the time at which the edge occurred. A number corresponding to the desired delay is added to this
captured value and stored to an output compare register (see 19.8.5 TIMB Channel Registers). Because
both input captures and output compares are referenced to the same 16-bit modulo counter, the delay
can be controlled to the resolution of the counter independent of software latencies.
Reset does not affect the contents of the input capture channel register (TBCHxH–TBCHxL).
19.3.3 Output Compare
With the output compare function, the TIMB can generate a periodic pulse with a programmable polarity,
duration, and frequency. When the counter reaches the value in the registers of an output compare
channel, the TIMB can set, clear, or toggle the channel pin. Output compares can generate TIMB CPU
interrupt requests.
19.3.3.1 Unbuffered Output Compare
Any output compare channel can generate unbuffered output compare pulses as described in 19.3.3
Output Compare. The pulses are unbuffered because changing the output compare value requires writing
the new value over the old value currently in the TIMB channel registers.
An unsynchronized write to the TIMB channel registers to change an output compare value could cause
incorrect operation for up to two counter overflow periods. For example, writing a new value before the
counter reaches the old value but after the counter reaches the new value prevents any compare during
that counter overflow period. Also, using a TIMB overflow interrupt routine to write a new, smaller output
compare value may cause the compare to be missed. The TIMB may pass the new value before it is
written.
Use these methods to synchronize unbuffered changes in the output compare value on channel x:
• When changing to a smaller value, enable channel x output compare interrupts and write the new
value in the output compare interrupt routine. The output compare interrupt occurs at the end of
the current output compare pulse. The interrupt routine has until the end of the counter overflow
period to write the new value.
MC68HC908AT32 Data Sheet, Rev. 3.1
206
Freescale Semiconductor
Functional Description
•
When changing to a larger output compare value, enable channel x TIMB overflow interrupts and
write the new value in the TIMB overflow interrupt routine. The TIMB overflow interrupt occurs at
the end of the current counter overflow period. Writing a larger value in an output compare interrupt
routine (at the end of the current pulse) could cause two output compares to occur in the same
counter overflow period.
19.3.3.2 Buffered Output Compare
Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the
PTF5/TBCH1 pin. The TIMB channel registers of the linked pair alternately control the output.
Setting the MS0B bit in TIMB channel 0 status and control register (TBSC0) links channel 0 and channel
1. The output compare value in the TIMB channel 0 registers initially controls the output on the
PTE2/TACH0 pin. Writing to the TIMB channel 1 registers enables the TIMB channel 1 registers to
synchronously control the output after the TIMB overflows. At each subsequent overflow, the TIMB
channel registers (0 or 1) that control the output are the ones written to last. TSC0 controls and monitors
the buffered output compare function, and TIMB channel 1 status and control register (TBSC1) is unused.
While the MS0B bit is set, the channel 1 pin, PTF4/TBCH0, is available as a general-purpose I/O pin.
NOTE
Channels 2 and 3 and channels 4 and 5 can be linked to operate as
specified previously.
In buffered output compare operation, do not write new output compare
values to the currently active channel registers. Writing to the active
channel registers is the same as generating unbuffered output compares.
19.3.4 Pulse-Width Modulation (PWM)
By using the toggle-on-overflow feature with an output compare channel, the TIMB can generate a PWM
signal. The value in the TIMB counter modulo registers determines the period of the PWM signal. The
channel pin toggles when the counter reaches the value in the TIMB counter modulo registers. The time
between overflows is the period of the PWM signal.
As Figure 19-3 shows, the output compare value in the TIMB channel registers determines the pulse width
of the PWM signal. The time between overflow and output compare is the pulse width. Program the TIMB
to clear the channel pin on output compare if the state of the PWM pulse is logic 1. Program the TIMB to
set the pin if the state of the PWM pulse is logic 0.
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
PULSE
WIDTH
PTBx/TCHx
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 19-3. PWM Period and Pulse Width
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
207
Timer Interface (TIMB)
The value in the TIMB counter modulo registers and the selected prescaler output determines the
frequency of the PWM output. The frequency of an 8-bit PWM signal is variable in 256 increments. Writing
$00FF (255) to the TIMB counter modulo registers produces a PWM period of 256 times the internal bus
clock period if the prescaler select value is $000 (see 19.8.1 TIMB Status and Control Register).
The value in the TIMB channel registers determines the pulse width of the PWM output. The pulse width
of an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIMB channel registers
produces a duty cycle of 128/256 or 50 percent.
19.3.4.1 Unbuffered PWM Signal Generation
Any output compare channel can generate unbuffered PWM pulses as described in 19.3.4 Pulse-Width
Modulation (PWM). The pulses are unbuffered because changing the pulse width requires writing the new
pulse width value over the value currently in the TIMB channel registers.
An unsynchronized write to the TIMB channel registers to change a pulse width value could cause
incorrect operation for up to two PWM periods. For example, writing a new value before the counter
reaches the old value but after the counter reaches the new value prevents any compare during that PWM
period. Also, using a TIMB overflow interrupt routine to write a new, smaller pulse width value may cause
the compare to be missed. The TIMB may pass the new value before it is written to the TIMB channel
registers.
Use these methods to synchronize unbuffered changes in the PWM pulse width on channel x:
• When changing to a shorter pulse width, enable channel x output compare interrupts and write the
new value in the output compare interrupt routine. The output compare interrupt occurs at the end
of the current pulse. The interrupt routine has until the end of the PWM period to write the new
value.
• When changing to a longer pulse width, enable channel x TIMB overflow interrupts and write the
new value in the TIMB overflow interrupt routine. The TIMB overflow interrupt occurs at the end of
the current PWM period. Writing a larger value in an output compare interrupt routine (at the end
of the current pulse) could cause two output compares to occur in the same PWM period.
NOTE
In PWM signal generation, do not program the PWM channel to toggle on
output compare. Toggling on output compare prevents reliable 0 percent
duty cycle generation and removes the ability of the channel to self-correct
in the event of software error or noise. Toggling on output compare also can
cause incorrect PWM signal generation when changing the PWM pulse
width to a new, much larger value.
19.3.4.2 Buffered PWM Signal Generation
Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the
PTF4/TBCH0 pin. The TIMB channel registers of the linked pair alternately control the pulse width of the
output.
Setting the MS0B bit in TIMB channel 0 status and control register (TBSC0) links channel 0 and
channel 1. The TIMB channel 0 registers initially control the pulse width on the PTF4/TBCH0 pin. Writing
to the TIMB channel 1 registers enables the TIMB channel 1 registers to synchronously control the pulse
width at the beginning of the next PWM period. At each subsequent overflow, the TIMB channel registers
(0 or 1) that control the pulse width are the ones written to last. TBSC0 controls and monitors the buffered
MC68HC908AT32 Data Sheet, Rev. 3.1
208
Freescale Semiconductor
Functional Description
PWM function, and TIMB channel 1 status and control register (TBSC1) is unused. While the MS0B bit is
set, the channel 1 pin, PTF5/TBCH1, is available as a general-purpose I/O pin.
NOTE
In buffered PWM signal generation, do not write new pulse width values to
the currently active channel registers. Writing to the active channel
registers is the same as generating unbuffered PWM signals.
19.3.4.3 PWM Initialization
To ensure correct operation when generating unbuffered or buffered PWM signals, use this initialization
procedure:
1. In the TIMB status and control register (TBSC):
a. Stop the TIMB counter by setting the TIMB stop bit, TSTOP.
b. Reset the TIMB counter by setting the TIMB reset bit, TRST.
2. In the TIMB counter modulo registers (TBMODH–TBMODL), write the value for the required PWM
period.
3. In the TIMB channel x registers (TBCHxH–TBCHxL), write the value for the required pulse width.
4. In TIMB channel x status and control register (TBSCx):
a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare
or PWM signals) to the mode select bits, MSxB–MSxA. (See Table 19-2.)
b. Write 1 to the toggle-on-overflow bit, TOVx.
c. Write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level
select bits, ELSxB–ELSxA. The output action on compare must force the output to the
complement of the pulse width level. (See Table 19-2.)
NOTE
In PWM signal generation, do not program the PWM channel to toggle on
output compare. Toggling on output compare prevents reliable 0 percent
duty cycle generation and removes the ability of the channel to self-correct
in the event of software error or noise. Toggling on output compare can also
cause incorrect PWM signal generation when changing the PWM pulse
width to a new, much larger value.
5. In the TIMB status control register (TBSC), clear the TIMB stop bit, TSTOP.
Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIMB channel
0 registers (TBCH0H–TBCH0L) initially control the buffered PWM output. TIMB status control register 0
(TBSC0) controls and monitors the PWM signal from the linked channels. MS0B takes priority over MS0A.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIMB overflows. Subsequent output
compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle
output.
Setting the channel x maximum duty cycle bit (CHxMAX) and clearing the TOVx bit generates a 100
percent duty cycle output. See 19.8.4 TIMB Channel Status and Control Registers.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
209
Timer Interface (TIMB)
19.4 Interrupts
These TIMB sources can generate interrupt requests:
• TIMB timer overflow flag (TOF) — The timer counter value changes on the falling edge of the
internal bus clock. The timer overflow flag (TOF) bit is set on the falling edge of the internal bus
clock following the timer rollover to $0000. The TIM overflow interrupt enable bit, TOIE, enables
TIM overflow interrupt requests. TOF and TOIE are in the TIM status and control registers.
• TIMB channel flags (CH1F–CH0F) — The CHxF bit is set when an input capture or output compare
occurs on channel x. Channel x TIMB CPU interrupt requests are controlled by the channel x
interrupt enable bit, CHxIE.
19.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power standby modes.
19.5.1 Wait Mode
The TIMB remains active after the execution of a WAIT instruction. In wait mode, the TIMB registers are
not accessible by the CPU. Any enabled CPU interrupt request from the TIMB can bring the MCU out of
wait mode.
If TIMB functions are not required during wait mode, reduce power consumption by stopping the TIMB
before executing the WAIT instruction.
19.5.2 Stop Mode
The TIMB is inactive after the execution of a STOP instruction. The STOP instruction does not affect
register conditions or the state of the TIMB counter. TIMB operation resumes when the MCU exits stop
mode.
19.6 TIMB during Break Interrupts
A break interrupt stops the TIMB counter and inhibits input captures.
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. See 7.7.3 SIM Break Flag Control Register.
To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status
bit is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its
default state), software can read and write I/O registers during the break state without affecting status bits.
Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit
before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the
break, doing the second step clears the status bit.
MC68HC908AT32 Data Sheet, Rev. 3.1
210
Freescale Semiconductor
I/O Signals
19.7 I/O Signals
Port D shares one of its pins with the TIMB. Port F shares two of its pins with the TIMB.
PTD4/ATD12/TBCLK is an external clock input to the TIMB prescaler. The two TIMB channel I/O pins are
PTF4/TBCH0 and PTF5/TBCH1.
19.7.1 TIMB Clock Pin (PTD4/ATD12/TBCLK)
PTD4/ATD12/TBCLK is an external clock input that can be the clock source for the TIMB counter instead
of the prescaled internal bus clock. Select the PTD4/ATD12/TBCLK input by writing logic 1s to the three
prescaler select bits, PS[2:0]. (See 19.8.1 TIMB Status and Control Register.) The minimum TCLK pulse
width, TCLKLMIN or TCLKHMIN, is:
1
------------------------------------- + t
bus frequency SU
The maximum TCLK frequency is the least: 4 MHz or bus frequency ÷ 2.
PTD4/ATD12/TBCLK is available as a general-purpose I/O pin or ADC channel when not used as the
TIMB clock input. When the PTD6/ATD14/TACLK pin is the TIMB clock input, it is an input regardless of
the state of the DDRD6 bit in data direction register D.
19.7.2 TIMB Channel I/O Pins (PTF5/TBCH1–PTF4/TBCH0)
Each channel I/O pin is programmable independently as an input capture pin or an output compare pin.
PTF4/TBCH0 and PTF5/TBCH1 can be configured as buffered output compare or buffered PWM pins.
19.8 I/O Registers
These I/O registers control and monitor TIMB operation:
• TIMB status and control register (TBSC)
• TIMB control registers (TBCNTH–TBCNTL)
• TIMB counter modulo registers (TBMODH–TBMODL)
• TIMB channel status and control registers (TBSC0 and TBSC1)
• TIMB channel registers (TBCH0H–TBCH0L and TBCH1H–TBCH1L)
19.8.1 TIMB Status and Control Register
The TIMB status and control register:
• Enables TIMB overflow interrupts
• Flags TIMB overflows
• Stops the TIMB counter
• Resets the TIMB counter
• Prescales the TIMB counter clock
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
211
Timer Interface (TIMB)
Address:
$0040
Bit 7
6
5
TOIE
TSTOP
1
Read:
TOF
Write:
0
Reset:
0
0
R
= Reserved
4
3
0
0
TRST
R
0
0
2
1
Bit 0
PS2
PS1
PS0
0
0
0
Figure 19-4. TIMB Status and Control Register (TBSC)
TOF — TIMB Overflow Flag
This read/write flag is set when the TIMB counter resets to $0000 after reaching the modulo value
programmed in the TIMB counter modulo registers. Clear TOF by reading the TIMB status and control
register when TOF is set and then writing a logic 0 to TOF. If another TIMB overflow occurs before the
clearing sequence is complete, then writing logic 0 to TOF has no effect. Therefore, a TOF interrupt
request cannot be lost due to inadvertent clearing of TOF. Reset clears the TOF bit. Writing a logic 1
to TOF has no effect.
1 = TIMB counter has reached modulo value.
0 = TIMB counter has not reached modulo value.
TOIE — TIMB Overflow Interrupt Enable Bit
This read/write bit enables TIMB overflow interrupts when the TOF bit becomes set. Reset clears the
TOIE bit.
1 = TIMB overflow interrupts enabled
0 = TIMB overflow interrupts disabled
TSTOP — TIMB Stop Bit
This read/write bit stops the TIMB counter. Counting resumes when TSTOP is cleared. Reset sets the
TSTOP bit, stopping the TIMB counter until software clears the TSTOP bit.
1 = TIMB counter stopped
0 = TIMB counter active
NOTE
Do not set the TSTOP bit before entering wait mode if the TIMB is required
to exit wait mode. Also, when the TSTOP bit is set and the timer is
configured for input capture operation, input captures are inhibited until
TSTOP is cleared.
TRST — TIMB Reset Bit
Setting this write-only bit resets the TIMB counter and the TIMB prescaler. Setting TRST has no effect
on any other registers. Counting resumes from $0000. TRST is cleared automatically after the TIMB
counter is reset and always reads as logic 0. Reset clears the TRST bit.
1 = Prescaler and TIMB counter cleared
0 = No effect
NOTE
Setting the TSTOP and TRST bits simultaneously stops the TIMB counter
at a value of $0000.
MC68HC908AT32 Data Sheet, Rev. 3.1
212
Freescale Semiconductor
I/O Registers
PS[2:0] — Prescaler Select Bits
These read/write bits select either the PTD4/ATD12/TBCLK pin or one of the seven prescaler outputs
as the input to the TIMB counter as Table 19-1 shows. Reset clears the PS[2:0] bits.
Table 19-1. Prescaler Selection
PS[2:0]
TIMB Clock Source
000
Internal bus clock ÷1
001
Internal bus clock ÷ 2
010
Internal bus clock ÷ 4
011
Internal bus clock ÷ 8
100
Internal bus clock ÷ 16
101
Internal bus clock ÷ 32
110
Internal bus clock ÷ 64
111
PTD6/ATD14/TACLK
19.8.2 TIMB Counter Registers
The two read-only TIMB counter registers contain the high and low bytes of the value in the TIMB counter.
Reading the high byte (TBCNTH) latches the contents of the low byte (TBCNTL) into a buffer. Subsequent
reads of TBCNTH do not affect the latched TBCNTL value until TBCNTL is read. Reset clears the TIMB
counter registers. Setting the TIMB reset bit (TRST) also clears the TIMB counter registers.
NOTE
If TBCNTH is read during a break interrupt, be sure to unlatch TBCNTL by
reading TBCNTL before exiting the break interrupt. Otherwise, TBCNTL
retains the value latched during the break.
Register Name and Address: TBCNTH — $0041
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write:
R
R
R
R
R
R
R
R
Reset:
0
0
0
0
0
0
0
0
Register Name and Address: TBCNTL — $0042
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
R
= Reserved
Reset:
Figure 19-5. TIMB Counter Registers (TBCNTH and TBCNTL)
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
213
Timer Interface (TIMB)
19.8.3 TIMB Counter Modulo Registers
The read/write TIMB modulo registers contain the modulo value for the TIMB counter. When the TIMB
counter reaches the modulo value, the overflow flag (TOF) becomes set, and the TIMB counter resumes
counting from $0000 at the next clock. Writing to the high byte (TMODH) inhibits the TOF bit and overflow
interrupts until the low byte (TMODL) is written. Reset sets the TIMB counter modulo registers.
Register Name and Address: TBMODH — $0043
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
1
1
1
1
1
1
1
1
Register Name and Address: TBMODL — $0044
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
Figure 19-6. TIMB Counter Modulo Registers (TMODH and TMODL)
NOTE
Reset the TIMB counter before writing to the TIMB counter modulo registers.
19.8.4 TIMB Channel Status and Control Registers
Each of the TIMB channel status and control registers:
• Flags input captures and output compares
• Enables input capture and output compare interrupts
• Selects input capture, output compare, or PWM operation
• Selects high, low, or toggling output on output compare
• Selects rising edge, falling edge, or any edge as the active input capture trigger
• Selects output toggling on TIMB overflow
• Selects 100 percent PWM duty cycle
• Selects buffered or unbuffered output compare/PWM operation
MC68HC908AT32 Data Sheet, Rev. 3.1
214
Freescale Semiconductor
I/O Registers
Register Name and Address: TBSC0 — $0045
Bit 7
Read:
CH0F
Write:
0
Reset:
0
6
5
4
3
2
1
Bit 0
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
0
0
0
0
0
0
0
4
3
2
1
Bit 0
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
0
0
0
0
0
Register Name and Address: TBSC1 — $0048
Bit 7
6
5
Read:
CH1F
Write:
0
Reset:
0
0
R
= Reserved
CH1IE
0
R
0
Figure 19-7. TIMB Channel Status and Control Registers (TBSC0–TBSC1)
CHxF — Channel x Flag
When channel x is an input capture channel, this read/write bit is set when an active edge occurs on
the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the
TIMB counter registers matches the value in the TIMB channel x registers.
When CHxIE = 0, clear CHxF by reading TIMB channel x status and control register with CHxF set,
and then writing a logic 0 to CHxF. If another interrupt request occurs before the clearing sequence is
complete, then writing logic 0 to CHxF has no effect. Therefore, an interrupt request cannot be lost due
to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIMB CPU interrupts on channel x.
Reset clears the CHxIE bit.
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
MSxB — Mode Select Bit B
This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIMB
channel 0.
Setting MS0B disables the channel 1 status and control register and reverts TBCH1 to
general-purpose I/O.
Reset clears the MSxB bit.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
215
Timer Interface (TIMB)
MSxA — Mode Select Bit A
When ELSxB:A ≠ 00, this read/write bit selects either input capture operation or unbuffered output
compare/PWM operation. (See Table 19-2.)
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
When ELSxB:A = 00, this read/write bit selects the initial output level of the TCHx pin once PWM, input
capture, or output compare operation is enabled. (See Table 19-2.). Reset clears the MSxA bit.
1 = Initial output level low
0 = Initial output level high
NOTE
Before changing a channel function by writing to the MSxB or MSxA bit, set
the TSTOP and TRST bits in the TIMB status and control register (TBSC).
ELSxB and ELSxA — Edge/Level Select Bits
When channel x is an input capture channel, these read/write bits control the active edge-sensing logic
on channel x.
When channel x is an output compare channel, ELSxB and ELSxA control the channel x output
behavior when an output compare occurs.
When ELSxB and ELSxA are both clear, channel x is not connected to port E or port F, and pin
PTEx/TBCHx or pin PTFx/TBCHx is available as a general-purpose I/O pin. However, channel x is at
a state determined by these bits and becomes transparent to the respective pin when PWM, input
capture, or output compare mode is enabled. Table 19-2 shows how ELSxB and ELSxA work. Reset
clears the ELSxB and ELSxA bits.
NOTE
Before enabling a TIMB channel register for input capture operation, make
sure that the PTEx/TBCHx pin or PTFx/TBCHx pin is stable for at least two
bus clocks.
Table 19-2. Mode, Edge, and Level Selection
MSxB:MSxA
ELSxB:ELSxA
X0
00
Mode
Output
preset
X1
00
00
01
00
10
00
11
01
01
01
10
01
11
1X
01
1X
10
1X
11
Configuration
Pin under port control;
Initialize timer
Output level high
Pin under port control;
Initialize timer
Output level low
Capture on rising edge only
Input
capture
Capture on falling edge only
Capture on rising or falling edge
Output
compare
or PWM
Toggle output on compare
Clear output on compare
Set output on compare
Toggle output on compare
Buffered
output compare Clear output on compare
or buffered PWM Set output on compare
MC68HC908AT32 Data Sheet, Rev. 3.1
216
Freescale Semiconductor
I/O Registers
TOVx — Toggle-On-Overflow Bit
When channel x is an output compare channel, this read/write bit controls the behavior of the channel
x output when the TIMB counter overflows. When channel x is an input capture channel, TOVx has no
effect. Reset clears the TOVx bit.
1 = Channel x pin toggles on TIMB counter overflow.
0 = Channel x pin does not toggle on TIMB counter overflow.
NOTE
When TOVx is set, a TIMB counter overflow takes precedence over a
channel x output compare if both occur at the same time.
CHxMAX — Channel x Maximum Duty Cycle Bit
When the TOVx bit is at logic 0, setting the CHxMAX bit forces the duty cycle of buffered and
unbuffered PWM signals to 100 percent. As Figure 19-8 shows, the CHxMAX bit takes effect in the
cycle after it is set or cleared. The output stays at the 100 percent duty cycle level until the cycle after
CHxMAX is cleared.
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
PTEx/TCHx
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
CHxMAX
Figure 19-8. CHxMAX Latency
19.8.5 TIMB Channel Registers
These read/write registers contain the captured TIMB counter value of the input capture function or the
output compare value of the output compare function. The state of the TIMB channel registers after reset
is unknown.
In input capture mode (MSxB–MSxA = 0:0), reading the high byte of the TIMB channel x registers
(TBCHxH) inhibits input captures until the low byte (TBCHxL) is read.
In output compare mode (MSxB–MSxA ≠ 0:0), writing to the high byte of the TIMB channel x registers
(TBCHxH) inhibits output compares until the low byte (TBCHxL) is written.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
217
Timer Interface (TIMB)
Register Name and Address: TBCH0H — $0046
Read:
Write:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Reset:
Indeterminate after reset
Register Name and Address: TBCH0L — $0047
Read:
Write:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset:
Indeterminate after reset
Register Name and Address: TBCH1H — $0049
Read:
Write:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Reset:
Indeterminate after reset
Register Name and Address: TBCH1L — $004A
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Indeterminate after reset
Figure 19-9. TIMB Channel Registers
(TBCH0H/L–TBCH1H/L)
MC68HC908AT32 Data Sheet, Rev. 3.1
218
Freescale Semiconductor
Chapter 20
Modulo Timer (TIM)
20.1 Introduction
This section describes the modulo timer which is a periodic interrupt timer whose counter is clocked
internally via software programmable options. Figure 20-1 is a block diagram of the TIM.
20.2 Features
Features of the TIM include:
• Programmable TIM clock input
• Free-running or modulo up-counter operation
• TIM counter stop and reset bits
20.3 Functional Description
Figure 20-1 shows the structure of the TIM. The central component of the TIM is the 16-bit TIM counter
that can operate as a free-running counter or a modulo up-counter. The counter provides the timing
reference for the interrupt. The TIM counter modulo registers, TMODH–TMODL, control the modulo value
of the counter. Software can read the counter value at any time without affecting the counting sequence.
PRESCALER SELECT
INTERNAL
BUS CLOCK
PRESCALER
CSTOP
PS2
CRST
PS1
PS0
16-BIT COUNTER
TOF
TOIE
INTERRUPT
LOGIC
16-BIT COMPARATOR
PITTMODH:PITTMODL
Figure 20-1. TIM Block Diagram
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
219
Modulo Timer (TIM)
Address
$004B
$004C
$004D
Register Name
Bit 7
TIM Status and Control Read:
Register (TSC) Write:
See page 222. Reset:
TOF
6
5
4
3
0
0
2
1
Bit 0
PS2
PS1
PS0
TOIE
TSTOP
0
0
1
0
0
0
0
0
TIM Counter Register Read:
High (TCNTH) Write:
See page 223. Reset:
Bit 15
14
13
12
11
10
9
Bit 8
0
0
0
0
0
0
0
0
TIM Counter Register Read:
Low (TCNTL) Write:
See page 223. Reset:
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
1
1
1
1
1
1
1
1
Bit 7
6
5
4
3
2
1
Bit 0
1
1
1
1
1
1
1
1
$004E
TIM Counter Modulo Read:
Register High (TMODH) Write:
See page 224. Reset:
$004F
TIM Counter Modulo Read:
Register Low (TMODL) Write:
See page 224. Reset:
0
TRST
= Unimplemented
Figure 20-2. TIM I/O Register Summary
20.4 TIM Counter Prescaler
The clock source can be one of the seven prescaler outputs. The prescaler generates seven clock rates
from the internal bus clock. The prescaler select bits, PS[2:0], in the status and control register select the
TIM clock source.
The value in the TIM counter modulo registers and the selected prescaler output determines the
frequency of the periodic interrupt. The TIM overflow flag (TOF) is set when the TIM counter value rolls
over to $0000 after matching the value in the TIM counter modulo registers. The TIM interrupt enable bit,
TOIE, enables TIM overflow CPU interrupt requests. TOF and TOIE are in the TIM status and control
register.
20.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power standby modes.
20.5.1 Wait Mode
The TIM remains active after the execution of a WAIT instruction. In wait mode the TIM registers are not
accessible by the CPU. Any enabled CPU interrupt request from the TIM can bring the MCU out of wait
mode.
If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before
executing the WAIT instruction.
MC68HC908AT32 Data Sheet, Rev. 3.1
220
Freescale Semiconductor
TIM during Break Interrupts
20.5.2 Stop Mode
The TIM is inactive after the execution of a STOP instruction. The STOP instruction does not affect
register conditions or the state of the TIM counter. TIM operation resumes when the MCU exits stop mode
after an external interrupt.
20.6 TIM during Break Interrupts
A break interrupt stops the TIM counter.
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. See 7.7.3 SIM Break Flag Control Register.
To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status
bit is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its
default state), software can read and write I/O registers during the break state without affecting status bits.
Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit
before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the
break, doing the second step clears the status bit.
20.7 I/O Registers
These I/O registers control and monitor operation of the TIM:
• TIM status and control register (TSC)
• TIM counter registers (TCNTH–TCNTL)
• TIM counter modulo registers (TMODH–TMODL)
20.7.1 TIM Status and Control Register
The TIM status and control register:
• Enables TIM interrupt
• Flags TIM overflows
• Stops the TIM counter
• Resets the TIM counter
• Prescales the TIM counter clock
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
221
Modulo Timer (TIM)
Address:
$004B
Bit 7
Read:
TOF
Write:
0
Reset:
0
6
5
TOIE
TSTOP
0
1
4
3
0
0
TRST
0
2
1
Bit 0
PS2
PS1
PS0
0
0
0
0
= Unimplemented
Figure 20-3. TIM Status and Control Register (TSC)
TOF — TIM Overflow Flag
This read/write flag is set when the TIM counter resets to $0000 after reaching the modulo value
programmed in the TIM counter modulo registers. Clear TOF by reading the TIM status and control
register when TOF is set and then writing a logic 0 to TOF. If another TIM overflow occurs before the
clearing sequence is complete, then writing logic 0 to TOF has no effect. Therefore, a TOF interrupt
request cannot be lost due to inadvertent clearing of TOF. Reset clears the TOF bit. Writing a logic 1
to TOF has no effect.
1 = TIM counter has reached modulo value.
0 = TIM counter has not reached modulo value.
TOIE — TIM Overflow Interrupt Enable Bit
This read/write bit enables TIM overflow interrupts when the TOF bit becomes set. Reset clears the
TOIE bit.
1 = TIM overflow interrupts enabled
0 = TIM overflow interrupts disabled
TSTOP — TIM Stop Bit
This read/write bit stops the TIM counter. Counting resumes when TSTOP is cleared. Reset sets the
TSTOP bit, stopping the TIM counter until software clears the TSTOP bit.
1 = TIM counter stopped
0 = TIM counter active
NOTE
Do not set the TSTOP bit before entering wait mode if the TIM is required
to exit wait mode.
TRST — TIM Reset Bit
Setting this write-only bit resets the TIM counter and the TIM prescaler. Setting TRST has no effect on
any other registers. Counting resumes from $0000. TRST is cleared automatically after the TIM
counter is reset and always reads as logic 0. Reset clears the TRST bit.
1 = Prescaler and TIM counter cleared
0 = No effect
NOTE
Setting the TSTOP and TRST bits simultaneously stops the TIM counter at
a value of $0000.
PS[2:0] — Prescaler Select Bits
These read/write bits select one of the seven prescaler outputs as the input to the TIM counter as Table
20-1 shows. Reset clears the PS[2:0] bits.
MC68HC908AT32 Data Sheet, Rev. 3.1
222
Freescale Semiconductor
I/O Registers
Table 20-1. Prescaler Selection
PS[2:0]
TIM Clock Source
000
Internal bus clock ÷1
001
Internal bus clock ÷ 2
010
Internal bus clock ÷ 4
011
Internal bus clock ÷ 8
100
Internal bus clock ÷ 16
101
Internal bus clock ÷ 32
110
Internal bus clock ÷ 64
111
Internal bus clock ÷ 64
20.7.2 TIM Counter Registers
The two read-only TIM counter registers contain the high and low bytes of the value in the TIM counter.
Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent
reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset clears the TIM counter
registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers.
NOTE
If you read TCNTH during a break interrupt, be sure to unlatch TCNTL by
reading TCNTL before exiting the break interrupt. Otherwise, TCNTL
retains the value latched during the break.
Address: $004C
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
0
0
0
0
0
0
0
0
Write:
Reset:
Address: $004D
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
Write:
Reset:
= Unimplemented
Figure 20-4. TIM Counter Registers (TCNTH–TCNTL)
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
223
Modulo Timer (TIM)
20.7.3 TIM Counter Modulo Registers
The read/write TIM modulo registers contain the modulo value for the TIM counter. When the TIM counter
reaches the modulo value, the overflow flag (TOF) becomes set, and the TIM counter resumes counting
from $0000 at the next clock. Writing to the high byte (TMODH) inhibits the TOF bit and overflow interrupts
until the low byte (TMODL) is written. Reset sets the TIM counter modulo registers.
Register and Address: TMODH — $004E
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
1
1
1
1
1
1
1
1
Register and Address: TMODL — $004F
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
1
1
1
1
1
1
1
1
Figure 20-5. TIM Counter Modulo Registers (TMODH–TMODL)
NOTE
Reset the TIM counter before writing to the TIM counter modulo registers.
MC68HC908AT32 Data Sheet, Rev. 3.1
224
Freescale Semiconductor
Chapter 21
Analog-to-Digital Converter (ADC-8)
NOTE
This analog-to-digital converter is for the CAN (64-pin QFP) protocol only.
21.1 Introduction
This section describes the analog-to-digital converter (ADC-8). The ADC is an 8-bit analog-to-digital
converter.
21.2 Features
Features of the ADC module include:
• Eight channels with multiplexed input
• Linear successive approximation
• 8-bit resolution
• Single or continuous conversion
• Conversion complete flag or conversion complete interrupt
• Selectable ADC clock
21.3 Functional Description
Eight ADC channels are available for sampling external sources at pins PTB7/ATD7–PTB0/ATD0. An
analog multiplexer allows the single ADC converter to select one of eight ADC channels as ADC voltage
in (ADCVIN). ADCVIN is converted by the successive approximation register-based counters. When the
conversion is completed, the ADC places the result in the ADC data register and sets a flag or generates
an interrupt. See Figure 21-1.
21.3.1 ADC Port I/O Pins
PTB7/ATD7–PTB0/ATD0 are general-purpose I/O pins that are shared with the ADC channels.
The channel select bits define which ADC channel/port pin will be used as the input signal. The ADC
overrides the port I/O logic by forcing that pin as input to the ADC. The remaining ADC channels/port pins
are controlled by the port I/O logic and can be used as general-purpose I/O. Writes to the port register or
DDR will not have any affect on the port pin that is selected by the ADC. Read of a port pin which is in
use by the ADC will return a logic 0 if the corresponding DDR bit is at logic 0. If the DDR bit is at logic 1,
the value in the port data latch is read.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
225
Analog-to-Digital Converter (ADC-8)
INTERNAL
DATA BUS
READ DDRB/DDRB
WRITE DDRB/DDRD
DISABLE
DDRBx
RESET
WRITE PTB/PTD
PTBx
PTBx
ADC CHANNEL x
READ PTB/PTD
DISABLE
ADC DATA REGISTER
INTERRUPT
LOGIC
AIEN
CONVERSION
COMPLETE
ADC VOLTAGE IN
ADCVIN
ADC
CHANNEL
SELECT
ADCH[4:0]
COCO
ADC CLOCK
CGMXCLK
BUS CLOCK
CLOCK
GENERATOR
ADIV[2:0]
ADICLK
Figure 21-1. ADC Block Diagram
21.3.2 Voltage Conversion
When the input voltage to the ADC equals VREFH (see 29.6 ADC Characteristics), the ADC converts the
signal to $FF (full scale). If the input voltage equals VSSA, the ADC converts it to $00. Input voltages
between VREFH and VSSA are a straight-line linear conversion. All other input voltages will result in $FF if
greater than VREFH and $00 if less than VSSA.
NOTE
Input voltage should not exceed the analog supply voltages.
21.3.3 Conversion Time
Conversion starts after a write to the ADSCR (ADC status control register, $0038) and requires between
16 and 17 ADC clock cycles to complete. Conversion time in terms of the number of bus cycles is a
function of ADICLK select, CGMXCLK frequency, bus frequency, and ADIV prescaler bits. For example,
with a CGMXCLK frequency of 4 MHz, bus frequency of 8 MHz, and fixed ADC clock frequency of 1 MHz,
MC68HC908AT32 Data Sheet, Rev. 3.1
226
Freescale Semiconductor
Interrupts
one conversion will take between 16 and 17 µs and there will be between 128 and 136 bus cycles
between each conversion. Sample rate is approximately 60 kHz.
Refer to 29.6 ADC Characteristics.
16 to 17 ADC Clock Cycles
Conversion Time = ⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
ADC Clock Frequency
Number of Bus Cycles = Conversion Time x Bus Frequency
21.3.4 Continuous Conversion
In the continuous conversion mode, the ADC data register will be filled with new data after each
conversion. Data from the previous conversion will be overwritten whether that data has been read or not.
Conversions will continue until the ADCO bit (ADC status control register, $0038) is cleared. The COCO
bit is set after the first conversion and will stay set for the next several conversions until the next write of
the ADC status and control register or the next read of the ADC data register.
21.3.5 Accuracy and Precision
The conversion process is monotonic and has no missing codes. See 29.6 ADC Characteristics for
accuracy information.
21.4 Interrupts
When the AIEN bit is set, the ADC module is capable of generating a CPU interrupt after each ADC
conversion. A CPU interrupt is generated if the COCO bit (ADC status control register, $0038) is at logic
0. If the COCO bit is set, an interrupt is generated. The COCO bit is not used as a conversion complete
flag when interrupts are enabled.
21.5 Low-Power Modes
The following subsections describe the low-power modes.
21.5.1 Wait Mode
The ADC continues normal operation during wait mode. Any enabled CPU interrupt request from the ADC
can bring the MCU out of wait mode. If the ADC is not required to bring the MCU out of wait mode, power
down the ADC by setting the ADCH[4:0] bits in the ADC status and control register before executing the
WAIT instruction.
21.5.2 Stop Mode
The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted.
ADC conversions resume when the MCU exits stop mode. Allow one conversion cycle to stabilize the
analog circuitry before attempting a new ADC conversion after exiting stop mode.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
227
Analog-to-Digital Converter (ADC-8)
21.6 I/O Signals
The ADC module has eight channels that are shared with I/O ports B. Refer to 29.6 ADC Characteristics
for voltages referenced below.
21.6.1 ADC Analog Power Pin (VDDAREF)/ADC Voltage Reference Pin (VREFH)
The ADC analog portion uses VDDAREF as its power pin. Connect the AVDD/VDDAREF pin to the same
voltage potential as VDD. External filtering may be necessary to ensure clean VDDAREF for good results.
VREFH is the high reference voltage for all analog-to-digital conversions. Connect the VREFH pin to a
voltage potential between 1.5 volts and VDDAREF/AVDD depending on the desired upper conversion
boundary.
NOTE
Route VDDAREF carefully for maximum noise immunity and place bypass
capacitors as close as possible to the package.
21.6.2 ADC Analog Ground Pin (AVSS)/ADC Voltage Reference Low Pin (VREFL)
The ADC analog portion uses AVSS as its ground pin. Connect the AVSS pin to the same voltage potential
as VSS.
VREFL is the lower reference supply for the ADC.
21.6.3 ADC Voltage In (ADCVIN)
ADCVIN is the input voltage signal from one of the eight ADC channels to the ADC module.
21.7 I/O Registers
These I/O registers control and monitor ADC operation:
• ADC status and control register (ADSCR)
• ADC data register (ADR)
• ADC clock register (ADICLK)
21.7.1 ADC Status and Control Register
The following paragraphs describe the function of the ADC status and control register.
Address:
$0038
Bit 7
6
5
4
3
2
1
Bit 0
AIEN
ADCO
ADCH4
ADCH3
ADCH2
ADCH1
ADCH0
0
1
1
1
1
1
Read:
COCO
Write:
R
Reset:
0
0
R
= Reserved
Figure 21-2. ADC Status and Control Register (ADSCR)
MC68HC908AT32 Data Sheet, Rev. 3.1
228
Freescale Semiconductor
I/O Registers
COCO — Conversions Complete Bit
When the AIEN bit is a logic 0, the COCO is a read-only bit which is set each time a conversion is
completed. This bit is cleared whenever the ADC status and control register is written or whenever the
ADC data register is read.
If the AIEN bit is a logic 1, the COCO is a read/write bit which selects the CPU to service the ADC
interrupt request. Reset clears this bit.
1 = Conversion completed (AIEN = 0)
0 = Conversion not completed (AIEN = 0)
or
1 = DMA interrupt enabled (AIEN = 1)
0 = CPU interrupt enabled (AIEN = 1)
AIEN — ADC Interrupt Enable Bit
When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is
cleared when the data register is read or the status/control register is written. Reset clears the AIEN bit.
1 = ADC interrupt enabled
0 = ADC interrupt disabled
ADCO — ADC Continuous Conversion Bit
When set, the ADC will convert samples continuously and update the ADR register at the end of each
conversion. Only one conversion is allowed when this bit is cleared. Reset clears the ADCO bit.
1 = Continuous ADC conversion
0 = One ADC conversion
ADCH[4:0] — ADC Channel Select Bits
ADCH4, ADCH3, ADCH2, ADCH1, and ADCH0 form a 5-bit field which is used to select one of eight
ADC channels. The six channels are detailed in Table 21-1. Care should be taken when using a port
pin as both an analog and a digital input simultaneously to prevent switching noise from corrupting the
analog signal.
The ADC subsystem is turned off when the channel select bits are all set to 1. This feature allows for
reduced power consumption for the MCU when the ADC is not used. Reset sets these bits.
NOTE
Recovery from the disabled state requires one conversion cycle to stabilize.
Table 21-1. MUX Channel Select
ADCH4
ADCH3
ADCH2
ADCH1
ADCH0
Input Select
0
0
0
0
0
PTB0/ATD0
0
0
0
0
1
PTB1/ATD1
0
0
0
1
0
PTB2/ATD2
0
0
0
1
1
PTB3/ATD3
0
0
1
0
0
PTB4/ATD4
0
0
1
0
1
PTB5/ATD5
0
0
1
1
0
PTB6/ATD6
0
0
1
1
1
PTB7/ATD7
0
1
0
0
0
Unused(1)
Continued on next page
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
229
Analog-to-Digital Converter (ADC-8)
Table 21-1. MUX Channel Select (Continued)
ADCH4
ADCH3
ADCH2
ADCH1
ADCH0
Input Select
0
1
0
0
1
Unused(1)
0
1
0
1
0
Unused(1)
0
1
0
1
1
Unused(1)
0
1
1
0
0
Unused(1)
0
1
1
0
1
Unused(1)
0
1
1
1
0
Unused(1)
Unused(1)
Range 01111 ($0F) to 11010 ($1A)
Unused(1)
1
1
0
1
1
Reserved
1
1
1
0
0
VDDAREF(2)
1
1
1
0
1
VREFH(2)
1
1
1
1
0
AVSS/VREFL(2)
1
1
1
1
1
ADC power off
1. If any unused channels are selected, the resulting ADC conversion will be unknown.
2. The voltage levels supplied from internal reference nodes as specified in the table are
used to verify the operation of the ADC converter both in production test and for user
applications.
21.7.2 ADC Data Register
One 8-bit result register is provided. This register is updated each time an ADC conversion completes.
Address:
$0039
Bit 7
6
5
4
3
2
1
Bit 0
Read:
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Write:
R
R
R
R
R
R
R
R
1
Bit 0
Reset:
Indeterminate afte reset
R
= Reserved
Figure 21-3. ADC Data Register (ADR)
21.7.3 ADC Input Clock Register
This register selects the clock frequency for the ADC.
Address:
Read:
Write:
Reset:
$003A
Bit 7
6
5
4
ADIV2
ADIV1
ADIV0
ADICLK
0
0
0
0
R
= Reserved
3
2
0
0
0
0
R
R
R
R
0
0
0
0
Figure 21-4. ADC Input Clock Register (ADICLK)
MC68HC908AT32 Data Sheet, Rev. 3.1
230
Freescale Semiconductor
I/O Registers
ADIV2–ADIV0 — ADC Clock Prescaler Bits
ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate
the internal ADC clock. Table 21-2 shows the available clock configurations. The ADC clock should be
set to approximately 1 MHz.
Table 21-2. ADC Clock Divide Ratio
ADIV2
ADIV1
ADIV0
ADC Clock Rate
0
0
0
ADC input clock ÷ 1
0
0
1
ADC input clock ÷ 2
0
1
0
ADC input clock ÷ 4
0
1
1
ADC input clock ÷ 8
1
X
X
ADC input clock ÷ 16
X = don’t care
ADICLK — ADC Input Clock Register Bit
ADICLK selects either bus clock or CGMXCLK as the input clock source to generate the internal ADC
clock. Reset selects CGMXCLK as the ADC clock source.
If the external clock (CGMXCLK) is equal to or greater than 1 MHz, CGMXCLK can be used as the
clock source for the ADC. If CGMXCLK is less than 1 MHz, use the PLL-generated bus clock as the
clock source. As long as the internal ADC clock is at approximately 1 MHz, correct operation can be
guaranteed. (See 29.6 ADC Characteristics.)
1 = Internal bus clock
0 = External clock (CGMXCLK)
fXCLK or Bus Frequency
1 MHz = ⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
ADIV[2:0]
NOTE
During the conversion process, changing the ADC clock will result in an
incorrect conversion.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
231
Analog-to-Digital Converter (ADC-8)
MC68HC908AT32 Data Sheet, Rev. 3.1
232
Freescale Semiconductor
Chapter 22
MC68HC08AZ32 Emulator Input/Output Ports
NOTE
This input/output (I/O) description is for MC68HC08AZ32 emulator only.
22.1 Introduction
FIfty bidirectional input/output (I/O) form seven parallel ports. All I/O pins are programmable as inputs or
outputs.
NOTE
Connect any unused I/O pins to an appropriate logic level, either VDD or
VSS. Although the I/O ports do not require termination for proper operation,
termination reduces excess current consumption and the possibility of
electrostatic damage.
Addr.
$0000
Register Name
Port A Data Register Read:
(PTA) Write:
See page 235. Reset:
$0001
Port B Data Register Read:
(PTB) Write:
See page 237. Reset:
$0002
Port C Data Register Read:
(PTC) Write:
See page 239. Reset:
$0003
$0004
$0005
Port D Data Register Read:
(PTD) Write:
See page 241. Reset:
Data Direction Register A Read:
(DDRA) Write:
See page 235. Reset:
Data Direction Register B Read:
(DDRB) Write:
See page 237. Reset:
Bit 7
6
5
4
3
2
1
Bit 0
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
PTB2
PTB1
PTB0
PTC2
PTC1
PTC0
PTD2
PTD1
PTD0
Unaffected by reset
PTB7
PTB6
0
0
R
R
PTB5
PTB4
PTB3
Unaffected by reset
PTC5
PTC4
PTC3
Unaffected by reset
PTD7
PTD6
PTD5
PTD4
PTD3
Unaffected by reset
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
0
0
0
0
0
0
0
0
DDRB7
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
0
0
0
0
0
0
0
0
R
= Reserved
Figure 22-1. MC68HC08AZ32 Emulator I/O Port Register Summary
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
233
MC68HC08AZ32 Emulator Input/Output Ports
Addr.
$0006
$0007
$0008
Register Name
Bit 7
Data Direction Register C Read: MCLKEN
(DDRC) Write:
See page 239. Reset:
0
Data Direction Register D Read: DDRD7
(DDRD) Write:
See page 241. Reset:
0
Port E Data Register Read:
(PTE) Write:
See page 243. Reset:
PTE7
6
5
4
3
2
1
Bit 0
DDRC5
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
0
0
0
0
0
0
0
DDRD6
DDRD5
DDRD4
DDRD3
DDR2
DDRD1
DDRD0
0
0
0
0
0
0
0
PTE6
PTE5
PTE4
PTE3
PTE2
PTE1
PTE0
PTF2
PTF1
PTF0
PTG2
PTG1
PTG0
PTH1
PTH0
0
R
Unaffected by reset
$0009
Port F Data Register Read:
(PTF) Write:
See page 245. Reset:
$000A
Port G Data Register Read:
(PTG) Write:
See page 247. Reset:
Port H Data Register Read:
(PTH) Write:
See page 249. Reset:
0
0
0
0
0
0
R
R
R
R
R
R
$000B
$000C
Data Direction Register E Read:
(DDRE) Write:
See page 244. Reset:
0
PTF6
PTF5
0
0
0
0
0
R
R
R
R
R
R
PTF4
PTF3
Unaffected by reset
Unaffected by reset
Unaffected by reset
DDRE7
DDRE6
DDRE5
DDRE4
DDRE3
DDRE2
DDRE1
DDRE0
0
0
0
0
0
0
0
0
DDRF6
DDRF5
DDRF4
DDRF3
DDRF2
DDRF1
DDRF0
0
0
0
0
DDRG2
DDRG1
DDRG0
0
0
0
DDRH1
DDRH0
0
0
$000D
Data Direction Register F Read:
(DDRF) Write:
See page 246. Reset:
0
0
0
0
0
0
0
0
0
$000E
Data Direction Register G Read:
(DDRG) Write:
See page 248. Reset:
R
R
R
R
R
0
0
0
0
0
Data Direction Register H Read:
(DDRH) Write:
See page 250. Reset:
0
0
0
0
0
0
R
R
R
R
R
R
0
0
0
0
0
0
$000F
0
R
R
= Reserved
Figure 22-1. MC68HC08AZ32 Emulator I/O Port Register Summary (Continued)
MC68HC908AT32 Data Sheet, Rev. 3.1
234
Freescale Semiconductor
Port A
22.2 Port A
Port A is an 8-bit, general-purpose, bidirectional I/O port.
22.2.1 Port A Data Register
The port A data register contains a data latch for each of the eight port A pins.
Address:
Read:
Write:
$0000
Bit 7
6
5
4
3
2
1
Bit 0
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
Reset:
Unaffected by reset
Figure 22-2. Port A Data Register (PTA)
PTA[7:0] — Port A Data Bits
These read/write bits are software programmable. Data direction of each port A pin is under the control
of the corresponding bit in data direction register A. Reset has no effect on port A data.
22.2.2 Data Direction Register A
Data direction register A determines whether each port A pin is an input or an output. Writing a logic 1 to
a DDRA bit enables the output buffer for the corresponding port A pin; a logic 0 disables the output
buffer.
Address:
Read:
Write:
Reset:
$0004
Bit 7
6
5
4
3
2
1
Bit 0
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
0
0
0
0
0
0
0
0
Figure 22-3. Data Direction Register A (DDRA)
DDRA[7:0] — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears DDRA[7:0], configuring all port A pins
as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 22-4 shows the port A I/O logic.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
235
MC68HC08AZ32 Emulator Input/Output Ports
READ DDRA ($0004)
INTERNAL DATA BUS
WRITE DDRA ($0004)
DDRAx
RESET
WRITE PTA ($0000)
PTAx
PTAx
READ PTA ($0000)
Figure 22-4. Port A I/O Circuit
When bit DDRAx is a logic 1, reading address $0000 reads the PTAx data latch. When bit DDRAx is a
logic 0, reading address $0000 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 22-1 summarizes the operation of the port A pins.
Table 22-1. Port A Pin Functions
DDRA
Bit
PTA
Bit
I/O Pin Mode
0
X
1
X
Accesses to
DDRA
Accesses to PTA
Read/Write
Read
Write
Input, Hi-Z
DDRA[7:0]
Pin
PTA[7:0](1)
Output
DDRA[7:0]
PTA[7:0]
PTA[7:0]
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
MC68HC908AT32 Data Sheet, Rev. 3.1
236
Freescale Semiconductor
Port B
22.3 Port B
Port B is an 8-bit special function port that shares all of its pins with the analog-to-digital converter.
22.3.1 Port B Data Register
The port B data register contains a data latch for each of the eight port B pins.
Address:
Read:
Write:
$0001
Bit 7
6
5
4
3
2
1
Bit 0
PTB7
PTB6
PTB5
PTB4
PTB3
PTB2
PTB1
PTB0
ATD2
ATD1
ATD0
Reset:
Alternate
Functions:
Unaffected by reset
ATD7
ATD6
ATD5
ATD4
ATD3
Figure 22-5. Port B Data Register (PTB)
PTB[7:0] — Port B Data Bits
These read/write bits are software programmable. Data direction of each port B pin is under the control
of the corresponding bit in data direction register B. Reset has no effect on port B data.
ATD[7:0] — ADC Channels
PTB7/ATD7–PTB0/ATD0 are eight of the analog-to-digital converter channels. The ADC channel
select bits, CH[4:0], determine whether the PTB7/ATD7–PTB0/ATD0 pins are ADC channels or
general-purpose I/O pins. If an ADC channel is selected and a read of this corresponding bit in the
port B data register occurs, the data will be 0 if the data direction for this bit is programmed as an input.
Otherwise, the data will reflect the value in the data latch. (See Chapter 21 Analog-to-Digital Converter
(ADC-8).) Data direction register B (DDRB) does not affect the data direction of port B pins that are
being used by the ADC. However, the DDRB bits always determine whether reading port B returns to
the states of the latches or logic 0.
22.3.2 Data Direction Register B
Data direction register B determines whether each port B pin is an input or an output. Writing a logic 1 to
a DDRB bit enables the output buffer for the corresponding port B pin; a logic 0 disables the output
buffer.
Address:
Read:
Write:
Reset:
$0005
Bit 7
6
5
4
3
2
1
Bit 0
DDRB7
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
0
0
0
0
0
0
0
0
Figure 22-6. Data Direction Register B (DDRB)
DDRB[7:0] — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears DDRB[7:0], configuring all port B pins
as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
237
MC68HC08AZ32 Emulator Input/Output Ports
NOTE
Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1.
Figure 22-7 shows the port B I/O logic.
READ DDRB ($0005)
INTERNAL DATA BUS
WRITE DDRB ($0005)
DDRBx
RESET
WRITE PTB ($0001)
PTBx
PTBx
READ PTB ($0001)
Figure 22-7. Port B I/O Circuit
When bit DDRBx is a logic 1, reading address $0001 reads the PTBx data latch. When bit DDRBx is a
logic 0, reading address $0001 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 22-2 summarizes the operation of the port B pins.
Table 22-2. Port B Pin Functions
DDRB
Bit
PTB
Bit
I/O Pin
Mode
0
X
1
X
Accesses to
DDRB
Accesses to PTB
Read/Write
Read
Write
Input, Hi-Z
DDRB[7:0]
Pin
PTB[7:0](1)
Output
DDRB[7:0]
PTB[7:0]
PTB[7:0]
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
MC68HC908AT32 Data Sheet, Rev. 3.1
238
Freescale Semiconductor
Port C
22.4 Port C
Port C is a 6-bit, general-purpose, bidirectional I/O port.
22.4.1 Port C Data Register
The port C data register contains a data latch for each of the six port C pins.
Address:
$0002
Bit 7
6
Read:
0
0
Write:
R
R
5
4
3
2
1
Bit 0
PTC5
PTC4
PTC3
PTC2
PTC1
PTC0
Reset:
Unaffected by reset
R
= Reserved
Alternate Function:
MCLK
Figure 22-8. Port C Data Register (PTC)
PTC[5:0] — Port C Data Bits
These read/write bits are software-programmable. Data direction of each port C pin is under the control
of the corresponding bit in data direction register C. Reset has no effect on port C data (5:0).
MCLK — T12 System Clock Bit
The system clock is driven out of PTC2 when enabled by MCLKEN bit in PTCDDR7.
22.4.2 Data Direction Register C
Data direction register C determines whether each port C pin is an input or an output. Writing a logic 1 to
a DDRC bit enables the output buffer for the corresponding port C pin; a logic 0 disables the output
buffer.
Address:
$0006
Bit 7
Read:
Write:
Reset:
6
MCLKEN
0
R
0
0
R
= Reserved
5
4
3
2
1
Bit 0
DDRC5
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
0
0
0
0
0
0
Figure 22-9. Data Direction Register C (DDRC)
MCLKEN — MCLK Enable Bit
This read/write bit enables MCLK to be an output signal on PTC2. If MCLK is enabled, DDRC2 has no
effect. Reset clears this bit.
1 = MCLK output enabled
0 = MCLK output disabled
DDRC[5:0] — Data Direction Register C Bits
These read/write bits control port C data direction. Reset clears DDRC[7:0], configuring all port C pins
as inputs.
1 = Corresponding port C pin configured as output
0 = Corresponding port C pin configured as input
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
239
MC68HC08AZ32 Emulator Input/Output Ports
NOTE
Avoid glitches on port C pins by writing to the port C data register before
changing data direction register C bits from 0 to 1.
Figure 22-10 shows the port C I/O logic.
READ DDRC ($0006)
INTERNAL DATA BUS
WRITE DDRC ($0006)
DDRCx
RESET
WRITE PTC ($0002)
PTCx
PTCx
READ PTC ($0002)
Figure 22-10. Port C I/O Circuit
When bit DDRCx is a logic 1, reading address $0002 reads the PTCx data latch. When bit DDRCx is a
logic 0, reading address $0002 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 22-3 summarizes the operation of the port C pins.
Table 22-3. Port C Pin Functions
Bit
Value
PTC
Bit
I/O Pin
Mode
0
2
1
Accesses to
DDRC
Accesses to PTC
Read/Write
Read
Write
Input, Hi-Z
DDRC[2]
Pin
PTC2
2
Output
DDRC[2]
0
—
0
X
Input, Hi-Z
DDRC[5:0]
Pin
PTC[5:0](1)
1
X
Output
DDRC[5:0]
PTC[5:0]
PTC[5:0]
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
MC68HC908AT32 Data Sheet, Rev. 3.1
240
Freescale Semiconductor
Port D
22.5 Port D
Port D is an 8-bit, general-purpose I/O port.
22.5.1 Port D Data Register
Port D is a 8-bit special function port that shares two of its pins with the timer interface modules.
Address:
$0003
Read:
Write:
Bit 7
6
5
4
3
2
1
Bit 0
PTD7
PTD6
PTD5
PTD4
PTD3
PTD2
PTD1
PTD0
Reset:
Unaffected by reset
Alternate Functions:
TACLK
TBCLK
Figure 22-11. Port D Data Register (PTD)
PTD[7:0] — Port D Data Bits
PTD[7:0] are read/write, software programmable bits. Data direction of PTD[7:0] pins are under the
control of the corresponding bit in data direction register D.
NOTE
Data direction register D (DDRD) does not affect the data direction of port
D pins that are being used by the TIMA or TIMB. However, the DDRD bits
always determine whether reading port D returns the states of the latches
or logic 0.
TACLK/TBCLK — Timer Clock Input Bit
The PTD6/ATD14/TACLK pin is the external clock input for the TIMA. The PTD4/ATD12/TBCLK pin is
the external clock input for the TIMB. The prescaler select bits, PS[2:0], select PTD6/ATD14/TACLK
or PTD4/ATD12/TBCLK as the TIM clock input. (See 18.8.4 TIMA Channel Status and Control
Registers and 19.8.1 TIMB Status and Control Register.) When not selected as the TIM clock,
PTD6/ATD14/TACLK and PTD4/ATD12/TBCLK are available for general-purpose I/O. While
TACLK/TBCLK are selected corresponding DDRD bits have no effect.
22.5.2 Data Direction Register D
Data direction register D determines whether each port D pin is an input or an output. Writing a logic 1 to
a DDRD bit enables the output buffer for the corresponding port D pin; a logic 0 disables the output
buffer.
Address:
Read:
Write:
Reset:
$0007
Bit 7
6
5
4
3
2
1
Bit 0
DDRD7
DDRD6
DDRD5
DDRD4
DDRD3
DDRD2
DDRD1
DDRD0
0
0
0
0
0
0
0
0
Figure 22-12. Data Direction Register D (DDRD)
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
241
MC68HC08AZ32 Emulator Input/Output Ports
DDRD[7:0] — Data Direction Register D Bits
These read/write bits control port D data direction. Reset clears DDRD[7:0], configuring all port D pins
as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
NOTE
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
Figure 22-13 shows the port D I/O logic.
READ DDRD ($0007)
INTERNAL DATA BUS
WRITE DDRD ($0007)
RESET
DDRDx
WRITE PTD ($0003)
PTDx
PTDx
READ PTD ($0003)
Figure 22-13. Port D I/O Circuit
When bit DDRDx is a logic 1, reading address $0003 reads the PTDx data latch. When bit DDRDx is a
logic 0, reading address $0003 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 22-4 summarizes the operation of the port D pins.
Table 22-4. Port D Pin Functions
DDRD
Bit
PTD
Bit
I/O Pin
Mode
0
X
1
X
Accesses
to DDRD
Accesses to PTD
Read/Write
Read
Write
Input, Hi-Z
DDRD[7:0]
Pin
PTD[7:0](1)
Output
DDRD[7:0]
PTD[7:0]
PTD[7:0]
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
MC68HC908AT32 Data Sheet, Rev. 3.1
242
Freescale Semiconductor
Port E
22.6 Port E
Port E is an 8-bit special function port that shares two of its pins with the timer interface module (TIMA),
two of its pins with the serial communications interface module (SCI), and four of its pins with the serial
peripheral interface module (SPI).
22.6.1 Port E Data Register
The port E data register contains a data latch for each of the eight port E pins.
Address:
$0008
Read:
Write:
Bit 7
6
5
4
3
2
1
Bit 0
PTE7
PTE6
PTE5
PTE4
PTE3
PTE2
PTE1
PTE0
TACH0
RxD
TxD
Reset:
Alternate Functions:
Unaffected by reset
SPSCK
MOSI
MISO
SS
TACH1
Figure 22-14. Port E Data Register (PTE)
PTE[7:0] — Port E Data Bits
PTE[7:0] are read/write, software programmable bits. Data direction of each port E pin is under the
control of the corresponding bit in data direction register E.
SPSCK — SPI Serial Clock Bit
The PTE7/SPSCK pin is the serial clock input of an SPI slave module and serial clock output of an SPI
master module. When the SPE bit is clear, the PTE7/SPSCK pin is available for general-purpose I/O.
See 17.13.1 SPI Control Register.
MOSI — Master Out/Slave In Bit
The PTE6/MOSI pin is the master out/slave in terminal of the SPI module. When the SPE bit is clear,
the PTE6/MOSI pin is available for general-purpose I/O.
MISO — Master In/Slave Out Bit
The PTE5/MISO pin is the master in/slave out terminal of the SPI module. When the SPI enable bit,
SPE, is clear, the SPI module is disabled, and the PTE5/MISO pin is available for general-purpose I/O.
See 17.13.1 SPI Control Register.
SS — Slave Select Bit
The PTE4/SS pin is the slave select input of the SPI module. When the SPE bit is clear, or when the
SPI master bit, SPMSTR, is set and MODFEN bit is low, the PTE4/SS pin is available for
general-purpose I/O. (See 17.12.4 SS (Slave Select).) When the SPI is enabled as a slave, the DDRF0
bit in data direction register E (DDRE) has no effect on the PTE4/SS pin.
NOTE
Data direction register E (DDRE) does not affect the data direction of port
E pins that are being used by the SPI module. However, the DDRE bits
always determine whether reading port E returns the states of the latches
or the states of the pins. See Table 22-5.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
243
MC68HC08AZ32 Emulator Input/Output Ports
TACH[1:0] — Timer Channel I/O Bits
The PTE3/TACH1–PTE2/TACH0 pins are the TIM input capture/output compare pins. The edge/level
select bits, ELSxB:ELSxA, determine whether the PTE3/TACH1–PTE2/TACH0 pins are timer channel
I/O pins or general-purpose I/O pins. See 18.8.4 TIMA Channel Status and Control Registers.
NOTE
Data direction register E (DDRE) does not affect the data direction of port
E pins that are being used by the TIM. However, the DDRE bits always
determine whether reading port E returns the states of the latches or the
states of the pins. See Table 22-5.
RxD — SCI Receive Data Input Bit
The PTE1/RxD pin is the receive data input for the SCI module. When the enable SCI bit, ENSCI, is
clear, the SCI module is disabled, and the PTE1/RxD pin is available for general-purpose I/O. See
16.8.1 SCI Control Register 1.
TxD — SCI Transmit Data Output
The PTE0/TxD pin is the transmit data output for the SCI module. When the enable SCI bit, ENSCI, is
clear, the SCI module is disabled, and the PTE0/TxD pin is available for general-purpose I/O. See
16.8.1 SCI Control Register 1.
NOTE
Data direction register E (DDRE) does not affect the data direction of port
E pins that are being used by the SCI module. However, the DDRE bits
always determine whether reading port E returns the states of the latches
or the states of the pins. See Table 22-5.
22.6.2 Data Direction Register E
Data direction register E determines whether each port E pin is an input or an output. Writing a logic 1 to
a DDRE bit enables the output buffer for the corresponding port E pin; a logic 0 disables the output
buffer.
Address:
Read:
Write:
Reset:
$000C
Bit 7
6
5
4
3
2
1
Bit 0
DDRE7
DDRE6
DDRE5
DDRE4
DDRE3
DDRE2
DDRE1
DDRE0
0
0
0
0
0
0
0
0
Figure 22-15. Data Direction Register E (DDRE)
DDRE[7:0] — Data Direction Register E Bits
These read/write bits control port E data direction. Reset clears DDRE[7:0], configuring all port E pins
as inputs.
1 = Corresponding port E pin configured as output
0 = Corresponding port E pin configured as input
NOTE
Avoid glitches on port E pins by writing to the port E data register before
changing data direction register E bits from 0 to 1.
Figure 22-16 shows the port E I/O logic.
MC68HC908AT32 Data Sheet, Rev. 3.1
244
Freescale Semiconductor
Port F
READ DDRE ($000C)
INTERNAL DATA BUS
WRITE DDRE ($000C)
DDREx
RESET
WRITE PTE ($0008)
PTEx
PTEx
READ PTE ($0008)
Figure 22-16. Port E I/O Circuit
When bit DDREx is a logic 1, reading address $0008 reads the PTEx data latch. When bit DDREx is a
logic 0, reading address $0008 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 22-5 summarizes the operation of the port E pins.
Table 22-5. Port E Pin Functions
DDRE
Bit
PTE
Bit
I/O Pin
Mode
0
X
1
X
Accesses to
DDRE
Accesses to PTE
Read/Write
Read
Write
Input, Hi-Z
DDRE[7:0]
Pin
PTE[7:0](1)
Output
DDRE[7:0]
PTE[7:0]
PTE[7:0]
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
22.7 Port F
Port F is a 7-bit special function port that shares two of its pins with the timer interface module (TIMA-4)
and two of its pins with the timer interface module (TIMB).
22.7.1 Port F Data Register
The port F data register contains a data latch for each of the seven port F pins.
Address:
$0009
Bit 7
Read:
0
Write:
R
6
5
4
3
2
1
Bit 0
PTF6
PTF5
PTF4
PTF3
PTF2
PTF1
PTF0
TACH3
TACH2
Reset:
Unaffected by reset
Alternate Functions:
TBCH1
R
TBCH0
= Reserved
Figure 22-17. Port F Data Register (PTF)
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
245
MC68HC08AZ32 Emulator Input/Output Ports
PTF[6:0] — Port F Data Bits
These read/write bits are software programmable. Data direction of each port F pin is under the control
of the corresponding bit in data direction register F. Reset has no effect on PTF[6:0].
TACH[3:2] — Timer A Channel I/O Bits
The PTF1/TACH3–PTF0/TACH2 pins are the TIM input capture/output compare pins. The edge/level
select bits, ELSxB:ELSxA, determine whether the PTF1/TACH3–PTF0/TACH2 pins are timer channel
I/O pins or general-purpose I/O pins. See 18.8.1 TIMA Status and Control Register.
TBCH[1:0] — Timer B Channel I/O Bits
The PTF5/TBCH1–PTF4/TBCH0 pins are the TIMB input capture/output compare pins. The edge/level
select bits, ELSxB:ELSxA, determine whether the PTF5/TBCH1–PTF4/TBCH0 pins are timer channel
I/O pins or general-purpose I/O pins. See 19.8.1 TIMB Status and Control Register.
NOTE
Data direction register F (DDRF) does not affect the data direction of port F
pins that are being used by the TIM. However, the DDRF bits always
determine whether reading port F returns the states of the latches or the
states of the pins. See Table 22-6.
22.7.2 Data Direction Register F
Data direction register F determines whether each port F pin is an input or an output. Writing a logic 1 to
a DDRF bit enables the output buffer for the corresponding port F pin; a logic 0 disables the output
buffer.
Address:
$000D
Bit 7
6
5
4
3
2
1
Bit 0
DDRF6
DDRF5
DDRF4
DDRF3
DDRF2
DDRF1
DDRF0
0
0
0
0
0
0
0
0
R
= Reserved
Read:
0
Write:
R
Reset:
Figure 22-18. Data Direction Register F (DDRF)
DDRF[6:0] — Data Direction Register F Bits
These read/write bits control port F data direction. Reset clears DDRF[6:0], configuring all port F pins
as inputs.
1 = Corresponding port F pin configured as output
0 = Corresponding port F pin configured as input
NOTE
Avoid glitches on port F pins by writing to the port F data register before
changing data direction register F bits from 0 to 1.
Figure 22-19 shows the port F I/O logic.
MC68HC908AT32 Data Sheet, Rev. 3.1
246
Freescale Semiconductor
Port G
READ DDRF ($000D)
INTERNAL DATA BUS
WRITE DDRF ($000D)
DDRFx
RESET
WRITE PTF ($0009)
PTFx
PTFx
READ PTF ($0009)
Figure 22-19. Port F I/O Circuit
When bit DDRFx is a logic 1, reading address $0009 reads the PTFx data latch. When bit DDRFx is a
logic 0, reading address $0009 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 22-6 summarizes the operation of the port F pins.
Table 22-6. Port F Pin Functions
DDRF
Bit
PTF
Bit
I/O Pin
Mode
0
X
1
X
Accesses to
DDRF
Accesses to PTF
Read/Write
Read
Write
Input, Hi-Z
DDRF[6:0]
Pin
PTF[6:0](1)
Output
DDRF[6:0]
PTF[6:0]
PTF[6:0]
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
22.8 Port G
Port G is a 3-bit special function port that shares all of its pins with the keyboard interrupt module (KBD).
22.8.1 Port G Data Register
The port G data register contains a data latch for each of the three port G pins.
Address:
$000A
Bit 7
6
5
4
3
Read:
0
0
0
0
0
Write:
R
R
R
R
R
Reset:
2
1
Bit 0
PTG2
PTG1
PTG0
KBD2
KBD1
KBD0
Unaffected by reset
Alternate Functions:
R
= Reserved
Figure 22-20. Port G Data Register (PTG)
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
247
MC68HC08AZ32 Emulator Input/Output Ports
PTG[2:0] — Port G Data Bits
These read/write bits are software programmable. Data direction of each port G pin is under the control
of the corresponding bit in data direction register G. Reset has no effect on PTG[2:0].
KBD[2:0] — Keyboard Wakeup pins
The keyboard interrupt enable bits, KBIE[2:0], in the keyboard interrupt control register, enable the port
G pins as external interrupt pins (See Chapter 24 Keyboard Interrupt Module (KBD).) Enabling an
external interrupt pin will override the corresponding DDRGx.
22.8.2 Data Direction Register G
Data direction register G determines whether each port G pin is an input or an output. Writing a logic 1 to
a DDRG bit enables the output buffer for the corresponding port G pin; a logic 0 disables the output
buffer.
Address:
$000E
Bit 7
6
5
4
3
Read:
0
0
0
0
0
Write:
R
R
R
R
R
Reset:
0
0
0
0
0
R
= Reserved
2
1
Bit 0
DDRG2
DDRG1
DDRG0
0
0
0
Figure 22-21. Data Direction Register G (DDRG)
DDRG[2:0] — Data Direction Register G Bits
These read/write bits control port G data direction. Reset clears DDRG[2:0], configuring all port G pins
as inputs.
1 = Corresponding port G pin configured as output
0 = Corresponding port G pin configured as input
NOTE
Avoid glitches on port G pins by writing to the port G data register before
changing data direction register G bits from 0 to 1.
Figure 22-22 shows the port G I/O logic.
READ DDRG ($000E)
INTERNAL DATA BUS
WRITE DDRG ($000E)
RESET
DDRGx
WRITE PTG ($000A)
PTGx
PTGx
READ PTG ($000A)
Figure 22-22. Port G I/O Circuit
MC68HC908AT32 Data Sheet, Rev. 3.1
248
Freescale Semiconductor
Port H
When bit DDRGx is a logic 1, reading address $000A reads the PTGx data latch. When bit DDRGx is a
logic 0, reading address $000A reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 22-7 summarizes the operation of the port G pins.
Table 22-7. Port G Pin Functions
DDRG
Bit
PTG
Bit
I/O Pin
Mode
0
X
1
X
Accesses to
DDRG
Accesses to PTG
Read/Write
Read
Write
Input, Hi-Z
DDRG[2:0]
Pin
PTG[2:0](1)
Output
DDRG[2:0]
PTG[2:0]
PTG[2:0]
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
22.9 Port H
Port H is a 2-bit special function port that shares all of its pins with the keyboard interrupt module (KBD).
22.9.1 Port H Data Register
The port H data register contains a data latch for each of the two port H pins.
Address:
$000B
Bit 7
6
5
4
3
2
Read:
0
0
0
0
0
0
Write:
R
R
R
R
R
R
Reset:
1
Bit 0
PTH1
PTH0
KBD4
KBD3
Unaffected by reset
Alternate
Functions:
R
= Reserved
Figure 22-23. Port H Data Register (PTH)
PTH[1:0] — Port H Data Bits
These read/write bits are software programmable. Data direction of each port H pin is under the control
of the corresponding bit in data direction register H. Reset has no effect on PTH[1:0].
KBD[4:3] — Keyboard Wake-up pins
The keyboard interrupt enable bits, KBIE[4:3], in the keyboard interrupt control register, enable the port
H pins as external interrupt pins. See Chapter 24 Keyboard Interrupt Module (KBD).
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
249
MC68HC08AZ32 Emulator Input/Output Ports
22.9.2 Data Direction Register H
Data direction register H determines whether each port H pin is an input or an output. Writing a logic 1 to
a DDRH bit enables the output buffer for the corresponding port H pin; a logic 0 disables the output
buffer.
Address:
$000F
Read:
Write:
Reset:
Bit 7
0
R
0
R
6
0
R
0
= Reserved
5
0
R
0
4
0
R
0
3
0
R
0
2
0
R
0
1
Bit 0
DDRH1
DDRH0
0
0
Figure 22-24. Data Direction Register H (DDRH)
DDRH[1:0] — Data Direction Register H Bits
These read/write bits control port H data direction. Reset clears DDRG[1:0], configuring all port H pins
as inputs.
1 = Corresponding port H pin configured as output
0 = Corresponding port H pin configured as input
NOTE
Avoid glitches on port H pins by writing to the port H data register before
changing data direction register H bits from 0 to 1.
Figure 22-25 shows the port H I/O logic.
READ DDRH ($000F)
INTERNAL DATA BUS
WRITE DDRH ($000F)
DDRHx
RESET
WRITE PTH ($000B)
PTHx
PTHx
READ PTH ($000B)
Figure 22-25. Port H I/O Circuit
When bit DDRHx is a logic 1, reading address $000B reads the PTHx data latch. When bit DDRHx is a
logic 0, reading address $000B reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 22-8 summarizes the operation of the port H pins.
Table 22-8. Port H Pin Functions
DDRH
Bit
PTH
Bit
I/O Pin
Mode
Accesses to
DDRH
Read/Write
Read
Write
0
X
Input, Hi-Z
DDRH[1:0]
Pin
PTH[1:0](1)
PTH[1:0]
1
X
Output
DDRH[1:0]
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
Accesses to PTH
PTH[1:0]
MC68HC908AT32 Data Sheet, Rev. 3.1
250
Freescale Semiconductor
Chapter 23
MSCAN Controller
23.1 Introduction
The MSCAN08 is the specific implementation of the scalable controller area network (MSCAN) concept
targeted for the Freescale M68HC08 Microcontroller Family.
The module is a communication controller implementing the CAN2.0A/B protocol as defined in the
BOSCH specification dated September 1991.
The CAN protocol was primarily, but not exclusively, designed to be used as a vehicle serial data bus,
meeting the specific requirements of this field: real-time processing, reliable operation in the
electromagnetic interference (EMI) environment of a vehicle, cost-effectiveness, and required bandwidth.
MSCAN08 utilizes an advanced buffer arrangement, resulting in a predictable real-time behavior, and
simplifies the application software.
23.2 Features
Basic features of the MSCAN08 are:
• Modular architecture
• Implementation of the CAN protocol — Version 2.0A/B:
– Standard and extended data frames
– 0–8 bytes data length
– Programmable bit rate up to 1 Mbps depending on the actual bit timing and the clock jitter of
the phase-locked loop (PLL)
• Support for remote frames
• Double-buffered receive storage scheme
• Triple-buffered transmit storage scheme with internal prioritization using a “local priority” concept
• Flexible maskable identifier filter supports alternatively one full size extended identifier filter or two
16-bit filters or four 8-bit filters
• Programmable wakeup functionality with integrated low-pass filter
• Programmable loop-back mode supports self-test operation
• Separate signalling and interrupt capabilities for all CAN receiver and transmitter error states
(warning, error passive, bus-off)
• Programmable MSCAN08 clock source either cpu bus clock or crystal oscillator output
• Programmable link to on-chip timer interface module (TIMB) for time-stamping and network
synchronization
• Low-power sleep mode
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
251
MSCAN Controller
23.3 External Pins
The MSCAN08 uses two external pins, one input (CANRx) and one output (CANTx). The CANTx output
pin represents the logic level on the CAN: 0 is for a dominant state, and 1 is for a recessive state.
A typical CAN system with MSCAN08 is shown in Figure 23-1.
CAN STATION 1
CAN NODE 1
CAN NODE 2
CAN NODE N
MCU
CAN CONTROLLER
(MSCAN08)
CANTX
CANRX
TRANSCEIVER
CAN_H
CAN_L
CAN BUS
Figure 23-1. CAN System
Each CAN station is connected physically to the CAN bus lines through a transceiver chip. The
transceiver is capable of driving the large current needed for the CAN and has current protection against
defected CAN or defected stations.
23.4 Message Storage
MSCAN08 facilitates a sophisticated message storage system which addresses the requirements of a
broad range of network applications.
23.4.1 Background
Modern application layer software is built under two fundamental assumptions:
1. Any CAN node is able to send out a stream of scheduled messages without releasing the bus
between two messages. Such nodes will arbitrate for the bus right after sending the previous
message and will only release the bus in case of lost arbitration.
2. The internal message queue within any CAN node is organized as such that the highest priority
message will be sent out first if more than one message is ready to be sent.
Above behavior cannot be achieved with a single transmit buffer. That buffer must be reloaded right after
the previous message has been sent. This loading process lasts a definite amount of time and has to be
MC68HC908AT32 Data Sheet, Rev. 3.1
252
Freescale Semiconductor
Message Storage
completed within the inter-frame sequence (IFS) to be able to send an uninterrupted stream of messages.
Even if this is feasible for limited CAN bus speeds, it requires that the CPU reacts with short latencies to
the transmit interrupt.
A double buffer scheme would de-couple the re-loading of the transmit buffers from the actual message
being sent and as such reduces the reactiveness requirements on the CPU. Problems may arise if the
sending of a message would be finished just while the CPU re-loads the second buffer. In that case, no
buffer would then be ready for transmission and the bus would be released.
Under all circumstances, at least three transmit buffers are required to meet the first of the above
requirements. The MSCAN08 has three transmit buffers.
The second requirement calls for some sort of internal prioritization which the MSCAN08 implements with
the “local priority” concept described in 23.4.2 Receive Structures.
23.4.2 Receive Structures
The received messages are stored in a 2-stage input first in first out (FIFO). The two message buffers are
mapped using a Ping Pong arrangement into a single memory area (see Figure 23-2). While the
background receive buffer (RxBG) is exclusively associated to the MSCAN08, the foreground receive
buffer (RxFG) is addressable by the CPU08. This scheme simplifies the handler software, because only
one address area is applicable for the receive process.
Each buffer has 13 bytes to store the CAN control bits, the identifier (standard or extended), and the data
content (for details, see 23.12 Programmer’s Model of Message Storage).
The receiver full flag (RXF) in the MSCAN08 receiver flag register (CRFLG) (see 23.13.5 MSCAN08
Receiver Flag Register) signals the status of the foreground receive buffer. When the buffer contains a
correctly received message with matching identifier, this flag is set.
After the MSCAN08 successfully receives a message into the background buffer, it copies the content of
RxBG into RxFG(1), sets the RXF flag, and emits a receive interrupt to the CPU(2). A new message, which
may follow immediately after the IFS field of the CAN frame, will be received into RxBG.
The user’s receive handler has to read the received message from RxFG and to reset the RXF flag to
acknowledge the interrupt and to release the foreground buffer.
An overrun condition occurs when both the foreground and the background receive message buffers that
are filled with correctly received messages and another message is being received from the bus. The
latter message will be discarded and an error interrupt with overrun indication will occur if enabled. The
over-writing of the background buffer is independent of the identifier filter function. In the overrun situation,
the MSCAN08 will stay synchronized to the CAN bus. While it is able to transmit messages, all incoming
messages will be discarded.
NOTE
MSCAN08 will receive its own messages into the background receive
buffer RxBG but will not overwrite RxFG and will NOT emit a receive
interrupt. It also will not acknowledge (ACK) its own messages on the CAN
bus. The only exception to this rule is in loop-back mode when MSCAN08
will treat its own messages exactly like all other incoming messages.
1. Only if the RXF flag is not set.
2. The receive interrupt will occur only if not masked. A polling scheme can be applied on RXF also.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
253
MSCAN Controller
CAN
Receive / Transmit
Engine
CPU08
Memory Mapped
I/O
CPU08 Ibus
MSCAN08
RxBG
RxFG
RXF
Tx0
TXE
PRIO
Tx1
TXE
PRIO
Tx2
TXE
PRIO
Figure 23-2. User Model for Message Buffer Organization
MC68HC908AT32 Data Sheet, Rev. 3.1
254
Freescale Semiconductor
Identifier Acceptance Filter
23.4.3 Transmit Structures
The MSCAN08 has a triple transmit buffer scheme to allow multiple messages to be set up in advance
and to achieve an optimized real-time performance. The three buffers are arranged as shown in
Figure 23-2.
All three buffers have a 13-byte data structure similar to the outline of the receive buffers (see 23.12
Programmer’s Model of Message Storage). An additional transmit buffer priority register (TBPR) contains
an 8-bit “local priority” field (PRIO) (see 23.12.5 Transmit Buffer Priority Registers).
To transmit a message, the CPU08 has to identify an available transmit buffer which is indicated by a set
transmit buffer empty (TXE) flag in the MSCAN08 transmitter flag register (CTFLG) (see 23.13.7
MSCAN08 Transmitter Flag Register).
The CPU08 then stores the identifier, the control bits and the data content into one of the transmit buffers.
Finally, the buffer has to be flagged ready for transmission by clearing the TXE flag.
The MSCAN08 then will schedule the message for transmission and will signal the successful
transmission of the buffer by setting the TXE flag. A transmit interrupt will be emitted(1) when TXE is set
and can be used to drive the application software to re-load the buffer.
In case more than one buffer is scheduled for transmission when the CAN bus becomes available for
arbitration, the MSCAN08 uses the local priority setting of the three buffers for prioritzation. For this
purpose, every transmit buffer has an 8-bit local priority field (PRIO). The application software sets this
field when the message is set up. The local priority reflects the priority of this particular message relative
to the set of messages being emitted from this node. The lowest binary value of the PRIO field is defined
as the highest priority.
The internal scheduling process takes place whenever the MSCAN08 arbitrates for the bus. This is also
the case after the occurrence of a transmission error.
When a high priority message is scheduled by the application software, it may become necessary to abort
a lower priority message being set up in one of the three transmit buffers. Because messages that are
already under transmission cannot be aborted, the user has to request the abort by setting the
corresponding abort request flag (ABTRQ) in the transmission control register (CTCR). The MSCAN08
will then grant the request, if possible, by setting the corresponding abort request acknowledge (ABTAK)
and the TXE flag to release the buffer and by emitting a transmit interrupt. The transmit interrupt handler
software can tell from the setting of the ABTAK flag whether the message was actually aborted
(ABTAK = 1) or sent (ABTAK = 0).
23.5 Identifier Acceptance Filter
A flexible, programmable generic identifier acceptance filter has been introduced to reduce the CPU
interrupt loading. The filter is programmable to operate in three different modes:
• Single identifier acceptance filter to be applied to the full 29 bits of the identifier and to these bits
of the CAN frame: RTR, IDE, and SRR. This mode implements a single filter for a full length CAN
2.0B compliant extended identifier.
• Double identifier acceptance filter to be applied to
– The 11 bits of the identifier and the RTR bit of CAN 2.0A messages or
– The 14 most significant bits of the identifier of CAN 2.0B messages
1. The transmit interrupt will occur only if not masked. A polling scheme can be applied on TXE also.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
255
MSCAN Controller
•
Quadruple identifier acceptance filter to be applied to the first eight bits of the identifier. This mode
implements four independent filters for the first eight bits of a CAN 2.0A compliant standard
identifier.
The identifier acceptance registers (CIAR) define the acceptable pattern of the standard or extended
identifier (ID10–ID0 or ID28–ID0). Any of these bits can be marked don’t care in the identifier mask
register (CIMR).
ID28
IDR0
ID21 ID20
IDR1
ID10
IDR0
ID3 ID2
IDR1
ID15 ID14
AC7
CIDMR0
AC0 AC7
CIDMR1
AC0 AC7
CIDMR2
AC7
CIDAR0
AC0 AC7
CIDAR1
AC0 AC7
CIDAR2
IDE
ID10
IDR2
ID7 ID6
IDR3
RTR
IDR2
ID3 ID10
IDR3
ID3
AC0 AC7
CIDMR3
AC0
AC0 AC7
CIDAR3
AC0
ID ACCEPTED (FILTER 0 HIT)
Figure 23-3. Single 32-Bit Maskable Identifier Acceptance Filter
The background buffer, RxBG, will be copied into the foreground buffer, RxFG, and the RxF flag will be
set only in case of an accepted identifier (an identifier acceptance filter hit). A hit also will cause a receiver
interrupt if enabled.
ID28
IDR0
ID21 ID20
IDR1
ID15 ID14
ID10
IDR0
ID3 ID2
IDR1
AC7
CIDMR0
AC0 AC7
CIDMR1
AC0
AC7
CIDAR0
AC0 AC7
CIDAR1
AC0
IDE
ID10
IDR2
ID7 ID6
IDR3
RTR
IDR2
ID3 ID10
IDR3
ID3
ID ACCEPTED (FILTER 0 HIT)
AC7
CIDMR2
AC0 AC7
CIDMR3
AC0
AC7
CIDAR2
AC0 AC7
CIDAR3
AC0
ID ACCEPTED (FILTER 1 HIT)
Figure 23-4. Dual 16-Bit Maskable Acceptance Filters
MC68HC908AT32 Data Sheet, Rev. 3.1
256
Freescale Semiconductor
Identifier Acceptance Filter
A filter hit is indicated to the application software by a set RXF (receiver buffer full flag, see
23.13.5 MSCAN08 Receiver Flag Register) and two bits in the identifier acceptance control register (see
23.13.9 MSCAN08 Identifier Acceptance Control Register). These identifier hit flags (IDHIT1–IDHIT0)
clearly identify the filter section that caused the acceptance. They simplify the application software’s task
to identify the cause of the receiver interrupt. When more than one hit occurs (two or more filters match),
the lower hit has priority.
ID28
IDR0
ID21 ID20
IDR1
ID10
IDR0
ID3 ID2
IDR1
AC7
CIDMR0
AC0
AC7
CIDAR0
AC0
ID15 ID14
IDE
ID10
IDR2
ID7 ID6
IDR3
RTR
IDR2
ID3 ID10
IDR3
ID3
ID ACCEPTED (FILTER 0 HIT)
AC7
CIDMR1
AC0
AC7
CIDAR1
AC0
ID ACCEPTED (FILTER 1 HIT)
AC7
CIDMR2
AC0
AC7
CIDAR2
AC0
ID ACCEPTED (FILTER 2 HIT)
AC7
CIDMR3
AC0
AC7
CIDAR3
AC0
ID ACCEPTED (FILTER 3 HIT)
Figure 23-5. Quadruple 8-Bit Maskable Acceptance Filters
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
257
MSCAN Controller
23.6 Interrupts
The MSCAN08 supports four interrupt vectors mapped onto 11 different interrupt sources, any of which
can be individually masked (for details see 23.13.5 MSCAN08 Receiver Flag Register to 23.13.8
MSCAN08 Transmitter Control Register).
• Transmit Interrupt: At least one of the three transmit buffers is empty (not scheduled) and can be
loaded to schedule a message for transmission. The TXE flags of the empty message buffers are
set.
• Receive Interrupt: A message has been received successfully and loaded into the foreground
receive buffer. This interrupt will be emitted immediately after receiving the EOF symbol. The RXF
flag is set.
• Wakeup Interrupt: An activity on the CAN bus occurred during MSCAN08 internal sleep mode.
• Error Interrupt: An overrun, error, or warning condition occurred. The receiver flag register
(CRFLG) will indicate one of the following conditions:
– Overrun: An overrun condition as described in 23.4.2 Receive Structures has occurred.
– Receiver Warning: The receive error counter has reached the CPU warning limit of 96.
– Transmitter Warning: The transmit error counter has reached the CPU warning limit of 96.
– Receiver Error Passive: The receive error counter has exceeded the error passive limit of 127
and MSCAN08 has gone to error passive state.
– Transmitter Error Passive: The transmit error counter has exceeded the error passive limit of
127 and MSCAN08 has gone to error passive state.
– Bus-off: The transmit error counter has exceeded 255 and MSCAN08 has gone to bus-off state.
23.6.1 Interrupt Acknowledge
Interrupts are directly associated with one or more status flags in either the MSCAN08 receiver flag
register (CRFLG) or the MSCAN08 transmitter control register (CTCR). Interrupts are pending as long as
one of the corresponding flags is set. The flags in the above registers must be reset within the interrupt
handler in order to handshake the interrupt. The flags are reset through writing a 1 to the corresponding
bit position. A flag cannot be cleared if the respective condition still prevails.
NOTE
Bit manipulation instructions (BSET) shall not be used to clear interrupt
flags. The OR instruction is the appropriate way to clear selected flags.
MC68HC908AT32 Data Sheet, Rev. 3.1
258
Freescale Semiconductor
Protocol Violation Protection
23.6.2 Interrupt Vectors
The MSCAN08 supports four interrupt vectors as shown in Table 23-1. The vector addresses are
dependent on the chip integration and are to be defined. The relative interrupt priority is also integration
dependent and is to be defined.
Table 23-1. MSCAN08 Interrupt Vector Addresses
Function
Source
Local
Mask
Wakeup
WUPIF
WUPIE
RWRNIF
RWRNIE
TWRNIF
TWRNIE
RERRIF
RERRIE
TERRIF
TERRIE
BOFFIF
BOFFIE
OVRIF
OVRIE
RXF
RXFIE
TXE0
TXEIE0
TXE1
TXEIE1
TXE2
TXEIE2
Global
Mask
Error interrupts
Receive
Transmit
I bit
23.7 Protocol Violation Protection
The MSCAN08 will protect the user from accidentally violating the CAN protocol through programming
errors. The protection logic implements these features:
• The receive and transmit error counters cannot be written or otherwise manipulated.
• All registers which control the configuration of the MSCAN08 can not be modified while the
MSCAN08 is on-line. The SFTRES bit in the MSCAN08 module control register (see 23.13.1
MSCAN08 Module Control Register) serves as a lock to protect the following registers:
– MSCAN08 module control register 1 (CMCR1)
– MSCAN08 bus timing register 0 and 1 (CBTR0 and CBTR1)
– MSCAN08 identifier acceptance control register (CIDAC)
– MSCAN08 identifier acceptance registers (CIDAR0–CIDAR3)
– MSCAN08 identifier mask registers (CIDMR0–CIDMR3)
• The TxCAN pin is forced to recessive if the CPU goes into stop mode.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
259
MSCAN Controller
23.8 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power stand-by mode.
23.8.1 MSCAN08 Internal Sleep Mode
The CPU can request the MSCAN08 to enter the low-power mode by asserting the SLPRQ bit in the
module configuration register (see Figure 23-6). This causes the MSCAN08 module internal clock to stop
unless the module is active (such as receiving a message). The SLPAK bit indicates whether the
MSCAN08 successfully went into sleep mode. The application software should use this flag as a
handshake indication for the request to go into sleep mode. If not set after the request, the MSCAN08 is
active and has not yet entered sleep mode. No wakeup interrupt will occur in that case.
MSCAN08 RUNNING
SLPRQ = 0
SLPAK = 0
MCU
MCU
OR MSCAN08
MSCAN08 SLEEPING
SLEEP REQUEST
SLPRQ = 1
SLPAK = 1
SLPRQ = 1
SLPAK = 0
MSCAN08
Figure 23-6. Sleep Request/Acknowledge Cycle
When in sleep mode, the MSCAN08 stops its own clocks, leaving the MCU in normal run mode.
The MSCAN08 will leave sleep mode (wakeup) when bus activity occurs or when the MCU clears the
SLPRQ bit.
The TxCAN pin will stay in a recessive state while the MSCAN08 is in internal sleep mode.
NOTE
The MCU cannot clear the SLPRQ bit before the MSCAN08 is in sleep
mode (SLPAK = 1).
MC68HC908AT32 Data Sheet, Rev. 3.1
260
Freescale Semiconductor
Timer Link
23.8.2 CPU Wait Mode
The MSCAN08 module remains active during CPU wait mode. The MSCAN08 will stay synchronized to
the CAN bus and will generate enabled transmit, receive, and error interrupts to the CPU. Any such
interrupt will bring the MCU out of wait mode.
23.8.3 CPU Stop Mode
A CPU STOP instruction will stop the crystal oscillator, thus shutting down all system clocks. The user is
responsible for ensuring that the MSCAN08 is not active when the CPU goes into stop mode. To protect
the CAN bus system from fatal consequences of violations to this rule, the MSCAN08 will drive the TxCAN
pin into a recessive state.
The recommended procedure is to bring the MSCAN08 into sleep mode before the CPU STOP instruction
is executed.
23.8.4 Programmable Wakeup Function
The MSCAN08 can be programmed to apply a low-pass filter function to the RxCAN input line while in
internal sleep mode (see information on control bit WUPM in 23.13.1 MSCAN08 Module Control
Register). This feature can be used to protect the MSCAN08 from wakeup due to short glitches on the
CAN bus lines. Such glitches can result from electromagnetic inference within noisy environments.
23.9 Timer Link
The MSCAN08 will generate a timer signal whenever a valid frame has been received. Because the CAN
specification defines a frame to be valid if no errors occurred before the EOF field has been transmitted
successfully, the timer signal will be generated right after the EOF. A pulse of one bit time is generated.
As the MSCAN08 receiver engine also receives the frames being sent by itself, a timer signal also will be
generated after a successful transmission.
The previously described timer signal can be routed into the on-chip timer interface module (TIM). Under
the control of the timer link enable (TLNKEN) bit in the CMCR0, this signal will be connected to the timer
n channel m input.
NOTE
The timer channel being used for the timer link is integration dependent.
After timer n has been programmed to capture rising edge events, it can be used to generate 16-bit time
stamps which can be stored under software control with the received message.
23.10 Clock System
Figure 23-7 shows the structure of the MSCAN08 clock generation circuitry and its interaction with the
clock generation module (CGM). With this flexible clocking scheme the MSCAN08 is able to handle CAN
bus rates ranging from 10 kbps up to 1 Mbps.
The clock source flag (CLKSRC) in the MSCAN08 module control register (CMCR1) (see 23.13.1
MSCAN08 Module Control Register) defines whether the MSCAN08 is connected to the output of the
crystal oscillator or to the PLL output.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
261
MSCAN Controller
CGMXCLK
÷2
OSC
CGMOUT
(TO SIM)
BCS
PLL
÷2
CGM
MSCAN08
(2 * BUS FREQ.)
÷2
MSCANCLK
PRESCALER
CLKSRC
(1 .. 64)
Figure 23-7. Clocking Scheme
The MSCAN08 clock is used to generate the atomic unit of time handled by the MSCAN08: the time
quantum. A bit time is subdivided into three segments defined here. For further explanation of the
underlying concepts, refer to ISO/DIS 11519-1, Section 10.3.
• SYNC_SEG: This segment has a fixed length of one time quantum. Signal edges are expected to
happen within this section.
• Time segment 1: This segment includes the PROP_SEG and the PHASE_SEG1 of the CAN
standard. It can be programmed by setting the parameter TSEG1 to consist of 4 to 16 time quanta.
• Time segment 2: This segment represents PHASE_SEG2 of the CAN standard. It can be
programmed by setting the TSEG2 parameter to be 2 to 8 time quanta long.
The synchronization jump width (SJW) can be programmed in a range of 1 to 4 time quanta by setting the
SJW parameter.
The parameters can be set by programming the bus timing registers, CBTR0–CBTR1 (see 23.13.3
MSCAN08 Bus Timing Register 0 and 23.13.4 MSCAN08 Bus Timing Register 1).
The user is responsible for making sure that the bit time settings comply with the CAN standard (see
Figure 23-8). Table 23-2 gives an overview on the CAN conforming segment settings and the related
parameter values.
MC68HC908AT32 Data Sheet, Rev. 3.1
262
Freescale Semiconductor
Memory Map
NRZ SIGNAL
SYNC
_SEG
TIME SEGMENT 1
(PROP_SEG + PHASE_SEG1)
TIME SEG. 2
(PHASE_SEG2)
1
4 ... 16
2 ... 8
8... 25 TIME QUANTA
= 1 BIT TIME
SAMPLE POINT
(SINGLE OR TRIPLE SAMPLING)
Figure 23-8. Segments within the Bit Time
Table 23-2. CAN Standard Compliant Bit Time
Segment Settings
Time Segment
1
TSEG1
Time Segment
2
TSEG2
Synchron.
Jump Width
SJW
5 .. 10
4 .. 9
2
1
1 .. 2
0 .. 1
4 .. 11
3 .. 10
3
2
1 .. 3
0 .. 2
5 .. 12
4 .. 11
4
3
1 .. 4
0 .. 3
6 .. 13
5 .. 12
5
4
1 .. 4
0 .. 3
7 .. 14
6 .. 13
6
5
1 .. 4
0 .. 3
8 .. 15
7 .. 14
7
6
1 .. 4
0 .. 3
9 .. 16
8 .. 15
8
7
1 .. 4
0 .. 3
23.11 Memory Map
The MSCAN08 occupies 128 bytes in the CPU08 memory space. The absolute mapping is
implementation dependent with the base address being a multiple of 128. The background receive buffer
can be read only in test mode.
NOTE
Due to design requirements, the absolute addresses and bit locations may
change with later revisions of this specification.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
263
MSCAN Controller
23.12 Programmer’s Model of Message Storage
This section details the organization of the receive and transmit message buffers and the associated
control registers. For reasons of programmer interface simplification, the receive and transmit message
buffers have the same outline. Each message buffer allocates 16 bytes in the memory map containing a
13-byte data structure. An additional transmit buffer priority register (TBPR) is defined for the transmit
buffers.
Addr.
Register Name
$05b0
IDENTIFIER REGISTER 0
$05b1
IDENTIFIER REGISTER 1
$05b2
IDENTIFIER REGISTER 2
$05b3
IDENTIFIER REGISTER 3
$05b4
DATA SEGMENT REGISTER 0
$05b5
DATA SEGMENT REGISTER 1
$05b6
DATA SEGMENT REGISTER 2
$05b7
DATA SEGMENT REGISTER 3
$05b8
DATA SEGMENT REGISTER 4
$05b9
DATA SEGMENT REGISTER 5
$05bA
DATA SEGMENT REGISTER 6
$05bB
DATA SEGMENT REGISTER 7
$05bC
DATA LENGTH REGISTER
$05bD
TRANSMIT BUFFER PRIORITY REGISTER(1)
$05bE
UNUSED
$05bF
UNUSED
1. Not applicable for receive buffers
Figure 23-9. Message Buffer Organization
MC68HC908AT32 Data Sheet, Rev. 3.1
264
Freescale Semiconductor
Programmer’s Model of Message Storage
23.12.1 Message Buffer Outline
Figure 23-10 shows the common 13-byte data structure of receive and transmit buffers for extended
identifiers. The mapping of standard identifiers into the IDR registers is shown in Figure 23-11. All bits of
the 13-byte data structure are undefined out of reset.
Addr.
Register
Bit 7
6
5
4
3
2
1
Bit 0
ID28
ID27
ID26
ID25
ID24
ID23
ID22
ID21
$05b0
IDR0
Read:
Write:
$05b1
IDR1
Read:
Write:
ID20
ID19
ID18
SRR (1)
IDE (1)
ID17
ID16
ID15
$05b2
IDR2
Read:
Write:
ID14
ID13
ID12
ID11
ID10
ID9
ID8
ID7
$05b3
IDR3
Read:
Write:
ID6
ID5
ID4
ID3
ID2
ID1
ID0
RTR
$05b4
DSR0
Read:
Write:
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
$05b5
DSR1
Read:
Write:
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
$05b6
DSR2
Read:
Write:
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
$05b7
DSR3
Read:
Write:
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
$05b8
DSR4
Read:
Write:
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
$05b9
DSR5
Read:
Write:
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
$05bA
DSR6
Read:
Write:
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
$05bB
DSR7
Read:
Write:
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
$05bC
DLR
Read:
Write:
DLC3
DLC2
DLC1
DLC0
= Unimplemented
Figure 23-10. Receive/Transmit Message Buffer Extended Identifier (IDRn)
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
265
MSCAN Controller
Addr.
Register
$05b0
IDR0
$05b1
IDR1
$05b2
IDR2
$05b3
IDR3
Read:
Write:
Read:
Write:
Bit 7
6
5
4
3
2
1
Bit 0
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
RTR
IDE(0)
Read:
Write:
Read:
Write:
= Unimplemented
Figure 23-11. Standard Identifier Mapping
23.12.2 Identifier Registers
The identifiers consist of either 11 bits (ID10–ID0) for the standard or 29 bits (ID28–ID0) for the extended
format. ID10/28 is the most significant bit and is transmitted first on the bus during the arbitration
procedure. The highest priority of an identifier is defined as the smallest binary number.
SRR — Substitute Remote Request Bit
This fixed recessive bit is used only in extended format. It must be set to 1 by the user for transmission
buffers and will be stored as received on the CAN bus for receive buffers.
IDE — ID Extended Flag
This flag indicates whether the extended or standard identifier format is applied in this buffer. In case
of a receive buffer, the flag is set as being received and indicates to the CPU how to process the buffer
identifier registers. In case of a transmit buffer, the flag indicates to the MSCAN08 what type of
identifier to send.
1 = Extended format, 29 bits
0 = Standard format, 11 bits
RTR — Remote Transmission Request Flag
This flag reflects the status of the remote transmission request bit in the CAN frame. In case of a
receive buffer, it indicates the status of the received frame and allows the transmission of an answering
frame in software to be supported. In case of a transmit buffer, this flag defines the setting of the RTR
bit to be sent.
1 = Remote frame
0 = Data frame
MC68HC908AT32 Data Sheet, Rev. 3.1
266
Freescale Semiconductor
Programmer’s Model of Message Storage
23.12.3 Data Length Register
The data length register (DLR) keeps the data length field of the CAN frame.
DLC3–DLC0 — Data Length Code Bits
The data length code contains the number of bytes (data byte count) of the respective message. At
transmission of a remote frame, the data length code is transmitted as programmed while the number
of transmitted bytes is always 0. The data byte count ranges from 0 to 8 for a data frame. Table 23-3
shows the effect of setting the DLC bits.
Table 23-3. Data Length Codes
Data Length Code
DLC3
DLC2
DLC1
DLC0
Data Byte
Count
0
0
0
0
0
0
0
0
1
1
0
0
1
0
2
0
0
1
1
3
0
1
0
0
4
0
1
0
1
5
0
1
1
0
6
0
1
1
1
7
1
0
0
0
8
23.12.4 Data Segment Registers
The eight data segment registers (DSRn) contain the data to be transmitted or received. The number of
bytes to be transmitted
or being received is determined by the data length code in the corresponding DLR.
23.12.5 Transmit Buffer Priority Registers
Address:
Read:
Write:
Reset:
$05bD
Bit 7
6
5
4
3
2
1
Bit 0
PRIO7
PRIO6
PRIO5
PRIO4
PRIO3
PRIO2
PRIO1
PRIO0
0
0
0
0
0
0
0
0
Figure 23-12. Transmit Buffer Priority Register (TBPR)
PRIO7–PRIO0 — Local Priority Field
This field defines the local priority of the associated message buffer. The local priority is used for the
internal prioritization process of the MSCAN08 and is defined to be highest for the smallest binary
number. The MSCAN08 implements the following internal prioritization mechanism:
• All transmission buffers with a cleared TXE flag participate in the priorization right before the SOF
is sent.
• The transmission buffer with the lowest local priority field wins the prioritization.
• In case more than one buffer has the same lowest priority, the message buffer with the lower index
number wins.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
267
MSCAN Controller
NOTE
To ensure data integrity, no registers of the transmit buffers shall be written
while the associated TXE flag is cleared.
To ensure data integrity, no registers of the receive buffer shall be read
while the RXF flag is cleared.
23.13 Programmer’s Model of Control Registers
The programmer’s model has been laid out for maximum simplicity and efficiency. Figure 23-13 gives an
overview on the control register block of the MSCAN08.
Addr.
Register
Bit 7
6
5
4
1
Bit 0
Module Control Read:
$0500 Register 0 (CMCR0) Write:
See page 270. Reset:
0
0
0
SYNCH
SLPRQ
SFTRES
0
0
0
0
0
0
0
1
0
0
0
0
0
LOOPB
WUPM
CLKSRC
0
0
0
0
0
0
0
0
SJW1
SJW0
BRP5
BRP4
BRP3
BRP2
BRP1
BRP0
0
0
0
0
0
0
0
0
SAMP
TSEG22
TSEG21
TSEG20
TSEG13
TSEG12
TSEG11
TSEG10
0
0
0
0
0
0
0
0
WUPIF
RWRNIF
TWRNIF
RERRIF
TERRIF
BOFFIF
OVRIF
RXF
0
0
0
0
0
0
0
0
WUPIE
RWRNIE
TWRNIE
RERRIE
TERRIE
BOFFIE
OVRIE
RXFIE
0
0
0
0
0
0
0
0
0
ABTAK2
ABTAK1
ABTAK0
0
$0506
Transmitter Flag Read:
Register (CTFLG) Write:
See page 276. Reset:
TXE2
TXE1
TXE0
0
0
0
0
1
1
1
0
TXEIE2
TXEIE1
TXEIE0
$0507
Transmitter Control Read:
Register Write:
(CTCR)
See page 277. Reset:
0
0
0
0
Ident. Acceptance Read:
Control Register Write:
(CIDAC)
See page 277. Reset:
0
0
IDHIT1
IDHIT0
Reserved Read:
Module Control Read:
$0501 Register 1 (CMCR1) Write:
See page 271. Reset:
Read:
$0502
$0503
$0504
$0505
$0508
$0509
Bus Timing Register
0 (CBTR0) Write:
See page 272. Reset:
Bus Timing Register Read:
1 (CBTR1) Write:
See page 273. Reset:
Receiver Flag Read:
Register (CRFLG) Write:
See page 274. Reset:
Receiver Interrupt Read:
Enable Register Write:
(CRIER)
See page 275. Reset:
3
TLNKEN
0
0
2
SLPAK
ABTRQ2
ABTRQ1
ABTRQ0
0
0
0
0
0
0
IDAM1
IDAM0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
= Reserved
= Unimplemented
Figure 23-13. MSCAN08 Control Register Structure (Sheet 1 of 2)
MC68HC908AT32 Data Sheet, Rev. 3.1
268
Freescale Semiconductor
Programmer’s Model of Control Registers
Addr.
Register
Bit 7
6
5
4
3
2
1
Bit 0
RXERR7
RXERR6
RXERR5
RXERR4
RXERR3
RXERR2
RXERR1
RXERR0
$050E
Receiver Error Read:
Counter Write:
(CRXERR)
See page 278. Reset:
0
0
0
0
0
0
0
0
Transmit Error Read:
Counter Write:
(CTXERR)
See page 278. Reset:
TXERR7
TXERR6
TXERR5
TXERR4
TXERR3
TXERR2
TXERR1
TXERR0
0
0
0
0
0
0
0
0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
AC2
AC1
AC0
AC2
AC1
AC0
AC2
AC1
AC0
AM2
AM1
AM0
AM2
AM1
AM0
AM2
AM1
AM0
AM2
AM1
AM0
$050F
Ident. Acceptance Read:
$0510 Register 0 (CIDAR0) Write:
See page 279. Reset:
Ident. Acceptance Read:
$0511 Register 1 (CIDAR1) Write:
See page 279. Reset:
Ident. Acceptance Read:
$0512 Register 2 (CIDAR2) Write:
See page 279. Reset:
Ident. Acceptance Read:
$0513 Register 3 (CIDAR3) Write:
See page 279. Reset:
$0514
$0515
$0516
$0517
Identifier Mask Read:
Register 0 Write:
(CIDMR0)
See page 280. Reset:
Identifier Mask Read:
Register 1 Write:
(CIDMR1)
See page 280. Reset:
Identifier Mask Read:
Register 2 Write:
(CIDMR2)
See page 280. Reset:
Identifier Mask Read:
Register 3 Write:
(CIDMR3)
See page 280. Reset:
Unaffected by reset
AC7
AC6
AC5
AC4
AC3
Unaffected by reset
AC7
AC6
AC5
AC4
AC3
Unaffected by reset
AC7
AC6
AC5
AC4
AC3
Unaffected by reset
AM7
AM6
AM5
AM4
AM3
Unaffected by reset
AM7
AM6
AM5
AM4
AM3
Unaffected by reset
AM7
AM6
AM5
AM4
AM3
Unaffected by reset
AM7
AM6
AM5
AM4
AM3
Unaffected by reset
= Unimplemented
R
= Reserved
Figure 23-13. MSCAN08 Control Register Structure (Sheet 2 of 2)
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
269
MSCAN Controller
23.13.1 MSCAN08 Module Control Register
Address:
Read:
$0500
Bit 7
6
5
4
0
0
0
SYNCH
0
0
0
0
Write:
Reset:
3
TLNKEN
2
SLPAK
0
0
1
Bit 0
SLPRQ
SFTRES
0
1
= Unimplemented
Figure 23-14. Module Control Register 0 (CMCR0)
SYNCH — Synchronized Status Bit
This bit indicates whether the MSCAN08 is synchronized to the CAN bus and as such can participate
in the communication process.
1 = MSCAN08 synchronized to the CAN bus
0 = MSCAN08 not synchronized to the CAN bus
TLNKEN — Timer Enable Flag
This flag is used to establish a link between the MSCAN08 and the on-chip timer (see 23.9 Timer Link).
1 = The MSCAN08 timer signal output is connected to the timer.
0 = No connection
SLPAK — Sleep Mode Acknowledge Flag
This flag indicates whether the MSCAN08 is in module internal sleep mode. It shall be used as a
handshake for the sleep mode request (see 23.8.1 MSCAN08 Internal Sleep Mode).
1 = Sleep — MSCAN08 in internal sleep mode
0 = Wakeup — MSCAN08 will function normally
SLPRQ — Sleep Request, Go to Internal Sleep Mode Flag
This flag allows a request for the MSCAN08 to go into an internal power-saving mode (see 23.8.1
MSCAN08 Internal Sleep Mode).
1 = Sleep — The MSCAN08 will go into internal sleep mode if and as long as there is no activity on
the bus.
0 = Wakeup — The MSCAN08 will function normally. If SLPAK is cleared by the CPU, then the
MSCAN08 will wake up, but will not issue a wakeup interrupt.
SFTRES — Soft Reset Bit
When this bit is set by the CPU, the MSCAN08 immediately enters the soft reset state. Any ongoing
transmission or reception is aborted and synchronization to the bus is lost.
These registers will go into the same state as out of hard reset: CMCR0, CRFLG, CRIER, CTFLG, and
CTCR.
The registers CMCR1, CBTR0, CBTR1, CIDAC, CIDAR0–CIDAR3, and CIDMR0–CIDMR3 can only
be written by the CPU when the MSCAN08 is in soft reset state. The values of the error counters are
not affected by soft reset.
When this bit is cleared by the CPU, the MSCAN08 will try to synchronize to the CAN bus. If the
MSCAN08 is not in bus-off state, it will be synchronized after 11 recessive bits on the bus; if the
MSCAN08 is in bus-off state, it continues to wait for 128 occurrences of 11 recessive bits.
1 = MSCAN08 in soft reset state
0 = Normal operation
MC68HC908AT32 Data Sheet, Rev. 3.1
270
Freescale Semiconductor
Programmer’s Model of Control Registers
23.13.2 MSCAN08 Module Control Register 1
Address:
Read:
$0501
Bit 7
6
5
4
3
0
0
0
0
0
2
1
Bit 0
LOOPB
WUPM
CLKSRC
0
0
0
Write:
Reset:
0
0
0
0
0
= Unimplemented
Figure 23-15. Module Control Register 1 (CMCR1)
LOOPB — Loopback Self-Test Mode Bit
When this bit is set, the MSCAN08 performs an internal loopback which can be used for self-test
operation and the bit stream output of the transmitter is fed back to the receiver. The RxCAN input pin
is ignored and the TxCAN output goes to the recessive state (1). Note that in this state, the MSCAN08
ignores the ACK bit to ensure proper reception of its own message and will treat messages being
received while in transmission as received messages from remote nodes.
1 = Activate loopback self-test mode
0 = Normal operation
WUPM — Wakeup Mode Flag
This flag defines whether the integrated low-pass filter is applied to protect the MSCAN08 from
spurious wakeups (see 23.8.4 Programmable Wakeup Function).
1 = MSCAN08 will wake up the CPU only in cases of a dominant pulse on the bus which has a
length of at least twup.
0 = MSCAN08 will wake up the CPU after any recessive to dominant edge on the CAN bus.
CLKSRC — Clock Source Flag
This flag defines which clock source the MSCAN08 module is driven from (see 23.10 Clock System).
1 = The MSCAN08 clock source is CGMOUT (see Figure 23-7).
0 = The MSCAN08 clock source is CGMXCLK/2 (see Figure 23-7).
NOTE
The CMCR1 register can be written only if the SFTRES bit in the MSCAN08
module control register is set.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
271
MSCAN Controller
23.13.3 MSCAN08 Bus Timing Register 0
Address:
Read:
Write:
Reset:
$0502
Bit 7
6
5
4
3
2
1
Bit 0
SJW1
SJW0
BRP5
BRP4
BRP3
BRP2
BRP1
BRP0
0
0
0
0
0
0
0
0
Figure 23-16. Bus Timing Register 0 (CBTR0)
SJW1 and SJW0 — Synchronization Jump Width Bit
The synchronization jump width (SJW) defines the maximum number of system clock (tSCL) cycles by
which a bit may be shortened, or lengthened, to achieve resynchronization on data transitions on the
bus (see Table 23-4).
Table 23-4. Synchronization Jump Width
SJW1
SJW0
Synchronization Jump Width
0
0
1 tSCL cycle
0
1
2 tSCL cycles
1
0
3 tSCL cycles
1
1
4 tSCL cycles
BRP5–BRP0 — Baud Rate Prescaler Bits
These bits determine the MSCAN08 system clock cycle time (tSCL), which is used to build up the
individual bit timing, according to Table 23-5.
Table 23-5. Baud Rate Prescaler
BRP5
BRP4
BRP3
BRP2
BRP1
BRP0
Prescaler Value (P)
0
0
0
0
0
0
1
0
0
0
0
0
1
2
0
0
0
0
1
0
3
0
0
0
0
1
1
4
:
:
:
:
:
:
:
:
:
:
:
:
:
:
1
1
1
1
1
1
64
NOTE
The CBTR0 register can be written only if the SFTRES bit in the MSCAN08
module control register is set.
MC68HC908AT32 Data Sheet, Rev. 3.1
272
Freescale Semiconductor
Programmer’s Model of Control Registers
23.13.4 MSCAN08 Bus Timing Register 1
Address:
$0503
Read:
Write:
Bit 7
6
5
4
3
2
1
Bit 0
SAMP
TSEG22
TSEG21
TSEG20
TSEG13
TSEG12
TSEG11
TSEG10
0
0
0
0
0
0
0
0
Reset:
Figure 23-17. Bus Timing Register 1 (CBTR1)
SAMP — Sampling Bit
This bit determines the number of serial bus samples to be taken per bit time. If set, three samples per
bit are taken, the regular one (sample point) and two preceding samples, using a majority rule. For
higher bit rates, SAMP should be cleared, which means that only one sample will be taken per bit.
1 = Three samples per bit
0 = One sample per bit
TSEG22–TSEG10 — Time Segment Bits
Time segments within the bit time fix the number of clock cycles per bit time and the location of the
sample point.
Table 23-6. Time Segment Syntax
Time Segment
Action
System expects transitions to occur on the bus during this
period.
SYNC_SEG
Transmit point
A node in transmit mode will transfer a new value to the CAN
bus at this point.
Sample point
A node in receive mode will sample the bus at this point. If the
three samples per bit option is selected then this point
marks the position of the third sample.
Time segment 1 (TSEG1) and time segment 2 (TSEG2) are programmable as shown in Table 23-7.
Table 23-7. Time Segment Values
TSEG13
TSEG12
TSEG11
TSEG10
0
0
0
0
Time
Segment 1
1 tSCL cycle
TSEG22
TSEG21
TSEG20
0
0
0
Time
Segment 2
1 tSCL cycle
0
0
1
2 tSCL cycles
.
0
0
0
1
2 tSCL cycles
0
0
1
0
3 tSCL cycles
.
.
.
0
0
1
1
4 tSCL cycles
.
.
.
.
1
8 tSCL cycles
.
.
.
.
.
.
.
.
.
.
1
1
1
1
16 tSCL cycles
1
1
The bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of bus
clock cycles (tSCL) per bit as shown in Table 23-7.
NOTE
The CBTR1 register can be written only if the SFTRES bit in the MSCAN08
module control register is set.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
273
MSCAN Controller
23.13.5 MSCAN08 Receiver Flag Register
All bits of this register are read and clear only. A flag can be cleared by writing a 1 to the corresponding
bit position. A flag can be cleared only when the condition which caused the setting is valid no more.
Writing a 0 has no effect on the flag setting. Every flag has an associated interrupt enable flag in the
CRIER register. A hard or soft reset will clear the register.
Address:
Read:
Write:
Reset:
$0504
Bit 7
6
5
4
3
2
1
Bit 0
WUPIF
RWRNIF
TWRNIF
RERRIF
TERRIF
BOFFIF
OVRIF
RXF
0
0
0
0
0
0
0
0
Figure 23-18. Receiver Flag Register (CRFLG)
WUPIF — Wakeup Interrupt Flag
If the MSCAN08 detects bus activity while it is asleep, it clears the SLPAKSLPAK bit in the CMCR0
register; the WUPIF bit will then be set. If not masked, a wakeup interrupt is pending while this flag is
set.
1 = MSCAN08 has detected activity on the bus and requested wakeup.
0 = No wakeup interrupt has occurred.
RWRNIF — Receiver Warning Interrupt Flag
This bit will be set when the MSCAN08 went into warning status because the receive error counter was
in the range of 96 to 127. If not masked, an error interrupt is pending while this flag is set.
1 = MSCAN08 went into warning status.
0 = No warning interrupt has occurred.
TWRNIF — Transmitter Warning Interrupt Flag
This bit will be set when the MSCAN08 went into warning status because the transmit error counter
was in the range of 96 to 127. If not masked, an error interrupt is pending while this flag is set.
1 = MSCAN08 went into warning status.
0 = No warning interrupt has occurred.
RERRIF — Receiver Error Passive Interrupt Flag
This bit will be set when the MSCAN08 went into error passive status because the receive error counter
exceeded 127. If not masked, an error interrupt is pending while this flag is set.
1 = MSCAN08 went into error passive status.
0 = No warning interrupt has occurred.
TERRIF — Transmitter Error Passive Interrupt Flag
This bit will be set when the MSCAN08 went into error passive status due to the transmit error counter
exceeded 127. If not masked, an error interrupt is pending while this flag is set.
1 = MSCAN08 went into error passive status.
0 = No warning interrupt has occurred.
BOFFIF — Bus-Off Interrupt Flag
This bit will be set when the MSCAN08 went into bus-off status, because the transmit error counter
exceeded 255. If not masked, an Error interrupt is pending while this flag is set.
1 = MSCAN08 went into warning status.
0 = No warning interrupt has occurred.
MC68HC908AT32 Data Sheet, Rev. 3.1
274
Freescale Semiconductor
Programmer’s Model of Control Registers
OVRIF — Overrun Interrupt Flag
This bit will be set when a data overrun condition occurred. If not masked, an error interrupt is pending
while this flag is set.
1 = A data overrun has been detected.
0 = No data overrun has occurred.
RXF — Receive Buffer Full Flag
The RXF flag is set by the MSCAN08 when a new message is available in the foreground receive
buffer. This flag indicates whether the buffer is loaded with a correctly received message. After the
CPU has read that message from the receive buffer the RXF flag must be handshaked to release the
buffer. A set RXF flag prohibits the exchange of the background receive buffer into the foreground
buffer. In that case the MSCAN08 will signal an overload condition. If not masked, a receive interrupt
is pending while this flag is set.
1 = The receive buffer is full. A new message is available.
0 = The receive buffer is released (not full).
23.13.6 MSCAN08 Receiver Interrupt Enable Register
Address:
$0505
Bit 7
6
5
4
3
2
1
Bit 0
WUPIE
RWRNIE
TWRNIE
RERRIE
TERRIE
BOFFIE
OVRIE
RXFIE
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 23-19. Receiver Interrupt Enable Register (CRIER)
WUPIE — Wakeup Interrupt Enable Bit
1 = A wakeup event will result in a wakeup interrupt.
0 = No interrupt will be generated from this event.
RWRNIE — Receiver Warning Interrupt Enable Bit
1 = A receiver warning status event will result in an error interrupt.
0 = No interrupt will be generated from this event.
TWRNIE — Transmitter Warning Interrupt Enable Bit
1 = A transmitter warning status event will result in an error interrupt.
0 = No interrupt will be generated from this event.
RERRIE — Receiver Error Passive Interrupt Enable Bit
1 = A receiver error passive status event will result in an error interrupt.
0 = No interrupt will be generated from this event.
TERRIE — Transmitter Error Passive Interrupt Enable Bit
1 = A transmitter error passive status event will result in an error interrupt.
0 = No interrupt will be generated from this event.
BOFFIE — Bus-Off Interrupt Enable Bit
1 = A bus-off event will result in an error interrupt.
0 = No interrupt will be generated from this event.
OVRIE — Overrun Interrupt Enable Bit
1 = An overrun event will result in an error interrupt.
0 = No interrupt will be generated from this event.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
275
MSCAN Controller
RXFIE — Receiver Full Interrupt Enable Bit
1 = A receive buffer full (successful message reception) event will result in a receive interrupt.
0 = No interrupt will be generated from this event.
23.13.7 MSCAN08 Transmitter Flag Register
All bits of this register are read and clear only. A flag can be cleared by writing a 1 to the corresponding
bit position. Writing a 0 has no effect on the flag setting. Every flag has an associated interrupt enable flag
in the CTCR register. A hard or soft reset will clear the register.
Address:
Read:
$0506
Bit 7
6
5
4
3
0
ABTAK2
ABTAK1
ABTAK0
0
0
0
0
0
0
Write:
Reset:
2
1
Bit 0
TXE2
TXE1
TXE0
1
1
1
= Unimplemented
Figure 23-20. Transmitter Flag Register (CTFLG)
ABTAK2–ABTAK0 — Abort Acknowledge Flags
This flag acknowledges that a message has been aborted due to a pending abort request from the
CPU. After a particular message buffer has been flagged empty, this flag can be used by the
application software to identify whether the message has been aborted successfully or has been sent.
The flag is reset implicitly whenever the associated TXE flag is set to 0.
1 = The message has been aborted.
0 = The message has not been aborted, thus has been sent out.
TXE2–TXE0 — Transmitter Empty Flags
This flag indicates that the associated transmit message buffer is empty, thus not scheduled for
transmission. The CPU must handshake (clear) the flag after a message has been set up in the
transmit buffer and is due for transmission. The MSCAN08 will set the flag after the message has been
sent successfully. The flag also will be set by the MSCAN08 when the transmission request was
successfully aborted due to a pending abort request (see 23.12.5 Transmit Buffer Priority Registers).
If not masked, a receive interrupt is pending while this flag is set.
A reset of this flag also will reset the abort acknowledge (ABTAK) and the abort request (ABTRQ, (see
23.13.8 MSCAN08 Transmitter Control Register) flags of the particular buffer.
1 = The associated message buffer is empty (not scheduled).
0 = The associated message buffer is full (loaded with a message due for transmission).
MC68HC908AT32 Data Sheet, Rev. 3.1
276
Freescale Semiconductor
Programmer’s Model of Control Registers
23.13.8 MSCAN08 Transmitter Control Register
Address:
$0507
Bit 7
Read:
0
Write:
Reset:
0
6
5
4
3
ABTRQ2
ABTRQ1
ABTRQ0
0
0
0
0
2
1
Bit 0
TXEIE2
TXEIE1
TXEIE0
0
0
0
0
= Unimplemented
Figure 23-21. Transmitter Control Register (CTCR)
ABTRQ2–ABTRQ0 — Abort Request Flag
The CPU sets this flag to request that an already scheduled message buffer (TXE = 0) be aborted. The
MSCAN08 will grant the request when the message is not already under transmission. When a
message is aborted, the associated TXE and the abort acknowledge flag (ABTAK) (see 23.13.7
MSCAN08 Transmitter Flag Register) will be set and an TXE interrupt will occur if enabled. The CPU
cannot reset this flag. The flag is reset implicitely whenever the associated TXE flag is set.
1 = Abort request pending
0 = No abort request
TXEIE2–TXEIE0 — Transmitter Empty Interrupt Enable Bits
1 = A transmitter empty (transmit buffer available for transmission) event will result in a transmitter
empty interrupt.
0 = No interrupt will be generated from this event.
23.13.9 MSCAN08 Identifier Acceptance Control Register
Address:
Read:
$0508
Bit 7
6
0
0
Write:
Reset:
0
5
4
IDAM1
IDAM0
0
0
0
3
2
1
Bit 0
0
0
IDHIT1
IDHIT0
0
0
0
0
= Unimplemented
Figure 23-22. Identifier Acceptance Control Register (CIDAC)
IDAM1–IDAM0— Identifier Acceptance Mode Flags
The CPU sets these flags to define the identifier acceptance filter organization (see 23.5 Identifier
Acceptance Filter). Table 23-8 summarizes the different settings. In “filter closed” mode no messages
will be accepted so that the foreground buffer will never be reloaded.
Table 23-8. Identifier Acceptance Mode Settings
IDAM1
IDAM0
Identifier Acceptance Mode
0
0
Single 32-bit acceptance filter
0
1
Two 16-bit acceptance filter
1
0
Four 8-bit acceptance filters
1
1
Filter closed
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
277
MSCAN Controller
IDHIT1–IDHIT0— Identifier Acceptance Hit Indicator Flags
The MSCAN08 sets these flags to indicate an identifier acceptance hit (see 23.5 Identifier Acceptance
Filter). Table 23-7 summarizes the different settings.
Table 23-9. Identifier Acceptance Hit Indication
IDHIT1
IDHIT0
Identifier Acceptance Hit
0
0
Filter 0 hit
0
1
Filter 1 hit
1
0
Filter 2 hit
1
1
Filter 3 hit
The IDHIT indicators are always related to the message in the foreground buffer. When a message gets
copied from the background to the foreground buffer, the indicators are updated as well.
NOTE
The CIDAC register can be written only if the SFTRES bit in the MSCAN08
module control register is set.
23.13.10 MSCAN08 Receive Error Counter
Address:
Read:
$050E
Bit 7
6
5
4
3
2
1
Bit 0
RXERR7
RXERR6
RXERR5
RXERR4
RXERR3
RXERR2
RXERR1
RXERR0
0
0
0
0
0
0
0
0
Write:
Reset:
= Unimplemented
Figure 23-23. Receiver Error Counter (CRXERR)
This register reflects the status of the MSCAN08 receive error counter. The register is read only.
23.13.11 MSCAN08 Transmit Error Counter
Address:
Read:
$050F
Bit 7
6
5
4
3
2
1
Bit 0
TXERR7
TXERR6
TXERR5
TXERR4
TXERR3
TXERR2
TXERR1
TXERR0
0
0
0
0
0
0
0
0
Write:
Reset:
= Unimplemented
Figure 23-24. Transmit Error Counter (CTXERR)
This register reflects the status of the MSCAN08 transmit error counter. The register is read only.
NOTE
For both error counters, there is no hardware synchronization between the
write accesses to those registers from the MSCAN08 side and the read
accesses by the CPU. It is the user’s responsibility to verify that a stable
value has been read by executing a second validation read and comparing
the two values.
MC68HC908AT32 Data Sheet, Rev. 3.1
278
Freescale Semiconductor
Programmer’s Model of Control Registers
23.13.12 MSCAN08 Identifier Acceptance Registers
On reception each message is written into the background receive buffer. The CPU is only signalled to
read the message, however, if it passes the criteria in the identifier acceptance and identifier mask
registers (accepted). Otherwise, the message will be overwritten by the next message (dropped).
The acceptance registers of the MSCAN08 are applied on the IDR0 to IDR3 registers of incoming
messages in a bit by bit manner.
For extended identifiers, all four acceptance and mask registers are applied. For standard identifiers only
the first two (IDAR0 and IDAR1) are applied. In the latter case, the mask register, CIDMR1, the three last
bits (AC2–AC0) must be programmed to don’t care.
Register Name and Address: CIDAR0 — $0510
Read:
Write:
Bit 7
6
5
4
3
2
1
Bit 0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
Reset:
Unaffected by reset
Register Name and Address: CIDAR1 — $0511
Read:
Write:
Bit 7
6
5
4
3
2
1
Bit 0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
Reset:
Unaffected by reset
Register Name and Address: CIDAR2 — $0512
Read:
Write:
Bit 7
6
5
4
3
2
1
Bit 0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
Reset:
Unaffected by reset
Register Name and Address: CIDAR3 — $0513
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
Unaffected by reset
Figure 23-25. Identifier Acceptance Registers
(CIDAR0–CIDAR3)
AC7–AC0 — Acceptance Code Bits
AC7–AC0 comprise a user-defined sequence of bits with which the corresponding bits of the related
identifier register (IDRn) of the receive message buffer are compared. The result of this comparison is
then masked with the corresponding identifier mask register.
NOTE
The CIDAR0–CIDAR3 registers can be written only if the SFTRES bit in the
MSCAN08 module control register is set
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
279
MSCAN Controller
23.13.13 MSCAN08 Identifier Mask Registers
The identifier mask registers specify which of the corresponding bits in the identifier acceptance register
are relevant for acceptance filtering.
Register Name and Address: CIDMR0 — $0514
Read:
Write:
Bit 7
6
5
4
3
2
1
Bit 0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
Reset:
Unaffected by reset
Register Name and Address: CIDMR1 — $0515
Read:
Write:
Bit 7
6
5
4
3
2
1
Bit 0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
Reset:
Unaffected by reset
Register Name and Address: CIDMR2 — $0516
Read:
Write:
Bit 7
6
5
4
3
2
1
Bit 0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
Reset:
Unaffected by reset
Register Name and Address: CIDMR3 — $0517
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
Unaffected by reset
Figure 23-26. Identifier Mask Registers
(CIDMR0–CIDMR3)
AM7–AM0 — Acceptance Mask Bits
If a particular bit in this register is cleared, this indicates that the corresponding bit in the identifier
acceptance register must be the same as its identifier bit before a match will be detected. The message
will be accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit
in the identifier acceptance register will not affect whether the message is accepted.
1 = Ignore corresponding acceptance code register bit.
0 = Match corresponding acceptance code register and identifier bits.
NOTE
The CIDMR0–CIDMR3 registers can be written only if the SFTRES bit in
the MSCAN08 module control register is set.
MC68HC908AT32 Data Sheet, Rev. 3.1
280
Freescale Semiconductor
Chapter 24
Keyboard Interrupt Module (KBD)
NOTE
This keyboard module is for the MC68HC08AZ32 emulator only.
24.1 Introduction
The keyboard interrupt module (KBD) provides five independently maskable external interrupt pins.
24.2 Features
KBD features include:
• Five keyboard interrupt pins with separate keyboard interrupt enable bits and one keyboard
interrupt mask
• Hysteresis buffers
• Programmable edge-only or edge- and level- interrupt sensitivity
• Automatic interrupt acknowledge
• Exit from low-power modes
24.3 Functional Description
Writing to the KBIE4–KBIE0 bits in the keyboard interrupt enable register independently enables or
disables each port G or port H pin as a keyboard interrupt pin. Enabling a keyboard interrupt pin also
enables its internal pullup device. A logic 0 applied to an enabled keyboard interrupt pin latches a
keyboard interrupt request.
A keyboard interrupt is latched when one or more keyboard pins goes low after all were high. The MODEK
bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt.
• If the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard pin does not latch an
interrupt request if another keyboard pin is already low. To prevent losing an interrupt request on
one pin because another pin is still low, software can disable the latter pin while it is low.
• If the keyboard interrupt is falling edge- and low level-sensitive, an interrupt request is present as
long as any keyboard pin is low.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
281
Keyboard Interrupt Module (KBD)
282
INTERNAL BUS
KBD0
ACKK
VDD
VECTOR FETCH
DECODER
KEYF
RESET
.
TO PULLUP ENABLE
D
CLR
Q
SYNCHRONIZER
.
CK
KB0IE
.
MC68HC908AT32 Data Sheet, Rev. 3.1
KEYBOARD
INTERRUPT FF
KBD7
KEYBOARD
INTERRUPT
REQUEST
IMASKK
MODEK
TO PULLUP ENABLE
KB7IE
Figure 24-1. Keyboard Module Block Diagram
Address
$001A
Freescale Semiconductor
$001B
Register Name
Bit 7
6
5
4
3
2
Read:
Keyboard Status and Control Register
(KBSCR) Write:
See page 285.
Reset:
0
0
0
0
KEYF
0
0
0
0
Read:
Keyboard Interrupt Enable Register
(KBIER) Write:
See page 285.
Reset:
0
0
0
1
Bit 0
IMASKK
MODEK
ACKK
0
0
0
0
0
0
0
0
KBIE4
KBIE3
KBIE2
KBIE1
KBIE0
0
0
0
0
0
= Unimplemented
Figure 24-2. I/O Register Summary
Keyboard Initialization
If the MODEK bit is set, the keyboard interrupt pins are both falling edge- and low level-sensitive, and both
of these actions must occur to clear a keyboard interrupt request:
• Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear
the interrupt request. Software may generate the interrupt acknowledge signal by writing a logic 1
to the ACKK bit in the keyboard status and control register (KBSCR). The ACKK bit is useful in
applications that poll the keyboard interrupt pins and require software to clear the keyboard
interrupt request. Writing to the ACKK bit prior to leaving an interrupt service routine also can
prevent spurious interrupts due to noise. Setting ACKK does not affect subsequent transitions on
the keyboard interrupt pins. A falling edge that occurs after writing to the ACKK bit latches another
interrupt request. If the keyboard interrupt mask bit, IMASKK, is clear, the CPU loads the program
counter with the vector address at locations $FFDE and $FFDF.
• Return of all enabled keyboard interrupt pins to logic 1 — As long as any enabled keyboard
interrupt pin is at logic 0, the keyboard interrupt remains set.
The vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur
in any order.
If the MODEK bit is clear, the keyboard interrupt pin is falling edge-sensitive only. With MODEK clear, a
vector fetch or software clear immediately clears the keyboard interrupt request.
Reset clears the keyboard interrupt request and the MODEK bit, clearing the interrupt request even if a
keyboard interrupt pin stays at logic 0.
The keyboard flag bit (KEYF) in the keyboard status and control register can be used to see if a pending
interrupt exists. The KEYF bit is not affected by the keyboard interrupt mask bit (IMASKK) which makes
it useful in applications where polling is preferred.
To determine the logic level on a keyboard interrupt pin, use the data direction register to configure the
pin as an input and read the data register.
NOTE
Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding
keyboard interrupt pin to be an input, overriding the data direction register.
However, the data direction register bit must be a logic 0 for software to
read the pin.
24.4 Keyboard Initialization
When a keyboard interrupt pin is enabled, it takes time for the internal pullup to reach a logic 1. Therefore,
a false interrupt can occur as soon as the pin is enabled.
To prevent a false interrupt on keyboard initialization:
1. Mask keyboard interrupts by setting the IMASKK bit in the keyboard status and control register
2. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register
3. Write to the ACKK bit in the keyboard status and control register to clear any false interrupts
4. Clear the IMASKK bit.
An interrupt signal on an edge-triggered pin can be acknowledged immediately after enabling the pin. An
interrupt signal on an edge- and level-triggered interrupt pin must be acknowledged after a delay that
depends on the external load.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
283
Keyboard Interrupt Module (KBD)
Another way to avoid a false interrupt:
1. Configure the keyboard pins as outputs by setting the appropriate DDRG bits in data direction
register G.
2. Configure the keyboard pins as outputs by setting the appropriate DDRH bits in data direction
register H.
3. Write logic 1s to the appropriate port G and port H data register bits.
4. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register.
24.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power standby modes.
24.5.1 Wait Mode
The keyboard module remains active in wait mode. Clearing the IMASKK bit in the keyboard status and
control register enables keyboard interrupt requests to bring the MCU out of wait mode.
24.5.2 Stop Mode
The keyboard module remains active in stop mode. Clearing the IMASKK bit in the keyboard status and
control register enables keyboard interrupt requests to bring the MCU out of stop mode.
24.6 Keyboard Module during Break Interrupts
The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the
break state. See Chapter 11 Break Module (BRK).
To allow software to clear the KEYF bit during a break interrupt, write a logic 1 to the BCFE bit. If KEYF
is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect the KEYF bit during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0, writing
to the keyboard acknowledge bit (ACKK) in the keyboard status and control register during the break state
has no effect. See 24.7.1 Keyboard Status and Control Register.
24.7 I/O Registers
Two registers control and monitor operation of the keyboard module:
• Keyboard status and control register (KBSCR)
• Keyboard interrupt enable register (KBIER)
24.7.1 Keyboard Status and Control Register
The keyboard status and control register:
• Flags keyboard interrupt requests
• Acknowledges keyboard interrupt requests
• Masks keyboard interrupt requests
• Controls keyboard interrupt triggering sensitivity
MC68HC908AT32 Data Sheet, Rev. 3.1
284
Freescale Semiconductor
I/O Registers
Address: $001B
Read:
Bit 7
6
5
4
3
2
0
0
0
0
KEYF
0
Write:
Reset:
ACKK
0
0
0
0
0
0
1
Bit 0
IMASKK
MODEK
0
0
= Unimplemented
Figure 24-3. Keyboard Status and Control Register (KBSCR)
Bits 7–4 — Not used
These read-only bits always read as logic 0s.
KEYF — Keyboard Flag Bit
This read-only bit is set when a keyboard interrupt is pending. Reset clears the KEYF bit.
1 = Keyboard interrupt pending
0 = No keyboard interrupt pending
ACKK — Keyboard Acknowledge Bit
Writing a logic 1 to this write-only bit clears the keyboard interrupt request. ACKK always reads as logic
0. Reset clears ACKK.
IMASKK — Keyboard Interrupt Mask Bit
Writing a logic 1 to this read/write bit prevents the output of the keyboard interrupt mask from
generating interrupt requests. Reset clears the IMASKK bit.
1 = Keyboard interrupt requests masked
0 = Keyboard interrupt requests not masked
MODEK — Keyboard Triggering Sensitivity Bit
This read/write bit controls the triggering sensitivity of the keyboard interrupt pins. Reset clears
MODEK.
1 = Keyboard interrupt requests on falling edges and low levels
0 = Keyboard interrupt requests on falling edges only
24.7.2 Keyboard Interrupt Enable Register
The keyboard interrupt enable register enables or disables each port G and each port H pin to operate as
a keyboard interrupt pin.
Address: $0021
Read:
Bit 7
6
5
0
0
0
0
0
0
Write:
Reset:
4
3
2
1
Bit 0
KBIE4
KBIE3
KBIE2
KBIE1
KBIE0
0
0
0
0
0
= Unimplemented
Figure 24-4. Keyboard Interrupt Enable Register (KBIER)
KBIE4–KBIE0 — Keyboard Interrupt Enable Bits
Each of these read/write bits enables the corresponding keyboard interrupt pin to latch interrupt
requests. Reset clears the keyboard interrupt enable register.
1 = PDx pin enabled as keyboard interrupt pin
0 = PDx pin not enabled as keyboard interrupt pin
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
285
Keyboard Interrupt Module (KBD)
MC68HC908AT32 Data Sheet, Rev. 3.1
286
Freescale Semiconductor
Chapter 25
Timer Interface (TIM-6)
NOTE
This timer is for the J1850 (52-pin PLCC) protocol only.
25.1 Introduction
This section describes the timer interface module (TIMA). The TIMA is a 6-channel timer that provides a
timing reference with input capture, output compare, and pulse-width modulation functions. Figure 25-1
is a block diagram of the TIMA.
25.2 Features
Features of the TIMA include:
• Six input capture/output compare channels:
– Rising-edge, falling-edge, or any-edge input capture trigger
– Set, clear, or toggle output compare action
• Buffered and unbuffered pulse-width modulation (PWM) signal generation
• Programmable TIMA clock input:
– 7-frequency internal bus clock prescaler selection
– External TIMA clock input (4-MHz maximum frequency)
• Free-running or modulo up-counter operation
• Toggle any channel pin on overflow
• TIMA counter stop and reset bits
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
287
Timer Interface (TIM-6)
TCLK
PTD6/ATD14/TACLK
PRESCALER SELECT
INTERNAL
BUS CLOCK
PRESCALER
TSTOP
PS2
TRST
PS1
PS0
16-BIT COUNTER
TOF
TOIE
INTERRUPT
LOGIC
16-BIT COMPARATOR
TMODH:TMODL
CHANNEL 0
ELS0B
ELS0A
TOV0
CH0MAX
16-BIT COMPARATOR
TCH0H:TCH0L
CH0F
16-BIT LATCH
MS0A
CHANNEL 1
ELS1B
MS0B
ELS1A
TOV1
CH1MAX
16-BIT COMPARATOR
TCH1H:TCH1L
CH0IE
CH1F
16-BIT LATCH
CH1IE
MS1A
CHANNEL 2
ELS2B
ELS2A
TOV2
CH2MAX
16-BIT COMPARATOR
TCH2H:TCH2L
CH2F
16-BIT LATCH
MS2A
CHANNEL 3
ELS3B
MS2B
ELS3A
TOV3
CH3MAX
16-BIT COMPARATOR
TCH3H:TCH3L
CH2IE
CH3F
16-BIT LATCH
CH3IE
MS3A
CHANNEL 4
ELS4B
ELS4A
TOV4
CH5MAX
16-BIT COMPARATOR
TCH4H:TCH4L
CH4F
16-BIT LATCH
MS4A
CHANNEL 5
ELS5B
MS4B
ELS5A
TOV5
CH5MAX
16-BIT COMPARATOR
TCH5H:TCH5L
CH4IE
CH5F
16-BIT LATCH
MS5A
CH5IE
PTE2
LOGIC
PTE2/TACH0
INTERRUPT
LOGIC
PTE3
LOGIC
PTE3/TACH1
INTERRUPT
LOGIC
PTF0
LOGIC
PTF0/TACH2
INTERRUPT
LOGIC
PTF1
LOGIC
PTF1/TACH3
INTERRUPT
LOGIC
PTF2
LOGIC
PTF2/TACH4
INTERRUPT
LOGIC
PTF3
LOGIC
PTF3/TACH5
INTERRUPT
LOGIC
Figure 25-1. TIMA Block Diagram
MC68HC908AT32 Data Sheet, Rev. 3.1
288
Freescale Semiconductor
Features
Addr.
Register Name
Bit 7
6
5
TOIE
TSTOP
Timer A Status and Control Register Read:
(TASC) Write:
See page 298. Reset:
TOF
0
0
1
Keyboard Interrupt Enable Register Read:
(KBIER) Write:
See page 285. Reset:
0
0
0
0
0
Bit 15
$0022
Timer A Counter Register Read:
High (TACNTH) Write:
See page 300. Reset:
$0023
Timer A Counter Register Read:
Low (TACNTL) Write:
See page 300. Reset:
$0020
$0021
$0024
$0025
Timer A Counter Modulo Read:
Register High (TAMODH) Write:
See page 300. Reset:
Timer A Counter Modulo Read:
Register Low (TAMODL) Write:
See page 300. Reset:
Read:
Timer A Channel 0 Status and Control
$0026
Register (TASC0) Write:
See page 301. Reset:
$0027
$0028
Read:
Timer A Channel 0 Register
High (TACH0H) Write:
See page 304. Reset:
Timer A Channel 0 Register Read:
Low (TACH0L) Write:
See page 304. Reset:
Timer A Channel 1 Status and Control Read:
$0029
Register (TASC1) Write:
See page 298. Reset:
$002A
Timer A Channel 1 Register Read:
High (TACH1H) Write:
See page 304. Reset:
$002B
Timer A Channel 1 Register Read:
Low (TACH1L) Write:
See page 304. Reset:
4
3
2
1
Bit 0
PS2
PS1
PS0
0
0
TRST
R
0
0
0
0
0
KBIE4
KBIE3
KBIE2
KBIE1
KBIE0
0
0
0
0
0
0
14
13
12
11
10
9
Bit 8
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
Bit 7
6
5
4
3
2
1
Bit 0
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
1
1
1
1
1
1
1
1
Bit 7
6
5
4
3
2
1
Bit 0
1
1
1
1
1
1
1
1
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
0
CH0F
0
Indeterminate after reset
Bit 7
6
5
4
3
Indeterminate after reset
CH1F
0
CH1IE
0
R
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
Indeterminate after reset
Bit 7
6
5
4
3
Indeterminate after reset
Italic Type = MC68HC08AS20 Specific
Boldface Type = MC68HC08AZ32 Specific
= Unimplemented
R
= Reserved
Figure 25-2. TIMA I/O Register Summary (Sheet 1 of 2)
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
289
Timer Interface (TIM-6)
Addr.
$002C
$002D
$002E
Register Name
Bit 7
Timer A Channel 2 Status and Control Read:
Register (TASC2) Write:
See page 301. Reset:
Timer A Channel 2 Register Read:
High (TACH2H) Write:
See page 304. Reset:
Timer A Channel 2 Register Read:
Low (TACH2L) Write:
See page 304. Reset:
Read:
$002F
$0030
$0031
Timer A Channel 3 Status and Control
Write:
Register (TASC3)
Reset:
Timer A Channel 3 Register Read:
High (TACH3H) Write:
See page 304. Reset:
Timer A Channel 3 Register Read:
Low (TACH3L) Write:
See page 304. Reset:
Timer A Channel 4 Status and Control Read:
$0032
Register (TASC4) Write:
See page 301. Reset:
$0033
$0034
Timer A Channel 4 Register High Read:
(TACH4H) Write:
See page 304. Reset:
Timer A Channel 4 Register Low Read:
(TACH4L) Write:
See page 304. Reset:
Read:
Timer A Channel 5 Status and Control
$0035
Register (TASC5) Write:
See page 301. Reset:
$0036
Timer A Channel 5 Register Read:
High (TACH5H) Write:
See page 304. Reset:
$0037
Timer A Channel 5 Register Read:
Low (TACH5L) Write:
See page 304. Reset:
6
5
4
3
2
1
Bit 0
CH2IE
MS2B
MS2A
ELS2B
ELS2A
TOV2
CH2MAX
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
CH2F
0
Indeterminate after reset
Bit 7
6
5
4
3
Indeterminate after reset
CH3F
0
CH3IE
0
R
MS3A
ELS3B
ELS3A
TOV3
CH3MAX
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
Indeterminate after reset
Bit 7
6
5
4
3
Indeterminate after reset
CH4F
CH4IE
MS4B
MS4A
ELS4B
ELS4A
TOV4
CH4MAX
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
0
Indeterminate after reset
Bit 7
6
5
4
3
Indeterminate after reset
CH5F
0
CH5IE
0
R
MS5A
ELS5B
ELS5A
TOV5
CH5MAX
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
Indeterminate after reset
Bit 7
6
5
4
3
Indeterminate after reset
Italic Type = MC68HC08AS20 Specific
Boldface Type = MC68HC08AZ32 Specific
= Unimplemented
R
= Reserved
Figure 25-2. TIMA I/O Register Summary (Sheet 2 of 2)
MC68HC908AT32 Data Sheet, Rev. 3.1
290
Freescale Semiconductor
Functional Description
25.3 Functional Description
Figure 25-1 shows the TIMA structure. The central component of the TIMA is the 16-bit TIMA counter that
can operate as a free-running counter or a modulo up-counter. The TIMA counter provides the timing
reference for the input capture and output compare functions. The TIMA counter modulo registers,
TAMODH–TAMODL, control the modulo value of the TIMA counter. Software can read the TIMA counter
value at any time without affecting the counting sequence.
The six TIMA channels are programmable independently as input capture or output compare channels.
25.3.1 TIMA Counter Prescaler
The TIMA clock source can be one of the seven prescaler outputs or the TIMA clock pin,
PTD6/ATD14/TACLK. The prescaler generates seven clock rates from the internal bus clock. The
prescaler select bits, PS[2:0], in the TIMA status and control register select the TIMA clock source.
25.3.2 Input Capture
An input capture function has three basic parts: edge select logic, an input capture latch, and a 16-bit
counter. Two 8-bit registers, which make up the 16-bit input capture register, are used to latch the value
of the free-running counter after the corresponding input capture edge detector senses a defined
transition. The polarity of the active edge is programmable. The level transition which triggers the counter
transfer is defined by the corresponding input edge bits (ELSxB and ELSxA in TASC0 through TASC5
control registers with x referring to the active channel number). When an active edge occurs on the pin of
an input capture channel, the TIMA latches the contents of the TIMA counter into the TIMA channel
registers, TACHxH–TACHxL. Input captures can generate TIMA CPU interrupt requests. Software can
determine that an input capture event has occurred by enabling input capture interrupts or by polling the
status flag bit.
The result obtained by an input capture will be two more than the value of the free-running counter on the
rising edge of the internal bus clock preceding the external transition. This delay is required for internal
synchronization.
The free-running counter contents are transferred to the TIMA channel status and control register
(TACHxH–TACHxL, see 25.8.5 TIMA Channel Registers) on each proper signal transition regardless of
whether the TIMA channel flag (CH0F–CH5F in TASC0–TASC5 registers) is set or clear. When the status
flag is set, a CPU interrupt is generated if enabled. The value of the count latched or “captured” is the time
of the event. Because this value is stored in the input capture register two bus cycles after the actual event
occurs, user software can respond to this event at a later time and determine the actual time of the event.
However, this must be done prior to another input capture on the same pin; otherwise, the previous time
value will be lost.
By recording the times for successive edges on an incoming signal, software can determine the period
and/or pulse width of the signal. To measure a period, two successive edges of the same polarity are
captured. To measure a pulse width, two alternate polarity edges are captured. Software should track the
overflows at the 16-bit module counter to extend its range.
Another use for the input capture function is to establish a time reference. In this case, an input capture
function is used in conjunction with an output compare function. For example, to activate an output signal
a specified number of clock cycles after detecting an input event (edge), use the input capture function to
record the time at which the edge occurred. A number corresponding to the desired delay is added to this
captured value and stored to an output compare register (see 25.8.5 TIMA Channel Registers). Because
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
291
Timer Interface (TIM-6)
both input captures and output compares are referenced to the same 16-bit modulo counter, the delay
can be controlled to the resolution of the counter independent of software latencies.
Reset does not affect the contents of the input capture channel register (TACHxH–TACHxL).
25.3.3 Output Compare
With the output compare function, the TIMA can generate a periodic pulse with a programmable polarity,
duration, and frequency. When the counter reaches the value in the registers of an output compare
channel, the TIMA can set, clear, or toggle the channel pin. Output compares can generate TIMA CPU
interrupt requests.
25.3.3.1 Unbuffered Output Compare
Any output compare channel can generate unbuffered output compare pulses as described in
25.3.3 Output Compare. The pulses are unbuffered because changing the output compare value requires
writing the new value over the old value currently in the TIMA channel registers.
An unsynchronized write to the TIMA channel registers to change an output compare value could cause
incorrect operation for up to two counter overflow periods. For example, writing a new value before the
counter reaches the old value but after the counter reaches the new value prevents any compare during
that counter overflow period. Also, using a TIMA overflow interrupt routine to write a new, smaller output
compare value may cause the compare to be missed. The TIMA may pass the new value before it is
written.
Use these methods to synchronize unbuffered changes in the output compare value on channel x:
• When changing to a smaller value, enable channel x output compare interrupts and write the new
value in the output compare interrupt routine. The output compare interrupt occurs at the end of
the current output compare pulse. The interrupt routine has until the end of the counter overflow
period to write the new value.
• When changing to a larger output compare value, enable channel x TIMA overflow interrupts and
write the new value in the TIMA overflow interrupt routine. The TIMA overflow interrupt occurs at
the end of the current counter overflow period. Writing a larger value in an output compare interrupt
routine (at the end of the current pulse) could cause two output compares to occur in the same
counter overflow period.
25.3.3.2 Buffered Output Compare
Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the
PTE2/TACH0 pin. The TIMA channel registers of the linked pair alternately control the output.
Setting the MS0B bit in TIMA channel 0 status and control register (TASC0) links channel 0 and channel
1. The output compare value in the TIMA channel 0 registers initially controls the output on the
PTE2/TACH0 pin. Writing to the TIMA channel 1 registers enables the TIMA channel 1 registers to
synchronously control the output after the TIMA overflows. At each subsequent overflow, the TIMA
channel registers (0 or 1) that control the output are the ones written to last. TASC0 controls and monitors
the buffered output compare function, and TIMA channel 1 status and control register (TASC1) is unused.
While the MS0B bit is set, the channel 1 pin, PTE3/TACH1, is available as a general-purpose I/O pin.
Channels 2 and 3 can be linked to form a buffered output compare channel whose output appears on the
PTF0/TACH2 pin. The TIMA channel registers of the linked pair alternately control the output.
MC68HC908AT32 Data Sheet, Rev. 3.1
292
Freescale Semiconductor
Functional Description
Setting the MS2B bit in TIMA channel 2 status and control register (TASC2) links channel 2 and channel
3. The output compare value in the TIMA channel 2 registers initially controls the output on the
PTF0/TACH2 pin. Writing to the TIMA channel 3 registers enables the TIMA channel 3 registers to
synchronously control the output after the TIMA overflows. At each subsequent overflow, the TIMA
channel registers (2 or 3) that control the output are the ones written to last. TASC2 controls and monitors
the buffered output compare function, and TIMA channel 3 status and control register (TASC3) is unused.
While the MS2B bit is set, the channel 3 pin, PTF1/TACH3, is available as a general-purpose I/O pin.
Channels 4 and 5 can be linked to form a buffered output compare channel whose output appears on the
PTF2/TACH4 pin. The TIMA channel registers of the linked pair alternately control the output.
Setting the MS4B bit in TIMA channel 4 status and control register (TSC4) links channel 4 and channel
5. The output compare value in the TIMA channel 4 registers initially controls the output on the
PTF2/TACH4 pin. Writing to the TIMA channel 5 registers enables the TIMA channel 5 registers to
synchronously control the output after the TIMA overflows. At each subsequent overflow, the TIMA
channel registers (4 or 5) that control the output are the ones written to last. TASC4 controls and monitors
the buffered output compare function, and TIMA channel 5 status and control register (TASC5) is unused.
While the MS4B bit is set, the channel 5 pin, PTF3/TACH5, is available as a general-purpose I/O pin.
NOTE
In buffered output compare operation, do not write new output compare
values to the currently active channel registers. Writing to the active
channel registers is the same as generating unbuffered output compares.
25.3.4 Pulse-Width Modulation (PWM)
By using the toggle-on-overflow feature with an output compare channel, the TIMA can generate a PWM
signal. The value in the TIMA counter modulo registers determines the period of the PWM signal. The
channel pin toggles when the counter reaches the value in the TIMA counter modulo registers. The time
between overflows is the period of the PWM signal.
As Figure 25-3 shows, the output compare value in the TIMA channel registers determines the pulse width
of the PWM signal. The time between overflow and output compare is the pulse width. Program the TIMA
to clear the channel pin on output compare if the state of the PWM pulse is logic 1. Program the TIMA to
set the pin if the state of the PWM pulse is logic 0.
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
PULSE
WIDTH
PTEx/TCHx
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 25-3. PWM Period and Pulse Width
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
293
Timer Interface (TIM-6)
The value in the TIMA counter modulo registers and the selected prescaler output determines the
frequency of the PWM output. The frequency of an 8-bit PWM signal is variable in 256 increments. Writing
$00FF (255) to the TIMA counter modulo registers produces a PWM period of 256 times the internal bus
clock period if the prescaler select value is $000 (see 25.8.1 TIMA Status and Control Register).
The value in the TIMA channel registers determines the pulse width of the PWM output. The pulse width
of an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIMA channel registers
produces a duty cycle of 128/256 or 50 percent.
25.3.4.1 Unbuffered PWM Signal Generation
Any output compare channel can generate unbuffered PWM pulses as described in 25.3.4 Pulse-Width
Modulation (PWM). The pulses are unbuffered because changing the pulse width requires writing the new
pulse width value over the value currently in the TIMA channel registers.
An unsynchronized write to the TIMA channel registers to change a pulse width value could cause
incorrect operation for up to two PWM periods. For example, writing a new value before the counter
reaches the old value but after the counter reaches the new value prevents any compare during that PWM
period. Also, using a TIMA overflow interrupt routine to write a new, smaller pulse width value may cause
the compare to be missed. The TIMA may pass the new value before it is written to the TIMA channel
registers.
Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x:
• When changing to a shorter pulse width, enable channel x output compare interrupts and write the
new value in the output compare interrupt routine. The output compare interrupt occurs at the end
of the current pulse. The interrupt routine has until the end of the PWM period to write the new
value.
• When changing to a longer pulse width, enable channel x TIMA overflow interrupts and write the
new value in the TIMA overflow interrupt routine. The TIMA overflow interrupt occurs at the end of
the current PWM period. Writing a larger value in an output compare interrupt routine (at the end
of the current pulse) could cause two output compares to occur in the same PWM period.
NOTE
In PWM signal generation, do not program the PWM channel to toggle on
output compare. Toggling on output compare prevents reliable 0 percent
duty cycle generation and removes the ability of the channel to self-correct
in the event of software error or noise. Toggling on output compare also can
cause incorrect PWM signal generation when changing the PWM pulse
width to a new, much larger value.
25.3.4.2 Buffered PWM Signal Generation
Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the
PTE2/TACH0 pin. The TIMA channel registers of the linked pair alternately control the pulse width of the
output.
Setting the MS0B bit in TIMA channel 0 status and control register (TASC0) links channel 0 and
channel 1. The TIMA channel 0 registers initially control the pulse width on the PTE2/TACH0 pin. Writing
to the TIMA channel 1 registers enables the TIMA channel 1 registers to synchronously control the pulse
width at the beginning of the next PWM period. At each subsequent overflow, the TIMA channel registers
(0 or 1) that control the pulse width are the ones written to last. TASC0 controls and monitors the buffered
MC68HC908AT32 Data Sheet, Rev. 3.1
294
Freescale Semiconductor
Functional Description
PWM function, and TIMA channel 1 status and control register (TASC1) is unused. While the MS0B bit is
set, the channel 1 pin, PTE3/TACH1, is available as a general-purpose I/O pin.
Channels 2 and 3 can be linked to form a buffered PWM channel whose output appears on the
PTF0/TACH2 pin. The TIMA channel registers of the linked pair alternately control the pulse width of the
output.
Setting the MS2B bit in TIMA channel 2 status and control register (TASC2) links channel 2 and
channel 3. The TIMA channel 2 registers initially control the pulse width on the PTF0/TACH2 pin. Writing
to the TIMA channel 3 registers enables the TIMA channel 3 registers to synchronously control the pulse
width at the beginning of the next PWM period. At each subsequent overflow, the TIMA channel registers
(2 or 3) that control the pulse width are the ones written to last. TASC2 controls and monitors the buffered
PWM function, and TIMA channel 3 status and control register (TASC3) is unused. While the MS2B bit is
set, the channel 3 pin, PTF1/TACH3, is available as a general-purpose I/O pin.
Channels 4 and 5 can be linked to form a buffered PWM channel whose output appears on the
PTF2/TACH4 pin. The TIMA channel registers of the linked pair alternately control the pulse width of the
output.
Setting the MS4B bit in TIMA channel 4 status and control register (TASC4) links channel 4 and
channel 5. The TIMA channel 4 registers initially control the pulse width on the PTF2/TACH4 pin. Writing
to the TIMA channel 5 registers enables the TIMA channel 5 registers to synchronously control the pulse
width at the beginning of the next PWM period. At each subsequent overflow, the TIMA channel registers
(4 or 5) that control the pulse width are the ones written to last. TASC4 controls and monitors the buffered
PWM function, and TIMA channel 5 status and control register (TASC5) is unused. While the MS4B bit is
set, the channel 5 pin, PTF3/TACH5, is available as a general-purpose I/O pin.
NOTE
In buffered PWM signal generation, do not write new pulse width values to
the currently active channel registers. Writing to the active channel
registers is the same as generating unbuffered PWM signals.
25.3.4.3 PWM Initialization
To ensure correct operation when generating unbuffered or buffered PWM signals, use the following
initialization procedure:
1. In the TIMA status and control register (TASC):
a. Stop the TIMA counter by setting the TIMA stop bit, TSTOP.
b. Reset the TIMA counter by setting the TIMA reset bit, TRST.
2. In the TIMA counter modulo registers (TAMODH–TAMODL), write the value for the required PWM
period.
3. In the TIMA channel x registers (TACHxH–TACHxL), write the value for the required pulse width.
4. In TIMA channel x status and control register (TSCx):
a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare
or PWM signals) to the mode select bits, MSxB–MSxA. (See Table 25-2.)
b. Write 1 to the toggle-on-overflow bit, TOVx.
c. Write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level
select bits, ELSxB–ELSxA. The output action on compare must force the output to the
complement of the pulse width level. (See Table 25-2.)
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
295
Timer Interface (TIM-6)
NOTE
In PWM signal generation, do not program the PWM channel to toggle on
output compare. Toggling on output compare prevents reliable 0 percent
duty cycle generation and removes the ability of the channel to self-correct
in the event of software error or noise. Toggling on output compare can also
cause incorrect PWM signal generation when changing the PWM pulse
width to a new, much larger value.
5. In the TIMA status control register (TASC), clear the TIMA stop bit, TSTOP.
Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIMA channel
0 registers (TACH0H–TACH0L) initially control the buffered PWM output. TIMA status control register 0
(TASC0) controls and monitors the PWM signal from the linked channels. MS0B takes priority over MS0A.
Setting MS2B links channels 2 and 3 and configures them for buffered PWM operation. The TIMA channel
2 registers (TACH2H–TACH2L) initially control the PWM output. TIMA status control register 2 (TASC2)
controls and monitors the PWM signal from the linked channels. MS2B takes priority over MS2A.
Setting MS4B links channels 4 and 5 and configures them for buffered PWM operation. The TIMA channel
4 registers (TACH4H–TACH4L) initially control the PWM output. TIMA status control register 4 (TASC4)
controls and monitors the PWM signal from the linked channels. MS4B takes priority over MS4A.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIMA overflows. Subsequent output
compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle
output.
Setting the channel x maximum duty cycle bit (CHxMAX) and clearing the TOVx bit generates a 100
percent duty cycle output. (See 25.8.4 TIMA Channel Status and Control Registers.)
25.4 Interrupts
These TIMA sources can generate interrupt requests:
• TIM overflow flag (TOF) — The timer counter value changes on the falling edge of the internal bus
clock. The timer overflow flag (TOF) bit is set on the falling edge of the internal bus clock following
the timer rollover to $0000. The TIM overflow interrupt enable bit, TOIE, enables TIM overflow
interrupt requests. TOF and TOIE are in the TIM status and control registers.
• TIMA channel flags (CH5F–CH0F) — The CHxF bit is set when an input capture or output compare
occurs on channel x. Channel x TIMA CPU interrupt requests are controlled by the channel x
interrupt enable bit, CHxIE.
25.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power standby modes.
25.5.1 Wait Mode
The TIMA remains active after the execution of a WAIT instruction. In wait mode, the TIMA registers are
not accessible by the CPU. Any enabled CPU interrupt request from the TIMA can bring the MCU out of
wait mode.
If TIMA functions are not required during wait mode, reduce power consumption by stopping the TIMA
before executing the WAIT instruction.
MC68HC908AT32 Data Sheet, Rev. 3.1
296
Freescale Semiconductor
TIMA during Break Interrupts
25.5.2 Stop Mode
The TIMA is inactive after the execution of a STOP instruction. The STOP instruction does not affect
register conditions or the state of the TIMA counter. TIMA operation resumes when the MCU exits stop
mode.
25.6 TIMA during Break Interrupts
A break interrupt stops the TIMA counter and inhibits input captures.
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. (See 7.7.3 SIM Break Flag Control Register.)
To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status
bit is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its
default state), software can read and write I/O registers during the break state without affecting status bits.
Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit
before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the
break, doing the second step clears the status bit.
25.7 I/O Signals
Port D shares one of its pins with the TIMA. Port E shares two of its pins with the TIMA and port F shares
four of its pins with the TIMA. PTD6/ATD14/TACLK is an external clock input to the TIMA prescaler. The
six TIMA channel I/O pins are PTE2/TACH0, PTE3/TACH1, PTF0/TACH2, PTF1/TACH3, PTF2/TACH4,
and PTF3/TACH5.
25.7.1 TIMA Clock Pin (PTD6/ATD14/TCLK)
PTD6/ATD14/TACLK is an external clock input that can be the clock source for the TIMA counter instead
of the prescaled internal bus clock. Select the PTD6/ATD14/TACLK input by writing logic 1s to the three
prescaler select bits, PS[2:0]. (See 25.8.1 TIMA Status and Control Register.) The minimum TCLK pulse
width, TCLKLMIN or TCLKHMIN, is:
1
------------------------------------- + t
bus frequency SU
The maximum TCLK frequency is the least: 4 MHz or bus frequency ÷ 2.
PTD6/ATD14/TACLK is available as a general-purpose I/O pin or ADC channel when not used as the
TIMA clock input. When the PTD6/ATD14/TACLK pin is the TIMA clock input, it is an input regardless of
the state of the DDRD6 bit in data direction register D.
25.7.2 TIMA Channel I/O Pins (PTF3/TACH5–PTF0/TACH2 and
PTE3/TACH1–PTE2/TACH0)
Each channel I/O pin is programmable independently as an input capture pin or an output compare pin.
PTE2/TACH0, PTE6/TACH2, and PTF2/TACH4 can be configured as buffered output compare or
buffered PWM pins.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
297
Timer Interface (TIM-6)
25.8 I/O Registers
These I/O registers control and monitor TIMA operation:
• TIMA status and control register (TASC)
• TIMA control registers (TACNTH–TACNTL)
• TIMA counter modulo registers (TAMODH–TAMODL)
• TIMA channel status and control registers (TASC0, TASC1, TASC2, TASC3, TASC4, and TSAC5)
• TIMA channel registers (TACH0H–TACH0L, TACH1H–TACH1L, TACH2H–TACH2L,
TACH3H–TACH3L, TACH4H–TACH4L, and TACH5H–TACH5L)
25.8.1 TIMA Status and Control Register
The TIMA status and control register:
• Enables TIMA overflow interrupts
• Flags TIMA overflows
• Stops the TIMA counter
• Resets the TIMA counter
• Prescales the TIMA counter clock
Address:
$0020
Bit 7
6
5
TOIE
TSTOP
1
Read:
TOF
Write:
0
Reset:
0
0
R
= Reserved
4
3
0
0
TRST
R
0
0
2
1
Bit 0
PS2
PS1
PS0
0
0
0
Figure 25-4. TIMA Status and Control Register (TASC)
TOF — TIMA Overflow Flag
This read/write flag is set when the TIMA counter resets to $0000 after reaching the modulo value
programmed in the TIMA counter modulo registers. Clear TOF by reading the TIMA status and control
register when TOF is set and then writing a logic 0 to TOF. If another TIMA overflow occurs before the
clearing sequence is complete, then writing logic 0 to TOF has no effect. Therefore, a TOF interrupt
request cannot be lost due to inadvertent clearing of TOF. Reset clears the TOF bit. Writing a logic 1
to TOF has no effect.
1 = TIMA counter has reached modulo value.
0 = TIMA counter has not reached modulo value.
TOIE — TIMA Overflow Interrupt Enable Bit
This read/write bit enables TIMA overflow interrupts when the TOF bit becomes set. Reset clears the
TOIE bit.
1 = TIMA overflow interrupts enabled
0 = TIMA overflow interrupts disabled
MC68HC908AT32 Data Sheet, Rev. 3.1
298
Freescale Semiconductor
I/O Registers
TSTOP — TIMA Stop Bit
This read/write bit stops the TIMA counter. Counting resumes when TSTOP is cleared. Reset sets the
TSTOP bit, stopping the TIMA counter until software clears the TSTOP bit.
1 = TIMA counter stopped
0 = TIMA counter active
NOTE
Do not set the TSTOP bit before entering wait mode if the TIMA is required
to exit wait mode. Also, when the TSTOP bit is set and input capture mode
is enabled, input captures are inhibited until TSTOP is cleared.
TRST — TIMA Reset Bit
Setting this write-only bit resets the TIMA counter and the TIMA prescaler. Setting TRST has no effect
on any other registers. Counting resumes from $0000. TRST is cleared automatically after the TIMA
counter is reset and always reads as logic 0. Reset clears the TRST bit.
1 = Prescaler and TIMA counter cleared
0 = No effect
NOTE
Setting the TSTOP and TRST bits simultaneously stops the TIMA counter
at a value of $0000.
PS[2:0] — Prescaler Select Bits
These read/write bits select either the PTD6/ATD14/TACLK pin or one of the seven prescaler outputs
as the input to the TIMA counter as Table 25-1 shows. Reset clears the PS[2:0] bits.
Table 25-1. Prescaler Selection
PS[2:0]
TIMA Clock Source
000
Internal bus clock ÷1
001
Internal bus clock ÷ 2
010
Internal bus clock ÷ 4
011
Internal bus clock ÷ 8
100
Internal bus clock ÷ 16
101
Internal bus clock ÷ 32
110
Internal bus clock ÷ 64
111
PTD6/ATD14/TACLK
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
299
Timer Interface (TIM-6)
25.8.2 TIMA Counter Registers
The two read-only TIMA counter registers contain the high and low bytes of the value in the TIMA counter.
Reading the high byte (TACNTH) latches the contents of the low byte (TACNTL) into a buffer. Subsequent
reads of TACNTH do not affect the latched TACNTL value until TACNTL is read. Reset clears the TIMA
counter registers. Setting the TIMA reset bit (TRST) also clears the TIMA counter registers.
NOTE
If TACNTH is read during a break interrupt, be sure to unlatch TACNTL by
reading TACNTL before exiting the break interrupt. Otherwise, TACNTL
retains the value latched during the break.
Register Name and Address: TCNTH — $0022
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write:
R
R
R
R
R
R
R
R
Reset:
0
0
0
0
0
0
0
0
Register Name and Address: TCNTL — $0023
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
R
R
R
R
R
R
R
R
Reset:
0
0
0
0
0
0
0
0
R
= Reserved
Figure 25-5. TIMA Counter Registers (TCNTH and TCNTL)
25.8.3 TIMA Counter Modulo Registers
The read/write TIMA modulo registers contain the modulo value for the TIMA counter. When the TIMA
counter reaches the modulo value, the overflow flag (TOF) becomes set, and the TIMA counter resumes
counting from $0000 at the next clock. Writing to the high byte (TAMODH) inhibits the TOF bit and
overflow interrupts until the low byte (TAMODL) is written. Reset sets the TIMA counter modulo
registers.
Register Name and Address: TAMODH — $0024
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
1
1
1
1
1
1
1
1
Register Name and Address: TAMODL — $0025
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
Figure 25-6. TIMA Counter Modulo Registers (TAMODH and TAMODL)
NOTE
Reset the TIMA counter before writing to the TIMA counter modulo registers.
MC68HC908AT32 Data Sheet, Rev. 3.1
300
Freescale Semiconductor
I/O Registers
25.8.4 TIMA Channel Status and Control Registers
Each of the TIMA channel status and control registers:
• Flags input captures and output compares
• Enables input capture and output compare interrupts
• Selects input capture, output compare, or PWM operation
• Selects high, low, or toggling output on output compare
• Selects rising edge, falling edge, or any edge as the active input capture trigger
• Selects output toggling on TIMA overflow
• Selects 100 percent PWM duty cycle
• Selects buffered or unbuffered output compare/PWM operation
Register Name and Address: TASC0 — $0026
Read:
Write:
Reset:
Bit 7
CH0F
0
0
6
5
4
3
2
1
Bit 0
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
0
0
0
0
0
0
0
3
2
1
Bit 0
ELS1B
ELS1A
TOV1
CH1MAX
0
0
0
0
3
2
1
Bit 0
ELS2B
ELS2A
TOV2
CH2MAX
0
0
0
0
3
2
1
Bit 0
ELS3B
ELS3A
TOV3
CH3MAX
0
0
0
0
3
2
1
Bit 0
ELS4B
ELS4A
TOV4
CH4MAX
0
0
0
0
3
2
1
Bit 0
ELS5B
ELS5A
TOV5
CH5MAX
0
0
0
0
Register Name and Address: TASC1 — $0029
Bit 7
6
5
4
Read:
CH1F
0
CH1IE
MS1A
Write:
0
R
Reset:
0
0
0
0
Register Name and Address: TASC2 — $002C
Bit 7
6
5
4
Read:
CH2F
CH2IE
MS2B
MS2A
Write:
0
Reset:
0
0
0
0
Register Name and Address: TASC3 — $002F
Bit 7
6
5
4
Read:
CH3F
0
CH3IE
MS3A
Write:
0
R
Reset:
0
0
0
0
Register Name and Address: TASC4 — $0032
Bit 7
6
5
4
Read:
CH4F
CH4IE
MS4B
MS4A
Write:
0
Reset:
0
0
0
0
Register Name and Address: TASC5 — $0035
Bit 7
6
5
4
Read:
CH5F
0
CH5IE
MS5A
Write:
0
R
Reset:
0
0
0
0
R
= Reserved
Figure 25-7. TIMA Channel Status
and Control Registers (TASC0–TASC5)
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
301
Timer Interface (TIM-6)
CHxF — Channel x Flag
When channel x is an input capture channel, this read/write bit is set when an active edge occurs on
the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the
TIMA counter registers matches the value in the TIMA channel x registers.
When CHxIE = 0, clear CHxF by reading TIMA channel x status and control register with CHxF set,
and then writing a logic 0 to CHxF. If another interrupt request occurs before the clearing sequence is
complete, then writing logic 0 to CHxF has no effect. Therefore, an interrupt request cannot be lost due
to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIMA CPU interrupts on channel x.
Reset clears the CHxIE bit.
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
MSxB — Mode Select Bit B
This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIMA
channel 0, TIMA channel 2, and TIMA channel 4 status and control registers.
Setting MS0B disables the channel 1 status and control register and reverts TACH1 pin to
general-purpose I/O.
Setting MS2B disables the channel 3 status and control register and reverts TACH3 pin to
general-purpose I/O.
Setting MS4B disables the channel 5 status and control register and reverts TACH5 pin to
general-purpose I/O.
Reset clears the MSxB bit.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
MSxA — Mode Select Bit A
When ELSxB:A ≠ 00, this read/write bit selects either input capture operation or unbuffered output
compare/PWM operation.
See Table 25-2.
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
When ELSxB:A = 00, this read/write bit selects the initial output level of the TCHx pin once PWM,
output compare mode, or input capture mode is enabled. (See Table 25-2.). Reset clears the MSxA bit.
1 = Initial output level low
0 = Initial output level high
NOTE
Before changing a channel function by writing to the MSxB or MSxA bit, set
the TSTOP and TRST bits in the TIMA status and control register (TSC).
MC68HC908AT32 Data Sheet, Rev. 3.1
302
Freescale Semiconductor
I/O Registers
ELSxB and ELSxA — Edge/Level Select Bits
When channel x is an input capture channel, these read/write bits control the active edge-sensing logic
on channel x.
When channel x is an output compare channel, ELSxB and ELSxA control the channel x output
behavior when an output compare occurs.
When ELSxB and ELSxA are both clear, channel x is not connected to port E or port F, and pin
PTEx/TACHx or pin PTFx/TACHx is available as a general-purpose I/O pin. However, channel x is at
a state determined by these bits and becomes transparent to the respective pin when PWM, input
capture mode, or output compare operation mode is enabled. Table 25-2 shows how ELSxB and
ELSxA work. Reset clears the ELSxB and ELSxA bits.
NOTE
Before enabling a TIMA channel register for input capture operation, make
sure that the PTEx/TACHx pin or PTFx/TACHx pin is stable for at least two
bus clocks.
TOVx — Toggle-On-Overflow Bit
When channel x is an output compare channel, this read/write bit controls the behavior of the channel
x output when the TIMA counter overflows. When channel x is an input capture channel, TOVx has no
effect. Reset clears the TOVx bit.
1 = Channel x pin toggles on TIMA counter overflow.
0 = Channel x pin does not toggle on TIMA counter overflow.
NOTE
When TOVx is set, a TIMA counter overflow takes precedence over a
channel x output compare if both occur at the same time.
CHxMAX — Channel x Maximum Duty Cycle Bit
When the TOVx bit is at logic 0, setting the CHxMAX bit forces the duty cycle of buffered and
unbuffered PWM signals to 100%. As Figure 25-8 shows, the CHxMAX bit takes effect in the cycle after
it is set or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is
cleared.
Table 25-2. Mode, Edge, and Level Selection
MSxB:MSxA
ELSxB:ELSxA
X0
00
Mode
Output preset
Configuration
Pin under port control;
Initialize timer
Output level high
Pin under port control;
Initialize timer
Output level low
X1
00
00
01
00
10
00
11
Capture on rising or falling edge
01
01
Toggle output on compare
01
10
01
11
1X
01
1X
10
1X
11
Capture on rising edge only
Input capture
Output compare
or PWM
Capture on falling edge only
Clear output on compare
Set output on compare
Toggle output on compare
Buffered
output compare Clear output on compare
or buffered PWM Set output on compare
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
303
Timer Interface (TIM-6)
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
PTEx/TCHx
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
CHxMAX
Figure 25-8. CHxMAX Latency
25.8.5 TIMA Channel Registers
These read/write registers contain the captured TIMA counter value of the input capture function or the
output compare value of the output compare function. The state of the TIMA channel registers after reset
is unknown.
In input capture mode (MSxB–MSxA = 0:0), reading the high byte of the TIMA channel x registers
(TCHxH) inhibits input captures until the low byte (TCHxL) is read.
In output compare mode (MSxB–MSxA ≠ 0:0), writing to the high byte of the TIMA channel x registers
(TCHxH) inhibits output compares until the low byte (TCHxL) is written.
Register Name and Address: TACH0H — $0027
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
2
1
Bit 0
Bit 2
Bit 1
Bit 0
2
1
Bit 0
Bit 10
Bit 9
Bit 8
2
1
Bit 0
Bit 2
Bit 1
Bit 0
Indeterminate after reset
Register Name and Address: TACH0L — $0028
Bit 7
6
5
4
3
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Write:
Reset:
Indeterminate after reset
Register Name and Address: TACH1H — $002A
Bit 7
6
5
4
3
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Write:
Reset:
Indeterminate after reset
Register Name and Address: TACH1L — $002B
Bit 7
6
5
4
3
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Write:
Reset:
Indeterminate after reset
Figure 25-9. TIMA Channel Registers (TACH0H/L–TACH3H/L)
MC68HC908AT32 Data Sheet, Rev. 3.1
304
Freescale Semiconductor
I/O Registers
Register Name and Address: TACH2H — $002D
Bit 7
6
5
4
3
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Write:
Reset:
Indeterminate after reset
Register Name and Address: TACH2L — $002E
Bit 7
6
5
4
3
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Write:
Reset:
Indeterminate after reset
Register Name and Address: TACH3H — $0030
Bit 7
6
5
4
3
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Write:
Reset:
Indeterminate after reset
Register Name and Address: TACH3L — $0031
Bit 7
6
5
4
3
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Write:
Reset:
Indeterminate after reset
Register Name and Address: TACH4H — $0033
Bit 7
6
5
4
3
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Write:
Reset:
Indeterminate after reset
Register Name and Address: TACH4L — $0034
Bit 7
6
5
4
3
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Write:
Reset:
Indeterminate after reset
Register Name and Address: TACH5H — $0036
Bit 7
6
5
4
3
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Write:
Reset:
Indeterminate after reset
Register Name and Address: TACH5L — $0037
Bit 7
6
5
4
3
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Write:
Reset:
Indeterminate after reset
2
1
Bit 0
Bit 10
Bit 9
Bit 8
2
1
Bit 0
Bit 2
Bit 1
Bit 0
2
1
Bit 0
Bit 10
Bit 9
Bit 8
2
1
Bit 0
Bit 2
Bit 1
Bit 0
2
1
Bit 0
Bit 10
Bit 9
Bit 8
2
1
Bit 0
Bit 2
Bit 1
Bit 0
2
1
Bit 0
Bit 10
Bit 9
Bit 8
2
1
Bit 0
Bit 2
Bit 1
Bit 0
Figure 25-9. TIMA Channel Registers (TACH0H/L–TACH3H/L) (Continued)
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
305
Timer Interface (TIM-6)
MC68HC908AT32 Data Sheet, Rev. 3.1
306
Freescale Semiconductor
Chapter 26
Analog-to-Digital Converter (ADC-15)
NOTE
This analog-to-digital converter (ADC) is for the J1850 (52-pin PLCC)
protocol only.
26.1 Introduction
This section describes the analog-to-digital converter (ADC-15). The ADC is an 8-bit analog-to-digital
converter.
26.2 Features
Features of the ADC module include:
• 15 channels with multiplexed input
• Linear successive approximation
• 8-bit resolution
• Single or continuous conversion
• Conversion complete flag or conversion complete interrupt
• Selectable ADC clock
26.3 Functional Description
Fifteen ADC channels are available for sampling external sources at pins
PTD6/ATD14/TACLK–PTD0/ATD8 and PTB7/ATD7–PTB0/ATD0. An analog multiplexer allows the
single ADC converter to select one of 15 ADC channels as ADC voltage in (ADCVIN). ADCVIN is
converted by the successive approximation register-based counters. When the conversion is completed,
ADC places the result in the ADC data register and sets a flag or generates an interrupt.
(See Figure 26-1.)
26.3.1 ADC Port I/O Pins
PTD6/ATD14/TACLK–PTD0/ATD8 and PTB7/ATD7–PTB0/ATD0 are general-purpose I/O pins that
share with the ADC channels. The channel select bits define which ADC channel/port pin will be used as
the input signal. The ADC overrides the port I/O logic by forcing that pin as input to the ADC. The
remaining ADC channels/port pins are controlled by the port I/O logic and can be used as
general-purpose I/O. Writes to the port register or DDR will not have any affect on the port pin that is
selected by the ADC. Read of a port pin which is in use by the ADC will return a logic 0 if the corresponding
DDR bit is at logic 0. If the DDR bit is at logic 1, the value in the port data latch is read.
NOTE
Do not use ADC channel ATD14 when using the PTD6/ATD14/TACLK pin
as the clock input for the TIM.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
307
Analog-to-Digital Converter (ADC-15)
INTERNAL
DATA BUS
READ DDRB/DDRB
WRITE DDRB/DDRD
RESET
WRITE PTB/PTD
DISABLE
DDRBx/DDRDx
PTBx/PTDx
PTBx/PTDx
ADC CHANNEL x
READ PTB/PTD
DISABLE
ADC DATA REGISTER
INTERRUPT
LOGIC
AIEN
CONVERSION
COMPLETE
ADC VOLTAGE IN
ADCVIN
ADC
CHANNEL
SELECT
ADCH[4:0]
COCO
ADC CLOCK
CGMXCLK
BUS CLOCK
CLOCK
GENERATOR
ADIV[2:0]
ADICLK
Figure 26-1. ADC Block Diagram
26.3.2 Voltage Conversion
When the input voltage to the ADC equals VREFH (see 29.6 ADC Characteristics), the ADC converts the
signal to $FF (full scale). If the input voltage equals VSSA, the ADC converts it to $00. Input voltages
between VREFH and VSSA are a straight-line linear conversion. All other input voltages will result in $FF if
greater than VREFH and $00 if less than VSSA.
NOTE
Input voltage should not exceed the analog supply voltages.
26.3.3 Conversion Time
Conversion starts after a write to the ADSCR (ADC status control register, $0038) and requires between
16 and 17 ADC clock cycles to complete. Conversion time in terms of the number of bus cycles is a
function of ADICLK select, CGMXCLK frequency, bus frequency, and ADIV prescaler bits. For example,
with a CGMXCLK frequency of 4 MHz, bus frequency of 8 MHz, and fixed ADC clock frequency of 1 MHz,
MC68HC908AT32 Data Sheet, Rev. 3.1
308
Freescale Semiconductor
Interrupts
one conversion will take between 16 and 17 µs and there will be between 128 bus cycles between each
conversion. Sample rate is approximately 60 kHz.
Refer to 29.6 ADC Characteristics.
16 to 17 ADC Clock Cycles
Conversion Time = ⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
ADC Clock Frequency
Number of Bus Cycles = Conversion Time x Bus Frequency
26.3.4 Continuous Conversion
In the continuous conversion mode, the ADC data register will be filled with new data after each
conversion. Data from the previous conversion will be overwritten whether that data has been read or not.
Conversions will continue until the ADCO bit (ADC status control register, $0038) is cleared. The COCO
bit is set after the first conversion and will stay set for the next several conversions until the next write of
the ADC status and control register or the next read of the ADC data register.
26.3.5 Accuracy and Precision
The conversion process is monotonic and has no missing codes. See 29.6 ADC Characteristics for
accuracy information.
26.4 Interrupts
When the AIEN bit is set, the ADC module is capable of generating a CPU interrupt after each ADC
conversion. A CPU interrupt is generated if the COCO bit (ADC status control register, $0038) is at logic
0. If the COCO bit is set, an interrupt is generated. The COCO bit is not used as a conversion complete
flag when interrupts are enabled.
26.5 Low-Power Modes
The following subsections describe the low-power modes.
26.5.1 Wait Mode
The ADC continues normal operation during wait mode. Any enabled CPU interrupt request from the ADC
can bring the MCU out of wait mode. If the ADC is not required to bring the MCU out of wait mode, power
down the ADC by setting the ADCH[4:0] bits in the ADC status and control register before executing the
WAIT instruction.
26.5.2 Stop Mode
The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted.
ADC conversions resume when the MCU exits stop mode. Allow one conversion cycle to stabilize the
analog circuitry before attempting a new ADC conversion after exiting stop mode.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
309
Analog-to-Digital Converter (ADC-15)
26.6 I/O Signals
The ADC module has 15 channels that are shared with I/O ports B and D and one channel with an
input-only port bit on port D. Refer to 29.6 ADC Characteristics for voltages referenced in the following
subsections.
26.6.1 ADC Analog Power Pin (VDDAREF)/ADC Voltage Reference Pin (VREFH)
The ADC analog portion uses VDDAREF as its power pin. Connect the VDDA/VDDAREF pin to the same
voltage potential as VDD. External filtering may be necessary to ensure clean VDDAREF for good results.
VREFH is the high reference voltage for all analog-to-digital conversions. Connect the VREFH pin to a
voltage potential between 1.5 volts and VDDAREF/VDDA depending on the desired upper conversion
boundary.
NOTE
Route VDDAREF carefully for maximum noise immunity and place bypass
capacitors as close as possible to the package.
26.6.2 ADC Analog Ground Pin (VSSA)/ADC Voltage Reference Low Pin (VREFL)
The ADC analog portion uses VSSA as its ground pin. Connect the VSSA pin to the same voltage potential
as VSS.
VREFL is the lower reference supply for the ADC.
26.6.3 ADC Voltage In (ADCVIN)
ADCVIN is the input voltage signal from one of the 15 ADC channels to the ADC module.
26.7 I/O Registers
These I/O registers control and monitor ADC operation:
• ADC status and control register (ADSCR)
• ADC data register (ADR)
• ADC clock register (ADICLK)
26.7.1 ADC Status and Control Register
The following paragraphs describe the function of the ADC status and control register.
Address:
$0038
Bit 7
6
5
4
3
2
1
Bit 0
AIEN
ADCO
ADCH4
ADCH3
ADCH2
ADCH1
ADCH0
0
0
0
1
1
1
1
1
R
= Reserved
Read:
COCO
Write:
R
Reset:
Figure 26-2. ADC Status and Control Register (ADSCR)
MC68HC908AT32 Data Sheet, Rev. 3.1
310
Freescale Semiconductor
I/O Registers
COCO — Conversions Complete Bit
When the AIEN bit is a logic 0, the COCO is a read-only bit which is set each time a conversion is
completed. This bit is cleared whenever the ADC status and control register is written or whenever the
ADC data register is read.
If the AIEN bit is a logic 1, the COCO is a read/write bit which selects the CPU to service the ADC
interrupt request. Reset clears this bit.
1 = Conversion completed (AIEN = 0)
0 = Conversion not completed (AIEN = 0)
or
1 = DMA interrupt enabled (AIEN = 1)
0 = CPU interrupt enabled (AIEN = 1)
AIEN — ADC Interrupt Enable Bit
When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is
cleared when the data register is read or the status/control register is written. Reset clears the AIEN bit.
1 = ADC interrupt enabled
0 = ADC interrupt disabled
ADCO — ADC Continuous Conversion Bit
When set, the ADC will convert samples continuously and update the ADR register at the end of each
conversion. Only one conversion is allowed when this bit is cleared. Reset clears the ADCO bit.
1 = Continuous ADC conversion
0 = One ADC conversion
ADCH[4:0] — ADC Channel Select Bits
ADCH4, ADCH3, ADCH2, ADCH1, and ADCH0 form a 5-bit field which is used to select one of 15 ADC
channels. The six channels are detailed in the following table. Care should be taken when using a port
pin as both an analog and a digital input simultaneously to prevent switching noise from corrupting the
analog signal. (See Table 26-1.)
The ADC subsystem is turned off when the channel select bits are all set to 1. This feature allows for
reduced power consumption for the MCU when the ADC is not used. Reset sets these bits.
NOTE
Recovery from the disabled state requires one conversion cycle to stabilize.
Table 26-1. MUX Channel Select
ADCH4
ADCH3
ADCH2
ADCH1
ADCH0
Input Select
0
0
0
0
0
PTB0/ATD0
0
0
0
0
1
PTB1/ATD1
0
0
0
1
0
PTB2/ATD2
0
0
0
1
1
PTB3/ATD3
0
0
1
0
0
PTB4/ATD4
0
0
1
0
1
PTB5/ATD5
0
0
1
1
0
PTB6/ATD6
0
0
1
1
1
PTB7/ATD7
0
1
0
0
0
PTD0/ATD8
0
1
0
0
1
PTD1/ATD9
Continued on next page
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
311
Analog-to-Digital Converter (ADC-15)
Table 26-1. MUX Channel Select
ADCH4
ADCH3
ADCH2
ADCH1
ADCH0
Input Select
0
1
0
1
0
PTD2/ATD10
0
1
0
1
1
PTD3/ATD11
0
1
1
0
0
PTD4/ATD12/TBCLK
0
1
1
0
1
PTD5/ATD13
0
1
1
1
0
PTD6/ATD14/TACLK
Unused(1)
Range 01111 ($0F) to 11010 ($1A)
Unused(1)
1
1
0
1
1
Reserved
1
1
1
0
0
VDDA/VDDAREF(2)
1
1
1
0
1
VREFH(2)
1
1
1
1
0
VSSA/VREFL(2)
1
1
1
1
1
[ADC power off]
1. If any unused channels are selected, the resulting ADC conversion will be unknown.
2. The voltage levels supplied from internal reference nodes as specified in the table
are used to verify the operation of the ADC converter both in production test and for user
applications.
26.7.2 ADC Data Register
One 8-bit result register is provided. This register is updated each time an ADC conversion completes.
Address:
$0039
Bit 7
6
5
4
3
2
1
Bit 0
Read:
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Write:
R
R
R
R
R
R
R
R
Reset:
Indeterminate after reset
R
= Reserved
Figure 26-3. ADC Data Register (ADR)
MC68HC908AT32 Data Sheet, Rev. 3.1
312
Freescale Semiconductor
I/O Registers
26.7.3 ADC Input Clock Register
This register selects the clock frequency for the ADC.
Address:
Read:
Write:
Reset:
$003A
Bit 7
6
5
4
ADIV2
ADIV1
ADIV0
ADICLK
0
0
0
0
R
= Reserved
3
2
1
Bit 0
0
0
0
0
R
R
R
R
0
0
0
0
Figure 26-4. ADC Input Clock Register (ADICLK)
ADIV2–ADIV0 — ADC Clock Prescaler Bits
ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate
the internal ADC clock. Table 26-2 shows the available clock configurations. The ADC clock should be
set to approximately 1 MHz.
Table 26-2. ADC Clock Divide Ratio
ADIV2
ADIV1
ADIV0
ADC Clock Rate
0
0
0
ADC input clock ÷ 1
0
0
1
ADC input clock ÷ 2
0
1
0
ADC input clock ÷ 4
0
1
1
ADC input clock ÷ 8
1
X
X
ADC input clock ÷ 16
X = don’t care
ADICLK — ADC Input Clock Register Bit
ADICLK selects either bus clock or CGMXCLK as the input clock source to generate the internal ADC
clock. Reset selects CGMXCLK as the ADC clock source.
If the external clock (CGMXCLK) is equal to or greater than 1 MHz, CGMXCLK can be used as the
clock source for the ADC. If CGMXCLK is less than 1 MHz, use the PLL-generated bus clock as the
clock source. As long as the internal ADC clock is at approximately 1 MHz, correct operation can be
guaranteed. (See 29.6 ADC Characteristics.)
1 = Internal bus clock
0 = External clock (CGMXCLK)
fXCLK or Bus Frequency
1 MHz = ⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
ADIV[2:0]
NOTE
During the conversion process, changing the ADC clock will result in an
incorrect conversion.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
313
Analog-to-Digital Converter (ADC-15)
MC68HC908AT32 Data Sheet, Rev. 3.1
314
Freescale Semiconductor
Chapter 27
MC68HC08AS20 Emulator Input/Output Ports
27.1 Introduction
Forty bidirectional input/output (I/O) pins form six parallel ports. All I/O pins are programmable as inputs
or outputs.
NOTE
Connect any unused I/O pins to an appropriate logic level, either VDD or
VSS. Although the I/O ports do not require termination for proper operation,
termination reduces excess current consumption and the possibility of
electrostatic damage.
Addr.
$0000
Register Name
Port A Data Register Read:
(PTA) Write:
See page 317. Reset:
$0001
Port B Data Register Read:
(PTB) Write:
See page 318. Reset:
$0002
Port C Data Register Read:
(PTC) Write:
See page 320. Reset:
$0003
$0004
Port D Data Register Read:
(PTD) Write:
See page 322. Reset:
Data Direction Register A Read:
(DDRA) Write:
See page 317. Reset:
Bit 7
6
5
4
3
2
1
Bit 0
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
PTB2
PTB1
PTB0
PTC2
PTC1
PTC0
PTD2
PTD1
PTD0
DDRA2
DDRA1
DDRA0
Unaffected by reset
PTB7
PTB6
0
0
R
R
PTB5
PTB4
PTB3
Unaffected by reset
PTC5
PTC4
PTC3
Unaffected by reset
PTD7
PTD6
PTD5
PTD4
PTD3
Unaffected by reset
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
Unaffected by reset
$0005
Data Direction Register B Read:
(DDRB) Write:
See page 319. Reset:
$0006
Data Direction Register C Read: MCLKEN
(DDRC) Write:
See page 321. Reset:
0
DDRB7
0
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
0
0
0
0
0
0
0
DDRC5
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
0
0
0
0
0
0
0
R
0
Boldface Type = MC68HC08AZ32 Specific
Figure 27-1. MC68HC08AS20 Emulator I/O Port Register Summary
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
315
MC68HC08AS20 Emulator Input/Output Ports
Addr.
$0007
$0008
$0009
$000A
Register Name
Bit 7
Data Direction Register D Read: DDRD7
(DDRD) Write:
See page 323. Reset:
0
Port E Data Register Read:
(PTE) Write:
See page 324. Reset:
Port F Data Register Read:
(PTF) Write:
See page 327.
Reset:
Port G Data Register Read:
(PTG) Write:
See page 247. Reset:
$000B
Port H Data Register Read:
(PTH) Write:
See page 249. Reset:
$000C
Data Direction Register E Read:
(DDRE) Write:
See page 325. Reset:
$000D
Data Direction Register F Read:
(DDRF) Write:
See page 327. Reset:
PTE7
6
5
4
3
2
1
Bit 0
DDRD6
DDRD5
DDRD4
DDRD3
DDR2
DDRD1
DDRD0
0
0
0
0
0
0
0
PTE6
PTE5
PTE4
PTE3
PTE2
PTE1
PTE0
PTF2
PTF1
PTF0
PTG2
PTG1
PTG0
PTH1
PTH0
Unaffected by reset
0
R
PTF6
PTF5
PTF4
PTF3
Unaffected by reset
0
0
0
0
0
R
R
R
R
R
Unaffected by reset
0
0
0
0
0
0
R
R
R
R
R
R
Unaffected by reset
DDRE7
DDRE6
DDRE5
DDRE4
DDRE3
DDRE2
DDRE1
DDRE0
0
0
0
0
0
0
0
0
DDRF6
DDRF5
DDRF4
DDRF3
DDRF2
DDRF1
DDRF0
0
0
0
0
0
0
0
0
R
0
Boldface Type = MC68HC08AZ32 Specific
Figure 27-1. MC68HC08AS20 Emulator I/O Port Register Summary (Continued)
MC68HC908AT32 Data Sheet, Rev. 3.1
316
Freescale Semiconductor
Port A
27.2 Port A
Port A is an 8-bit, general-purpose, bidirectional I/O port.
27.2.1 Port A Data Register
The port A data register contains a data latch for each of the eight
port A pins.
Address:
Read:
Write:
$0000
Bit 7
6
5
4
3
2
1
Bit 0
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
Reset:
Unaffected by reset
Figure 27-2. Port A Data Register (PTA)
PTA[7:0] — Port A Data Bits
These read/write bits are software programmable. Data direction of each port A pin is under the control
of the corresponding bit in data direction register A. Reset has no effect on port A data.
27.2.2 Data Direction Register A
Data direction register A determines whether each port A pin is an input or an output. Writing a logic 1 to
a DDRA bit enables the output buffer for the corresponding port A pin; a logic 0 disables the output
buffer.
Address:
Read:
Write:
$0004
Bit 7
6
5
4
3
2
1
Bit 0
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
Reset:
Unaffected by reset
Figure 27-3. Data Direction Register A (DDRA)
DDRA[7:0] — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears DDRA[7:0], configuring all port A pins
as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 27-4 shows the port A I/O logic.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
317
MC68HC08AS20 Emulator Input/Output Ports
READ DDRA ($0004)
INTERNAL DATA BUS
WRITE DDRA ($0004)
DDRAx
RESET
WRITE PTA ($0000)
PTAx
PTAx
READ PTA ($0000)
Figure 27-4. Port A I/O Circuit
When bit DDRAx is a logic 1, reading address $0000 reads the PTAx data latch. When bit DDRAx is a
logic 0, reading address $0000 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 27-1 summarizes the operation of the port A pins.
Table 27-1. Port A Pin Functions
DDRA
Bit
PTA
Bit
I/O Pin Mode
0
X
1
X
Accesses to
DDRA
Accesses to PTA
Read/Write
Read
Write
Input, Hi-Z
DDRA[7:0]
Pin
PTA[7:0](1)
Output
DDRA[7:0]
PTA[7:0]
PTA[7:0]
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
27.3 Port B
Port B is an 8-bit special-function port that shares all of its pins with the analog-to-digital converter.
27.3.1 Port B Data Register
The port B data register contains a data latch for each of the eight port B pins.
Address:
$0001
Read:
Write:
Bit 7
6
5
4
3
2
1
Bit 0
PTB7
PTB6
PTB5
PTB4
PTB3
PTB2
PTB1
PTB0
ATD2
ATD1
ATD0
Reset:
Alternate Functions:
Unaffected by reset
ATD7
ATD6
ATD5
ATD4
ATD3
Figure 27-5. Port B Data Register (PTB)
PTB[7:0] — Port B Data Bits
These read/write bits are software programmable. Data direction of each port B pin is under the control
of the corresponding bit in data direction register B. Reset has no effect on port B data.
MC68HC908AT32 Data Sheet, Rev. 3.1
318
Freescale Semiconductor
Port B
ATD[7:0] — ADC Channels
PTB7/ATD7–PTB0/ATD0 are eight of the 15 analog-to-digital converter channels. The ADC channel
select bits, CH[4:0], determine whether the PTB7/ATD7–PTB0/ATD0 pins are ADC channels or
general-purpose I/O pins. If an ADC channel is selected and a read of this corresponding bit in the port
B data register occurs, the data will be 0 if the data direction for this bit is programmed as an input.
Otherwise, the data will reflect the value in the data latch. (See Chapter 26 Analog-to-Digital Converter
(ADC-15).) Data direction register B (DDRB) does not affect the data direction of port B pins that are
being used by the ADC. However, the DDRB bits always determine whether reading port B returns to
the states of the latches or logic 0.
27.3.2 Data Direction Register B
Data direction register B determines whether each port B pin is an input or an output. Writing a logic 1 to
a DDRB bit enables the output buffer for the corresponding port B pin; a logic 0 disables the output
buffer.
Address:
Read:
Write:
Reset:
$0005
Bit 7
6
5
4
3
2
1
Bit 0
DDRB7
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
0
0
0
0
0
0
0
0
Figure 27-6. Data Direction Register B (DDRB)
DDRB[7:0] — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears DDRB[7:0], configuring all port B pins
as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE
Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1.
Figure 27-7 shows the port B I/O logic.
READ DDRB ($0005)
INTERNAL DATA BUS
WRITE DDRB ($0005)
RESET
DDRBx
WRITE PTB ($0001)
PTBx
PTBx
READ PTB ($0001)
Figure 27-7. Port B I/O Circuit
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
319
MC68HC08AS20 Emulator Input/Output Ports
When bit DDRBx is a logic 1, reading address $0001 reads the PTBx data latch. When bit DDRBx is a
logic 0, reading address $0001 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 27-2 summarizes the operation of the port B pins.
Table 27-2. Port B Pin Functions
DDRB
Bit
PTB
Bit
I/O Pin
Mode
0
X
1
X
Accesses to
DDRB
Accesses to PTB
Read/Write
Read
Write
Input, Hi-Z
DDRB[7:0]
Pin
PTB[7:0](1)
Output
DDRB[7:0]
PTB[7:0]
PTB[7:0]
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
27.4 Port C
Port C is a 5-bit, general-purpose, bidirectional I/O port.
27.4.1 Port C Data Register
The port C data register contains a data latch for each of the five port C pins.
Address:
$0002
Bit 7
6
5
Read:
0
0
0
Write:
R
R
R
Reset:
Alternate
Functions:
4
3
2
1
Bit 0
PTC4
PTC3
PTC2
PTC1
PTC0
MCLK
R
R
Unaffected by reset
R
= Reserved
R
R
R
R
R
Figure 27-8. Port C Data Register (PTC)
PTC[4:0] — Port C Data Bits
These read/write bits are software-programmable. Data direction of each port C pin is under the control
of the corresponding bit in data direction register C. Reset has no effect on port C data.
MCLK — T12 System Clock Bit
The system clock is driven out of PTC2 when enabled by MCLKEN bit in PTCDDR7.
MC68HC908AT32 Data Sheet, Rev. 3.1
320
Freescale Semiconductor
Port C
27.4.2 Data Direction Register C
Data direction register C determines whether each port C pin is an input or an output. Writing a logic 1 to
a DDRC bit enables the output buffer for the corresponding port C pin; a logic 0 disables the output
buffer.
Address:
$0006
Bit 7
Read:
Write:
Reset:
6
5
0
0
R
R
0
0
0
R
= Reserved
MCLKEN
4
3
2
1
Bit 0
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
0
0
0
0
0
Figure 27-9. Data Direction Register C (DDRC)
MCLKEN — MCLK Enable Bit
This read/write bit enables MCLK to be an output signal on PTC2. If MCLK is enabled, PTC2 is under
the control of MCLKEN. Reset clears this bit.
1 = MCLK output enabled
0 = MCLK output disabled
DDRC[4:0] — Data Direction Register C Bits
These read/write bits control port C data direction. Reset clears DDRC[7:0], configuring all port C pins
as inputs.
1 = Corresponding port C pin configured as output
0 = Corresponding port C pin configured as input
NOTE
Avoid glitches on port C pins by writing to the port C data register before
changing data direction register C bits from 0 to 1.
Figure 27-10 shows the port C I/O logic.
READ DDRC ($0006)
INTERNAL DATA BUS
WRITE DDRC ($0006)
RESET
DDRCx
WRITE PTC ($0002)
PTCx
PTCx
READ PTC ($0002)
Figure 27-10. Port C I/O Circuit
When bit DDRCx is a logic 1, reading address $0002 reads the PTCx data latch. When bit DDRCx is a
logic 0, reading address $0002 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 27-3 summarizes the operation of the port C pins.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
321
MC68HC08AS20 Emulator Input/Output Ports
Table 27-3. Port C Pin Functions
DDRC
Bit
PTC
Bit
I/O Pin
Mode
0
2
1
Accesses to
DDRC
Accesses to PTC
Read/Write
Read
Write
Input, Hi-Z
DDRC[7]
Pin
PTC2
2
Output
DDRC[7]
0
—
0
X
Input, Hi-Z
DDRC[4:0]
Pin
PTC[4:0](1)
1
X
Output
DDRC[4:0]
PTC[4:0]
PTC[4:0]
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
27.5 Port D
Port D is an 8-bit, general-purpose I/O port.
27.5.1 Port D Data Register
Port D is a 7-bit special function port that shares all of its pins with the analog-to-digital converter.
Address:
$0003
Bit 7
Read:
0
Write:
R
6
5
4
3
2
1
Bit 0
PTD6
PTD5
PTD4
PTD3
PTD2
PTD1
PTD0
ATD10
ATD9
ATD8
Reset:
Alternate Functions:
Unaffected by reset
R
ATD14/
TACLK
R
= Reserved
ATD13
ATD12
ATD11
Figure 27-11. Port D Data Register (PTD)
PTD[6:0] — Port D Data Bits
PTD[6:0] are read/write, software programmable bits. Data direction of PTD[6:0] pins are under the
control of the corresponding bit in data direction register D.
ATD[14:8] — ADC Channel Status Bits
PTD6/ATD14/TACLK–PTD0/ATD8 are seven of the 15 analog-to-digital converter channels. The ADC
channel select bits, CH[4:0], determine whether the PTD6/ATD14/TACLK–PTD0/ATD8 pins are ADC
channels or general-purpose I/O pins. If an ADC channel is selected and a read of this corresponding
bit in the port B data register occurs, the data will be 0 if the data direction for this bit is programmed
as an input. Otherwise, the data will reflect the value in the data latch. See Chapter 26 Analog-to-Digital
Converter (ADC-15).
NOTE
Data direction register D (DDRD) does not affect the data direction of port
D pins that are being used by the ADC. However, the DDRD bits always
determine whether reading port D returns the states of the latches or
logic 0.
MC68HC908AT32 Data Sheet, Rev. 3.1
322
Freescale Semiconductor
Port D
TACLK — Timer Clock Input Bit
The PTD6/ATD14/TACLK pin is the external clock input for the TIMA. The prescaler select bits,
PS[2:0], select PTD6/ATD14/TACLK as the TIMA clock input. (See 25.8.1 TIMA Status and Control
Register.) When not selected as the TIMA clock, PTD6/ATD14/TACLK is available for general-purpose
I/O or as an ADC channel.
NOTE
Do not use ADC channel ATD14 when using the PTD6/ATD14/TACLK pin
as the clock input for the TIMA.
27.5.2 Data Direction Register D
Data direction register D determines whether each port D pin is an input or an output. Writing a logic 1 to
a DDRD bit enables the output buffer for the corresponding port D pin; a logic 0 disables the output
buffer.
Address:
$0007
Bit 7
Read:
0
Write:
0
Reset:
0
6
5
4
3
2
1
Bit 0
DDRD6
DDRD5
DDRD4
DDRD3
DDRD2
DDRD1
DDRD0
0
0
0
0
0
0
0
Figure 27-12. Data Direction Register D (DDRD)
DDRD[6:0] — Data Direction Register D Bits
These read/write bits control port D data direction. Reset clears DDRD[6:0], configuring all port D pins
as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
NOTE
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
Figure 27-13 shows the port D I/O logic.
READ DDRD ($0007)
INTERNAL DATA BUS
WRITE DDRD ($0007)
RESET
DDRDx
WRITE PTD ($0003)
PTDx
PTDx
READ PTD ($0003)
Figure 27-13. Port D I/O Circuit
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
323
MC68HC08AS20 Emulator Input/Output Ports
When bit DDRDx is a logic 1, reading address $0003 reads the PTDx data latch. When bit DDRDx is a
logic 0, reading address $0003 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 27-4 summarizes the operation of the port D pins.
Table 27-4. Port D Pin Functions
DDRD
Bit
PTD
Bit
I/O Pin
Mode
0
X
1
X
Accesses
to DDRD
Accesses to PTD
Read/Write
Read
Write
Input, Hi-Z
DDRD[6:0]
Pin
PTD[6:0](1)
Output
DDRD[6:0]
PTD[6:0]
PTD[6:0]
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
27.6 Port E
Port E is an 8-bit special function port that shares two of its pins with the timer interface module (TIMA),
two of its pins with the serial communications interface module (SCI), and four of its pins with the serial
peripheral interface module (SPI).
27.6.1 Port E Data Register
The port E data register contains a data latch for each of the eight port E pins.
Address:
Read:
Write:
$0008
Bit 7
6
5
4
3
2
1
Bit 0
PTE7
PTE6
PTE5
PTE4
PTE3
PTE2
PTE1
PTE0
SPSCK
MOSI
MISO
TACH0
RxD
TxD
Reset:
Alternate Function:
Unaffected by reset
SS
TACH1
Figure 27-14. Port E Data Register (PTE)
PTE[7:0] — Port E Data Bits
PTE[7:0] are read/write, software programmable bits. Data direction of each port E pin is under the
control of the corresponding bit in data direction register E.
SPSCK — SPI Serial Clock Bit
The PTE7/SPSCK pin is the serial clock input of an SPI slave module and serial clock output of an SPI
master module. When the SPE bit is clear, the PTE7/SPSCK pin is available for general-purpose I/O.
MOSI — Master Out/Slave In Bit
The PTE6/MOSI pin is the master out/slave in terminal of the SPI module. When the SPE bit is clear,
the PTE6/MOSI pin is available for general-purpose I/O. See 17.13.1 SPI Control Register.
MISO — Master In/Slave Out Bit
The PTE5/MISO pin is the master in/slave out terminal of the SPI module. When the SPI enable bit,
SPE, is clear, the SPI module is disabled, and the PTE5/MISO pin is available for general-purpose I/O.
See 17.13.1 SPI Control Register.
MC68HC908AT32 Data Sheet, Rev. 3.1
324
Freescale Semiconductor
Port E
SS — Slave Select Bit
The PTE4/SS pin is the slave select input of the SPI module. When the SPE bit is clear, or when the
SPI master bit, SPMSTR, is set and MODFEN bit is low, the PTE4/SS pin is available for
general-purpose I/O. (See 17.12.4 SS (Slave Select).) When the SPI is enabled as a slave, the DDRF4
bit in data direction register E (DDRE) has no effect on the PTE4/SS pin.
NOTE
Data direction register E (DDRE) does not affect the data direction of port
E pins that are being used by the SPI module. However, the DDRE bits
always determine whether reading port E returns the states of the latches
or the states of the pins. (See Table 27-5.)
TACH[1:0] — Timer Channel I/O Bits
The PTE3/TACH1–PTE2/TACH0 pins are the TIMA input capture/output compare pins. The
edge/level select bits, ELSxB–ELSxA, determine whether the PTE3/TACH1–PTE2/TACH0 pins are
timer channel I/O pins or general-purpose I/O pins. See 25.8.4 TIMA Channel Status and Control
Registers.
NOTE
Data direction register E (DDRE) does not affect the data direction of port
E pins that are being used by the TIMA. However, the DDRE bits always
determine whether reading port E returns the states of the latches or the
states of the pins. (See Table 27-5.)
RxD — SCI Receive Data Input Bit
The PTE1/RxD pin is the receive data input for the SCI module. When the enable SCI bit, ENSCI, is
clear, the SCI module is disabled, and the PTE1/RxD pin is available for general-purpose I/O. See
16.8.1 SCI Control Register 1.
TxD — SCI Transmit Data Output
The PTE0/TxD pin is the transmit data output for the SCI module. When the enable SCI bit, ENSCI, is
clear, the SCI module is disabled, and the PTE0/TxD pin is available for general-purpose I/O. See
16.8.1 SCI Control Register 1.
NOTE
Data direction register E (DDRE) does not affect the data direction of port
E pins that are being used by the SCI module. However, the DDRE bits
always determine whether reading port E returns the states of the latches
or the states of the pins. (See Table 27-5.)
27.6.2 Data Direction Register E
Data direction register E determines whether each port E pin is an input or an output. Writing a logic 1 to
a DDRE bit enables the output buffer for the corresponding port E pin; a logic 0 disables the output
buffer.
Address:
Read:
Write:
Reset:
$000C
Bit 7
6
5
4
3
2
1
Bit 0
DDRE7
DDRE6
DDRE5
DDRE4
DDRE3
DDRE2
DDRE1
DDRE0
0
0
0
0
0
0
0
0
Figure 27-15. Data Direction Register E (DDRE)
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
325
MC68HC08AS20 Emulator Input/Output Ports
DDRE[7:0] — Data Direction Register E Bits
These read/write bits control port E data direction. Reset clears DDRE[7:0], configuring all port E pins
as inputs.
1 = Corresponding port E pin configured as output
0 = Corresponding port E pin configured as input
NOTE
Avoid glitches on port E pins by writing to the port E data register before
changing data direction register E bits from 0 to 1.
Figure 27-16 shows the port E I/O logic.
READ DDRE ($000C)
INTERNAL DATA BUS
WRITE DDRE ($000C)
DDREx
RESET
WRITE PTE ($0008)
PTEx
PTEx
READ PTE ($0008)
Figure 27-16. Port E I/O Circuit
When bit DDREx is a logic 1, reading address $0008 reads the PTEx data latch. When bit DDREx is a
logic 0, reading address $0008 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 27-5 summarizes the operation of the port E pins.
Table 27-5. Port E Pin Functions
DDRE
Bit
PTE
Bit
I/O Pin
Mode
0
X
1
X
Accesses to
DDRE
Accesses to PTE
Read/Write
Read
Write
Input, Hi-Z
DDRE[7:0]
Pin
PTE[7:0](1)
Output
DDRE[7:0]
PTE[7:0]
PTE[7:0]
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
MC68HC908AT32 Data Sheet, Rev. 3.1
326
Freescale Semiconductor
Port F
27.7 Port F
Port F is a 4-bit special function port that shares four of its pins with the timer interface module (TIMA).
27.7.1 Port F Data Register
The port F data register contains a data latch for each of the six port F pins.
Address:
$0009
Bit 7
6
5
4
Read:
0
0
0
0
Write:
R
R
R
R
3
2
1
Bit 0
PTF3
PTF2
PTF1
PTF0
TACH4
TACH3
TACH2
Reset:
Unaffected by reset
Alternate Function:
TACH5
R
= Reserved
Figure 27-17. Port F Data Register (PTF)
PTF[3:0] — Port F Data Bits
These read/write bits are software programmable. Data direction of each port F pin is under the control
of the corresponding bit in data direction register F. Reset has no effect on PTF[3:0].
TACH[5:2] — Timer Channel I/O Bits
The PTF3/TACH5–PTF0/TACH2 pins are the TIMA input capture/output compare pins. The edge/level
select bits, ELSxB–ELSxA, determine whether the PTF3/TACH5–PTF0/TACH2 pins are timer channel
I/O pins or general-purpose I/O pins. See 25.8.4 TIMA Channel Status and Control Registers.
NOTE
Data direction register F (DDRF) does not affect the data direction of port F
pins that are being used by the TIMA. However, the DDRF bits always
determine whether reading port F returns the states of the latches or the
states of the pins. (See Table 27-6.)
27.7.2 Data Direction Register F
Data direction register F determines whether each port F pin is an input or an output. Writing a logic 1 to
a DDRF bit enables the output buffer for the corresponding port F pin; a logic 0 disables the output
buffer.
Address:
$000D
Bit 7
6
5
4
Read:
0
0
0
0
Write:
R
R
R
R
Reset:
0
0
0
0
R
= Reserved
3
2
1
Bit 0
DDRF3
DDRF2
DDRF1
DDRF0
0
0
0
0
Figure 27-18. Data Direction Register F (DDRF)
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
327
MC68HC08AS20 Emulator Input/Output Ports
DDRF[3:0] — Data Direction Register F Bits
These read/write bits control port F data direction. Reset clears DDRF[3:0], configuring all port F pins
as inputs.
1 = Corresponding port F pin configured as output
0 = Corresponding port F pin configured as input
NOTE
Avoid glitches on port F pins by writing to the port F data register before
changing data direction register F bits from 0 to 1.
Figure 27-19 shows the port F I/O logic.
READ DDRF ($000D)
INTERNAL DATA BUS
WRITE DDRF ($000D)
DDRFx
RESET
WRITE PTF ($0009)
PTFx
PTFx
READ PTF ($0009)
Figure 27-19. Port F I/O Circuit
When bit DDRFx is a logic 1, reading address $0009 reads the PTFx data latch. When bit DDRFx is a
logic 0, reading address $0009 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 27-6 summarizes the operation of the port F pins.
Table 27-6. Port F Pin Functions
DDRF
Bit
PTF
Bit
I/O Pin
Mode
0
X
1
X
Accesses to
DDRF
Accesses to PTF
Read/Write
Read
Write
Input, Hi-Z
DDRF[3:0]
Pin
PTF[3:0](1)
Output
DDRF[3:0]
PTF[3:0]
PTF[3:0]
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
MC68HC908AT32 Data Sheet, Rev. 3.1
328
Freescale Semiconductor
Chapter 28
Byte Data Link Controller-Digital (BDLC-D)
28.1 Introduction
The byte data link controller (BDLC) provides access to an external serial communication multiplex bus,
operating according to the SAE J1850 protocol.
28.2 Features
Features of the byte data link controller (BDLC) module include:
• SAE J1850 Class B Data Communications Network Interface compatible and ISO compatible for
low-speed (<125 kbps) serial data communications in automotive applications
• 10.4 kbps variable pulse width (VPW) bit format
• Digital noise filter
• Collision detection
• Hardware cyclical redundancy check (CRC) generation and checking
• Two power-saving modes with automatic wakeup on network activity
• Polling or central processor unit (CPU) interrupts
• Block mode receive and transmit supported
• 4X receive mode, 41.6 kbps, supported
• Digital loopback mode
• Analog loopback mode
• In-frame response (IFR) types 0, 1, 2, and 3 supported
28.3 Functional Description
Figure 28-1 shows the organization of the BDLC module. The CPU interface contains the software
addressable registers and provides the link between the CPU and the buffers. The buffers provide storage
for data received and data to be transmitted onto the J1850 bus. The protocol handler is responsible for
the encoding and decoding of data bits and special message symbols during transmission and reception.
The multiplex (MUX) interface provides the link between the BDLC digital section and the analog physical
interface. The wave shaping, driving, and digitizing of data is performed by the physical interface.
Use of the BDLC module in message networking fully implements the SAE Standard J1850 Class B Data
Communication Network Interface specification.
NOTE
It is recommended that the reader be familiar with the SAE J1850 document
and ISO Serial Communication document prior to proceeding with this
section.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
329
Byte Data Link Controller-Digital (BDLC-D)
TO CPU
CPU INTERFACE
PROTOCOL HANDLER
MUX INTERFACE
PHYSICAL INTERFACE
BDLC
TO J1850 BUS
Figure 28-1. BDLC Block Diagram
Addr.
$003B
Name
BDLC Analog and Round-Trip Read:
Delay Register (BARD) Write:
See page 347. Reset:
$003C
BDLC Control Register 1 Read:
(BCR1) Write:
See page 348. Reset:
$003D
BDLC Control Register 2 Read:
(BCR2) Write:
See page 349. Reset:
$003E
$003F
BDLC State Vector Register Read:
(BSVR) Write:
See page 354. Reset:
BDLC Data Register Read:
(BDR) Write:
See page 355. Reset:
Bit 7
6
5
4
3
2
1
Bit 0
ATE
RXPOL
0
0
BO3
BO2
BO1
BO0
1
1
0
0
0
1
1
1
IMSG
CLKS
R1
R0
0
0
R
R
IE
WCM
1
1
1
0
0
0
0
0
ALOOP
DLOOP
RX4XE
NBFS
TEOD
TSIFR
TMIFR1
TMIFR0
1
1
0
0
0
0
0
0
0
0
I3
I2
I1
I0
0
0
0
0
0
0
0
0
0
0
BD7
BD6
BD5
BD4
BD3
BD2
BD1
BD0
Indeterminate after reset
= Unimplemented
R
= Reserved
Table 28-1. BDLC Input/Output (I/O) Register Summary
MC68HC908AT32 Data Sheet, Rev. 3.1
330
Freescale Semiconductor
Functional Description
28.3.1 BDLC Operating Modes
The BDLC has five main modes of operation which interact with the power supplies, pins, and reset of the
MCU as shown in Figure 28-2.
28.3.1.1 Power Off Mode
For the BDLC to guarantee operation, this mode is entered from reset mode whenever the BDLC supply
voltage, VDD, drops below its minimum specified value. The BDLC will be placed in reset mode by
low-voltage reset (LVR) before being powered down. In power off mode, the pin input and output
specifications are not guaranteed.
POWER OFF
VDD > VDD (MINIMUM) AND
ANY MCU RESET SOURCE ASSERTED
VDD ≤ VDD (MINIMUM)
RESET
ANY MCU RESET SOURCE ASSERTED
FROM ANY MODE
(COP, ILLADDR, PU, RESET, LVR, POR)
NETWORK ACTIVITY OR
OTHER MCU WAKEUP
NO MCU RESET SOURCE ASSERTED
NETWORK ACTIVITY OR
OTHER MCU WAKEUP
RUN
BDLC WAIT
BDLC STOP
STOP INSTRUCTION OR
WAIT INSTRUCTION AND WCM = 1
WAIT INSTRUCTION AND WCM = 0
Figure 28-2. BDLC Operating Modes State Diagram
28.3.1.2 Reset Mode
This mode is entered from power off mode whenever the BDLC supply voltage, VDD, rises above its
minimum specified value
(VDD –10 percent) and some MCU reset source is asserted. The internal MCU reset must be asserted
while powering up the BDLC or an unknown state will be entered and correct operation cannot be
guaranteed. Reset mode is also entered from any other mode as soon as one of the MCU’s possible reset
sources (such as LVR, POR, COP watchdog, reset pin, etc.) is asserted.
In reset mode, the internal BDLC voltage references are operative, VDD is supplied to the internal circuits
which are held in their reset state, and the internal BDLC system clock is running. Registers will assume
their reset condition. Because outputs are held in their programmed reset state, inputs and network
activity are ignored.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
331
Byte Data Link Controller-Digital (BDLC-D)
28.3.1.3 Run Mode
This mode is entered from reset mode after all MCU reset sources are no longer asserted. Run mode is
entered from the BDLC wait mode whenever activity is sensed on the J1850 bus.
Run mode is entered from the BDLC stop mode whenever network activity is sensed, although messages
will not be received properly until the clocks have stabilized and the CPU is also in run mode.
In this mode, normal network operation takes place. The user should ensure that all BDLC transmissions
have ceased before exiting this mode.
28.3.1.4 BDLC Wait Mode
This power-conserving mode is entered automatically from run mode whenever the CPU executes a
WAIT instruction and if the WCM bit in the BCR1 register is cleared previously.
In this mode, the BDLC internal clocks continue to run. The first passive-to-active transition of the bus
generates a CPU interrupt request from the BDLC, which wakes up the BDLC and the CPU. In addition,
if the BDLC receives a valid end-of-frame (EOF) symbol while operating in wait mode, then the BDLC also
will generate a CPU interrupt request, which wakes up the BDLC and the CPU. See 28.7.1 Wait Mode.
28.3.1.5 BDLC Stop Mode
This power-conserving mode is entered automatically from run mode whenever the CPU executes a
STOP instruction or if the CPU executes a WAIT instruction and the WCM bit in the BCR1 is set
previously.
In this mode, the BDLC internal clocks are stopped but the physical interface circuitry is placed in a
low-power mode and awaits network activity. If network activity is sensed, then a CPU interrupt request
will be generated, restarting the BDLC internal clocks. See 28.7.2 Stop Mode.
28.3.1.6 Digital Loopback Mode
When a bus fault has been detected, the digital loopback mode is used to determine if the fault condition
is caused by failure in the node’s internal circuits or elsewhere in the network, including the node’s analog
physical interface. In this mode, the transmit digital output pin (BDTxD) and the receive digital input pin
(BDRxD) of the digital interface are disconnected from the analog physical interface and tied together to
allow the digital portion of the BDLC to transmit and receive its own messages without driving the J1850
bus.
28.3.1.7 Analog Loopback Mode
Analog loopback mode is used to determine if a bus fault has been caused by a failure in the node’s
off-chip analog transceiver or elsewhere in the network. The BDLC analog loopback mode does not
modify the digital transmit or receive functions of the BDLC. It does, however, ensure that once analog
loopback mode is exited, the BDLC will wait for an idle bus condition before participation in network
communication resumes. If the off-chip analog transceiver has a loopback mode, it usually causes the
input to the output drive stage to be looped back into the receiver, allowing the node to receive messages
it has transmitted without driving the J1850 bus. In this mode, the output to the J1850 bus typically is high
impedance. This allows the communication path through the analog transceiver to be tested without
interfering with network activity. Using the BDLC analog loopback mode in conjunction with the analog
transceiver’s loopback mode ensures that, once the off-chip analog transceiver has exited loopback
mode, the BCLD will not begin communicating before a known condition exists on the J1850 bus.
MC68HC908AT32 Data Sheet, Rev. 3.1
332
Freescale Semiconductor
BDLC MUX Interface
28.4 BDLC MUX Interface
The MUX interface is responsible for bit encoding/decoding and digital noise filtering between the protocol
handler and the physical interface.
TO CPU
CPU INTERFACE
PROTOCOL HANDLER
MUX INTERFACE
PHYSICAL INTERFACE
BDLC
TO J1850 BUS
Figure 28-3. BDLC Block Diagram
28.4.1 Rx Digital Filter
The receiver section of the BDLC includes a digital low pass filter to remove narrow noise pulses from the
incoming message. An outline of the digital filter is shown in Figure 28-4.
RX DATA
FROM
PHYSICAL
INTERFACE
(BDRXD)
INPUT
SYNC
4-BIT UP/DOWN COUNTER
DATA
LATCH
FILTERED
RX DATA OUT
D
Q
UP/DOWN
OUT
D
Q
MUX
INTERFACE
CLOCK
Figure 28-4. BDLC Rx Digital Filter Block Diagram
28.4.1.1 Operation
The clock for the digital filter is provided by the MUX interface clock (see fBDLC parameter in Table 28-4).
At each positive edge of the clock signal, the current state of the receiver physical interface (BDRxD)
signal is sampled. The BDRxD signal state is used to determine whether the counter should increment or
decrement at the next negative edge of the clock signal.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
333
Byte Data Link Controller-Digital (BDLC-D)
The counter will increment if the input data sample is high but decrement if the input sample is low.
Therefore, the counter will thus progress either up toward 15 if, on average, the BDRxD signal remains
high or progress down toward 0 if, on average, the BDRxD signal remains low.
When the counter eventually reaches the value 15, the digital filter decides that the condition of the
BDRxD signal is at a stable logic level 1 and the data latch is set, causing the filtered Rx data signal to
become a logic level 1. Furthermore, the counter is prevented from overflowing and can be decremented
only from this state.
Alternatively, should the counter eventually reach the value 0, the digital filter decides that the condition
of the BDRxD signal is at a stable logic level 0 and the data latch is reset, causing the filtered Rx data
signal to become a logic level 0. Furthermore, the counter is prevented from underflowing and can only
be incremented from this state.
The data latch will retain its value until the counter next reaches the opposite end point, signifying a
definite transition of the signal.
28.4.1.2 Performance
The performance of the digital filter is best described in the time domain rather than the frequency domain.
If the signal on the BDRxD signal transitions, then there will be a delay before that transition appears at
the filtered Rx data output signal. This delay will be between 15 and 16 clock periods, depending on where
the transition occurs with respect to the sampling points. This filter delay must be taken into account when
performing message arbitration.
For example, if the frequency of the MUX interface clock (fBDLC) is 1.0486 MHz, then the period (tBDLC)
is 954 ns and the maximum filter delay in the absence of noise will be 15.259 µs.
The effect of random noise on the BDRxD signal depends on the characteristics of the noise itself. Narrow
noise pulses on the BDRxD signal will be ignored completely if they are shorter than the filter delay. This
provides a degree of low pass filtering.
If noise occurs during a symbol transition, the detection of that transition can be delayed by an amount
equal to the length of the noise burst. This is just a reflection of the uncertainty of where the transition is
truly occurring within the noise.
Noise pulses that are wider than the filter delay, but narrower than the shortest allowable symbol length,
will be detected by the next stage of the BDLC’s receiver as an invalid symbol.
Noise pulses that are longer than the shortest allowable symbol length will be detected normally as an
invalid symbol or as invalid data when the frame’s CRC is checked.
28.4.2 J1850 Frame Format
All messages transmitted on the J1850 bus are structured using the format shown in Figure 28-5.
J1850 states that each message has a maximum length of 101 PWM bit times or 12 VPW bytes, excluding
SOF, EOD, NB, and EOF, with each byte transmitted most significant bit (MSB) first.
All VPW symbol lengths in the following descriptions are typical values at a 10.4-kbps bit rate.
MC68HC908AT32 Data Sheet, Rev. 3.1
334
Freescale Semiconductor
BDLC MUX Interface
DATA
IDLE
SOF
PRIORITY
(Data0)
MESSAGE ID
(DATA1)
DATAn
CRC
E
O
D
OPTIONAL
N
B
IFR
EOF
I
F
S
IDLE
Figure 28-5. J1850 Bus Message Format (VPW)
SOF — Start-of-Frame Symbol
All messages transmitted onto the J1850 bus must begin with a long-active 200 µs period SOF symbol.
This indicates the start of a new message transmission. The SOF symbol is not used in the CRC
calculation.
Data — In-Message Data Bytes
The data bytes contained in the message include the message priority/type, message ID byte (typically
the physical address of the responder), and any actual data being transmitted to the receiving node.
The message format used by the BDLC is similar to the 3-byte consolidated header message format
outlined by the SAE J1850 document. See SAE J1850 Class B Data Communications Network
Interface for more information about 1- and 3-byte headers.
Messages transmitted by the BDLC onto the J1850 bus must contain at least one data byte, and,
therefore, can be as short as one data byte and one CRC byte. Each data byte in the message is eight
bits in length and is transmitted MSB to LSB (least significant bit).
CRC — Cyclical Redundancy Check Byte
This byte is used by the receiver(s) of each message to determine if any errors have occurred during
the transmission of the message. The BDLC calculates the CRC byte and appends it onto any
messages transmitted onto the J1850 bus. It also performs CRC detection on any messages it
receives from the J1850 bus.
CRC generation uses the divisor polynomial X8 + X4 + X3 + X2 + 1. The remainder polynomial initially
is set to all 1s. Each byte in the message after the start-of-frame (SOF) symbol is processed serially
through the CRC generation circuitry. The one’s complement of the remainder then becomes the 8-bit
CRC byte, which is appended to the message after the data bytes, in MSB-to-LSB order.
When receiving a message, the BDLC uses the same divisor polynomial. All data bytes, excluding the
SOF and end of data symbols (EOD) but including the CRC byte, are used to check the CRC. If the
message is error free, the remainder polynomial will equal X7 + X6 + X2 = $C4, regardless of the data
contained in the message. If the calculated CRC does not equal $C4, the BDLC will recognize this as
a CRC error and set the CRC error flag in the BSVR.
EOD — End-of-Data Symbol
The EOD symbol is a long 200-µs passive period on the J1850 bus used to signify to any recipients of
a message that the transmission by the originator has completed. No flag is set upon reception of the
EOD symbol.
IFR — In-Frame Response Bytes
The IFR section of the J1850 message format is optional. Users desiring further definition of in-frame
response should review the SAE J1850 Class B Data Communications Network Interface
specification.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
335
Byte Data Link Controller-Digital (BDLC-D)
EOF — End-of-Frame Symbol
This symbol is a long 280-µs passive period on the J1850 bus and is longer than an end-of-data (EOD)
symbol, which signifies the end of a message. Since an EOF symbol is longer than a 200-µs EOD
symbol, if no response is transmitted after an EOD symbol, it becomes an EOF, and the message is
assumed to be completed. The EOF flag is set upon receiving the EOF symbol.
IFS — Inter-Frame Separation Symbol
The IFS symbol is a 20-µs passive period on the J1850 bus which allows proper synchronization
between nodes during continuous message transmission. The IFS symbol is transmitted by a node
after the completion of the end-of-frame (EOF) period and, therefore is seen as a 300-µs passive
period.
When the last byte of a message has been transmitted onto the J1850 bus and the EOF symbol time
has expired, all nodes then must wait for the IFS symbol time to expire before transmitting a
start-of-frame (SOF) symbol, marking the beginning of another message.
However, if the BDLC is waiting for the IFS period to expire before beginning a transmission and a
rising edge is detected before the IFS time has expired, it will synchronize internally to that edge.
A rising edge may occur during the IFS period because of varying clock tolerances and loading of the
J1850 bus, causing different nodes to observe the completion of the IFS period at different times. To
allow for individual clock tolerances, receivers must synchronize to any SOF occurring during an IFS
period.
BREAK — Break
The BDLC cannot transmit a BREAK symbol.
If the BDLC is transmitting at the time a BREAK is detected, it treats the BREAK as if a transmission
error had occurred and halts transmission.
If the BDLC detects a BREAK symbol while receiving a message, it treats the BREAK as a reception
error and sets the invalid symbol flag in the BSVR, also ignoring the frame it was receiving. If while
receiving a message in 4X mode, the BDLC detects a BREAK symbol, it treats the BREAK as a
reception error, sets the invalid symbol flag, and exits 4X mode (for example, the RX4XE bit in BCR2
is cleared automatically). If bus control is required after the BREAK symbol is received and the IFS
time has elapsed, the programmer must resend the transmission byte using highest priority.
NOTE
The J1850 protocol BREAK symbol is not related to the HC08 break
module. See Chapter 11 Break Module (BRK).
IDLE — Idle Bus
An idle condition exists on the bus during any passive period after expiration of the IFS period (for
example, > 300 µs). Any node sensing an idle bus condition can begin transmission immediately.
28.4.3 J1850 VPW Symbols
Huntsinger’s variable pulse-width modulation (VPW) is an encoding technique in which each bit is defined
by the time between successive transitions and by the level of the bus between transitions, (for instance,
active or passive). Active and passive bits are used alternately. This encoding technique is used to reduce
the number of bus transitions for a given bit rate.
Each logic 1 or logic 0 contains a single transition and can be at either the active or passive level and one
of two lengths, either 64 µs or 128 µs (tNOM at 10.4 kbps baud rate), depending upon the encoding of the
previous bit. The start-of-frame (SOF), end-of-data (EOD), end-of-frame (EOF), and inter-frame
separation (IFS) symbols always will be encoded at an assigned level and length. See Figure 28-6.
MC68HC908AT32 Data Sheet, Rev. 3.1
336
Freescale Semiconductor
BDLC MUX Interface
ACTIVE
128 µs
OR
64 µs
OR
64 µs
PASSIVE
(A) LOGIC 0
ACTIVE
128 µs
PASSIVE
(B) LOGIC 1
ACTIVE
≥ 240 µs
200 µs
200 µs
PASSIVE
(C) BREAK
(D) START OF FRAME
(E) END OF DATA
300 µs
ACTIVE
280 µs
20 µs
IDLE > 300 µs
PASSIVE
(F) END OF FRAME
(G) INTER-FRAME
SEPARATION
(H) IDLE
Figure 28-6. J1850 VPW Symbols with Nominal Symbol Times
Each message will begin with an SOF symbol, an active symbol, and, therefore, each data byte (including
the CRC byte) will begin with a passive bit, regardless of whether it is a logic 1 or a logic 0.
All VPW bit lengths stated in the following descriptions are typical values at a 10.4-kbps bit rate. EOF,
EOD, IFS, and IDLE, however, are not driven J1850 bus states. They are passive bus periods observed
by each node’s CPU.
Logic 0
A logic 0 is defined as either:
– An active-to-passive transition followed by a passive period 64 µs in length, or
– A passive-to-active transition followed by an active period 128 µs in length
See Figure 28-6(a).
Logic 1
A logic 1 is defined as either:
– An active-to-passive transition followed by a passive period 128 µs in length, or
– A passive-to-active transition followed by an active period 64 µs in length
See Figure 28-6(b).
Normalization Bit (NB)
The NB symbol has the same property as a logic 1 or a logic 0. It is only used in IFR message
responses.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
337
Byte Data Link Controller-Digital (BDLC-D)
Break Signal (BREAK)
The BREAK signal is defined as a passive-to-active transition followed by an active period of at least
240 µs (see Figure 28-6(c)).
Start-of-Frame Symbol (SOF)
The SOF symbol is defined as passive-to-active transition followed by an active period 200 µs in length
(see Figure 28-6(d)). This allows the data bytes which follow the SOF symbol to begin with a passive
bit, regardless of whether it is a logic 1 or a logic 0.
End-of-Data Symbol (EOD)
The EOD symbol is defined as an active-to-passive transition followed by a passive period 200 µs in
length (see Figure 28-6(e)).
End-of-Frame Symbol (EOF)
The EOF symbol is defined as an active-to-passive transition followed by a passive period 280 µs in
length (see Figure 28-6(f)). If no IFR byte is transmitted after an EOD symbol is transmitted, after
another 80 µs the EOD becomes an EOF, indicating completion of the message.
Inter-Frame Separation Symbol (IFS)
The IFS symbol is defined as a passive period 300 µs in length. The 20-µs IFS symbol contains no
transition, since when it is used it always appends to a 280-µs EOF symbol (see Figure 28-6(g)).
Idle
An idle is defined as a passive period greater than 300 µs in length.
28.4.4 J1850 VPW Valid/Invalid Bits and Symbols
The timing tolerances for receiving data bits and symbols from the J1850 bus have been defined to allow
for variations in oscillator frequencies. In many cases, the maximum time allowed to define a data bit or
symbol is equal to the minimum time allowed to define another data bit or symbol.
Since the minimum resolution of the BDLC for determining what symbol is being received is equal to a
single period of the MUX interface clock (tBDLC), an apparent separation in these maximum time/minimum
time concurrences equals one cycle of tBDLC.
This one clock resolution allows the BDLC to differentiate properly between the different bits and symbols.
This is done without reducing the valid window for receiving bits and symbols from transmitters onto the
J1850 bus, which has varying oscillator frequencies.
In Huntsinger’s variable pulse-width (VPW) modulation bit encoding, the tolerances for both the passive
and active data bits received and the symbols received are defined with no gaps between definitions. For
example, the maximum length of a passive logic 0 is equal to the minimum length of a passive logic 1,
and the maximum length of an active logic 0 is equal to the minimum length of a valid SOF symbol.
Invalid Passive Bit
See Figure 28-7(1). If the passive-to-active received transition beginning the next data bit or symbol
occurs between the active-to-passive transition beginning the current data bit (or symbol) and a, the
current bit would be invalid.
MC68HC908AT32 Data Sheet, Rev. 3.1
338
Freescale Semiconductor
BDLC MUX Interface
200 µs
128 µs
64 µs
ACTIVE
(1) INVALID PASSIVE BIT
PASSIVE
a
ACTIVE
(2) VALID PASSIVE LOGIC 0
PASSIVE
a
b
ACTIVE
(3) VALID PASSIVE LOGIC 1
PASSIVE
b
c
ACTIVE
(4) VALID EOD SYMBOL
PASSIVE
c
d
Figure 28-7. J1850 VPW Received Passive Symbol Times
Valid Passive Logic 0
See Figure 28-7(2). If the passive-to-active received transition beginning the next data bit (or symbol)
occurs between a and b, the current bit would be considered a logic 0.
Valid Passive Logic 1
See Figure 28-7(3). If the passive-to-active received transition beginning the next data bit (or symbol)
occurs between b and c, the current bit would be considered a logic 1.
Valid EOD Symbol
See Figure 28-7(4). If the passive-to-active received transition beginning the next data bit (or symbol)
occurs between c and d, the current symbol would be considered a valid end-of-data symbol (EOD).
300 µs
280 µs
ACTIVE
(1) VALID EOF SYMBOL
PASSIVE
a
b
ACTIVE
(2) VALID EOF+
IFS SYMBOL
PASSIVE
c
d
Figure 28-8. J1850 VPW Received Passive
EOF and IFS Symbol Times
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
339
Byte Data Link Controller-Digital (BDLC-D)
Valid EOF and IFS Symbols
In Figure 28-8(1), if the passive-to-active received transition beginning the SOF symbol of the next
message occurs between a and b, the current symbol will be considered a valid end-of-frame (EOF)
symbol.
See Figure 28-8(2). If the passive-to-active received transition beginning the SOF symbol of the next
message occurs between c and d, the current symbol will be considered a valid EOF symbol followed
by a valid inter-frame separation symbol (IFS). All nodes must wait until a valid IFS symbol time has
expired before beginning transmission. However, due to variations in clock frequencies and bus
loading, some nodes may recognize a valid IFS symbol before others and immediately begin
transmitting. Therefore, any time a node waiting to transmit detects a passive-to-active transition once
a valid EOF has been detected, it should immediately begin transmission, initiating the arbitration
process.
Idle Bus
In Figure 28-8(2), if the passive-to-active received transition beginning the start-of-frame (SOF) symbol
of the next message does not occur before d, the bus is considered to be idle, and any node wishing
to transmit a message may do so immediately.
200 µs
128 µs
64 µs
ACTIVE
(1) INVALID ACTIVE BIT
PASSIVE
a
ACTIVE
(2) VALID ACTIVE LOGIC 1
PASSIVE
a
b
ACTIVE
(3) VALID ACTIVE LOGIC 0
PASSIVE
b
c
ACTIVE
(4) VALID SOF SYMBOL
PASSIVE
c
d
Figure 28-9. J1850 VPW Received Active Symbol Times
Invalid Active Bit
In Figure 28-9(1), if the active-to-passive received transition beginning the next data bit (or symbol)
occurs between the passive-to-active transition beginning the current data bit (or symbol) and a, the
current bit would be invalid.
Valid Active Logic 1
In Figure 28-9(2), if the active-to-passive received transition beginning the next data bit (or symbol)
occurs between a and b, the current bit would be considered a logic 1.
MC68HC908AT32 Data Sheet, Rev. 3.1
340
Freescale Semiconductor
BDLC MUX Interface
Valid Active Logic 0
In Figure 28-9(3), if the active-to-passive received transition beginning the next data bit (or symbol)
occurs between b and c, the current bit would be considered a logic 0.
Valid SOF Symbol
In Figure 28-9(4), if the active-to-passive received transition beginning the next data bit (or symbol)
occurs between c and d, the current symbol would be considered a valid SOF symbol.
Valid BREAK Symbol
In Figure 28-10, if the next active-to-passive received transition does not occur until after e, the current
symbol will be considered a valid BREAK symbol. A BREAK symbol should be followed by a
start-of-frame (SOF) symbol beginning the next message to be transmitted onto the J1850 bus. See
28.4.2 J1850 Frame Format for BDLC response to BREAK symbols.
240 µs
ACTIVE
(2) VALID BREAK SYMBOL
PASSIVE
e
Figure 28-10. J1850 VPW Received BREAK Symbol Times
28.4.5 Message Arbitration
Message arbitration on the J1850 bus is accomplished in a non-destructive manner, allowing the
message with the highest priority to be transmitted, while any transmitters which lose arbitration simply
stop transmitting and wait for an idle bus to begin transmitting again.
If the BDLC wants to transmit onto the J1850 bus, but detects that another message is in progress, it waits
until the bus is idle. However, if multiple nodes begin to transmit in the same synchronization window,
message arbitration will occur beginning with the first bit after the SOF symbol and continue with each bit
thereafter. If a write to the BDR (for instance, to initiate transmission) occurred on or before
104 • tBDLC from the received rising edge, then the BDLC will transmit and arbitrate for the bus. If a CPU
write to the BDR occurred after
104 • tBDLC from the detection of the rising edge, then the BDLC will not transmit, but will wait for the next
IFS period to expire before attempting to transmit the byte.
The variable pulse-width modulation (VPW) symbols and J1850 bus electrical characteristics are chosen
carefully so that a logic 0 (active or passive type) will always dominate over a logic 1 (active or passive
type) simultaneously transmitted. Hence, logic 0s are said to be dominant and logic 1s are said to be
recessive.
Whenever a node detects a dominant bit on BDRxD when it transmitted a recessive bit, it loses arbitration
and immediately stops transmitting. This is known as bitwise arbitration.
Since a logic 0 dominates a logic 1, the message with the lowest value will have the highest priority and
will always win arbitration. For instance, a message with priority 000 will win arbitration over a message
with priority 011.
This method of arbitration will work no matter how many bits of priority encoding are contained in the
message.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
341
Byte Data Link Controller-Digital (BDLC-D)
0
1
1
0
1
1
TRANSMITTER A DETECTS
AN ACTIVE STATE ON
THE BUS AND STOPS
TRANSMITTING
1
ACTIVE
TRANSMITTER A
PASSIVE
0
0
ACTIVE
TRANSMITTER B
PASSIVE
0
1
1
0
0
DATA
DATA
DATA
DATA
DATA
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
TRANSMITTER B WINS
ARBITRATION AND
CONTINUES
TRANSMITTING
ACTIVE
J1850 BUS
PASSIVE
SOF
Figure 28-11. J1850 VPW Bitwise Arbitrations
During arbitration, or even throughout the transmitting message, when an opposite bit is detected,
transmission is stopped immediately unless it occurs on the eighth bit of a byte. In this case, the BDLC
automatically will append up to two extra logic 1 bits and then stop transmitting. These two extra bits will
be arbitrated normally and thus will not interfere with another message. The second logic 1 bit will not be
sent if the first loses arbitration. If the BDLC has lost arbitration to another valid message, then the two
extra logic 1s will not corrupt the current message. However, if the BDLC has lost arbitration due to noise
on the bus, then the two extra logic 1s will ensure that the current message will be detected and ignored
as a noise-corrupted message.
28.5 BDLC Protocol Handler
The protocol handler is responsible for framing, arbitration, CRC generation/checking, and error
detection. The protocol handler conforms to SAE J1850 Class B Data Communications Network
Interface.
NOTE
Freescale assumes that the reader is familiar with the J1850 specification
before reading this protocol handler description.
TO CPU
CPU INTERFACE
PROTOCOL HANDLER
MUX INTERFACE
PHYSICAL INTERFACE
BDLC
TO J1850 BUS
Figure 28-12. BDLC Block Diagram
MC68HC908AT32 Data Sheet, Rev. 3.1
342
Freescale Semiconductor
BDLC Protocol Handler
28.5.1 Protocol Architecture
The protocol handler contains the state machine, Rx shadow register, Tx shadow register, Rx shift
register, Tx shift register, and loopback multiplexer as shown in Figure 28-13.
TO PHYSICAL INTERFACE
BDTxD
BDRxD
DLOOP FROM BCR2
LOOPBACK CONTROL
ALOOP
BDTxD
RxD
MULTIPLEXER
CONTROL
LOOPBACK
STATE MACHINE
Tx SHADOW REGISTER
8
Tx DATA
Rx SHADOW REGISTER
CONTROL
Tx SHIFT REGISTER
Rx DATA
Rx SHIFT REGISTER
8
TO CPU INTERFACE AND Rx/Tx BUFFERS
Figure 28-13. BDLC Protocol Handler Outline
28.5.2 Rx and Tx Shift Registers
The Rx shift register gathers received serial data bits from the J1850 bus and makes them available in
parallel form to the Rx shadow register. The Tx shift register takes data, in parallel form, from the Tx
shadow register and presents it serially to the state machine so that it can be transmitted onto the J1850
bus.
28.5.3 Rx and Tx Shadow Registers
Immediately after the Rx shift register has completed shifting in a byte of data, this data is transferred to
the Rx shadow register and RDRF or RXIFR is set (see 28.6.4 BDLC State Vector Register). An interrupt
is generated if the interrupt enable bit (IE) in BCR1 is set. After the transfer takes place, this new data
byte in the Rx shadow register is available to the CPU interface, and the Rx shift register is ready to shift
in the next byte of data. Data in the Rx shadow register must be retrieved by the CPU before it is
overwritten by new data from the Rx shift register.
Once the Tx shift register has completed its shifting operation for the current byte, the data byte in the Tx
shadow register is loaded into the Tx shift register. After this transfer takes place, the Tx shadow register
is ready to accept new data from the CPU when the TDRE flag in the BSVR is set.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
343
Byte Data Link Controller-Digital (BDLC-D)
28.5.4 Digital Loopback Multiplexer
The digital loopback multiplexer connects RxD to either BDTxD or BDRxD, depending on the state of the
DLOOP bit in the BCR2 (See 28.6.3 BDLC Control Register 2).
28.5.5 State Machine
All functions associated with performing the protocol are executed or controlled by the state machine. The
state machine is responsible for framing, collision detection, arbitration, CRC generation/checking, and
error detection. The following sections describe the BDLC’s actions in a variety of situations.
28.5.5.1 4X Mode
The BDLC can exist on the same J1850 bus as modules which use a special 4X (41.6 kbps) mode of
J1850 variable pulse-width modulation (VPW) operation. The BDLC cannot transmit in 4X mode, but it
can receive messages in 4X mode, if the RX4X bit is set in BCR2. If the RX4X bit is not set in the BCR2,
any 4X message on the J1850 bus is treated as noise by the BDLC and is ignored.
28.5.5.2 Receiving a Message in Block Mode
Although not a part of the SAE J1850 protocol, the BDLC does allow for a special block mode of operation
of the receiver. As far as the BDLC is concerned, a block mode message is simply a long J1850 frame
that contains an indefinite number of data bytes. All other features of the frame remain the same, including
the SOF, CRC, and EOD symbols.
Another node wishing to send a block mode transmission must first inform all other nodes on the network
that this is about to happen. This is usually accomplished by sending a special predefined message.
28.5.5.3 Transmitting a Message in Block Mode
A block mode message is transmitted inherently by simply loading the bytes one by one into the BDR until
the message is complete. The programmer should wait until the TDRE flag (see 28.6.4 BDLC State
Vector Register) is set prior to writing a new byte of data into the BDR. The BDLC does not contain any
predefined maximum J1850 message length requirement.
28.5.5.4 J1850 Bus Errors
The BDLC detects several types of transmit and receive errors which can occur during the transmission
of a message onto the J1850 bus.
Transmission Error
If the message transmitted by the BDLC contains invalid bits or framing symbols on non-byte
boundaries, this constitutes a transmission error. When a transmission error is detected, the BDLC
immediately will cease transmitting. The error condition is reflected in the BSVR (see Table 28-6). If
the interrupt enable bit (IE in BCR1) is set, a CPU interrupt request from the BDLC is generated.
CRC Error
A cyclical redundancy check (CRC) error is detected when the data bytes and CRC byte of a received
message are processed and the CRC calculation result is not equal. The CRC code will detect any
single and 2-bit errors, as well as all 8-bit burst errors and almost all other types of errors. The CRC
error flag (in BSVR) is set when a CRC error is detected. (See 28.6.4 BDLC State Vector Register.)
MC68HC908AT32 Data Sheet, Rev. 3.1
344
Freescale Semiconductor
BDLC Protocol Handler
Symbol Error
A symbol error is detected when an abnormal (invalid) symbol is detected in a message being received
from the J1850 bus. The invalid symbol is set when a symbol error is detected. (See 28.6.4 BDLC State
Vector Register.)
Framing Error
A framing error is detected if an EOD or EOF symbol is detected on a non-byte boundary from the
J1850 bus. A framing error also is detected if the BDLC is transmitting the EOD and instead receives
an active symbol. The symbol invalid, or the out-of-range flag, is set when a framing error is detected.
(See 28.6.4 BDLC State Vector Register.)
Bus Fault
If a bus fault occurs, the response of the BDLC will depend upon the type of bus fault.
If the bus is shorted to battery, the BDLC will wait for the bus to fall to a passive state before it will
attempt to transmit a message. As long as the short remains, the BDLC will never attempt to transmit
a message onto the J1850 bus.
If the bus is shorted to ground, the BDLC will see an idle bus, begin to transmit the message, and then
detect a transmission error (in BSVR), since the short to ground would not allow the bus to be driven
to the active (dominant) SOF state. The BDLC will abort that transmission and wait for the next CPU
command to transmit.
In any case, if the bus fault is temporary, as soon as the fault is cleared, the BDLC will resume normal
operation. If the bus fault is permanent, it may result in permanent loss of communication on the J1850
bus. (See 28.6.4 BDLC State Vector Register.)
BREAK — Break
If a BREAK symbol is received while the BDLC is transmitting or receiving, an invalid symbol (in BSVR)
interrupt will be generated. Reading the BSVR (see 28.6.4 BDLC State Vector Register) will clear this
interrupt condition. The BDLC will wait for the bus to idle, then wait for a start-of-frame (SOF) symbol.
The BDLC cannot transmit a BREAK symbol. It only can receive a BREAK symbol from the J1850 bus.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
345
Byte Data Link Controller-Digital (BDLC-D)
28.5.5.5 Summary
Table 28-2. BDLC J1850 Bus Error Summary
Error Condition
BDLC Function
Transmission error
For invalid bits or framing symbols on non-byte boundaries, invalid
symbol interrupt will be generated. BDLC stops transmission.
Cyclical redundancy check (CRC) error
CRC error interrupt will be generated. The BDLC will wait for EOF.
Invalid symbol:
BDLC transmits,but receives invalid bits (noise)
The BDLC will abort transmission immediately. Invalid symbol interrupt
will be generated.
Framing error
Invalid symbol interrupt will be generated. The BDLC will wait for end
of frame (EOF).
Bus short to VDD
The BDLC will not transmit until the bus is idle. Invalid symbol interrupt
will be generated. EOF interrupt also must be seen before another
transmission attempt. Depending on length of the short, LOA flag
also may be set.
Bus short to GND
Thermal overload will shut down physical interface. Fault condition is
seen as invalid symbol flag. EOF interrupt must also be seen before
another transmission attempt.
BDLC receives BREAK symbol
Invalid symbol interrupt will be generated. The BDLC will wait for the
next valid start-of-frame (SOF).
28.6 BDLC CPU Interface
The CPU interface provides the interface between the CPU and the BDLC and consists of five user
registers.
TO CPU
CPU INTERFACE
PROTOCOL HANDLER
MUX INTERFACE
PHYSICAL INTERFACE
BDLC
TO J1850 BUS
Figure 28-14. BDLC Block Diagram
MC68HC908AT32 Data Sheet, Rev. 3.1
346
Freescale Semiconductor
BDLC CPU Interface
28.6.1 BDLC Analog and Round-Trip Delay
This register programs the BDLC to compensate for various delays of different external transceivers. The
default delay value is 16 µs. Timing adjustments from 9 µs to 24 µs in steps of 1 µs are available. The
BARD register can be written only once after each reset, after which they become read-only bits. The
register may be read at any time.
Address:
$003B
Bit 7
6
ATE
RXPOL
1
1
Read:
5
4
0
0
3
2
1
Bit 0
BO3
BO2
BO1
BO0
0
1
1
1
Write:
Reset:
0
0
= Unimplemented
Figure 28-15. BDLC Analog and Round-Trip Delay Register (BARD)
ATE — Analog Transceiver Enable Bit
The analog transceiver enable (ATE) bit is used to select either the on-board or an off-chip analog
transceiver.
1 = Select on-board analog transceiver
0 = Select off-chip analog transceiver
NOTE
This device does not contain an on-board transceiver. This bit should be
programmed to a logic 0 for proper operation.
RXPOL — Receive Pin Polarity Bit
The receive pin polarity (RXPOL) bit is used to select the polarity of an incoming signal on the receive
pin. Some external analog transceivers invert the receive signal from the J1850 bus before feeding it
back to the digital receive pin.
1 = Select normal/true polarity; true non-inverted signal from the J1850 bus; for example, the
external transceiver does not invert the receive signal
0 = Select inverted polarity, where an external transceiver inverts the receive signal from the J1850
bus
BO3–BO0 — BARD Offset Bits
Table 28-3 shows the expected transceiver delay with respect to BARD offset values.
Table 28-3. BDLC Transceiver Delay
BARD Offset Bits
BO[3:0]
Corresponding Expected
Transceiver’s Delays (µs)
BARD Offset Bits
BO[3:0]
Corresponding Expected
Transceiver’s Delays (µs)
0000
9
1000
17
0001
10
1001
18
0010
11
1010
19
0011
12
1011
20
0100
13
1100
21
0101
14
1101
22
0110
15
1110
23
0111
16
1111
24
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
347
Byte Data Link Controller-Digital (BDLC-D)
28.6.2 BDLC Control Register 1
This register is used to configure and control the BDLC.
Address:
Read:
Write:
Reset:
$003C
Bit 7
6
5
4
IMSG
CLKS
R1
R0
1
1
1
0
R
= Reserved
3
2
0
0
R
R
0
0
1
Bit 0
IE
WCM
0
0
Figure 28-16. BDLC Control Register 1 (BCR1)
IMSG — Ignore Message Bit
This bit is used to disable the receiver until a new start-of-frame (SOF) is detected.
1 = Disable receiver. When set, all BDLC interrupt requests will be masked (except $20 in BSVR)
and the status bits will be held in their reset state. If this bit is set while the BDLC is receiving
a message, the rest of the incoming message will be ignored.
0 = Enable receiver. This bit is cleared automatically by the reception of an SOF symbol or a BREAK
symbol. It will then generate interrupt requests and will allow changes of the status register to
occur. However, these interrupts may still be masked by the interrupt enable (IE) bit.
CLKS — Clock Bit
For J1850 bus communications to take place, the nominal BDLC operating frequency (fBDLC) must
always be 1.048576 MHz or 1 MHz. The CLKS register bit allows the user to select the frequency
(1.048576 MHz or 1 MHz) used to automatically adjust symbol timing.
1 = Binary frequency (1.048576 MHz) selected for fBDLC
0 = Integer frequency (1 MHz) selected for fBDLC
R1 and R0 — Rate Select Bits
These bits determine the amount by which the frequency of the MCU CGMXCLK signal is divided to
form the MUX interface clock (fBDLC) which defines the basic timing resolution of the MUX interface.
They may be written only once after reset, after which they become read-only bits.
The nominal frequency of fBDLC must always be 1.048576 MHz or 1.0 MHz for J1850 bus
communications to take place. Hence, the value programmed into these bits is dependent on the
chosen MCU system clock frequency per Table 28-4.
Table 28-4. BDLC Rate Selection
fXCLK Frequency
R1
R0
Division
fBDLC
1.049 MHz
0
0
1
1.049 MHz
2.097 MHz
0
1
2
1.049 MHz
4.194 MHz
1
0
4
1.049 MHz
8.389 MHz
1
1
8
1.049 MHz
1.000 MHz
0
0
1
1.00 MHz
2.000 MHz
0
1
2
1.00 MHz
4.000 MHz
1
0
4
1.00 MHz
8.000 MHz
1
1
8
1.00 MHz
MC68HC908AT32 Data Sheet, Rev. 3.1
348
Freescale Semiconductor
BDLC CPU Interface
IE— Interrupt Enable Bit
This bit determines whether the BDLC will generate CPU interrupt requests in run mode. It does not
affect CPU interrupt requests when exiting the BDLC stop or BDLC wait modes. Interrupt requests will
be maintained until all of the interrupt request sources are cleared by performing the specified actions
upon the BDLC’s registers. Interrupts that were pending at the time that this bit is cleared may be lost.
1 = Enable interrupt requests from BDLC
0 = Disable interrupt requests from BDLC
If the programmer does not want to use the interrupt capability of the BDLC, the BDLC state vector
register (BSVR) can be polled periodically by the programmer to determine BDLC states. See 28.6.4
BDLC State Vector Register for a description of the BSVR.
WCM — Wait Clock Mode Bit
This bit determines the operation of the BDLC during CPU wait mode. See 28.7.2 Stop Mode and
28.7.1 Wait Mode for more details on its use.
1 = Stop BDLC internal clocks during CPU wait mode
0 = Run BDLC internal clocks during CPU wait mode
28.6.3 BDLC Control Register 2
This register controls transmitter operations of the BDLC. It is recommended that BSET and BCLR
instructions be used to manipulate data in this register to ensure that the register’s content does not
change inadvertently.
Address:
Read:
Write:
Reset:
$003D
Bit 7
6
5
4
3
2
1
Bit 0
ALOOP
DLOOP
RX4XE
NBFS
TEOD
TSIFR
TMIFR1
TMIFR0
1
1
0
0
0
0
0
0
Figure 28-17. BDLC Control Register 2 (BCR2)
ALOOP — Analog Loopback Mode Bit
This bit determines whether the J1850 bus will be driven by the analog physical interface’s final drive
stage. The programmer can use this bit to reset the BDLC state machine to a known state after the
off-chip analog transceiver is placed in loopback mode. When the user clears ALOOP, to indicate that
the off-chip analog transceiver is no longer in loopback mode, the BDLC waits for an EOF symbol
before attempting to transmit. Most transceivers have the ALOOP feature available.
1 = Input to the analog physical interface’s final drive stage is looped back to the BDLC receiver.
The J1850 bus is not driven.
0 = The J1850 bus will be driven by the BDLC. After the bit is cleared, the BDLC requires the bus
to be idle for a minimum of end-of-frame symbol time (tTRV4) before message reception or a
minimum of inter-frame symbol time (tTRV6) before message transmission. (See 29.14 BDLC
Receiver VPW Symbol Timings.)
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
349
Byte Data Link Controller-Digital (BDLC-D)
DLOOP — Digital Loopback Mode Bit
This bit determines the source to which the digital receive input (BDRxD) is connected and can be used
to isolate bus fault conditions (see Figure 28-13). If a fault condition has been detected on the bus, this
control bit allows the programmer to connect the digital transmit output to the digital receive input. In
this configuration, data sent from the transmit buffer will be reflected back into the receive buffer. If no
faults exist in the BDLC, the fault is in the physical interface block or elsewhere on the J1850 bus.
1 = When set, BDRxD is connected to BDTxD. The BDLC is now in digital loopback mode.
0 = When cleared, BDTxD is not connected to BDRxD. The BDLC is taken out of digital loopback
mode and can now drive or receive the J1850 bus normally (given ALOOP is not set). After
writing DLOOP to 0, the BDLC requires the bus to be idle for a minimum of end-of-frame symbol
(ttv4) time before allowing a reception of a message. The BDLC requires the bus to be idle for
a minimum of inter-frame separator symbol (ttv6) time before allowing any message to be
transmitted.
RX4XE — Receive 4X Enable Bit
This bit determines if the BDLC operates at normal transmit and receive speed (10.4 kbps) or receive
only at 41.6 kbps. This feature is useful for fast downloading of data into a J1850 node for diagnostic
or factory programming of the node.
1 = When set, the BDLC is put in 4X receive-only operation.
0 = When cleared, the BDLC transmits and receives at 10.4 kbps. Reception of a BREAK symbol
automatically clears this bit and sets BDLC state vector register (BSVR) to $001C.
NBFS — Normalization Bit Format Select Bit
This bit controls the format of the normalization bit (NB). (See Figure 28-18.) SAE J1850 strongly
encourages using an active long (logic 0) for in-frame responses containing cyclical redundancy check
(CRC) and an active short (logic 1) for in-frame responses without CRC.
1 = NB that is received or transmitted is a 0 when the response part of an in-frame response (IFR)
ends with a CRC byte. NB that is received or transmitted is a 1 when the response part of an
in-frame response (IFR) does not end with a CRC byte.
0 = NB that is received or transmitted is a 1 when the response part of an in-frame response (IFR)
ends with a CRC byte. NB that is received or transmitted is a 0 when the response part of an
in-frame response (IFR) does not end with a CRC byte.
TEOD — Transmit End-of-Data Bit
This bit is set by the programmer to indicate the end of a message is being sent by the BDLC. It will
append an 8-bit CRC after completing transmission of the current byte. This bit also is used to end an
in-frame response (IFR). If the transmit shadow register is full when TEOD is set, the CRC byte will be
transmitted after the current byte in the Tx shift register and the byte in the Tx shadow register have
been transmitted. (See 28.5.3 Rx and Tx Shadow Registers for a description of the transmit shadow
register.) Once TEOD is set, the transmit data register empty flag (TDRE) in the BDLC state vector
register (BSVR) is cleared to allow lower priority interrupts to occur. (See 28.6.4 BDLC State Vector
Register.)
1 = Transmit end-of-data (EOD) symbol
0 = The TEOD bit will be cleared automatically at the rising edge of the first CRC bit that is sent or
if an error is detected. When TEOD is used to end an IFR transmission, TEOD is cleared when
the BDLC receives back a valid EOD symbol or an error condition occurs.
MC68HC908AT32 Data Sheet, Rev. 3.1
350
Freescale Semiconductor
BDLC CPU Interface
TSIFR, TMIFR1, and TMIFR0 — Transmit In-Frame Response Control Bits
These three bits control the type of in-frame response being sent. The programmer should not set
more than one of these control bits to a 1 at any given time. However, if more than one of these three
control bits are set to 1, the priority encoding logic will force these register bits to a known value as
shown in Table 28-5. For example, if 011 is written to TSIFR, TMIFR1, and TMIFR0, then internally
they will be encoded as 010. However, when these bits are read back, they will read 011.
Table 28-5. BDLC Transmit In-Frame Response
Control Bit Priority Encoding
Write/Read
TSIFR
Write/Read
TMIFR1
Write/Read
TMIFR0
Actual
TSIFR
Actual
TMIFR1
Actual
TMIFR0
0
0
0
0
0
0
1
X
X
1
0
0
0
1
X
0
1
0
0
0
1
0
0
1
The BDLC supports the in-frame response (IFR) feature of J1850 by setting these bits correctly. The
four types of J1850 IFR are shown in Figure 28-18. The purpose of the in-frame response modes is to
allow multiple nodes to acknowledge receipt of the data by responding with their personal ID or
physical address in a concatenated manner after they have seen the EOD symbol. If transmission
arbitration is lost by a node while sending its response, it continues to transmit its ID/address until
observing its unique byte in the response stream. For VPW modulation, the first bit of the IFR is always
passive; therefore, an active normalization bit must be generated by the responder and sent prior to
its ID/address byte. When there are multiple responders on the J1850 bus, only one normalization bit
is sent which assists all other transmitting nodes to sync their responses.
TSIFR — Transmit Single Byte IFR with No CRC (Type 1 or 2) Bit
The TSIFR bit is used to request the BDLC to transmit the byte in the BDLC data register (BDR) as a
single byte IFR with no CRC. Typically, the byte transmitted is a unique identifier or address of the
transmitting (responding) node. See Figure 28-18.
1 = If this bit is set prior to a valid EOD being received with no CRC error, once the EOD symbol
has been received the BDLC will attempt to transmit the appropriate normalization bit followed
by the byte in the BDR.
0 = The TSIFR bit will be cleared automatically, once the BDLC
has successfully transmitted the byte in the BDR onto the
bus, or TEOD is set, or an error is detected on the bus.
If the programmer attempts to set the TSIFR bit immediately after the EOD symbol has been received
from the bus, the TSIFR bit will remain in the reset state and no attempt will be made to transmit the IFR
byte.
If a loss of arbitration occurs when the BDLC attempts to transmit and after the IFR byte winning
arbitration completes transmission, the BDLC will again attempt to transmit the BDR (with no
normalization bit). The BDLC will continue transmission attempts until an error is detected on the bus, or
TEOD is set, or the BDLC transmission is successful.
If loss of arbitration occurs in the last two bits of the IFR byte, two additional 1 bits will not be sent out
because the BDLC will attempt to retransmit the byte in the transmit shift register after the IRF byte
winning arbitration completes transmission.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
351
Byte Data Link Controller-Digital (BDLC-D)
CRC
CRC
EOD
DATA FIELD
EOF
EOD
SOF
HEADER
TYPE 0 — NO IFR
DATA FIELD
NB
EOF
EOD
SOF
HEADER
ID
TYPE 1 — SINGLE BYTE TRANSMITTED FROM A SINGLE RESPONDER
CRC
NB
ID1
ID N
EOF
EOD
DATA FIELD
EOD
SOF
HEADER
TYPE 2 — SINGLE BYTE TRANSMITTED FROM MULTIPLE RESPONDERS
CRC
NB
IFR DATA FIELD
CRC
(OPTIONAL)
EOF
EOD
DATA FIELD
EOD
SOF
HEADER
TYPE 3 — MULTIPLE BYTES TRANSMITTED FROM A SINGLE RESPONDER
NB = Normalization Bit
ID = Identifier, usually the physical address of the responder(s)
Figure 28-18. Types of In-Frame Response (IFR)
TMIFR1 — Transmit Multiple Byte IFR with CRC (Type 3) Bit
The TMIFR1 bit requests the BDLC to transmit the byte in the BDLC data register (BDR) as the first
byte of a multiple byte IFR with CRC or as a single byte IFR with CRC. Response IFR bytes are still
subject to J1850 message length maximums (see 28.4.2 J1850 Frame Format). See Figure 28-18
1 = If this bit is set prior to a valid EOD being received with no CRC error, once the EOD symbol
has been received, the BDLC will attempt to transmit the appropriate normalization bit followed
by IFR bytes. The programmer should set TEOD after the last IFR byte has been written into
the BDR. After TEOD has been set and the last IFR byte has been transmitted, the CRC byte
is transmitted.
0 = The TMIFR1 bit will be cleared automatically, once the BDLC has successfully transmitted the
CRC byte and EOD symbol, by the detection of an error on the multiplex bus or by a transmitter
underrun caused when the programmer does not write another byte to the BDR after the TDRE
interrupt.
If the TMIFR1 bit is set, the BDLC will attempt to transmit the normalization symbol followed by the byte
in the BDR. After the byte in the BDR has been loaded into the transmit shift register, a TDRE interrupt
(see 28.6.4 BDLC State Vector Register) will occur similar to the main message transmit sequence.
The programmer should then load the next byte of the IFR into the BDR for transmission. When the
last byte of the IFR has been loaded into the BDR, the programmer should set the TEOD bit in the
BDLC control register 2 (BCR2). This will instruct the BDLC to transmit a CRC byte once the byte in
the BDR is transmitted, and then transmit an EOD symbol, indicating the end of the IFR portion of the
message frame.
However, if the programmer wishes to transmit a single byte followed by a CRC byte, the programmer
should load the byte into the BDR before the EOD symbol has been received, and then set the TMIFR1
bit. Once the TDRE interrupt occurs, the programmer should then set the TEOD bit in the BCR2. This
will result in the byte in the BDR being the only byte transmitted before the IFR CRC byte, and no TDRE
interrupt will be generated.
MC68HC908AT32 Data Sheet, Rev. 3.1
352
Freescale Semiconductor
BDLC CPU Interface
If the programmer attempts to set the TMIFR1 bit immediately after the EOD symbol has been received
from the bus, the TMIFR1 bit will remain in the reset state, and no attempt will be made to transmit an
IFR byte.
If a loss of arbitration occurs when the BDLC is transmitting any byte of a multiple byte IFR, the BDLC
will go to the loss of arbitration state, set the appropriate flag, and cease transmission.
If the BDLC loses arbitration during the IFR, the TMIFR1 bit will be cleared and no attempt will be
made to retransmit the byte in the BDR. If loss of arbitration occurs in the last two bits of the IFR byte,
two additional 1 bits will be sent out.
NOTE
The extra logic 1s are an enhancement to the J1850 protocol which forces
a byte boundary condition fault. This is helpful in preventing noise on the
J1850 bus from corrupting a message.
TMIFR0 — Transmit Multiple Byte IFR without CRC (Type 3) Bit
The TMIFR0 bit is used to request the BDLC to transmit the byte in the BDLC data register (BDR) as
the first byte of a multiple byte IFR without CRC. Response IFR bytes are still subject to J1850
message length maximums (see 28.4.2 J1850 Frame Format).
See Figure 28-18.
1 = If this bit is set prior to a valid EOD being received with no CRC error, once the EOD symbol
has been received, the BDLC will attempt to transmit the appropriate normalization bit followed
by IFR bytes. The programmer should set TEOD after the last IFR byte has been written into
the BDR. After TEOD has been set, the last IFR byte to be transmitted will be the last byte
which was written into the BDR.
0 = The TMIFR0 bit will be cleared automatically, once the BDLC has successfully transmitted the
EOD symbol, by the detection of an error on the multiplex bus or by a transmitter underrun
caused when the programmer does not write another byte to the BDR after the TDRE interrupt.
If the TMIFR0 bit is set, the BDLC will attempt to transmit the normalization symbol followed by the byte
in the BDR. After the byte in the BDR has been loaded into the transmit shift register, a TDRE interrupt
(see 28.6.4 BDLC State Vector Register) will occur similar to the main message transmit sequence.
The programmer should then load the next byte of the IFR into the BDR for transmission. When the
last byte of the IFR has been loaded into the BDR, the programmer should set the TEOD bit in the
BCR2. This will instruct the BDLC to transmit an EOD symbol once the byte in the BDR is transmitted,
indicating the end of the IFR portion of the message frame. The BDLC will not append a CRC when
the TMIFR0 is set.
If the programmer attempts to set the TMIFR0 bit after the EOD symbol has been received from the
bus, the TMIFR0 bit will remain in the reset state, and no attempt will be made to transmit an IFR byte.
If a loss of arbitration occurs when the BDLC is transmitting, the TMIFR0 bit will be cleared, and no
attempt will be made to retransmit the byte in the BDR. If loss of arbitration occurs in the last two bits
of the IFR byte, two additional 1 bits (active short bits) will be sent out.
NOTE
The extra logic 1s are an enhancement to the J1850 protocol which forces
a byte boundary condition fault. This is helpful in preventing noise on the
J1850 bus from a corrupted message.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
353
Byte Data Link Controller-Digital (BDLC-D)
28.6.4 BDLC State Vector Register
This register is provided to substantially decrease the CPU overhead associated with servicing interrupts
while under operation of a multiplex protocol. It provides an index offset that is directly related to the
BDLC’s current state, which can be used with a user-supplied jump table to rapidly enter an interrupt
service routine. This eliminates the need for the user to maintain a duplicate state machine in software.
Address:
$003E
Bit 7
6
5
4
3
2
1
Bit 0
0
0
I3
I2
I1
I0
0
0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
= Unimplemented
Figure 28-19. BDLC State Vector Register (BSVR)
I0, I1, I2, and I3 — Interrupt Source Bits
These bits indicate the source of the interrupt request that currently is pending. The encoding of these
bits are listed in Table 28-6.
Table 28-6. BDLC Interrupt Sources
BSVR
I3
I2
I1
I0
Interrupt Source
Priority
$00
0
0
0
0
No interrupts pending
$04
0
0
0
1
Received EOF
1
$08
0
0
1
0
Received IFR byte (RXIFR)
2
$0C
0
0
1
1
BDLC Rx data register full (RDRF)
3
$10
0
1
0
0
BDLC Tx data register empty (TDRE)
4
$14
0
1
0
1
Loss of arbitration
5
$18
0
1
1
0
Cyclical redundancy check (CRC) error
6
$1C
0
1
1
1
Symbol invalid or out of range
7
$20
1
0
0
0
Wakeup
0 (lowest)
8 (highest)
Bits I0, I1, I2, and I3 are cleared by a read of the BSVR except when the BDLC data register needs
servicing (RDRF, RXIFR, or TDRE conditions). RXIFR and RDRF can be cleared only by a read of the
BSVR followed by a read of the BDLC data register (BDR). TDRE can either be cleared by a read of the
BSVR followed by a write to the BDLC BDR or by setting the TEOD bit in BCR2.
MC68HC908AT32 Data Sheet, Rev. 3.1
354
Freescale Semiconductor
BDLC CPU Interface
Upon receiving a BDLC interrupt, the user can read the value within the BSVR, transferring it to the CPU’s
index register. The value can then be used to index into a jump table, with entries four bytes apart, to
quickly enter the appropriate service routine. For example:
Service
*
*
JMPTAB
LDX
JMP
BSVR
JMPTAB,X
Fetch State Vector Number
Enter service routine,
(must end in RTI)
JMP
NOP
JMP
NOP
JMP
NOP
SERVE0
Service condition #0
SERVE1
Service condition #1
SERVE2
Service condition #2
JMP
END
SERVE8
Service condition #8
*
NOTE
The NOPs are used only to align the JMPs onto 4-byte boundaries so that
the value in the BSVR can be used intact. Each of the service routines must
end with an RTI instruction to guarantee correct continued operation of the
device. Note also that the first entry can be omitted since it corresponds to
no interrupt occurring.
The service routines should clear all of the sources that are causing the pending interrupts. Note that the
clearing of a high priority interrupt may still leave a lower priority interrupt pending, in which case bits I0,
I1, and I2 of the BSVR will then reflect the source of the remaining interrupt request.
If fewer states are used or if a different software approach is taken, the jump table can be made smaller
or omitted altogether.
28.6.5 BDLC Data Register
Address:
Read:
Write:
Reset:
$003F
Bit 7
6
5
4
3
2
1
Bit 0
BD7
BD6
BD5
BD4
BD3
BD2
BD1
BD0
Indeterminate after reset
Figure 28-20. BDLC Data Register (BDR)
This register is used to pass the data to be transmitted to the J1850 bus from the CPU to the BDLC. It is
also used to pass data received from the J1850 bus to the CPU. Each data byte (after the first one) should
be written only after a Tx data register empty (TDRE) state is indicated in the BSVR.
Data read from this register will be the last data byte received from the J1850 bus. This received data
should only be read after an Rx data register full (RDRF) interrupt has occurred. (See 28.6.4 BDLC State
Vector Register.)
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
355
Byte Data Link Controller-Digital (BDLC-D)
The BDR is double buffered via a transmit shadow register and a receive shadow register. After the byte
in the transmit shift register has been transmitted, the byte currently stored in the transmit shadow register
is loaded into the transmit shift register. Once the transmit shift register has shifted the first bit out, the
TDRE flag is set, and the shadow register is ready to accept the next data byte. The receive shadow
register works similarly. Once a complete byte has been received, the receive shift register stores the
newly received byte into the receive shadow register. The RDRF flag is set to indicate that a new byte of
data has been received. The programmer has one BDLC byte reception time to read the shadow register
and clear the RDRF flag before the shadow register is overwritten by the newly received byte.
To abort an in-progress transmission, the programmer should stop loading data into the BDR. This will
cause a transmitter underrun error and the BDLC automatically will disable the transmitter on the next
non-byte boundary. This means that the earliest a transmission can be halted is after at least one byte
plus two extra logic 1s have been transmitted. The receiver will pick this up as an error and relay it in the
state vector register as an invalid symbol error.
NOTE
The extra logic 1s are an enhancement to the J1850 protocol which forces
a byte boundary condition fault. This is helpful in preventing noise on the
J1850 bus from corrupting a message.
28.7 Low-Power Modes
The following information concerns wait mode and stop mode.
28.7.1 Wait Mode
This power-conserving mode is entered automatically from run mode whenever the CPU executes a
WAIT instruction and the WCM bit in BDLC control register 1 (BCR1) is previously clear. In BDLC wait
mode, the BDLC cannot drive any data.
A subsequent successfully received message, including one that is in progress at the time that this mode
is entered, will cause the BDLC to wake up and generate a CPU interrupt request if the interrupt enable
(IE) bit in the BDLC control register 1 (BCR1) is previously set (see 28.6.2 BDLC Control Register 1 for a
better understanding of IE). This results in less of a power saving, but the BDLC is guaranteed to receive
correctly the message which woke it up, since the BDLC internal operating clocks are kept running.
NOTE
Ensuring that all transmissions are complete or aborted before putting the
BDLC into wait mode is important.
28.7.2 Stop Mode
This power-conserving mode is entered automatically from run mode whenever the CPU executes a
STOP instruction or if the CPU executes a WAIT instruction and the WCM bit in the BDLC control
register 1 (BCR1) is previously set. This is the lowest power mode that the BDLC can enter.
A subsequent passive-to-active transition on the J1850 bus will cause the BDLC to wake up and generate
a non-maskable CPU interrupt request. When a STOP instruction is used to put the BDLC in stop mode,
the BDLC is not guaranteed to correctly receive the message which woke it up, since it may take some
time for the BDLC internal operating clocks to restart and stabilize. If a WAIT instruction is used to put the
BDLC in stop mode, the BDLC is guaranteed to correctly receive the byte which woke it up, if and only if
MC68HC908AT32 Data Sheet, Rev. 3.1
356
Freescale Semiconductor
Low-Power Modes
an end-of-frame (EOF) has been detected prior to issuing the WAIT instruction by the CPU. Otherwise,
the BDLC will not correctly receive the byte that woke it up.
If this mode is entered while the BDLC is receiving a message, the first subsequent received edge will
cause the BDLC to wake up immediately, generate a CPU interrupt request, and wait for the BDLC
internal operating clocks to restart and stabilize before normal communications can resume. Therefore,
the BDLC is not guaranteed to receive that message correctly.
NOTE
It is important to ensure all transmissions are complete or aborted prior to
putting the BDLC into stop mode.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
357
Byte Data Link Controller-Digital (BDLC-D)
MC68HC908AT32 Data Sheet, Rev. 3.1
358
Freescale Semiconductor
Chapter 29
Electrical Specifications
29.1 Maximum Ratings
Maximum ratings are the extreme limits to which the microcontroller unit (MCU) can be exposed without
permanently damaging it.
NOTE
This device is not guaranteed to operate properly at the maximum ratings.
Refer to 29.4 5.0-Volt DC Electrical Characteristics for guaranteed
operating conditions.
Rating(1)
Symbol
Value
Unit
Supply voltage
VDD
–0.3 to +6.0
V
Input voltage
VIn
VSS –0.3 to VDD +0.3
V
I
± 25
mA
Storage temperature
TSTG
–55 to +150
°C
Maximum current out of VSS
IMVSS
100
mA
Maximum current into VDD
IMVDD
100
mA
VHI
VDD to VDD + 2
V
Maximum current per pin excluding VDD and VSS
Reset IRQ input voltage
1. Voltages are referenced to VSS.
NOTE
This device contains circuitry to protect the inputs against damage due to
high static voltages or electric fields; however, it is advised that normal
precautions be taken to avoid application of any voltage higher than
maximum-rated voltages to this high-impedance circuit. For proper
operation, it is recommended that VIn and VOut be constrained to the range
VSS ≤ (VIn or VOut) ≤ VDD. Reliability of operation is enhanced if unused
inputs are connected to an appropriate logic voltage level (for example,
either VSS or VDD).
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
359
Electrical Specifications
29.2 Functional Operating Range
Rating
Symbol
Value
Unit
TA
–40 to 125
°C
VDD
5.0 ± 10%
V
Symbol
Value
Unit
Thermal resistance
QFP (64 pins)
θJA
70
°C/W
Thermal resistance
PLCC (52 pins)
θJA
50
°C/W
I/O pin power dissipation
PI/O
User determined
W
Power dissipation(1)
PD
PD = (IDD x VDD) + PI/O =
K/(TJ + 273°C
W
Constant(2)
K
Average junction temperature
TJ
Operating temperature range
Operating voltage range
29.3 Thermal Characteristics
Characteristic
Maximum junction temperature
TJM
PD x (TA + 273°C)
+ (PD2 x θJA)
TA = PD
x θJA
125
W/°C
°C
°C
1. Power dissipation is a function of temperature.
2. K is a constant unique to the device. K can be determined from a known TA and
measured PD. With this value of K, PD and TJ can be determined for any value of TA.
MC68HC908AT32 Data Sheet, Rev. 3.1
360
Freescale Semiconductor
5.0-Volt DC Electrical Characteristics
29.4 5.0-Volt DC Electrical Characteristics
Characteristic(1)
Symbol
Min
Typ(2)
Max
Unit
Output high voltage
(ILoad = –2.0 mA) all ports
VOH
VDD –0.8
—
—
V
Output low voltage
(ILoad = 1.6 mA) all ports
VOL
—
—
0.4
V
Input high voltage
All ports, IRQs, RESET, OSC1
VIH
0.7 x VDD
—
VDD
V
Input low voltage
All ports, IRQs, RESET, OSC1
VIL
VSS
—
0.3 x VDD
V
—
—
—
—
30
15
mA
mA
—
—
—
—
—
—
—
—
5
50
400
500
µA
µA
µA
µA
VDD + VDDA supply current
Run(3)
Wait(4)
Stop(5)
25°C
–40°C to +125°C
25°C with LVI enabled
–40°C to +125°C with LVI enabled
IDD
I/O ports Hi-Z leakage current
IL
—
—
±1
µA
Input current
IIn
—
—
±1
µA
Capacitance
Ports (as input or output)
COut
CIn
—
—
—
—
12
8
pF
Low-voltage reset inhibit
VLVII
—
4.2
—
V
Low-voltage reset inhibit/recover hysteresis
HLVI
—
200
—
mV
POR re-arm voltage(6)
VPOR
0
—
200
mV
VPORRST
0
—
800
mV
RPOR
0.02
—
—
V/ms
VHI
VDD
VDD + 2
V
POR reset voltage(7)
POR rise time ramp rate
(8)
High COP disable voltage(9)
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +125°C, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25°C only.
3. Run (Operating) IDD measured using external square wave clock source (fOP = 8.4 MHz). All inputs 0.2 V from rail. No dc loads. Less than
4.
5.
6.
7.
8.
9.
100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run IDD. Measured with all
modules enabled.
Wait IDD measured using external square wave clock source (fOP = 8.4 MHz). All inputs 0.2 Vdc from rail. No dcloads. Less than 100 pF
on all outputs, CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait IDD. Measured with all modules
enabled.
Stop IDD measured with OSC1 = VSS.
Maximum is highest voltage that POR is guaranteed.
Maximum is highest voltage that POR is possible.
If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until
minimum VDD is reached.
See 13.8 COP Module during Break Interrupts.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
361
Electrical Specifications
29.5 Control Timing
Characteristic(1)
Symbol
Min
Max
Unit
fBUS
—
8.4 M
Hz
RESET pulse width low
tRL
1.5
—
tcyc
IRQ interrupt pulse width low (edge-triggered)
tILHI
1.5
—
tcyc
IRQ interrupt pulse period
tILIL
(3)
—
tcyc
EEPROM programming time per byte
tEEPGM
10
—
ms
EEPROM erasing time per byte
tEBYTE
10
—
ms
EEPROM erasing time per block
tEBLOCK
10
—
ms
EEPROM erasing time per bulk
tEBULK
10
—
ms
EEPROM programming voltage discharge period
tEEFPV
100
—
µs
tTH, tTL
tTLTL
2
—
—
tcyc
(4)
Bus operating frequency (4.5–5.5 V — VDD only)
(2)
16-bit timer
Input capture pulse width(3)
Input capture period
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +105°C, unless otherwise noted.
2. The 2-bit timer prescaler is the limiting factor in determining timer resolution.
3. Refer to Table 18-2. Mode, Edge, and Level Selection and supporting note.
4. The minimum period tTLTL or tILIL should not be less than the number of cycles it takes to execute the capture interrupt
service routine plus TBD tcyc.
29.6 ADC Characteristics
Characteristic(1)
Min
Max
Unit
Resolution
8
8
Bits
Absolute accuracy
(VREFL = 0 V, VDDA = VREFH = 5 V ± 10%)
–1
+1
LSB
Includes quantization
VREFL
VREFH
V
VREFL = VSSA
Conversion time period
Conversion range
16
17
µs
leakage(2)
Input
Ports B and D
—
±1
µA
Conversion time
16
17
ADC clock
cycles
Power-up time
Monotonicity
Comments
Includes sampling time
Inherent within total error
Zero input reading
00
01
Hex
VIn = VREFL
Full-scale reading
FE
FF
Hex
VIn = VREFH
Sample time(3)
5
—
ADC clock
cycles
Input capacitance
—
8
pF
Not tested
ADC internal clock
500 k
1.048 M
Hz
Tested only at 1 MHz
Analog input voltage
VREFL
VREFH
V
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, VDDA/VDDAREF = 5.0 Vdc ± 10%, VSSA = 0 Vdc, VREFH = 5.0 Vdc ± 10%
2. The external system error caused by input leakage current is approximately equal to the product of R source and input
current.
3. Source impedances greater than 10 kΩ adversely affect internal RC charging time during input sampling.
MC68HC908AT32 Data Sheet, Rev. 3.1
362
Freescale Semiconductor
5.0 Vdc ± 10% Serial Peripheral Interface (SPI) Timing
29.7 5.0 Vdc ± 10% Serial Peripheral Interface (SPI) Timing
Num(1)
Characteristic(2)
Symbol
Min
Max
Unit
Operating frequency(3)
Master
Slave
fBUS(M)
fBus(S)
fBUS/128
dc
fBUS/2
fBUS
MHz
1
Cycle time
Master
Slave
tcyc(M)
tcyc(S)
2
1
128
—
tcyc
2
Enable lead time
tLead
15
—
ns
3
Enable lag time
tLag
15
—
ns
4
Clock (SCK) high time
Master
Slave
tW(SCKH)M
tW(SCKH)S
100
50
—
—
ns
5
Clock (SCK) low time
Master
Slave
tW(SCKL)M
tW(SCKL)S
100
50
—
—
ns
6
Data setup time (inputs)
Master
Slave
tSU(M)
tSU(S)
45
5
—
—
ns
7
Data hold time (inputs)
Master
Slave
tH(M)
tH(S)
0
15
—
—
ns
tA(CP0)
tA(CP1)
0
0
40
20
ns
8
Access time, slave(4)
CPHA = 0
CPHA = 1
9
Slave disable time (hold time to high-impedance state)(5)
tDIS
—
25
ns
10
Data valid time after enable edge(6)
Master
Slave
tV(M)
tV(S)
—
—
10
40
ns
11
Data hold time (outputs, after enable edge)
Master
Slave
tHO(M)
tHO(S)
0
5
—
—
ns
1. Item numbers refer to dimensions in Figure 29-1 and Figure 29-2.
2. All timing is shown with respect to 30% VDD and 70% VDD, unless otherwise noted; assumes 100 pF load on all SPI pins.
3. fBus = the currently active bus frequency for the microcontroller.
4. Time to data active from high-impedance state.
5. Hold time to high-impedance state.
6. With 100 pF on all SPI pins
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
363
Electrical Specifications
SS
INPUT
SS PIN OF MASTER HELD HIGH
12
1
SCK (CPOL = 0)
OUTPUT
13
12
5
NOTE
4
12
SCK (CPOL = 1)
OUTPUT
13
5
NOTE
4
6
MISO
INPUT
MSB IN
BIT 6–1
10 (REF)
LSB IN
11
MOSI
OUTPUT
7
10
MASTER MSB OUT
11 (REF)
BIT 6–1
MASTER LSB OUT
13
12
Note: This first clock edge is generated internally, but is not seen at the SCK pin.
a) SPI Master Timing (CPHA = 0)
SS
INPUT
SS PIN OF MASTER HELD HIGH
1
SCK (CPOL = 0)
OUTPUT
13
12
5
NOTE
4
12
SCK (CPOL = 1)
OUTPUT
13
5
NOTE
4
6
MISO
INPUT
MSB IN
10 (REF)
BIT 6–1
11
MOSI
OUTPUT
MASTER MSB OUT
7
LSB IN
10
BIT 6–1
13
11
MASTER LSB OUT
12
Note: This last clock edge is generated internally, but is not seen at the SCK pin.
b) SPI Master Timing (CPHA = 1)
Figure 29-1. SPI Master Timing Diagram
MC68HC908AT32 Data Sheet, Rev. 3.1
364
Freescale Semiconductor
5.0 Vdc ± 10% Serial Peripheral Interface (SPI) Timing
SS
INPUT
1
SCK (CPOL = 0)
INPUT
13
12
12
13
3
5
4
2
SCK (CPOL = 1)
INPUT
5
4
8
MISO
INPUT
SLAVE
MSB OUT
6
MOSI
OUTPUT
BIT 6–1
10
7
MSB IN
9
SLAVE LSB OUT
11
NOTE
11
BIT 6–1
LSB IN
Note: Not defined but normally MSB of character just received
a) SPI Slave Timing (CPHA = 0)
SS
INPUT
13
1
SCK (CPOL = 0)
INPUT
12
5
4
2
3
SCK (CPOL = 1)
INPUT
8
MISO
OUTPUT
5
4
10
NOTE
MOSI
INPUT
12
SLAVE
MSB OUT
6
7
13
BIT 6–1
10
MSB IN
9
SLAVE LSB OUT
11
BIT 6–1
LSB IN
Note: Not defined but normally LSB of character previously transmitted
a) SPI Slave Timing (CPHA = 1)
Figure 29-2. SPI Slave Timing Diagram
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
365
Electrical Specifications
29.8 CGM Operating Conditions
Characteristic
Symbol
Min
Typ
Max
Comments
Operating voltage
VDD
4.5 V
—
5.5 V
Crystal reference frequency
fRCLK
1
—
8.4
Module crystal reference frequency
fXCLK
—
4.9152 MHz
—
Same frequency as fRCLK
Range nominal multiplier (MHz)
fNOM
—
4.9152
—
4.5–5.5 V, VDD only
VCO center-of-range frequency (MHz)
fVRS
4.9152
—
32.0
4.5–5.5 V, VDD only
VCO operating frequency (MHZ)
fVCLK
4.9152
—
32.0
Min
Typ
Max
29.9 CGM Component Information
Description
Symbol
Comments
Crystal load capacitance
CL
—
—
—
Consult crystal
manufacturer’s data
Crystal fixed capacitance
C1
—
2 x CL
—
Consult crystal
manufacturer’s data
Crystal tuning capacitance
C2
—
2 x CL
—
Consult crystal
manufacturer’s data
CFact
—
0.0154
—
F/s V
CF
—
CFact x
(VDDA/
fXCLK)
—
See 8.4.3 External Filter
Capacitor Pin
(CGMXFC)
—
CBYP must provide low ac
impedance from
f = fXCLK/100 to 100 x
fVCLK, so series
resistance must be
considered.
Filter capacitor multiply factor
Filter capacitor
Bypass capacitor
CBYP
—
0.1 µF
MC68HC908AT32 Data Sheet, Rev. 3.1
366
Freescale Semiconductor
CGM Acquisition/Lock Time Information
29.10 CGM Acquisition/Lock Time Information
Description(1)
Symbol
Min
Typ
Max
tACQ
—
(8 x VDDA)/(fXCLK x KACQ)
—
If CF chosen
correctly
tAL
—
(4 x VDDA)/(fXCLK x KTRK)
—
If CF chosen
correctly
Manual acquisition time
tLock
—
tACQ+tAL
—
Tracking mode entry frequency
tolerance
DTRK
0
—
± 3.6%
Acquisition mode entry
frequency tolerance
DUNT
± 6.3%
—
± 7.2%
LOCK entry frequency
tolerance
DLOCK
0
—
± 0.9%
LOCK exit frequency tolerance
DUNL
± 0.9%
—
± 1.8%
Reference cycles per
acquisition mode
measurement
nACQ
—
32
—
Reference cycles per tracking
mode measurement
nTRK
—
128
—
Automatic mode time
to stable
tACQ
nACQ/fXCLK
(8 x VDDA)/(fXCLK x KACQ)
tAL
nTRK/fXCLK
(4 x VDDA)/(fXCLK x KTRK)
—
tLock
—
tACQ+tAL
—
0
—
± (fCRYS)
x (.025%)
x (N/4)
Manual mode time to stable
Manual stable to lock time
Automatic stable to lock time
Automatic lock time
PLL jitter, deviation of average
bus frequency over 2 ms
Notes
If CF chosen
correctly
If CF chosen
correctly
N = VCO Freq.
Mult.
(GBNT)(2)
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +125°C, unless otherwise noted.
2. GBNT guaranteed but not tested
29.11 Timer Module Characteristics
Characteristic
Input capture pulse width
Input clock pulse width
Symbol
Min
Max
Unit
tTIH, tTIL
125
—
ns
tTCH, tTCL
(1/fOP) + 5
—
ns
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
367
Electrical Specifications
29.12 Memory Characteristics
Characteristic
Symbol
Min
Max
Unit
VRDR
0.7
—
V
EEPROM write/erase cycles
@ 10 ms write time + 85°C
—
10,000
—
Cycles
EEPROM data retention
After 10,000 write/erase cycles
—
10
—
Years
FLASH bus clock period
tcyc
250
—
ns
tErase
500
—
ms
tKill
200
—
µs
FLASH return to read time
tHVD
50
—
µs
FLASH program time, tPROG
tProg
1
100
ms
FLASH HVEN low to VERF high time, tHVTV
tHVTV
50
—
µs
FLASH VERIFY high to PGM low time, tVTP
tVTP
150
—
µs
Erase/program cycles
—
1000
Cycles
Erase/program cycles for a block
while maintaining data in the rest of
the array
—
100
Cycles
RAM data retention voltage
FLASH erase time
FLASH high-voltage kill time
FLASH endurance
FLASH block endurance
29.13 BDLC Transmitter VPW Symbol Timings
Characteristic(1)
Number
Symbol(2)
Min
Typ
Max
Unit
10
tTVP1
62
64
66
µs
Passive logic 1
11
tTVP2
126
128
130
µs
Active logic 0
12
tTVA1
126
128
130
µs
Active logic 1
13
tTVA2
62
64
66
µs
Start-of-frame (SOF)
14
tTVA3
198
200
202
µs
End of data (EOD)
15
tTVP3
198
200
202
µs
End of frame (EOF)
16
tTV4
278
280
282
µs
Inter-frame separator (IFS)
17
tTV6
298
300
302
µs
Passive logic 0
1. fBDLC = 1.048576 or 1.0 MHz, VDD = 5.0 V ± 10%, VSS = 0 V.
2. The transmitter symbol timing boundaries are subject to an uncertainty of 1 tBDLC µs due to sampling considerations.
MC68HC908AT32 Data Sheet, Rev. 3.1
368
Freescale Semiconductor
BDLC Receiver VPW Symbol Timings
29.14 BDLC Receiver VPW Symbol Timings
Characteristic(1)
Number
Symbol(2)
Min
Typ
Max
Unit
Passive logic 0
10
tTRVP1
34
64
96
µs
Passive logic 1
11
tTRVP2
96
128
163
µs
Active logic 0
12
tTRVA1
96
128
163
µs
Active logic 1
13
tTRVA2
34
64
96
µs
Start-of-frame (SOF)
14
tTRVA3
163
200
239
µs
End-of-data (EOD)
15
tTRVP3
163
200
239
µs
End-of-frame (EOF)
16
tTRV4
239
280
320
µs
Break
18
tTRV6
280
—
—
µs
1. fBDLC = 1.048576 or 1.0 MHz, VDD = 5.0 V ± 10%, VSS = 0 V.
2. The transmitter symbol timing boundaries are subject to an uncertainty of 1 tBDLC µs due to sampling considerations.
13
11
1
1
14
10
12
SOF
0
0
15
0
EOD
16
EOF
18
BRK
Figure 29-3. BDLC Variable Pulse-Width Modulation (VPW) Symbol Timing
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
369
Electrical Specifications
MC68HC908AT32 Data Sheet, Rev. 3.1
370
Freescale Semiconductor
Chapter 30
Mechanical Data
30.1 Introduction
This section provides package dimensions for:
• MC68HC08AS20 emulator packaged in a 52-pin plastic leaded chip carrier (PLCC)
• MC68HC08AZ32 emulator packaged in a 64-pin quad flat pack (QFP)
The following figures show the latest package drawings at the time of this publication. To make sure that
you have the latest package specifications, contact your local Freescale Sales Office.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
371
Mechanical Data
30.2 52-Pin Plastic Leaded Chip Carrier Package (Case 778)
0.007 (0.18)
B
Y BRK
–N–
M
T L–M
0.007 (0.18)
U
M
S
N
S
T L–M
S
N
S
D
Z
–M–
–L–
W
D
52
1
V
A
0.007 (0.18)
M
T L–M
S
N
S
R
0.007 (0.18)
M
T L–M
S
N
S
E
C
0.004 (0.100)
–T– SEATING
J
VIEW S
G
PLANE
G1
0.010 (0.25)
T L–M
S
H
N
S
0.007 (0.18)
M
T L–M
S
N
S
K1
K
F
S
T L–M
S
N
S
VIEW D–D
Z
S
G1
0.010 (0.25)
X
0.007 (0.18)
M
T L–M
S
N
S
VIEW S
NOTES:
1. DATUMS –L–, –M–, AND –N– DETERMINED WHERE
TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT
MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE MEASURED
AT DATUM –T–, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.012 (0.300).
DIMENSIONS R AND U ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE
BURRS AND INTERLEAD FLASH, BUT INCLUDING
ANY MISMATCH BETWEEN THE TOP AND BOTTOM
OF THE PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037 (0.940).
THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE
H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.785
0.795
0.785
0.795
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
–––
0.025
–––
0.750
0.756
0.750
0.756
0.042
0.048
0.042
0.048
0.042
0.056
–––
0.020
2_
10 _
0.710
0.730
0.040
–––
MILLIMETERS
MIN
MAX
19.94
20.19
19.94
20.19
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
–––
0.64
–––
19.05
19.20
19.05
19.20
1.07
1.21
1.07
1.21
1.07
1.42
–––
0.50
2_
10 _
18.04
18.54
1.02
–––
MC68HC908AT32 Data Sheet, Rev. 3.1
372
Freescale Semiconductor
64-Pin Quad Flat Pack (QFP)
30.3 64-Pin Quad Flat Pack (QFP)
L
33
48
49
DETAIL A
S
D
S
H A-B
D
V
P
B
M
B
B
0.20 (0.008)
L
0.20 (0.008) M C A-B
0.05 (0.002) A-B
-B-
-A-
S
S
32
-A-, -B-, DDETAIL A
17
64
1
F
16
-DA
0.20 (0.008) M C A-B
0.05 (0.002) A-B
0.20 (0.008)
M
S
H A-B
S
S
D
S
D
S
J
N
BASE METAL
M
E
DETAIL C
D
0.20 (0.008)
C
-H-
-CH
SEATING
PLANE
M
G
U
T
R
DATUM
PLANE
-HQ
K
W
X
DETAIL C
DATUM
PLANE
M
C A-B
S
D
S
SECTION B-B
0.01 (0.004)
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE ĆHĆ IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD WHERE
THE LEAD EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
4. DATUMS A-B AND ĆDĆ TO BE DETERMINED AT
DATUM PLANE ĆHĆ.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE ĆCĆ.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE DETERMINED
AT DATUM PLANE ĆHĆ.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT.
DIM
A
B
C
D
E
F
G
H
J
K
L
M
N
P
Q
R
S
T
U
V
W
X
MILLIMETERS
MIN
MAX
13.90 14.10
13.90 14.10
2.45
2.15
0.45
0.30
2.40
2.00
0.40
0.30
0.80 BSC
0.25
Ċ
0.23
0.13
0.95
0.65
12.00 REF
10°
5°
0.17
0.13
0.40 BSC
7°
0°
0.30
0.13
16.95 17.45
Ċ
0.13
Ċ
0°
16.95 17.45
0.45
0.35
1.6 REF
INCHES
MIN
MAX
0.547 0.555
0.547 0.555
0.085 0.096
0.012 0.018
0.079 0.094
0.012 0.016
0.031 BSC
Ċ
0.010
0.005 0.009
0.026 0.037
0.472 REF
5°
10°
0.005 0.007
0.016 BSC
0°
7°
0.005 0.012
0.667 0.687
0.005
Ċ
0°
Ċ
0.667 0.687
0.014 0.018
0.063 REF
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
373
Mechanical Data
MC68HC908AT32 Data Sheet, Rev. 3.1
374
Freescale Semiconductor
Chapter 31
Ordering Information
31.1 Introduction
This section contains instructions for ordering the MC68HC908AT32.
31.2 MC Order Numbers
Table 31-1. MC Order Numbers
MC Order Number
Operating
Temperature Range
MC68HC908AT32FN(1)
MC68HC908AT32CFN
MC68HC908AT32VFN
MC68HC908AT32MFN
0°C to + 70°C
– 40°C to + 85°C
– 40°C to + 105°C
– 40°C to + 125°C
MC68HC908AT32FU(2)
MC68HC908AT32CFU
MC68HC908AT32VFU
MC68HC908AT32MFU
0°C to + 70°C
– 40°C to + 85°C
– 40°C to + 105°C
– 40°C to + 125°C
1. FN = Plastic leaded chip carrier (PLCC) — MC68HC08AS20 emulator
2. FU = Quad flat pack (QFP) — MC68HC08AZ32 emulator
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
375
Ordering Information
MC68HC908AT32 Data Sheet, Rev. 3.1
376
Freescale Semiconductor
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MC68HC908AT32
Rev. 3.1, 09/2005
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