LC75890W 1/4-Duty and Static Drive General-Purpose LCD Driver Overview The LC75890W is the 1/4 duty and static drive general-purpose LCD display driver that can be used for displaying segments for household appliances, home audio visual products, portable devices and other such products under the control of a microcontroller.The LC75890W can drive up to 148 segments directly. In addition the LC75890W can control up to 12 general-purpose output ports. They can control the brightness of the LED backlight of RGB, because they have the PWM output of greatest 3CH built-in. Incorporation of the oscillation circuit helps to reduce the number of external resistors and capacitors required. Incorporation of the LCD drive bias voltage stabilization circuit helps to reduce the capacitors for the LCD drive bias voltage stabilization. www.onsemi.com SPQFP48 7x7 / SQFP48 Features Support for 1/4-duty 1/3-bias or static drive techniques under serial data control. When 1/4-duty drive : Capable of driving up to 148 segments When Static drive : Capable of driving up to 37 segments Support for display segment on, off, or blinking for each segment output pin under serial data control. Serial data control of the power-saving mode based backup function and the all segments forced off function. Serial data control of switching between the segment output port and general-purpose output port function. Support for up to 12 general-purpose output ports Support for the PWM output function of a maximum of 3 ch. (It can output from the general-purpose output port ). Serial data control of the frame frequency of the common and segment output waveforms. Serial data control of the segment blinking frequency. Serial data control of switching between the internal oscillator operating mode and external clock operating mode. Serial data input supports CCB* format communication with the system controller. Independent VLCD for the LCD driver block. Built-in LCD drive bias voltage stabilization circuit. The INH pin allows the display to be forced to the off state. Incorporation of an oscillator circuit. (Incorporation of resistor and capacitor for an oscillation) * Computer Control Bus (CCB) is an ON Semiconductor’s original bus format and the bus addresses are controlled by ON Semiconductor. ORDERING INFORMATION See detailed ordering and shipping information on page 29 of this data sheet. © Semiconductor Components Industries, LLC, 2017 July 2017 - Rev. 2 1 Publication Order Number : LC75890W/D LC75890W Specifications Absolute Maximum Ratings at Ta = 25C, VSS = 0 V Parameter Symbol Conditions Ratings Unit VDD max VDD 0.3 to +4.2 VLCD max VLCD 0.3 to +6.5 VIN1 CE, CL, DI, INH VIN2 OSCI : External clock operating mode 0.3 to VDD+0.3 V Output voltage VOUT S1 to S37, COM1 to COM4, P1 to P12 0.3 to VLCD+0.3 V Output current IOUT1 IOUT2 S1 to S36 300 A COM1 to COM4, S37 3 IOUT3 P1 to P12 *1 5 Allowable power dissipation Pd max Ta = 85C Operating temperature Topr 40 to +85 C Storage temperature Tstg 55 to +125 C Maximum supply voltage Input voltage V 0.3 to +4.2 100 mA mW Note : *1 The sum of output current through P1 to P12 must be 40 mA or less. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Allowable Operating Ranges at Ta = 40 to +85C, VSS = 0 V Parameter Supply voltage Symbol Conditions Input low-level voltage External clock operating frequency External clock duty cycle typ max VDD VDD 2.7 3.6 VLCD VLCD: Internal oscillator operating mode 2.7 5.5 VDD 5.5 0.7VDD 0.7VDD VDD VLCD: External clock operating mode Input high-level voltage Ratings min VIH1 CE, CL, DI, INH VIH2 OSCI: External clock operating mode Unit V 3.6 0.2VDD 0.2VDD V VIL1 CE, CL, DI, INH 0 VIL2 OSCI: External clock operating mode 0 fCK 160 ns 160 ns V Data setup time tds OSCI: External clock operating mode [Figure 3] OSCI: External clock operating mode [Figure 3] CL, DI [Figure 1], [Figure 2] Data hold time tdh CL, DI [Figure 1], [Figure 2] CE wait time tcp CE, CL [Figure 1], [Figure 2] 160 ns CE setup time tcs CE, CL [Figure 1], [Figure 2] 160 ns CE hold time tch CE, CL [Figure 1], [Figure 2] 160 ns High-level clock pulse width tH CL [Figure 1], [Figure 2] 160 ns Low-level clock pulse width tL CL [Figure 1], [Figure 2] 160 ns Rise time tr CE, CL, DI [Figure 1], [Figure 2] 160 Fall time tf CE, CL, DI [Figure 1], [Figure 2] 160 INH switching time tc INH [Figure 4], [Figure 5] DCK 10 38 600 kHz 30 50 70 % 10 ns ns s Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. www.onsemi.com 2 LC75890W Electrical Characteristics for the Allowable Operating Ranges Parameter Hysteresis Input high-level current Input low-level current Output highlevel voltage Output low-level voltage Output middlelevel voltage Symbol Conditions Ratings min typ Unit max VH IIH1 CE, CL, DI, INH CE, CL, DI, INH VI = 3.6 V 1.0 IIH2 OSCI 1.0 IIL1 CE, CL, DI, INH VI = VDD : External clock operating mode VI = 0 V IIL2 OSCI VOH1 VOH2 S1 to S37 0.1VDD VI = 0 V : External clock operating mode IO = 10 A IO = 100 A V A 1.0 VLCD0.9 VOH3 IO = 1 mA VOL1 S1 to S37 IO = 10 A 0.9 VOL2 IO = 100 A 0.9 VOL3 COM1 to COM4 P1 to P12 IO = 1 mA 0.9 VMID1 S1 to S37 1/4 duty IO = ±10 A VMID2 S1 to S37 1/4 duty IO = ±10 A VMID3 1/4 duty IO = ±100 A IDD1 COM1 to COM4 COM1 to COM4 Internal oscillator circuit VDD IDD2 VDD VDD = 3.3 V, Normal mode, External clock operating mode *2 VDD = 3.3 V, Normal mode, External clock operating mode *2 Serial data transfer *3 VDD = 3.3 V, Normal mode, Internal oscilloator operating mode VDD = 3.3 V, Normal mode, Internal oscilloator operating mode, Serial data transfer *3 Power-saving mode fosc IDD3 IDD4 IDD5 VDD VDD VDD ILCD1 VLCD ILCD2 VLCD ILCD3 VLCD ILCD4 VLCD ILCD5 VLCD A 1.0 COM1 to COM4 P1 to P12 VMID4 Oscillator frequency Current drain Pin VLCD0.9 V VLCD0.9 1/4 duty IO = ±100 A Internal oscillator operating mode Power-saving mode VLCD = 3.3 V, Output open, Normal mode, Static drive VLCD = 3.3 V, Output open, Normal mode, 1/4 duty drive VLCD = 5.0 V, Output open, Normal mode, Static drive VLCD = 5.0 V, Output open, Normal mode, 1/4 duty drive 2/3VLCD 0.9 1/3VLCD 0.9 2/3VLCD 0.9 1/3VLCD 0.9 240 2/3VLCD +0.9 1/3VLCD +0.9 2/3VLCD +0.9 1/3VLCD +0.9 300 360 V V kHz 2 5 10 90 180 50 100 135 270 A 2 8 16 70 140 10 20 90 180 Note : *2 External clock operating mode (fCK = 38 kHz, VIH2 = VDD, VIL2 = 0 V, rise/fall time = 20 ns) *3 Serial data transfer (data transfer frequency 2 MHz, VIH1 = VDD, VIL1 = 0 V, rise/fall time = 20 ns) Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 3 LC75890W 1. When CL is stopped at the low level VIH1 tL tH tf tr VIH1 DI VIL1 tds tcp VIH1 50% VIL1 CL VIL1 CE tcs tch tdh [Figure 1] 2. When CL is stopped at the high level VIH1 VIL1 CE tH tL tf tr DI VIL1 tds tcp tcs tch VIH1 VIH1 50% VIL1 CL tdh [Figure 2] 3. OSCI pin clock timing in external clock operating mode tCKH OSCI fCK= tCKL VIH2 50% VIL2 1 tCKH + tCKL DCK= t [Figure 3] www.onsemi.com 4 [kHz] tCKH 100[%] CKH + tCKL LC75890W Package Dimensions unit : mm SPQFP48 7x7 / SQFP48 CASE 131AJ ISSUE A 0.50.2 9.00.2 9.00.2 48 7.00.1 7.00.1 1 2 0.5 0.150.05 0.18 0.10 (1.5) 0 to 10 0.10.1 1.7 MAX (0.75) 0.10 SOLDERING FOOTPRINT* GENERIC MARKING DIAGRAM* 8.40 XXXXXXXX YDD 8.40 (Unit: mm) XXXXX = Specific Device Code Y = Year DD = Additional Traceability Data XXXXXXXX YMDDD XXXXX = Specific Device Code Y = Year M = Month DDD = Additional Traceability Data 0.50 0.28 1.00 *This information is generic. Please refer to device data sheet for actual part marking. NOTE: The measurements are not to guarantee but for reference only. *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 5 LC75890W COM4 36 37 S25 S27 S26 S28 S30 S29 S31 S32 S33 S35 S34 S36 Pin Assignment 25 24 COM3 S24 S23 COM2 COM1 S22 S21 OSCI/S37 S20 LC75890W SQFP48(7×7) VDD VLCD S19 S18 VSS INH S17 S16 CE S15 S14 S13 P12/S12 P11/S11 P9/S9 P10/S10 P8/S8 P7/S7 P6/S6 P5/S5 P4/S4 P3/S3 13 12 P2/S2 48 1 P1/S1 CL DI Top view COMMON DRIVER SEGMENT DRIVER & LATCH INH OSCI/S37 CLOCK GENERATOR CONTROL REGISTER VDD VLCD SHIFT REGISTER LCD DRIVE BIAS VOLTAGE STABILIZATION CIRCUIT 2/3VLCD CCB INTERFACE 1/3VLCD www.onsemi.com 6 CE CL DI VSS S1/P1 S2/P2 S12/P12 S13 S36 COM3 COM4 COM2 COM1 Block Diagram LC75890W Pin Functions Handling Symbol Pin No. Function Active I/O when unused S1/P1 1 S2/P2 2 S3/P3 3 S4/P4 4 S5/P5 5 S6/P6 6 S7/P7 7 S8/P8 8 S9/P9 9 S10/P10 10 S11/P11 11 S12/P12 12 S13 13 S14 14 S15 15 S16 16 S17 17 Segment outputs for displaying the display data transferred by S18 18 serial data input. S19 19 The S1/P1 to S12/P12 pins can be used as general-purpose S20 20 output ports under serial data control. S21 21 S22 22 S23 23 S24 24 S25 25 S26 26 S27 27 S28 28 S29 29 S30 30 S31 31 S32 32 S33 33 S34 34 S35 35 S36 36 COM4 37 COM3 38 COM2 39 COM1 40 S37/OSCI 41 Common driver outputs The frame frequency is fo[Hz]. - O OPEN - O OPEN - I/O OPEN H I Segment output. This pin can also be used as the external clock input pin when the external clock operating mode is selected by control data. CE 46 Serial data transfer inputs. Must be connected to the controller. CL 47 I CE : Chip enable GND CL : Synchronization clock DI 48 - DI : Transfer data I Continued on next page. www.onsemi.com 7 LC75890W Continued from preceding page. Handling Symbol Pin No. Function Active I/O when unused Display off control input • INH = low (VSS) ...Display forced off S1/P1 to S12/P12=low (VSS) (These pins are forcibly set to the general-purpose output port function and held at the VSS level.) S13 to S36=low (VSS) COM1 to COM4=low (VSS) S37/OSCI=low (VSS) (This pin is forcibly set to the segment output port function and held at the VSS level.) INH 45 LCD drive bias voltage stabilization circuit stopped. L I GND - - - - - - - - - Stops the internal oscillator. Inhibits external clock input. • INH = high (VDD) ...Display on LCD drive bias voltage stabilization circuit is enabled. Enables the internal oscillator circuit. (Internal oscillator operating mode) Enables external clock input. (External clock operating mode) However, serial data transfer is possible when the display is forced off. VDD 42 VLCD 43 VSS 44 Logic block power supply pin. A power voltage of 2.7 to 3.6 V must be applied to this pin. LCD driver block power supply pin. A power voltage of 2.7 to 5.5 V must be applied to this pin. Ground pin. Must be connected to ground. www.onsemi.com 8 LC75890W Serial Data Input 1. 1/4 duty drive (1) When CL is stopped at the low level • Display data Input CE CL DI 0 0 0 0 1 0 1 0 D1 D2 D3 D4 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bits D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 D49 D50 D51 D52 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bits D77 D78 D79 D80 D81 D82 D83 D84 D85 D86 D87 D88 D89 D90 D91 D92 D93 D94 D95 D96 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 D97 D98 D99 D100 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bits D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 D142 D143 D144 D145 D146 D147 D148 0 0 1 0 Display data 48 bits Fixed data 5 bits DD 3 bits CE CL DI Display data 48 bits Fixed data 5 bits DD 3 bits CE CL DI Display data 52 bits DD Fixed data 3 bits 1 bits • Control data Input CE CL DI 0 0 0 0 1 0 1 0 BD1 BD2 BD3 BD4 BD5 BD6 BD7 BD8 BD9 BD10 BD11 BD12 BD13 BD14 BD15 BD16 BD17 BD18 BD19 BD20 BD21 BD22 BD23 BD24 BD25 BD26 BD27 BD28 B0 B1 B2 B3 A0 A1 A2 A3 CCB address Control data 8 bits 53 bits BD29 BD30 BD31 BD32 BD33 BD34 BD35 BD36 BD37 BF0 BF1 BF2 FC0 FC1 FC2 DT EXF OC SC BU 0 0 0 0 0 0 1 1 DD 3 bits CE CL DI 0 0 0 0 1 0 1 0 W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 PF0 PF1 PF2 PF3 P1A P1B P2A P2B P3A P3B B0 B1 B2 B3 A0 A1 A2 A3 CCB address Control data 8 bits 53 bits P4A P4B P5A P5B P6A P6B P7A P7B P8A P8B P9A P9B P10A P10B P11A P11B P12A P12B P0 P1 P2 P3 0 0 0 1 0 0 DD 3 bits Note: DD is the direction data. www.onsemi.com 9 LC75890W (2) When CL is stopped at the high level • Display data Input CE CL DI 0 0 0 0 1 0 1 0 D1 D2 D3 D4 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bits D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 D49 D50 D51 D52 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bits D77 D78 D79 D80 D81 D82 D83 D84 D85 D86 D87 D88 D89 D90 D91 D92 D93 D94 D95 D96 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 D97 D98 D99 D100 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bits D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 D142 D143 D144 D145 D146 D147 D148 0 0 1 0 Display data 48 bits Fixed data 5 bits DD 3 bits CE CL DI Display data 48 bits Fixed data 5 bits DD 3 bits CE CL DI Display data 52 bits DD Fixed data 3 bits 1 bits • Control data Input CE CL DI 0 0 0 0 1 0 1 0 BD1 BD2 BD3 BD4 BD5 BD6 BD7 BD8 BD9 BD10 BD11 BD12 BD13 BD14 BD15 BD16 BD17 BD18 BD19 BD20 BD21 BD22 BD23 BD24 BD25 BD26 BD27 BD28 B0 B1 B2 B3 A0 A1 A2 A3 CCB address Control data 8 bits 53 bits BD29 BD30 BD31 BD32 BD33 BD34 BD35 BD36 BD37 BF0 BF1 BF2 FC0 FC1 FC2 DT EXF OC SC BU 0 0 0 0 0 0 1 1 DD 3 bits CE CL DI 0 0 0 0 1 0 1 0 W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 PF0 PF1 PF2 PF3 P1A P1B P2A P2B P3A P3B B0 B1 B2 B3 A0 A1 A2 A3 CCB address Control data 8 bits 53 bits P4A P4B P5A P5B P6A P6B P7A P7B P8A P8B P9A P9B P10A P10B P11A P11B P12A P12B P0 P1 P2 P3 0 0 0 1 0 0 DD 3 bits Note: DD is the direction data. www.onsemi.com 10 LC75890W • CCB address ......................... • D1 to D148 ........................... • BD1 to BD37 ........................ • BF0 to BF2 ........................... • FC0 to FC2 ........................... • DT ........................................ • EXF ...................................... • OC ........................................ • SC ......................................... • BU ........................................ • W10 to W15, W20 to W25, ... W30 to W35 • PF0 to PF3 ............................ • P1A, P1B to P12A, P12B ..... “50H” Display data Display blinking control data of each segment output pin Segment blinking frequency setting control data Common/segment output waveform frame frequency setting control data 1/4-duty 1/3-bias drive or static drive switching control data External clock operating frequency setting control data Internal oscillator operating mode/external clock operating mode switching control data Segment on/off control data Normal mode/power-saving mode control data PWM data of the PWM output PWM output waveform frame frequency setting control data General-purpose output function/PWM output function switiching control data of the general-purpose output port • P0 to P3 ................................ Segment output port/general-purpose output port switching control data 2. Static drive (1) When CL is stopped at the low level • Display data Input CE CL DI 0 0 0 0 1 0 1 0 D1 D2 D3 D4 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bits D29 D30 D31 D32 D33 D34 D35 D36 D37 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Display data 37 bits Fixed data 16 bits DD 3 bits • Control data Input CE CL DI 0 0 0 0 1 0 1 0 BD1 BD2 BD3 BD4 BD5 BD6 BD7 BD8 BD9 BD10 BD11 BD12 BD13 BD14 BD15 BD16 BD17 BD18 BD19 BD20 BD21 BD22 BD23 BD24 BD25 BD26 BD27 BD28 B0 B1 B2 B3 A0 A1 A2 A3 CCB address Control data 8 bits 53 bits BD29 BD30 BD31 BD32 BD33 BD34 BD35 BD36 BD37 BF0 BF1 BF2 FC0 FC1 FC2 DT EXF OC SC BU 0 0 0 0 0 0 1 1 DD 3 bits CE CL DI 0 0 0 0 1 0 1 0 W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 PF0 PF1 PF2 PF3 P1A P1B P2A P2B P3A P3B B0 B1 B2 B3 A0 A1 A2 A3 CCB address Control data 8 bits 53 bits P4A P4B P5A P5B P6A P6B P7A P7B P8A P8B P9A P9B P10A P10B P11A P11B P12A P12B P0 P1 P2 P3 0 0 0 1 0 0 DD 3 bits Note: DD is the direction data. www.onsemi.com 11 LC75890W (2) When CL is stopped at the high level • Display data Input CE CL DI 0 0 0 0 1 0 1 0 D1 D2 D3 D4 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bits D29 D30 D31 D32 D33 D34 D35 D36 D37 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Display data 37 bits Fixed data 16 bits DD 3 bits • Control data Input CE CL DI 0 0 0 0 1 0 1 0 BD1 BD2 BD3 BD4 BD5 BD6 BD7 BD8 BD9 BD10 BD11 BD12 BD13 BD14 BD15 BD16 BD17 BD18 BD19 BD20 BD21 BD22 BD23 BD24 BD25 BD26 BD27 BD28 B0 B1 B2 B3 A0 A1 A2 A3 CCB address Control data 8 bits 53 bits BD29 BD30 BD31 BD32 BD33 BD34 BD35 BD36 BD37 BF0 BF1 BF2 FC0 FC1 FC2 DT EXF OC SC BU 0 0 0 0 0 0 1 1 DD 3 bits CE CL DI 0 0 0 0 1 0 1 0 W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 PF0 PF1 PF2 PF3 P1A P1B P2A P2B P3A P3B B0 B1 B2 B3 A0 A1 A2 A3 CCB address Control data 8 bits 53 bits P4A P4B P5A P5B P6A P6B P7A P7B P8A P8B P9A P9B P10A P10B P11A P11B P12A P12B P0 P1 P2 P3 0 0 0 1 0 0 DD 3 bits Note: DD is the direction data. • CCB address ......................... • D1 to D37 ............................. • BD1 to BD37 ........................ • BF0 to BF2 ........................... • FC0 to FC2 ........................... • DT ........................................ • EXF ...................................... • OC ........................................ • SC ......................................... • BU ........................................ • W10 to W15, W20 to W25, ... W30 to W35 • PF0 to PF3 ............................ • P1A, P1B to P12A, P12B ..... “50H” Display data Display blinking control data of each segment output pin Segment blinking frequency setting control data Common/segment output waveform frame frequency setting control data 1/4-duty 1/3-bias drive or static drive switching control data External clock operating frequency setting control data Internal oscillator operating mode/external clock operating mode switching control data Segment on/off control data Normal mode/power-saving mode control data PWM data of the PWM output PWM output waveform frame frequency setting control data General-purpose output function/PWM output function switiching control data of the general-purpose output port • P0 to P3 ................................ Segment output port/general-purpose output port switching control data www.onsemi.com 12 LC75890W Serial Data Transfer Example 1. 1/4 duty drive • When 97 or more segments are used All 320 bits of serial data (including CCB address) must be sent. 8 bits 0 0 0 0 1 56 bits 0 1 0 BD1 BD2 BD3 BD4 BD5 BD6 BD7 BD8 BD9 BD10 BD11 BD12 BD13 BD14 BD15 BD16 BD17 BD18 BD19 BD20 BD21 BD22 BD23 BD24 BD25 BD26 BD27 BD28 BD29 BD30 BD31 BD32 B0 B1 B2 B3 A0 A1 A2 A3 BD33 BD34 BD35 BD36 BD37 BF0 BF1 BF2 FC0 FC1 FC2 DT EXF OC SC BU 0 8 bits 0 0 0 0 1 0 0 0 0 0 1 1 56 bits 0 1 0 W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 PF0 PF1 PF2 PF3 P1A P1B P2A P2B P3A P3B P4A P4B P5A P5B B0 B1 B2 B3 A0 A1 A2 A3 P6A P6B P7A P7B P8A P8B P9A P9B P10A P10B P11A P11B P12A P12B P0 P1 P2 P3 0 8 bits 0 0 0 0 1 0 0 1 0 0 56 bits 0 1 0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 B0 B1 B2 B3 A0 A1 A2 A3 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 0 8 bits 0 0 0 0 1 0 0 0 0 0 0 0 56 bits 0 1 0 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 D64 D65 D66 D67 D68 D69 D70 D71 D72 D73 D74 D75 D76 D77 D78 D79 D80 B0 B1 B2 B3 A0 A1 A2 A3 D81 D82 D83 D84 D85 D86 D87 D88 D89 D90 D91 D92 D93 D94 D95 D96 0 8 bits 0 0 0 0 1 0 0 0 0 0 0 1 56 bits 0 1 0 D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 D120 D121 D122 D123 D124 D125 D126 D127 D128 B0 B1 B2 B3 A0 A1 A2 A3 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 D142 D143 D144 D145 D146 D147 D148 0 0 1 0 • When fewer than 97 segments are used Depending on the number of segments used, 192 bits or 256 bits (including CCB address) must be sent as serial data. However, the serial data (control data) shown in the figure below must be sent without fail. 56 bits 8 bits 0 0 0 0 1 0 1 0 BD1 BD2 BD3 BD4 BD5 BD6 BD7 BD8 BD9 BD10 BD11 BD12 BD13 BD14 BD15 BD16 BD17 BD18 BD19 BD20 BD21 BD22 BD23 BD24 BD25 BD26 BD27 BD28 BD29 BD30 BD31 BD32 B0 B1 B2 B3 A0 A1 A2 A3 BD33 BD34 BD35 BD36 BD37 BF0 BF1 BF2 FC0 FC1 FC2 DT EXF OC SC BU 0 0 0 0 1 0 0 0 0 1 1 56 bits 8 bits 0 0 0 1 0 W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 PF0 PF1 PF2 PF3 P1A P1B P2A P2B P3A P3B P4A P4B P5A P5B B0 B1 B2 B3 A0 A1 A2 A3 P6A P6B P7A P7B P8A P8B P9A P9B P10A P10B P11A P11B P12A P12B P0 P1 P2 P3 0 0 0 1 0 0 Note : After the above serial data is sent, the contents of the display data can be changed by transferring only the serial data (CCB address, display data, fixed data, and direction data) including the display data to be changed in 64-bit units. www.onsemi.com 13 LC75890W 2. Static drive • All 192 bits of serial data (including CCB address) must be sent. 8 bits 0 0 0 0 1 56 bits 0 1 0 BD1 BD2 BD3 BD4 BD5 BD6 BD7 BD8 BD9 BD10 BD11 BD12 BD13 BD14 BD15 BD16 BD17 BD18 BD19 BD20 BD21 BD22 BD23 BD24 BD25 BD26 BD27 BD28 BD29 BD30 BD31 BD32 B0 B1 B2 B3 A0 A1 A2 A3 BD33 BD34 BD35 BD36 BD37 BF0 BF1 BF2 FC0 FC1 FC2 DT EXF OC SC BU 0 0 0 0 1 0 0 0 0 1 1 56 bits 8 bits 0 0 0 1 0 W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 PF0 PF1 PF2 PF3 P1A P1B P2A P2B P3A P3B P4A P4B P5A P5B B0 B1 B2 B3 A0 A1 A2 A3 P6A P6B P7A P7B P8A P8B P9A P9B P10A P10B P11A P11B P12A P12B P0 P1 P2 P3 0 8 bits 0 0 0 0 1 0 0 1 0 0 56 bits 0 1 0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 B0 B1 B2 B3 A0 A1 A2 A3 D33 D34 D35 D36 D37 0 0 0 0 0 0 0 0 0 www.onsemi.com 14 0 0 0 0 0 0 0 0 0 0 LC75890W Control Data Functions (1) BD1 to BD37 … Display blinking control data of each segment output pin These control data bits are used to set the display segment blinking corresponding to each segment output pin. BDn Display segment blinking states of segment output pin Sn 0 The display segments are not blinked. The display segments corresponding to the segment output pin Sn that the contents of display 1 data are "1" are blinked. Note: The BDn (n=1 to 37) are the control data setting the blinking state of the display segments for segment output pins Sn (n=1 to 37). For example, the display state of segment output pin S21 becomes as follows when the contents of display data are (D81, D82, D83, D84) = (1, 0, 1, 0) in 1/4 duty drive Display data Display states of segment output pin S21 BD21 D81 D82 D83 D84 COM1 COM2 COM3 COM4 0 1 0 1 0 on off on off 1 1 0 1 0 blink off blink off (2) BF0 to BF2 … Segment blinking frequency setting control data These control data bits are used to set the display segment blinking frequency Control data BF0 BF1 Segment blinking frequency fb[Hz] BF2 Internal oscillator operating mode External clock operating mode (The control data OC is 0, (The control data OC is 1 External clock operating mode (The control data OC is 1 fosc=300[kHz]typ) and EXF is 0, fCK1=300[kHz]typ) and EXF is 1, fCK2=38[kHz]typ) 0 0 0 fosc/600000 fCK1/600000 fCK2/75000 1 0 0 fosc/360000 fCK1/360000 fCK2/45000 0 1 0 fosc/300000 fCK1/300000 fCK2/37500 1 1 0 fosc/240000 fCK1/240000 fCK2/30000 0 0 1 fosc/180000 fCK1/180000 fCK2/22500 1 0 1 fosc/150000 fCK1/150000 fCK2/18750 0 1 1 fosc/120000 fCK1/120000 fCK2/15000 1 1 1 fosc/100000 fCK1/100000 fCK2/12500 (3) FC0 to FC2 … Common/segment output waveform frame frequency setting control data These control data bits set the frame frequency of the common and segment output waveforms. Control data FC0 FC1 Common/segment output waveform frame frequency fo[Hz] FC2 Internal oscillator operating mode External clock operating mode (The control data OC is 0, (The control data OC is 1 External clock operating mode (The control data OC is 1 fosc=300[kHz]typ) and EXF is 0, fCK1=300[kHz]typ) and EXF is 1, fCK2=38[kHz]typ) 0 0 0 fosc/4608 fCK1/4608 fCK2/576 0 0 1 fosc/3456 fCK1/3456 fCK2/432 0 1 0 fosc/3072 fCK1/3072 fCK2/384 0 1 1 fosc/2304 fCK1/2304 fCK2/288 1 0 0 fosc/1536 fCK1/1536 fCK2/192 1 0 1 fosc/1152 fCK1/1152 fCK2/144 1 1 0 fosc/768 fCK1/768 fCK2/96 Note: When is setting (FC0, FC1, FC2)=(1, 1, 1), the frame frequency is same as frame frequency at the time of the (FC0, FC1, FC2)=(0, 1, 0) setting (fosc/3072, fCK1/3072, fCK2/384). www.onsemi.com 15 LC75890W (4) DT … 1/4-duty 1/3-bias drive or static drive switching control data This control data bit selects either 1/4-duty 1/3-bias drive or static drive. Common output pins states DT Drive scheme COM2 COM3 COM4 0 1/4 duty 1/3 bias drive COM2 COM3 COM4 1 Static drive “L” (VSS) “L” (VSS) “L” (VSS) Note: COM2, COM3, COM4 : Common output “L” (VSS) : ”L” (VSS) level output (5) EXF … External clock operating frequency setting control data This control data bit sets the operating frequency of the external clock which input into the OSCI pin, when the external clock operating mode (OC = "1") is set. However, this control data is effective only when external clock operating mode (OC = "1") is set. EXF External clock operating frequency fCK[kHz] 0 fCK1=300[kHz]typ 1 fCK2=38[kHz]typ (6) OC … Internal oscillator operating mode/external clock operating mode switching control data This control data bit selects either the internal oscillator operating mode or external clock operating mode. OC Fundamental clock operating mode I/O pin (S37/OSCI) state 0 Internal oscillator operating mode S37 1 External clock operating mode OSCI Note: S37: Segment output OSCI: External clock input (7) SC … Segment on/off control data This control data bit controls the on/off state of the segments. SC Display state 0 On 1 Off Note that when the segments are turned off by setting SC to 1, the segments are turned off by outputting segment off waveforms from the segment output pins. (8) BU … Normal mode/power-saving mode control data This control data bit selects either normal mode or power-saving mode. BU 0 Mode Normal mode Power saving mode In this mode, the internal oscillator circuit stops oscillation (the S37/OSCI pin is configured for segment output) if the IC is in the internal oscillator operating mode (OC=0) and the IC stops receiving external clock signals (the S37/OSCI pin is configured for external clock input) if the IC is in the external clock operating 1 mode (OC=1). In addition, the common and segment output pins go to the VSS level and the operation of LCD drive bias voltage stabilization circuit stops. However, the S1/P1 to S12/P12 output pins can be used as general-purpose output ports under the control of the data bits P0 to P3. (The general-purpose output port P1 to P12 can not be used as PWM output). www.onsemi.com 16 LC75890W (9) W10 to W15, W20 to W25, W30 to W35 … PWM data of the PWM output These control data bits set the pulse width of the PWM output P1 to P12. However, when the PWM output function isn’t used, these control data bits become invalid. In addition, when the external clock operating frequency is set the fCK2 = 38[kHz]typ (EXF="1") in external clock operating mode (OC = "1"), these control data bits become invalid. Wn0 Wn1 Wn2 Wn3 Wn4 Wn5 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 1 1 0 0 1 Pulse width of Pulse width of Wn0 Wn1 Wn2 Wn3 Wn4 Wn5 (1/64)×Tp 0 0 0 0 0 1 (33/64)×Tp 0 (2/64)×Tp 1 0 0 0 0 1 (34/64)×Tp 0 0 (3/64)×Tp 0 1 0 0 0 1 (35/64)×Tp 0 0 (4/64)×Tp 1 1 0 0 0 1 (36/64)×Tp 0 0 0 (5/64)×Tp 0 0 1 0 0 1 (37/64)×Tp 1 0 0 0 (6/64)×Tp 1 0 1 0 0 1 (38/64)×Tp 1 1 0 0 0 (7/64)×Tp 0 1 1 0 0 1 (39/64)×Tp 1 1 0 0 0 (8/64)×Tp 1 1 1 0 0 1 (40/64)×Tp 0 0 0 1 0 0 (9/64)×Tp 0 0 0 1 0 1 (41/64)×Tp 1 0 0 1 0 0 (10/64)×Tp 1 0 0 1 0 1 (42/64)×Tp 0 1 0 1 0 0 (11/64)×Tp 0 1 0 1 0 1 (43/64)×Tp 1 1 0 1 0 0 (12/64)×Tp 1 1 0 1 0 1 (44/64)×Tp 0 0 1 1 0 0 (13/64)×Tp 0 0 1 1 0 1 (45/64)×Tp 1 0 1 1 0 0 (14/64)×Tp 1 0 1 1 0 1 (46/64)×Tp 0 1 1 1 0 0 (15/64)×Tp 0 1 1 1 0 1 (47/64)×Tp 1 1 1 1 0 0 (16/64)×Tp 1 1 1 1 0 1 (48/64)×Tp 0 0 0 0 1 0 (17/64)×Tp 0 0 0 0 1 1 (49/64)×Tp 1 0 0 0 1 0 (18/64)×Tp 1 0 0 0 1 1 (50/64)×Tp 0 1 0 0 1 0 (19/64)×Tp 0 1 0 0 1 1 (51/64)×Tp 1 1 0 0 1 0 (20/64)×Tp 1 1 0 0 1 1 (52/64)×Tp 0 0 1 0 1 0 (21/64)×Tp 0 0 1 0 1 1 (53/64)×Tp 1 0 1 0 1 0 (22/64)×Tp 1 0 1 0 1 1 (54/64)×Tp 0 1 1 0 1 0 (23/64)×Tp 0 1 1 0 1 1 (55/64)×Tp 1 1 1 0 1 0 (24/64)×Tp 1 1 1 0 1 1 (56/64)×Tp 0 0 0 1 1 0 (25/64)×Tp 0 0 0 1 1 1 (57/64)×Tp 1 0 0 1 1 0 (26/64)×Tp 1 0 0 1 1 1 (58/64)×Tp 0 1 0 1 1 0 (27/64)×Tp 0 1 0 1 1 1 (59/64)×Tp 1 1 0 1 1 0 (28/64)×Tp 1 1 0 1 1 1 (60/64)×Tp 0 0 1 1 1 0 (29/64)×Tp 0 0 1 1 1 1 (61/64)×Tp 1 0 1 1 1 0 (30/64)×Tp 1 0 1 1 1 1 (62/64)×Tp 0 1 1 1 1 0 (31/64)×Tp 0 1 1 1 1 1 (63/64)×Tp 1 1 1 1 1 0 (32/64)×Tp 1 1 1 1 1 1 (64/64)×Tp PWM output Note: W10 to W15 … PWM data of the PWM output (Ch1) W20 to W25 … PWM data of the PWM output (Ch2) W30 to W35 … PWM data of the PWM output (Ch3) www.onsemi.com 17 PWM output Tp= 1 fp LC75890W (10) PF0 to PF3 … PWM output waveform frame frequency setting control data These control data bits set the frame frequency of the PWM output waveforms. However, when the PWM output function isn’t used, these control data bits become invalid. In addition, when the external clock operating frequency is set the fCK2 = 38[kHz]typ (EXF="1") in external clock operating mode (OC = "1"), these control data bits become invalid. Control data PWM output waveform frame frequency fp[Hz] Internal oscillator operating mode External clock operating mode (The control data OC is 0, (The control data OC is 1 and EXF is 0, PF0 PF1 PF2 PF3 fosc=300[kHz] typ) fCK1=300[kHz] typ) 0 0 0 0 fosc/1536 fCK1/1536 1 0 0 0 fosc/1408 fCK1/1408 0 1 0 0 fosc/1280 fCK1/1280 1 1 0 0 fosc/1152 fCK1/1152 0 0 1 0 fosc/1024 fCK1/1024 1 0 1 0 fosc/896 fCK1/896 0 1 1 0 fosc/768 fCK1/768 1 1 1 0 fosc/640 fCK1/640 0 0 0 1 fosc/512 fCK1/512 1 0 0 1 fosc/384 fCK1/384 0 1 0 1 fosc/256 fCK1/256 Note: When are setting (PF0, PF1, PF2, PF3)=(1, 1, 0, 1) and (X, X, 1, 1), the frame frequency is same as frame frequency at the time of the (PF0, PF1, PF2, PF3)=(1, 0, 1, 0) setting (fosc/896, fCK1/896). X: don’t care (11) P1A, P1B to P12A, P12B … General-purpose output function/PWM output function switiching control data of the general-purpose output port These control data bits set the general-purpose output function (High or low level output) or PWM output function of the general-purpose output ports P1 to P12. However, when the S1/P1 to S12/P12 output pins arn’t set the general-purpose output port, these control data bits become invalid. In addition, be careful of being unable to set a PWM output function when the external clock operating frequency is set the fCK2 = 38[kHz]typ (EXF="1") in external clock operating mode (OC = "1"). PnA PnB Functions of the general-purpose output port (Pn) 0 0 General-purpose output function (High or low level output) 1 0 PWM output function (Ch1) 0 1 PWM output function (Ch2) 1 1 PWM output function (Ch3) Note: The data PnA, PnB (n=1 to 12) are the control data switching the general-purpose output function or PWM output function of the general-purpose output ports P1 to p12. For example, if the S10/P10 output pin is set the general-purpose output port, the general-purpose output port P10 pin is selected the PWM output function (Ch1) when (P10A, P10B) = (1, 0). www.onsemi.com 18 LC75890W (12) P0 to P3 … Segment output port/general-purpose output port switching control data These control data bits switch the segment output port/general-purpose output port functions of the S1/P1 to S12/P12 output pins. Control data Output pin state P0 P1 P2 P3 S1/P1 S2/P2 S3/P3 S4/P4 S5/P5 S6/P6 S7/P7 S8/P8 S9/P9 S10/P10 S11/P11 S12/P12 0 0 0 0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 0 0 0 1 P1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 0 0 1 0 P1 P2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 0 0 1 1 P1 P2 P3 S4 S5 S6 S7 S8 S9 S10 S11 S12 0 1 0 0 P1 P2 P3 P4 S5 S6 S7 S8 S9 S10 S11 S12 0 1 0 1 P1 P2 P3 P4 P5 S6 S7 S8 S9 S10 S11 S12 0 1 1 0 P1 P2 P3 P4 P5 P6 S7 S8 S9 S10 S11 S12 0 1 1 1 P1 P2 P3 P4 P5 P6 P7 S8 S9 S10 S11 S12 1 0 0 0 P1 P2 P3 P4 P5 P6 P7 P8 S9 S10 S11 S12 1 0 0 1 P1 P2 P3 P4 P5 P6 P7 P8 P9 S10 S11 S12 1 0 1 0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 S11 S12 1 0 1 1 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 S12 1 1 0 0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 Note1: Sn (n=1 to 12)…Segment output port Pn (n=1 to 12)…General-purpose output port Note2: When are setting (P0, P1, P2, P3)=(1, 1, 0, 1), (1, 1, 1, 0) and (1, 1, 1, 1), the all S1/P1 to S12/P12 output pins are selected the segment output port. The table below lists the correspondence between the display data and the output pins when these pins are selected to be general-purpose output ports (general-purpose output function). Correspondence display data Output pin 1/4 duty drive Static drive S1/P1 D1 D1 S2/P2 D5 D2 S3/P3 D9 D3 S4/P4 D13 D4 S5/P5 D17 D5 S6/P6 D21 D6 S7/P7 D25 D7 S8/P8 D29 D8 S9/P9 D33 D9 S10/P10 D37 D10 S11/P11 D41 D11 S12/P12 D45 D12 For example, if the circuit is operated in 1/4 duty and the S4/P4 output pin is selected to be a general-purpose output port and is set general-purpose output function, the S4/P4 output pin will output a high (VLCD) level when the display data D13 is 1, and will output a low (VSS) level when D13 is 0. www.onsemi.com 19 LC75890W Display Data and Display Blinking Control Data and Output Pin Correspondence (1/4 Duty Drive) Output pin COM1 COM2 COM3 COM4 S1/P1 D1 D2 D3 D4 Blinking control data BD1 Output pin COM1 COM2 COM3 COM4 S19 D73 D74 D75 D76 Blinking control data BD19 S2/P2 D5 D6 D7 D8 BD2 S20 D77 D78 D79 D80 BD20 S3/P3 D9 D10 D11 D12 BD3 S21 D81 D82 D83 D84 BD21 S4/P4 D13 D14 D15 D16 BD4 S22 D85 D86 D87 D88 BD22 S5/P5 D17 D18 D19 D20 BD5 S23 D89 D90 D91 D92 BD23 S6/P6 D21 D22 D23 D24 BD6 S24 D93 D94 D95 D96 BD24 S7/P7 D25 D26 D27 D28 BD7 S25 D97 D98 D99 D100 BD25 S8/P8 D29 D30 D31 D32 BD8 S26 D101 D102 D103 D104 BD26 S9/P9 D33 D34 D35 D36 BD9 S27 D105 D106 D107 D108 BD27 S10/P10 D37 D38 D39 D40 BD10 S28 D109 D110 D111 D112 BD28 S11/P11 D41 D42 D43 D44 BD11 S29 D113 D114 D115 D116 BD29 S12/P12 D45 D46 D47 D48 BD12 S30 D117 D118 D119 D120 BD30 S13 D49 D50 D51 D52 BD13 S31 D121 D122 D123 D124 BD31 S14 D53 D54 D55 D56 BD14 S32 D125 D126 D127 D128 BD32 S15 D57 D58 D59 D60 BD15 S33 D129 D130 D131 D132 BD33 S16 D61 D62 D63 D64 BD16 S34 D133 D134 D135 D136 BD34 S17 D65 D66 D67 D68 BD17 S35 D137 D138 D139 D140 BD35 S18 D69 D70 D71 D72 BD18 S36 D141 D142 D143 D144 BD36 S37/OSCI D145 D146 D147 D148 BD37 Note: This table assumes that pins S1/P1 to S12/P12 and S37/OSCI are configured for segment output. For example, the table below lists the output states for the S21 output pin. Display data Blinking control data Output pin (S21) state D81 D82 D83 D84 BD21 0 0 0 0 0 The LCD segments corresponding to COM1, COM2, COM3, and COM4 are off. 0 0 0 1 0 The LCD segment corresponding to COM4 is on. 0 0 1 0 0 The LCD segment corresponding to COM3 is on. 0 0 1 1 0 The LCD segments corresponding to COM3 and COM4 are on. 0 1 0 0 0 The LCD segment corresponding to COM2 is on. 0 1 0 1 0 The LCD segments corresponding to COM2 and COM4 are on. 0 1 1 0 0 The LCD segments corresponding to COM2 and COM3 are on. 0 1 1 1 0 The LCD segments corresponding to COM2, COM3, and COM4 are on. 1 0 0 0 0 The LCD segment corresponding to COM1 is on. 1 0 0 1 0 The LCD segments corresponding to COM1 and COM4 are on. 1 0 1 0 0 The LCD segments corresponding to COM1 and COM3 are on. 1 0 1 1 0 The LCD segments corresponding to COM1, COM3, and COM4 are on. 1 1 0 0 0 The LCD segments corresponding to COM1 and COM2 are on. 1 1 0 1 0 The LCD segments corresponding to COM1, COM2, and COM4 are on. 1 1 1 0 0 The LCD segments corresponding to COM1, COM2, and COM3 are on. 1 1 1 1 0 The LCD segments corresponding to COM1, COM2, COM3, and COM4 are on. 0 0 0 0 1 The LCD segments corresponding to COM1, COM2, COM3, and COM4 are off. 0 1 0 1 1 The LCD segments corresponding to COM2 and COM4 are blinking. 1 0 1 0 1 The LCD segments corresponding to COM1 and COM3 are blinking. 1 1 1 1 1 The LCD segments corresponding to COM1, COM2, COM3, and COM4 are blinking. www.onsemi.com 20 LC75890W Display Data and Display Blinking Control Data and Output Pin Correspondence (Static Drive) Output pin COM1 Blinking control data Output pin COM1 Blinking control data S1/P1 D1 BD1 S19 D19 BD19 S2/P2 D2 BD2 S20 D20 BD20 S3/P3 D3 BD3 S21 D21 BD21 S4/P4 D4 BD4 S22 D22 BD22 S5/P5 D5 BD5 S23 D23 BD23 S6/P6 D6 BD6 S24 D24 BD24 S7/P7 D7 BD7 S25 D25 BD25 S8/P8 D8 BD8 S26 D26 BD26 S9/P9 D9 BD9 S27 D27 BD27 S10/P10 D10 BD10 S28 D28 BD28 S11/P11 D11 BD11 S29 D29 BD29 S12/P12 D12 BD12 S30 D30 BD30 S13 D13 BD13 S31 D31 BD31 S14 D14 BD14 S32 D32 BD32 S15 D15 BD15 S33 D33 BD33 S16 D16 BD16 S34 D34 BD34 S17 D17 BD17 S35 D35 BD35 S18 D18 BD18 S36 D36 BD36 S37/OSCI D37 BD37 Note: This table assumes that pins S1/P1 to S12/P12 and S37/OSCI are configured for segment output. For example, the table below lists the output states for the S21 output pin. Display data Blinking control data D21 BD21 0 0 Output pin (S21) state The LCD segment corresponding to COM1 is off. 1 0 The LCD segment corresponding to COM1 is on. 0 1 The LCD segment corresponding to COM1 is off. 1 1 The LCD segment corresponding to COM1 is blinking. www.onsemi.com 21 LC75890W Output waveforms (1/4-Duty 1/3-Bias Drive Scheme) fo[Hz] VLCD 2/3VLCD 1/3VLCD 0V VLCD 2/3VLCD 1/3VLCD 0V VLCD 2/3VLCD 1/3VLCD 0V VLCD 2/3VLCD 1/3VLCD 0V VLCD 2/3VLCD 1/3VLCD 0V VLCD 2/3VLCD 1/3VLCD 0V VLCD 2/3VLCD 1/3VLCD 0V VLCD 2/3VLCD 1/3VLCD 0V VLCD 2/3VLCD 1/3VLCD 0V VLCD 2/3VLCD 1/3VLCD 0V VLCD 2/3VLCD 1/3VLCD 0V VLCD 2/3VLCD 1/3VLCD 0V VLCD 2/3VLCD 1/3VLCD 0V VLCD 2/3VLCD 1/3VLCD 0V VLCD 2/3VLCD 1/3VLCD 0V COM1 COM2 COM3 COM4 LCD driver output when all LCD segments corresponding to COM1, COM2, COM3, and COM4 are off. LCD driver output when only LCD segments corresponding to COM1 are on. LCD driver output when only LCD segments corresponding to COM2 are on. LCD driver output when LCD segments corresponding to COM1 and COM2 are on. LCD driver output when only LCD segments corresponding to COM3 are on. LCD driver output when LCD segments corresponding to COM1 and COM3 are on. LCD driver output when LCD segments corresponding to COM2 and COM3 are on. LCD driver output when LCD segments corresponding to COM1, COM2, and COM3 are on. LCD driver output when only LCD segments corresponding to COM4 are on. LCD driver output when LCD segments corresponding to COM2 and COM4 are on. LCD driver output when all LCD segments corresponding to COM1, COM2, COM3, and COM4 are on. Control data Common/segment output waveform frame frequency fo[Hz] FC0 FC1 FC2 Internal oscillator operating mode (The control data OC is 0, fosc=300[kHz]typ) 0 0 0 fosc/4608 fCK1/4608 fCK2/576 0 0 1 fosc/3456 fCK1/3456 fCK2/432 0 1 0 fosc/3072 fCK1/3072 fCK2/384 0 1 1 fosc/2304 fCK1/2304 fCK2/288 1 0 0 fosc/1536 fCK1/1536 fCK2/192 1 0 1 fosc/1152 fCK1/1152 fCK2/144 1 1 0 fosc/768 fCK1/768 fCK2/96 External clock operating mode (The control data OC is 1 and EXF is 0, fCK1=300[kHz]typ) External clock operating mode (The control data OC is 1 and EXF is 1, fCK2=38[kHz]typ) Note: When is setting (FC0, FC1, FC2) = (1, 1, 1), the frame frequency is same as frame frequency at the time of the (FC0, FC1, FC2) = (0, 1, 0) setting (fosc/3072, fCK1/3072, fCK2/384). www.onsemi.com 22 LC75890W Output waveforms (Static Drive Scheme) fo[Hz] VLCD COM1 0V VLCD LCD driver output when off. 0V VLCD LCD driver output when on. 0V Control data Common/segment output waveform frame frequency fo[Hz] FC0 FC1 FC2 Internal oscillator operating mode (The control data OC is 0, fosc=300[kHz]typ) 0 0 0 fosc/4608 fCK1/4608 fCK2/576 0 0 1 fosc/3456 fCK1/3456 fCK2/432 0 1 0 fosc/3072 fCK1/3072 fCK2/384 0 1 1 fosc/2304 fCK1/2304 fCK2/288 1 0 0 fosc/1536 fCK1/1536 fCK2/192 1 0 1 fosc/1152 fCK1/1152 fCK2/144 1 1 0 fosc/768 fCK1/768 fCK2/96 External clock operating mode (The control data OC is 1 and EXF is 0, fCK1=300[kHz]typ) External clock operating mode (The control data OC is 1 and EXF is 1, fCK2=38[kHz]typ) Note: When is setting (FC0, FC1, FC2) = (1, 1, 1), the frame frequency is same as frame frequency at the time of the (FC0, FC1, FC2) = (0, 1, 0) setting (fosc/3072, fCK1/3072, fCK2/384). www.onsemi.com 23 LC75890W PWM output waveforms VLCD Pn (PWM output Ch1) (1) VSS (56/64)Tp (56/64)Tp VLCD Pn (PWM output Ch2) VSS (48/64)Tp (48/64)Tp VLCD Pn (PWM output Ch3) VSS (40/64)Tp (40/64)Tp VLCD Pn (PWM output Ch1) (8/64)Tp (2) VSS (8/64)Tp VLCD Pn (PWM output Ch2) VSS (16/64)Tp (16/64)Tp VLCD Pn (PWM output Ch3) VSS (24/64)Tp (24/64)Tp VLCD Pn (PWM output Ch1) (32/64)Tp (3) VSS (32/64)Tp VLCD Pn (PWM output Ch2) (32/64)Tp VSS (32/64)Tp VLCD Pn (PWM output Ch3) (32/64)Tp Pn (n=1 to 12) VSS (32/64)Tp Tp Tp= Tp Control data 1 fp PWM output W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 waveforms 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 0 0 1 (1) 1 1 1 0 0 0 1 1 1 1 0 0 1 1 1 0 1 0 (2) 1 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0 (3) Control data PF0 PF1 PF2 PWM output waveform frame frequency fp[Hz] PF3 Internal oscillator operating mode External clock operating mode (The control data OC is 0, (The control data OC is 1 and fosc=300[kHz] typ) EXF is 0, fCK1=300[kHz] typ) 0 0 0 0 fosc/1536 fCK1/1536 1 0 0 0 fosc/1408 fCK1/1408 0 1 0 0 fosc/1280 fCK1/1280 1 1 0 0 fosc/1152 fCK1/1152 0 0 1 0 fosc/1024 fCK1/1024 1 0 1 0 fosc/896 fCK1/896 0 1 1 0 fosc/768 fCK1/768 1 1 1 0 fosc/640 fCK1/640 0 0 0 1 fosc/512 fCK1/512 1 0 0 1 fosc/384 fCK1/384 0 1 0 1 fosc/256 fCK1/256 Note1: When is setting (PF0, PF1, PF2, PF3) = (1, 1, 0, 1) and (X, X, 1, 1), the frame frequency is same as frame frequency at the time of the (PF0, PF1, PF2, PF3) = (1, 0, 1, 0) setting (fosc/896, fCK1/896). X: don’t care www.onsemi.com 24 LC75890W Display Control and the INH Pin Since the LSI internal data (1/4 duty drive : the display data D1 to D148 and the control data, Static drive : the display data D1 to D37 and the control data) is undefined when power is first applied, applications should set the INH pin low at the same time as power is applied to turn off the display (This sets the S1/P1 to S12/P12, S13 to S36, COM4 to COM1, and S37/OSCI pins to the VSS level.) and during this period send serial data from the controller. The controller should then set the INH pin high after the data transfer has completed. This procedure prevents meaningless display at power on. (See Figure 4 and Figure 5.) Notes on the Power On/Off Sequences Applications should observe the following sequences when turning the LC75890 power on and off. (See Figures 4 and Figure 5.) • At power on : Logic block power supply (VDD) on LCD driver block power supply (VLCD) on • At power off : LCD driver block power supply (VLCD) off Logic block power supply (VDD) off However, if the logic and LCD driver block use a shared power supply, then the power supplies can be turned on and off at the same time. (1)1/4 duty drive t2 t1 t3 VDD VLCD INH VIL1 CE BD1 to BD37,BF0 to BF2, FC0 to FC2,DT,EXF,OC,SC,BU VIL1 Display data and control data transferred tc Undefined Defined Undefined W10 to W15,W20 to W25, Internal data W30 to W35,PF0 to PF3,P1A, P1B to P12A,P12B,P0 to P3 Undefined Defined Undefined Internal data (D1 to D48) Undefined Defined Undefined Undefined Defined Undefined Undefined Defined Undefined Internal data Internal data (D49 to D96) Internal data (D97 to D148) Note1 : t10 t20 t30 (t2t3) tc 10 s min [Figure 4] www.onsemi.com 25 LC75890W (2)Static drive t2 t1 t3 VDD VLCD INH VIL1 CE Internal data BD1 to BD37,BF0 to BF2, FC0 to FC2,DT,EXF,OC,SC,BU VIL1 Display data and control data transferred Undefined Defined W10 to W15,W20 to W25, Internal data W30 to W35,PF0 to PF3,P1A, P1B to P12A,P12B,P0 to P3 Undefined Defined Internal data (D1 to D37) Undefined Defined tc Undefined Undefined Undefined Note1 : t10 t20 t30 (t2t3) tc 10 s min [Figure 5] Notes on Controller Transfer of Display Data When using the LC75890 in 1/4 duty, applications transfer the display data (D1 to D148) in three operations. In either case, applications should transfer all of the display data within 30 ms to maintain the quality of displayed image. www.onsemi.com 26 LC75890W S37/OSCI Pin Peripheral Circuit (1) Internal oscillator operating mode (control data OC = 0) Connect the S37/OSCI pin to the LCD panel when the internal oscillator operating mode is selected. OSCI/S37 To LCD panel (2) External clock operating mode (control data OC = 1) When the external clock operating mode is selected, insert a current protection resistor Rg (2.2 to 22 k) between the S37/OSCI pin and external clock output pin (external oscillator). Determine the value of the resistance according to the allowable current value at the external clock output pin. Also make sure that the waveform of the external clock is not heavily distorted. In addition, the following conditions must be met : VDD VLCD. External clock output pin OSCI/S37 Rg External oscillator Note: Allowable current value at external clock output pin > VDDVLCD VLCD Rg (3) Unused pin treatment When the S37/OSCI pin is not to be used, select the internal oscillator operating mode (setting control data OC to 0) to keep the pin open. OSCI/S37 OPEN P1 to P12 pin peripheral circuit It is recommended the circuit shown below be used to adjust the brightness of the LED backlight using the PWM output P1 to P12 +5V LED P1 to P12 www.onsemi.com 27 LC75890W Sample Applications Circuit 1 1/4 Duty, 1/3 Bias Drive (P1) (P2) +3.3V VDD COM1 COM2 VSS COM3 COM4 +5V VLCD P1/S1 P2/S2 P12/S12 S13 INH From the controller CE Used for functions such as backlight control LCD panel (up to 148 segments) (P12) General-purpose output ports S35 CL S36 DI *4 OSCI/S37 *4 Connect the S37/OSCI pin to the LCD panel in the internal oscillator operating mode and insert a current protection resistor Rg(2.2 to 22 k) between the S37/OSCI pin and external clock output pin (external oscillator) in the external clock operating mode. (See “S37/OSCI Pin Peripheral Circuit”) Sample Applications Circuit 2 Static Drive (P1) (P2) (P12) +3.3V VDD COM1 VSS P1/S1 VLCD P12/S12 S13 S36 INH From the controller *4 OSCI/S37 CE COM2 CL COM3 DI COM4 Used for functions such as backlight control LCD panel (up to 37 segments) P2/S2 +5V General-purpose output ports OPEN *4 Connect the S37/OSCI pin to the LCD panel in the internal oscillator operating mode and insert a current protection resistor Rg(2.2 to 22 k) between the S37/OSCI pin and external clock output pin (external oscillator) in the external clock operating mode. (See “S37/OSCI Pin Peripheral Circuit”) www.onsemi.com 28 LC75890W ORDERING INFORMATION Device Package Shipping (Qty / Packing) LC75890W-2H SQFP80 12x12 / SQFP80 (Pb-Free / Halogen Free) 1250 / Tray JEDEC LC75890W-NH SQFP80 12x12 / SQFP80 (Pb-Free / Halogen Free) 1000 / Tape & Reel † For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://www.onsemi.com/pub_link/Collateral/BRD8011-D.PDF ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. 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