Octal Ultrasound AFE with Digital Demodulator AD9670 Data Sheet FEATURES GENERAL DESCRIPTION 8 channels of LNA, VGA, antialiasing filter, ADC, and digital demodulator/decimator Low power 150 mW per channel, time gain compensation (TGC) mode, 40 MSPS 62.5 mW per channel, continuous wave (CW) mode; <30 mW in power-down mode 10 mm × 10 mm, 144-ball CSP_BGA TGC channel, input referred noise voltage: 0.82 nV/√Hz, maximum gain Flexible power-down modes Fast recovery from low power standby mode: <2 μs Low noise preamplifier (LNA) Input noise voltage: 0.78 nV/√Hz, gain = 21.6 dB Programmable gain: 15.6 dB/17.9 dB/21.6 dB 0.1 dB input compression point: 1.00 V p-p/0.75 V p-p/ 0.45 V p-p Flexible active input impedance matching Variable gain amplifier (VGA) Attenuator range: 45 dB, linear-in-dB gain control Postamplifier gain (PGA): 21 dB/24 dB/27 dB/30 dB Antialiasing filter Programmable, second-order low-pass filter from 8 MHz to 18 MHz or 13.5 MHz to 30 MHz and high-pass filter Analog-to-digital converter (ADC) Signal-to-noise ratio (SNR): 75 dB, 14 bits up to 125 MSPS Configurable serial low voltage differential signaling (LVDS) CW mode harmonic rejection I/Q demodulator Individual programmable phase rotation Dynamic range per channel: >160 dBFS/√Hz Close in SNR: 156 dBc/√Hz, 1 kHz offset, −3 dBFS Digital demodulator/decimator I/Q demodulator with programmable oscillator FIR decimation filter The AD9670 is designed for low cost, low power, small size, and ease of use for medical ultrasound applications. It contains eight channels of a VGA with an LNA, a CW harmonic rejection I/Q demodulator with programmable phase rotation, an antialiasing filter, an ADC, and a digital demodulator and decimator for data processing and bandwidth reduction. Each channel features a maximum gain of up to 52 dB, a fully differential signal path, and an active input preamplifier termination. The channel is optimized for high dynamic performance and low power in applications where a small package size is critical. The LNA has a single-ended-to-differential gain that is selectable through the serial port interface (SPI). Assuming a 15 MHz noise bandwidth (NBW) and a 21.6 dB LNA gain, the LNA input SNR is 94 dB. In CW Doppler mode, each LNA output drives an I/Q demodulator that has independently programmable phase rotation with 16 phase settings. Power-down of individual channels is supported to increase battery life for portable applications. Standby mode allows quick power-up for power cycling. In CW Doppler operation, the VGA, antialiasing filter, and ADC are powered down. The ADC contains several features designed to maximize flexibility and minimize system cost, such as a programmable clock, data alignment, and programmable digital test pattern generation. The digital test patterns include built-in fixed patterns, built-in pseudorandom patterns, and custom user-defined test patterns entered via the SPI. APPLICATIONS Medical imaging/ultrasound Nondestructive testing (NDT) Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. 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AD9670 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 CW Doppler Operation............................................................. 33 Applications ....................................................................................... 1 Digital Demodulator/Decimator .................................................. 35 General Description ......................................................................... 1 Vector Profile .............................................................................. 35 Revision History ............................................................................... 2 RF Decimator .............................................................................. 36 Functional Block Diagram .............................................................. 3 Baseband Demodulator and Decimator.................................. 37 Specifications..................................................................................... 4 Digital Test Waveforms.............................................................. 38 AC Specifications.......................................................................... 4 Digital Block Power Saving Scheme ........................................ 38 Digital Specifications ................................................................... 7 Serial Port Interface (SPI) .............................................................. 39 Switching Specifications .............................................................. 8 Hardware Interface..................................................................... 39 Timing Diagrams.......................................................................... 9 Memory Map .................................................................................. 41 Absolute Maximum Ratings.......................................................... 11 Reading the Memory Map Table .............................................. 41 Thermal Impedance ................................................................... 11 Reserved Locations .................................................................... 41 ESD Caution ................................................................................ 11 Default Values ............................................................................. 41 Pin Configuration and Function Descriptions ........................... 12 Logic Levels ................................................................................. 41 Typical Performance Characteristics ........................................... 15 Recommended Startup Sequence ............................................ 41 TGC Mode Characteristics ....................................................... 15 Memory Map Register Descriptions ........................................ 51 CW Doppler Mode Characteristics ......................................... 19 Outline Dimensions ....................................................................... 52 Theory of Operation ...................................................................... 20 Ordering Guide .......................................................................... 52 TGC Operation ........................................................................... 20 Analog Test Signal Generation ................................................. 33 REVISION HISTORY 2/16—Revision A: Initial Version Rev. A | Page 2 of 52 Data Sheet AD9670 FUNCTIONAL BLOCK DIAGRAM AVDD1 AVDD2 LO-A TO LO-H DVDD PDWN STBY DRVDD CWQ+ CWQ– CWI+ CWI– CWD AND I/Q DEMODULATOR LOSW-A TO LOSW-H LI-A TO LI-H LNA LG-A TO LG-H VGA 14-BIT ADC AAF DEMODULATOR/ DECIMATOR SERIALIZER LVDS DOUTA+ TO DOUTH+ DOUTA– TO DOUTH– AD9670 8 CHANNELS Figure 1. Rev. A | Page 3 of 52 FCO+ FCO– DCO+ DCO– 11041-001 CLK– DATA RATE MULTIPLIER CLK+ SDIO CSB SCLK GPO0 TO GPO3 SERIAL PORT INTERFACE ADDR0 TO ADDR4 TX_TRIG+ NCO TX_TRIG– VREF RBIAS REFERENCE GAIN+ GAIN– MLO– MLO+ RESET– RESET+ LO GENERATION AD9670 Data Sheet SPECIFICATIONS AC SPECIFICATIONS AVDD1 = 1.8 V, AVDD2 = 3.0 V, DVDD = 1.4 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, full temperature range (0°C to 85°C), fIN = 5 MHz, local oscillator (LO) band mode, RS = 50 Ω, RFB = ∞ (unterminated), LNA gain = 21.6 dB, LNA bias = midhigh, PGA gain = 27 dB, analog gain control, VGAIN = (GAIN+) − (GAIN−) = 1.6 V, antialiasing filter, low-pass filter (LPF) cutoff = fSAMPLE/3 in Mode I/Mode II, antialiasing filter LPF cutoff = fSAMPLE /4.5 in Mode III/Mode IV, high-pass filter (HPF) cutoff = LPF cutoff/12.00, Mode I = fSAMPLE = 40 MSPS, Mode II = fSAMPLE = 65 MSPS, Mode III = fSAMPLE = 80 MSPS, Mode IV = 125 MSPS, radio frequency (RF) decimator bypassed, digital demodulator and baseband decimator bypassed, digital high-pass filter bypassed, low power LVDS mode, unless otherwise noted. All gain setting options are listed, which can be configured via SPI registers, and all power supply currents and power dissipations are listed for the four mode settings (Mode I, Mode II, Mode III, and Mode IV), respectively, via slashes in Table 1. Table 1. Parameter1 LNA CHARACTERISTICS Gain 0.1 dB Input Compression Point 1 dB Input Compression Point Input Common Mode (LI-x, LG-x) Output Common Mode LO-x LOSW-x Input Resistance (LI-x) Input Capacitance (LI-x) Input Noise Voltage Input Noise Current FULL CHANNEL (TGC) CHARACTERISTICS Antialiasing Filter Low-Pass Cutoff In Range Antialiasing Filter Bandwidth Tolerance Group Delay Variation Input Referred Noise Voltage Noise Figure Active Termination Matched Unterminated Correlated Noise Ratio Output Offset Test Conditions/Comments Min Typ Max Unit Single-ended input to differential output Single-ended input to single-ended output LNA gain = 15.6 dB LNA gain = 17.9 dB LNA gain = 21.6 dB LNA gain = 15.6 dB LNA gain = 17.9 dB LNA gain = 21.6 dB 15.6/17.9/21.6 9.6/11.9/15.6 1.00 0.75 0.45 1.20 0.90 0.60 2.2 dB dB V p-p V p-p V p-p V p-p V p-p V p-p V Switch off Switch on Switch off Switch on RFB = 300 Ω RFB = 1350 Ω High-Z 1.5 High-Z 1.5 50 200 6 20 Ω V Ω V Ω Ω kΩ pF 0.83 0.82 0.78 2.6 nV/√Hz nV/√Hz nV/√Hz pA/√Hz RS = 0 Ω LNA gain = 15.6 dB LNA gain = 17.9 dB LNA gain = 21.6 dB −3 dB, programmable, low band mode −3 dB, programmable, high band mode 8 13.5 f = 1 MHz to 18 MHz, VGAIN = −1.6 V to +1.6 V LNA gain = 15.6 dB LNA gain = 17.9 dB LNA gain = 21.6 dB RS = 50 Ω LNA gain = 15.6 dB, RFB = 150 Ω LNA gain = 17.9 dB, RFB = 200 Ω LNA gain = 21.6 dB, RFB = 300 Ω LNA gain = 15.6 dB LNA gain = 17.9 dB LNA gain = 21.6 dB No signal, correlated/uncorrelated −100 Rev. A | Page 4 of 52 18 30 ±10 MHz MHz % ±350 0.96 0.90 0.82 ps nV/√Hz nV/√Hz nV/√Hz 5.6 4.8 3.8 3.2 2.9 2.6 −30 dB dB dB dB dB dB dB LSB +100 Data Sheet Parameter1 Signal-to-Noise Ratio (SNR) Close In SNR Second Harmonic Third Harmonic Two-Tone Intermodulation Distortion (IMD3) Channel-to-Channel Crosstalk GAIN ACCURACY Gain Law Conformance Error Linear Gain Error Channel-to-Channel Matching PGA Gain GAIN CONTROL INTERFACE Control Range Control Common Mode Input Impedance Gain Range Scale Factor Response Time CW DOPPLER MODE LO Frequency Phase Resolution Output DC Bias (Single-Ended) Output AC Current Range Transconductance (Differential) Input Referred Noise Voltage Noise Figure Dynamic Range Close In SNR AD9670 Test Conditions/Comments fIN = 5 MHz at −12 dBFS, VGAIN = −1.6 V fIN = 5 MHz at −1 dBFS fIN = 3.5 MHz at −1 dBFS, VGAIN = 0 V, 1 kHz offset fIN = 5 MHz at −12 dBFS, VGAIN = −1.6 V fIN = 5 MHz at −1 dBFS, VGAIN = 1.6 V fIN = 5 MHz at −12 dBFS, VGAIN = −1.6 V fIN = 5 MHz at −1 dBFS, VGAIN = 1.6 V fRF1 = 5.015 MHz, fRF2 = 5.020 MHz, ARF1 = −1 dBFS, ARF2 = −21 dBFS, VGAIN = 1.6 V, IMD3 relative to ARF2 fIN1 = 5.0 MHz at −1 dBFS Overrange condition2 TA = 25°C −1.6 < VGAIN < −1.28 V −1.28 V < VGAIN ≤ +1.28 V 1.28 V < VGAIN < 1.6 V VGAIN = 0 V, normalized for ideal antialiasing filter loss −1.28 V < VGAIN < +1.28 V, 1 σ Min Differential GAIN+, GAIN− GAIN+, GAIN− −1.6 0.7 Rev. A | Page 5 of 52 Max −60 −55 +1.3 −0.5 −1.3 +1.3 0.1 21/24/27/30 0.8 10 45 14 3.5 750 1 45 22.5 AVDD2/2 ±2.2 Unit dBFS dBFS dBc/√Hz dBc dBc dBc dBc dBc dB dB 0.4 −1.3 Analog Digital step size Analog 45 dB change fLO = fMLO/M Per channel, 4LO3 mode Per channel, 8LO mode, 16LO mode CWI+, CWI−, CWQ+, and CWQ− Per CWI+, CWI−, CWQ+, and CWQ−, each channel enabled (2 fLO and baseband signal) Demodulated IOUT/VIN, per CWI+, CWI−, CWQ+, and CWQ− LNA gain = 15.6 dB LNA gain = 17.9 dB LNA gain = 21.6 dB RS = 0 Ω, RFB = ∞ LNA gain = 15.6 dB LNA gain = 17.9 dB LNA gain = 21.6 dB RS = 50 Ω, RFB = ∞ LNA gain = 15.6 dB LNA gain = 17.9 dB LNA gain = 21.6 dB RS = 0 Ω, RFB = ∞ LNA gain = 15.6 dB LNA gain = 17.9 dB LNA gain = 21.6 dB −3 dBFS input, fRF = 2.5 MHz, fLO = 40 MHz, 1 kHz offset, 16LO mode, 1 channel enabled −3 dBFS input, fRF = 2.5 MHz, fLO = 40 MHz, 1 kHz offset, 16LO mode, 8 channels enabled Typ 69 59 −130 −70 −62 −61 −55 −54 dB dB dB dB dB dB +1.6 0.9 V V MΩ dB dB/V dB ns 10 MHz Degrees Degrees V mA ±2.5 3.3 4.3 6.6 mA/V mA/V mA/V 1.6 1.3 1.0 nV/√Hz nV/√Hz nV/√Hz 5.7 4.5 3.4 dB dB dB 164 162 160 156 dBFS/√Hz dBFS/√Hz dBFS/√Hz dBc/√Hz 161 dBc/√Hz AD9670 Parameter1 Two-Tone Intermodulation Distortion (IMD3) LO Harmonic Rejection Quadrature Phase Error I/Q Amplitude Imbalance Channel-to-Channel Matching POWER SUPPLY, MODE I/MODE II/ MODE III/MODE IV AVDD1 AVDD2 DVDD DRVDD IAVDD1 IAVDD2 IDVDD IDRVDD Total Power Dissipation (Including Output Drivers) Power-Down Dissipation Standby Power Dissipation ADC RESOLUTION ADC REFERENCE Output Voltage Error Load Regulation at 1.0 mA Input Resistance Data Sheet Test Conditions/Comments fRF1 = 5.015 MHz, fRF2 = 5.020 MHz, fLO = 80 MHz, ARF1 = −1 dBFS, ARF2 = −21 dBFS, IMD3 relative to ARF2 16LO, 8LO, and 4LO modes I to Q, all phases, 1 σ I to Q, all phases, 1 σ Phase I to I, Q to Q, 1 σ Amplitude I to I, Q to Q, 1 σ Demodulator/decimator enabled Demodulator/decimator disabled TGC mode, LO band mode CW Doppler mode TGC mode, no signal, low band mode TGC mode, no signal, high band mode CW Doppler mode, 8 channels enabled RF decimator enabled in Mode III and Mode IV; demodulator/decimator enabled all modes ANSI-644 mode Low power (IEEE 1596.3 similar) mode, 1 channel per lane mode TGC mode, no signal, RF decimator enabled in Mode III and Mode IV, demodulator/decimator disabled TGC mode, no signal, RF decimator enabled in Mode III and Mode IV, demodulator/decimator enabled CW Doppler mode, 8 channels enabled Min Typ −58 Max Unit dB −20 dBc Degrees dB Degrees dB 1.9 3.6 1.9 1.9 1.9 V V V V V mA 0.15 0.015 0.5 0.25 1.7 2.85 1.3 1.3 1.7 1.8 3.0 1.4 1.8 1.8 148/187/ 223/291 4 230 239 140 156/247/ 166/255 133/184/ 141/146 119/170/ 127/169 1200/1400/ 1380/1630 1400/1695/ 1570/1900 500 mA mA mA mA mA mA mA 1345/1555/ 1535/2100 1560/1880/ 1740/2100 30 630 14 VREF = 1 V VREF = 1 V ±50 2 7.5 1 mW mW mW mW mW Bits mV mV kΩ For a complete set of definitions and information about how these tests were completed, see the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation. The overrange condition is specified as 6 dB more than the full-scale input range. 3 The internal LO frequency, fLO, is generated from the supplied multiplier local oscillator frequency, fMLO, by dividing it up by a configurable divider value (M) that can be 4, 8, or 16; the MLO signal is named 4LO, 8LO, or 16LO, accordingly. 2 Rev. A | Page 6 of 52 Data Sheet AD9670 DIGITAL SPECIFICATIONS AVDD1 = 1.8 V, AVDD2 = 3.0 V, DVDD = 1.4 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, full temperature range (0°C to 85°C), unless otherwise noted. Table 2. Parameter1 INPUTS CLK+, CLK−, TX_TRIG+, TX_TRIG− Logic Compliance Differential Input Voltage42 Input Voltage Range Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance MLO+, MLO−, RESET+, RESET− Logic Compliance Differential Input Voltage2 Input Voltage Range Input Common-Mode Voltage Input Resistance (Single-Ended) Input Capacitance LOGIC INPUTS PDWN, STBY, SCLK, SDIO, ADDRx Logic 1 Voltage Logic 0 Voltage Input Resistance3 Input Capacitance3 CSB Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC OUTPUTS SDIO4 Logic 1 Voltage (IOH = 800 μA) Logic 0 Voltage (IOL = 50 μA) GPO0/GPO1/GPO2/GPO3 Logic 0 Voltage (IOL = 50 μA) DIGITAL OUTPUTS (DOUTx+, DOUTx−) ANSI-644 Logic Compliance Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding (Default) Low Power, Reduced Signal Option Logic Compliance Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding (Default) Temperature Min Typ Max Unit 3.6 AVDD1 + 0.2 V p-p V V kΩ pF 2 × AVDD2 AVDD2 + 0.2 +0.3 V p-p V V kΩ pF DRVDD + 0.3 0.3 V V kΩ pF DRVDD + 0.3 0.3 V V kΩ pF CMOS/LVDS/LVPECL 0.2 GND − 0.2 0.9 15 4 25°C 25°C LVDS/LVPECL 0.250 GND − 0.2 −0.3 25°C 25°C AVDD2/2 20 1.5 1.2 25°C 25°C 30 (26 for SDIO) 2 (5 for SDIO) 1.2 25°C 25°C 26 2 1.79 0.05 V V 0.05 V 454 1.375 mV V 250 1.30 mV V LVDS 247 1.125 Offset binary LVDS 150 1.10 Offset binary 1 For a complete set of definitions and information about how these tests were completed, see the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation. 2 Specified for LVDS and LVPECL only. 3 The typical input resistance and input capacitance values deviate for SDIO; these deviations are noted in the Typ column. 4 Specified for 13 SDIO pins sharing the same connection. Rev. A | Page 7 of 52 AD9670 Data Sheet SWITCHING SPECIFICATIONS AVDD1 = 1.8 V, AVDD2 = 3.0 V, DVDD = 1.4 V, DRVDD = 1.8 V, full temperature range (0°C to 85°C), RF decimator bypassed, digital demodulator and baseband decimator bypassed, unless otherwise noted. Table 3. Parameter1 CLOCK2 Clock Rate 40 MSPS (Mode I) 65 MSPS (Mode II) 80 MSPS (Mode III)3 125 MSPS (Mode IV)4 Clock Pulse Width High (tEH) Clock Pulse Width Low (tEL) OUTPUT PARAMETERS2, 5 Propagation Delay (tPD) Rise Time (tR) (20% to 80%) Fall Time (tF) (20% to 80%) DCO Period (tDCO)6 FCO Propagation Delay (tFCO) DCO Propagation Delay (tCPD)7 DCO to Data Delay (tDATA)7 DCO to FCO Delay (tFRAME)7 Data-to-Data Skew (tDATA-MAX − tDATA-MIN) TX_TRIG to CLK Setup Time (tSETUP) TX_TRIG to CLK Hold Time (tHOLD) Wake-Up Time Standby Power-Down ADC Pipeline Latency APERTURE Aperture Uncertainty (Jitter) LO GENERATION MLO8 Frequency 4LO Mode 8LO Mode 16LO Mode RESET9 to MLO Setup Time (tSETUP) RESET to MLO Hold Time (tHOLD) Temperature Min Full Full Full Full Full Full 20.5 20.5 20.5 20.5 Full Full Full Full Full Full Full Full Full 25°C 25°C 10.8 − 1.5 × tDCO Typ Max Unit 40 65 80 125 MHz MHz MHz MHz ns ns 10.8 + 1.5 × tDCO ns ps ps ns ns ns ps ps ps ns ns 3.75 3.75 10.8 − 1.5 × tDCO (tSAMPLE/28) − 300 (tSAMPLE/28) − 300 10.8 300 300 tSAMPLE/7 10.8 tFCO + (tSAMPLE/28) (tSAMPLE/28) (tSAMPLE/28) ±225 10.8 + 1.5 × tDCO (tSAMPLE/28) + 300 (tSAMPLE/28) + 300 ±400 1 1 25°C 25°C Full 2 375 16 μs μs Clock cycles 25°C <1 ps rms Full Full Full Full Full 4 8 16 1 1 1 40 80 160 tMLO10/2 tMLO10/2 MHz MHz MHz ns ns For a complete set of definitions and information about how these tests were completed, see the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation. 2 The clock can be adjusted via the SPI. 3 Mode III must have the RF decimator enabled because the maximum data rate of the baseband demodulator and decimator is 65 MSPS. 4 Mode IV must have the RF decimator enabled because the maximum data rate of the baseband demodulator and decimator is 65 MSPS. 5 Measurements were taken using a device soldered to FR-4 material. 6 In the typical value, tSAMPLE/7, 7 is based on the number of bits (14) divided by 2 because the interface uses double data rate (DDR) sampling. 7 tSAMPLE/28 is based on the number of bits divided by 2 because the delays are based on half duty cycles. 8 MLO refers to the differential signal created via the MLO− pin and the MLO+ pin. This notation is used throughout the data sheet. 9 RESET refers to the differential signal created via the RESET− pin and the RESET+ pin. This notation is used throughout the data sheet. 10 The period of the MLO clock signal is represented by tMLO. Rev. A | Page 8 of 52 Data Sheet AD9670 TIMING DIAGRAMS ADC Timing Diagram N–1 AIN tA N tSETUP tHOLD TX_TRIG+ TX_TRIG– tEH CLK– tEL CLK+ tCPD DCO– DCO+ tFRAME tFCO FCO– FCO+ tPD MSB D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB D12 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 DOUTx+ Figure 2. 14-Bit Data Serial Stream (Default, RF Decimator Bypassed, Demodulator Bypassed, Baseband Decimator Bypassed), 1 Channel/Lane Mode, FCO Mode = Word CW Timing Diagrams tMLO MLO– MLO+ tHOLD 11041-003 RESET– tSETUP RESET+ Figure 3. CW Doppler Mode Input MLO±, Continuous Synchronous RESET± Timing, Sampled on the Falling MLO± Edge, 4LO Mode Rev. A | Page 9 of 52 11041-002 tDATA DOUTx– AD9670 Data Sheet tMLO MLO– MLO+ tSETUP tHOLD 11041-004 RESET– RESET+ Figure 4. CW Doppler Mode Input MLO±, Continuous Synchronous RESET± Timing, Sampled on the Falling MLO± Edge, 8LO Mode tMLO MLO– MLO+ 11041-105 RESET– tHOLD tSETUP RESET+ Figure 5. CW Doppler Mode Input MLO±, Pulse Synchronous RESET± Timing, 4LO/8LO/16LO Mode tMLO MLO– MLO+ tSETUP 11041-106 RESET– tHOLD RESET+ Figure 6. CW Doppler Mode Input MLO±, Pulse Asynchronous RESET± Timing, 4LO/8LO/16LO Mode Rev. A | Page 10 of 52 Data Sheet AD9670 ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE Table 4. Parameter AVDD1 to GND AVDD2 to GND DVDD to GND DRVDD to GND GND to GND AVDD2 to AVDD1 AVDD1 to DRVDD AVDD2 to DRVDD Digital Outputs (DOUTx+, DOUTx−, DCO+, DCO−, FCO+, FCO−) to GND LI-x, LG-x, LO-x, LOSW-x, CWI−, CWI+, CWQ−, CWQ+, GAIN+, GAIN−, RESET+, RESET−, MLO+, MLO−, GPO0, GPO1, GPO2, GPO3 to GND CLK+, CLK−, TX_TRIG+, TX_TRIG−, VREF to GND SDIO, PDWN, STBY, SCLK, CSB, ADDRx Operating Temperature Range (Ambient) Storage Temperature Range (Ambient) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Rating −0.3 V to +2.0 V −0.3 V to +3.9 V −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +0.3 V −2.0 V to +3.9 V −2.0 V to +2.0 V −2.0 V to +3.9 V −0.3 V to DRVDD + 0.3 V −0.3 V to AVDD2 + 0.3 V −0.3 V to AVDD1 + 0.3 V −0.3 V to DRVDD + 0.3 V 0°C to 85°C −65°C to +150°C 150°C 300°C Table 5. Thermal Impedance Symbol θJA ΨJB ΨJT 1 Description Junction-to-ambient thermal resistance, 0.0 m/sec air flow per JEDEC JESD51-2 (still air) Junction-to-board thermal characterization parameter, 0 m/sec air flow per JEDEC JESD51-8 (still air) Junction-to-top-of-package characterization parameter, 0 m/sec air flow per JEDEC JESD51-2 (still air) Value1 22.0 Unit °C/W 9.2 °C/W 0.12 °C/W Thermal impedance results are from simulations. The printed circuit board (PCB) is JEDEC multilayer. The thermal performance for actual applications requires careful inspection of the conditions in the application to determine if they are similar to those assumed in these calculations. ESD CAUTION Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. A | Page 11 of 52 AD9670 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 A LI-E LI-F LI-G LI-H VREF RBIAS GAIN+ GAIN– LI-A LI-B LI-C LI-D B LG-E LG-F LG-G LG-H GND GND CLNA GND LG-A LG-B LG-C LG-D C LO-E LO-F LO-G LO-H GND GND GND GND LO-A LO-B LO-C LO-D GND GND GND GND LOSW-A LOSW-B LOSW-C LOSW-D E GND AVDD2 AVDD2 AVDD2 GND GND GND GND AVDD2 AVDD2 AVDD2 GND F AVDD1 GND AVDD1 GND AVDD1 GND GND AVDD1 GND AVDD1 GND AVDD1 G GND AVDD1 GND DVDD GND GND GND GND AVDD1 GND DVDD GND H CLK– TX_TRIG– GND GND GND GND ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 CSB J CLK+ TX_TRIG+ CWQ+ GND CWI+ AVDD2 MLO+ RESET– GPO3 GPO1 PDWN SDIO K GND GND CWQ– GND CWI– AVDD2 MLO– RESET+ GPO2 GPO0 STBY SCLK DCO+ FCO+ DOUTD+ DOUTC+ DOUTB+ DOUTA+ DRVDD DCO– FCO– DOUTD– DOUTC– DOUTB– DOUTA– M DRVDD DOUTH+ DOUTG+ DOUTF+ DOUTE+ GND DOUTH– DOUTG– DOUTF– DOUTE– Figure 7. Pin Configuration 1 2 4 3 6 5 7 10 8 9 12 11 A B C D E F G H J K L M TOP VIEW (Not to Scale) Figure 8. CSP_BGA Pin Location Rev. A | Page 12 of 52 11041-006 L GND 11041-005 D LOSW-E LOSW-F LOSW-G LOSW-H Data Sheet AD9670 Table 6. Pin Function Descriptions Pin No. B5, B6, B8, C5 to C8, D5 to D8, E1, E5 to E8, E12, F2, F4, F6, F7, F9, F11, G1, G3, G5 to G8, G10, G12, H3 to H6, J4, K1, K2, K4, M1, M12 F1, F3, F5, F8, F10, F12, G2, G9, G4, G11 E2 to E4, E9 to E11, J6, K6 B7 L1, L12 C1 D1 A1 B1 C2 D2 A2 B2 C3 D3 A3 B3 C4 D4 A4 B4 H1 J1 H2 J2 H11 H10 H9 H8 H7 M2 L2 M3 L3 M4 L4 M5 L5 M6 L6 M7 L7 M8 L8 M9 L9 M10 L10 Mnemonic GND Description Ground. Tie these pins to a quiet analog ground. AVDD1 DVDD AVDD2 CLNA DRVDD LO-E LOSW-E LI-E LG-E LO-F LOSW-F LI-F LG-F LO-G LOSW-G LI-G LG-G LO-H LOSW-H LI-H LG-H CLK− CLK+ TX_TRIG− TX_TRIG+ ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 DOUTH− DOUTH+ DOUTG− DOUTG+ DOUTF− DOUTF+ DOUTE− DOUTE+ DCO− DCO+ FCO− FCO+ DOUTD− DOUTD+ DOUTC− DOUTC+ DOUTB− DOUTB+ 1.8 V Analog Supply. 1.4 V/1.8 V Digital Supply. 3.0 V Analog Supply. LNA External Capacitor. 1.8 V Digital Output Driver Supply. LNA Analog Inverted Output for Channel E. LNA Analog Switched Output for Channel E. LNA Analog Input for Channel E. LNA Ground for Channel E. LNA Analog Inverted Output for Channel F. LNA Analog Switched Output for Channel F. LNA Analog Input for Channel F. LNA Ground for Channel F. LNA Analog Inverted Output for Channel G. LNA Analog Switched Output for Channel G. LNA Analog Input for Channel G. LNA Ground for Channel G. LNA Analog Inverted Output for Channel H. LNA Analog Switched Output for Channel H. LNA Analog Input for Channel H. LNA Ground for Channel H. Clock Input Complement. Clock Input True. Transmit Trigger Complement. Transmit Trigger True. Chip Address Bit 0. Chip Address Bit 1. Chip Address Bit 2. Chip Address Bit 3. Chip Address Bit 4. ADC H Digital Output Complement. ADC H Digital Output True. ADC G Digital Output Complement. ADC G Digital Output True. ADC F Digital Output Complement. ADC F Digital Output True. ADC E Digital Output Complement. ADC E Digital Output True. Digital Clock Output Complement. Digital Clock Output True. Frame Clock Digital Output Complement. Frame Clock Digital Output True. ADC D Digital Output Complement. ADC D Digital Output True. ADC C Digital Output Complement. ADC C Digital Output True. ADC B Digital Output Complement. ADC B Digital Output True. Rev. A | Page 13 of 52 AD9670 Pin No. M11 L11 K11 J11 K12 J12 H12 B9 A9 D9 C9 B10 A10 D10 C10 B11 A11 D11 C11 B12 A12 D12 C12 K10 J10 K9 J9 J8 K8 K7 J7 A8 A7 A6 A5 K5 J5 K3 J3 Data Sheet Mnemonic DOUTA− DOUTA+ STBY PDWN SCLK SDIO CSB LG-A LI-A LOSW-A LO-A LG-B LI-B LOSW-B LO-B LG-C LI-C LOSW-C LO-C LG-D LI-D LOSW-D LO-D GPO0 GPO1 GPO2 GPO3 RESET− RESET+ MLO− MLO+ GAIN− GAIN+ RBIAS VREF CWI− CWI+ CWQ− CWQ+ Description ADC A Digital Output Complement. ADC A Digital Output True. Standby Power-Down. Full Power-Down. Serial Clock. Serial Data Input/Output. Chip Select Bar. LNA Ground for Channel A. LNA Analog Input for Channel A. LNA Analog Switched Output for Channel A. LNA Analog Inverted Output for Channel A. LNA Ground for Channel B. LNA Analog Input for Channel B. LNA Analog Switched Output for Channel B. LNA Analog Inverted Output for Channel B. LNA Ground for Channel C. LNA Analog Input for Channel C. LNA Analog Switched Output for Channel C. LNA Analog Inverted Output for Channel C. LNA Ground for Channel D. LNA Analog Input for Channel D. LNA Analog Switched Output for Channel D. LNA Analog Inverted Output for Channel D. General-Purpose Open Drain Output 0. General-Purpose Open Drain Output 1. General-Purpose Open Drain Output 2. General-Purpose Open Drain Output 3. Synchronizing Input for LO Divide by M Counter Complement. Synchronizing Input for LO Divide by M Counter True. CW Doppler Multiplier Local Oscillator (MLO) Input Complement. CW Doppler MLO Input True. Gain Control Voltage Input Complement. Gain Control Voltage Input True. External Resistor to Set the Internal ADC Core Bias Current. Voltage Reference Input/Output. CW Doppler I Output Complement. CW Doppler I Output True. CW Doppler Q Output Complement. CW Doppler Q Output True. Rev. A | Page 14 of 52 Data Sheet AD9670 TYPICAL PERFORMANCE CHARACTERISTICS TGC MODE CHARACTERISTICS Mode I = fSAMPLE = 40 MSPS, fIN = 5 MHz, LO band mode, RS = 50 Ω, RFB = ∞ (unterminated), LNA gain = 21.6 dB, LNA bias = midhigh, PGA gain = 27 dB, VGAIN = (GAIN+) − (GAIN−) = 1.6 V, antialiasing filter LPF cutoff = fSAMPLE /3, HPF cutoff = LPF cutoff/12.00 (default), RF decimator bypassed, digital demodulator and baseband decimator bypassed, unless otherwise noted. 2.0 25 PERCENTAGE OF UNITS (%) 1.5 GAIN ERROR (dB) 1.0 0°C 0.5 0 25°C –0.5 85°C –1.0 20 15 10 5 –1.5 –0.4 0 0.4 0.8 1.2 1.6 VGAIN (V) 0 GAIN ERROR (dB) Figure 9. Gain Error vs. VGAIN Figure 12. Gain Error Histogram, VGAIN = 1.28 V 25 20 20 PERCENTAGE OF UNITS (%) 15 10 5 0 15 10 5 GAIN ERROR (dB) –1.0 –0.9 –0.8 –0.7 –0.6 –0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 11041-108 –1.0 –0.9 –0.8 –0.7 –0.6 –0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 CHANNEL-TO-CHANNEL GAIN MATCHING (dB) Figure 10. Gain Error Histogram, VGAIN = −1.28 V 11041-111 PERCENTAGE OF UNITS (%) 11041-110 –0.8 –1.0 –0.9 –0.8 –0.7 –0.6 –0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 –1.2 11041-107 –2.0 –1.6 Figure 13. Gain Matching Histogram, VGAIN = −1.2 V 35 20 PERCENTAGE OF UNITS (%) 25 20 15 10 15 10 5 5 0 Figure 11. Gain Error Histogram, VGAIN = 0 V –1.0 –0.9 –0.8 –0.7 –0.6 –0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 CHANNEL-TO-CHANNEL GAIN MATCHING (dB) Figure 14. Gain Matching Histogram, VGAIN = 1.2 V Rev. A | Page 15 of 52 11041-112 GAIN ERROR (dB) 11041-109 0 –1.0 –0.9 –0.8 –0.7 –0.6 –0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 PERCENTAGE OF UNITS (%) 30 AD9670 Data Sheet 1.4 70 LNA GAIN = 17.9dB 66 64 1.0 SNR (dBFS) INPUT REFERRED NOISE (nV/√Hz) 68 1.2 0.8 LNA GAIN = 15.6dB 62 60 LNA GAIN = 21.3dB 58 56 54 0.6 52 2 3 4 5 6 7 8 9 10 FREQUENCY (MHz) 11041-008 1 50 10 25 30 35 40 45 50 55 Figure 18. SNR vs. Channel Gain and LNA Gain, AOUT = −1.0 dBFS 74 PGA GAIN = 21dB PGA GAIN = 21dB 72 –134 70 –136 PGA GAIN = 24dB 68 SNR (dBFS) OUTPUT REFERRED NOISE (dBc/√Hz) 20 CHANNEL GAIN (dB) Figure 15. Short-Circuit, Input Referred Noise vs. Frequency –132 15 11041-011 PGA GAIN = 27dB 0.4 –138 –140 66 64 PGA GAIN = 27dB 62 60 –142 PGA GAIN = 30dB 58 –144 56 5 10 15 20 25 30 35 40 45 CHANNEL GAIN (dB) 54 –5 11041-009 0 10 15 20 25 0 PGA GAIN = 21dB 68 66 40 45 50 55 –2 AMPLITUDE (dBFS) 64 62 PGA GAIN = 27dB 58 PGA GAIN = 30dB 56 35 SPEED MODE = I (40MSPS) LO BAND MODE –1 PGA GAIN = 24dB 60 30 Figure 19. SNR vs. Channel Gain and PGA Gain, AIN = −45 dBm 70 54 –3 –4 –5 –6 –7 –8 52 15 20 25 30 35 40 45 50 55 CHANNEL GAIN (dB) Figure 17. SNR vs. Channel Gain and PGA Gain, AOUT = −1.0 dBFS –10 0 5 10 15 INPUT FREQUENCY (MHz) Figure 20. Antialiasing Filter Pass-Band Response, LPF Cutoff = 1/3 × fSAMPLE, HPF = 1/12 × LPF Cutoff Rev. A | Page 16 of 52 20 11041-013 –9 LNA GAIN = 21.3dB 11041-010 SNR (dBFS) 5 CHANNEL GAIN (dB) Figure 16. Short-Circuit, Output Referred Noise vs. Channel Gain, PGA Gain = 21 dB, VGAIN = 1.6 V 50 10 0 11041-117 LNA GAIN = 21.3dB –146 –5 –20 –30 –40 THIRD ORDER, MIN VGAIN –50 THIRD ORDER, MAX VGAIN –60 –70 SECOND ORDER, MIN VGAIN –80 –90 –100 SECOND ORDER, MAX VGAIN 2 3 4 5 6 7 8 9 10 11 INPUT FREQUENCY (MHz) 11041-014 PGA GAIN = 24dB –10 –20 –30 –40 –50 –60 LNA GAIN = 17.9dB –70 LNA GAIN = 21.6dB –80 LNA GAIN = 15.6dB –90 –100 10 15 20 25 30 35 40 45 50 CHANNEL GAIN (dB) –50 VGAIN = –1.2V –60 VGAIN = 0V –70 –80 –90 VGAIN = +1.6V –100 –110 –120 –40 –35 –30 –25 –20 –15 –10 0 –5 0 –10 –20 –30 –40 VGAIN = –1.2V –50 –60 VGAIN = 0V –70 –80 –90 VGAIN = +1.6V –100 –110 –120 –40 –35 –30 –25 –20 –15 –10 –5 0 ADC OUTPUT LEVEL (dBFS) Figure 25. Third-Order Harmonic Distortion vs. ADC Output Level (AOUT) –100 PGA GAIN = 24dB –10 –110 PHASE NOISE (dBc/√Hz) –20 –30 –40 LNA GAIN = 17.9dB –50 LNA GAIN = 21.6dB –60 LNA GAIN = 15.6dB –70 –80 –120 –130 –140 –150 –90 –100 10 15 20 25 30 35 40 45 CHANNEL GAIN (dB) 11041-016 THIRD-ORDER HARMONIC DISTORTION (dBFS) Figure 22. Second-Order Harmonic Distortion vs. Channel Gain, AOUT = −1.0 dBFS 0 –40 Figure 24. Second-Order Harmonic Distortion vs. ADC Output Level (AOUT) THIRD-ORDER HARMONIC DISTORTION (dBFS) 0 –30 ADC OUTPUT LEVEL (dBFS) 11041-015 SECOND-ORDER HARMONIC DISTORTION (dBFS) Figure 21. Second-Order and Third-Order Harmonic Distortion vs. Input Frequency, AOUT = −1.0 dBFS –20 –160 100 1k 10k OFFSET FREQUENCY FROM CARRIER (Hz) Figure 26. TGC Path Phase Noise, LNA Gain = 21.6 dB, PGA Gain = 27 dB, VGAIN = 0 V Figure 23. Third-Order Harmonic Distortion vs. Channel Gain, AOUT = −1.0 dBFS Rev. A | Page 17 of 52 100k 11041-017 HARMONIC DISTORTION (dBFS) –10 0 –10 11041-122 LNA GAIN = 21.6dB PGA GAIN = 27dB MIN VGAIN, AOUT = –12.0dBFS MAX VGAIN, AOUT = –1.0dBFS 11041-123 0 AD9670 SECOND-ORDER HARMONIC DISTORTION (dBFS) Data Sheet Data Sheet 0 8 7 6 5 4 3 2 1 0 100k –10 –20 1M 10M FREQUENCY (Hz) IMD3 (dBFS) –40 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 100k 100M –50 –60 –80 –90 –100 –20 10M FREQUENCY (Hz) 100M –120 –40 –35 –30 –25 –20 –15 –10 –5 0 AMPLITUDE LEVEL (dBFS) Figure 29. IMD3 vs. ADC Output Amplitude Level 7 fIN1 = 2.3MHz fIN2 = 2.31MHz ARF1 LEVEL = –1dBFS ARF2 LEVEL = –21dBFS RS = 50Ω 6 NOISE FIGURE (dB) –40 –50 –60 –70 RIN = 300Ω, 1000Ω –80 5 4 3 2 –90 RIN = 50Ω 20 25 30 35 40 CHANNEL GAIN (dB) 45 50 11041-019 –100 15 VGAIN = 0V 11041-127 1M –30 IMD3 (dBFS) VGAIN = +1.6V –110 Figure 28. IMD3 vs. Channel Gain 1 0 2 4 6 8 10 12 14 16 18 20 FREQUENCY (MHz) Figure 30. Noise Figure vs. Frequency, RS = RIN = 100 Ω, LNA Gain = 17.9 dB, PGA Gain = 30 dB, VGAIN = 1.6 V Rev. A | Page 18 of 52 11041-020 0 VGAIN = –1.2V –70 Figure 27. LNA Input Impedance Magnitude and Phase, Unterminated –10 fIN1 = 5.0MHZ fIN2 = 5.01MHZ ARF1 LEVEL = –1dBFS ARF2 LEVEL = –21dBFS –30 11041-018 PHASE (Degrees) MAGNITUDE (kΩ) AD9670 Data Sheet AD9670 CW DOPPLER MODE CHARACTERISTICS fIN = 5 MHz, fLO = 20 MHz, 4LO mode, RS = 50 Ω, LNA gain = 21.6 dB, LNA bias = mid-high, all CW channels enabled, phase rotation = 0°. 10 165 9 160 155 SNR (dBc/√Hz) 7 6 5 4 3 2 145 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 BASEBAND FREQUENCY (Hz) Figure 31. Noise Figure vs. Baseband Frequency 130 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 BASEBAND FREQUENCY (Hz) Figure 32. SNR vs. Baseband Frequency, −3 dBFS LNA Input Rev. A | Page 19 of 52 11041-022 135 1 0 150 140 11041-021 NOISE FIGURE (dB) 8 AD9670 Data Sheet THEORY OF OPERATION MLO– MLO+ RESET+ RESET– LO-x RFB2 LOSW-x S CWQ+ CWQ– LI-x LG-x CSH ATTENUATOR –45dB TO 0dB LNA 15.6dB, 17.9dB, 21.6dB CLG TRANSDUCER CWI+ CWI– gm GAIN INTERPOLATOR GAIN+ POST AMP FILTER PIPELINE ADC 21dB, 24dB, 27dB, 30dB DEMOD/ DEC SERIAL LVDS DOUTx+ DOUTx– NCO GAIN– TX_TRIG+ TX_TRIG– 11041-023 T/R SWITCH C RFB1 LO GENERATION Figure 33. Simplified Block Diagram of a Single Channel Each channel in the AD9670 contains both a TGC signal path and a CW Doppler signal path. Common to both signal paths, the LNA provides four user adjustable input impedance termination options for matching different probe impedances. The CW Doppler path includes an I/Q demodulator with programmable phase rotation needed for analog beamforming. The TGC path includes a differential X-AMP® VGA, an antialiasing filter, an ADC, and a digital demodulator and decimator. Figure 33 shows a simplified block diagram with external components. TGC OPERATION The system gain for TGC operation is distributed as shown in Table 7. Channel Gain (dB) = LNAGAIN + VGAATT + PGAGAIN (3 ) In its default condition, the LNA has a gain of 21.6 dB (12×), and the VGA postamplifier gain is 24 dB. If the voltage on the GAIN+ pin is 0 V and the voltage on the GAIN− pin is 1.6 V (45.1 dB attenuation), the total gain of the channel is 0.5 dB if the LNA input is unmatched. The channel gain is −5.5 dB if the LNA is matched to 50 Ω (RFB = 300 Ω). However, if the voltage on the GAIN+ pin is 1.6 V and the voltage on the GAIN− pin is 0 V (0 dB attenuation), VGAATT = 0 dB. This results in a total gain of 45.3 dB through the TGC path if the LNA input is unmatched or a total gain of 39.3 dB if the LNA input is matched. In addition to the analog VGA attenuation described in Equation 2, the attenuation level can be digitally controlled in 3.5 dB increments. In this case, Equation 3 is still valid and the value of VGAATT is equal to the attenuation level set in SPI Register 0x011, Bits [7:4]. Table 7. Channel Analog Gain Distribution Section LNA Attenuator VGA Filter ADC Then, calculate the total channel gain using Equation 3. Nominal Gain (dB) 15.6/17.9/21.6 (LNAGAIN) −45 to 0 (VGAATT) 21/24/27/30 (PGAGAIN) 0 0 Low Noise Amplifier (LNA) Each LNA output is dc-coupled to a VGA input. The VGA consists of an attenuator with a range of −45 dB to 0 dB, followed by an amplifier with 21 dB/24 dB/27 dB/30 dB of gain. The X-AMP gain interpolation technique results in low gain error and uniform bandwidth, and differential signal paths minimize distortion. The linear in dB gain (law conformance) range of the TGC path is 45 dB. The slope of the gain control interface is 14 dB/V, and the gain control range is −1.6 V to +1.6 V. Equation 1 is the expression for the differential voltage, VGAIN, at the gain control interface. Equation 2 is the expression for the VGA attenuation, VGAATT, as a function of VGAIN. VGAIN (V) = (GAIN+) − (GAIN−) (1) VGAATT (dB) = −14 dB/V (1.6) − VGAIN (2) Good system sensitivity relies on a proprietary ultralow noise LNA at the beginning of the signal chain, which minimizes the noise contribution in the following VGA. Active impedance control optimizes noise performance for applications that benefit from input impedance matching. The LNA inputs, LI-x, are capacitively coupled to the source. An on-chip bias generator establishes dc input bias voltages of approximately 2.2 V and centers the output common-mode levels at 1.5 V (AVDD2 divided by 2). A capacitor, CLG, of the same value as the input coupling capacitor, CS, is connected from the LG-x pins into ground. The LNA supports three gain settings, 21.6 dB, 17.9 dB, or 15.6 dB, set through the SPI. Overload protection ensures quick recovery time from large input voltages. Low value feedback resistors and the current driving capability of the output stage allow the LNA to achieve a low input referred noise voltage of 0.78 nV/√Hz (at a gain of 21.6 dB). On-chip resistor matching results in precise single-ended gains, which Rev. A | Page 20 of 52 Data Sheet AD9670 The LNA consists of a single-ended voltage gain amplifier with differential outputs. The negative output is externally available on two output pins, LO-x and LOSW-x, that are controlled via internal switches. This configuration allows the active input impedance synthesis of three different impedance values (and an unterminated value) by connecting up to two external resistances in parallel and controlling the internal switch states via the SPI. For example, with a fixed gain of 8× (17.9 dB), an active input termination is synthesized by connecting a feedback resistor between the negative output pin, LO-x, and the positive input pin, LI-x. This well known technique is used for interfacing multiple probe impedances to a single system. The input resistance (RIN) calculation is shown in Equation 4. RIN (RFB1 20 ) || (RFB2 20 ) 30 (4) (1 A / 2) where: RFB1 and RFB2 are the external feedback resistors. 20 Ω is the internal switch on resistance. 30 Ω is an internal series resistance common to the two internal switches. A/2 is the single-ended gain or the gain from the LI-x inputs to the LO-x outputs. RFB can be equal to RFB1, RFB2, or (RFB1 + 20 Ω)||(RFB2 + 20 Ω), depending on the connection status of the internal switches. Because the amplifier has a gain of 8× from its input to its differential output, it is important to note that the gain, A/2, is the gain from the LI-x pin to the LO-x pin and that it is 6 dB less than the gain of the amplifier, or 12.1 dB (4×). The input resistance is reduced by an internal bias resistor of 6 kΩ in parallel with the source resistance connected to the LI-x pin, with the LG-x pin ac grounded. Use Equation 5 to calculate the required RFB for a desired RIN, even for higher values of RIN. R IN ( R FB1 20 ) || ( R FB2 20 ) 30 (1 A / 2) || 6 k Table 8. Active Termination Example for LNA Gain = 21.6 dB, RFB1 = 650 Ω, and RFB2 = 1350 Ω Reg. 0x02C Value 00 (default) 01 10 11 1 2 LO-x Switch On On Off Off LOSW-x Switch Off On On Off RFB (Ω) RFB1 RFB1 || RFB2 RFB2 ∞ RIN (Ω)1 100 66 200 ∞ See Equation 4. N/A means not applicable. The bandwidth (BW) of the LNA is greater than 80 MHz. Ultimately, the BW of the LNA limits the accuracy of the synthesized RIN. For RIN = RS up to about 200 Ω, the best match is between 100 kHz and 10 MHz, where the lower frequency limit is determined by the size of the ac coupling capacitors, and the upper limit is determined by the LNA BW. Furthermore, the input capacitance and RS limit the BW at higher frequencies. Figure 34 shows RIN vs. frequency for various values of RFB. 1k RS = 500Ω, RFB = 2kΩ RS = 200Ω, RFB = 800Ω 100 RS = 100Ω, RFB = 400Ω, CSH = 20pF RS = 50Ω, RFB = 200Ω, CSH = 70pF 10 100k 1M 10M FREQUENCY (Hz) 100M Figure 34. RIN vs. Frequency for Various Values of RFB (Effects of RSH and CSH Are Also Shown) (5) For example, to set RIN to 200 Ω with a single-ended LNA gain of 12.1 dB (4×), the value of RFB from Equation 4 must be 950 Ω, while the switch for RFB2 is open. If the more accurate equation (Equation 5) is used to calculate RIN, the value is then 194 Ω instead of 200 Ω, resulting in a gain error of less than 0.27 dB. Some factors, such as the presence of a dynamic source resistance, may influence the absolute gain accuracy more significantly. At higher frequencies, the input capacitance of the LNA must be considered. The user must determine the level of matching accuracy and adjust RFB accordingly. RS (Ω) 100 50 200 N/A2 11041-024 Active Impedance Matching RFB is the resulting impedance of the RFB1 and RFB2 combination (see Figure 33). Using Register 0x02C in the SPI memory map, the AD9670 can be programmed for four impedance matching options: three active terminations and one unterminated option. Table 8 shows an example of how to select RFB1 and RFB2 for 66 Ω, 100 Ω, and 200 Ω input impedances for LNA gain = 21.6 dB (12×). INPUT RESISTANCE (Ω) are critical for accurate impedance control. The use of a fully differential topology and negative feedback minimizes distortion. Low second-order harmonic distortion is particularly important in harmonic ultrasound imaging applications. However, as seen for larger RIN values, parasitic capacitance starts rolling off the signal BW before the LNA produces peaking. CSH further degrades the match; therefore, do not use CSH for values of RIN that are greater than 100 Ω. Rev. A | Page 21 of 52 AD9670 Data Sheet Figure 36 shows the noise figure as it relates to RS for various values of RIN, which is helpful for design purposes. 8 RFB (Ω) 150 200 300 350 450 650 750 950 1350 Minimum CSH (pF) 90 70 50 30 20 10 Not applicable Not applicable Not applicable 6 0 10 100 RS (Ω) 1k Figure 36. Noise Figure vs. RS for Various Fixed Values of RIN, Active Termination Matched Inputs, VGAIN = 1.6 V CLNA Connection Attach a 1 nF capacitor from CLNA (Ball B7) to AVDD2. DC Offset Correction/High-Pass Filter The AD9670 LNA architecture is designed to correct for dc offset voltages that can develop on the external CS capacitor due to leakage of the T/R switch during ultrasound transmit cycles. The dc offset correction, as shown in Figure 37, provides a feedback mechanism to the LG-x input of the LNA to correct for this dc voltage. AD9670 RFB1 LO-x RFB2 LOSW-x T/R SWITCH CS LI-x LG-x CSH LNA 15.6dB, 17.9dB, 21.6dB CLG TRANSDUCER gm 12.0 DC OFFSET CORRECTION 10.5 Figure 37. Simplified LNA Input Configuration 9.0 NOISE FIGURE (dB) 3 1 Figure 35 shows the relative noise figure performance. With an LNA gain of 21.6 dB, the input impedance is swept with RS to preserve the match at each point. The noise figures for a source impedance of 50 Ω are 7 dB, 4 dB, and 2.5 dB for the shunt termination, active termination, and unterminated configurations, respectively. The noise figures for 200 Ω are 4.5 dB, 1.7 dB, and 1 dB, respectively. The feedback acts as high-pass filter providing dynamic correction of the dc offset. The cutoff frequency of the high-pass filter response is dependent on the value of the CLG capacitor, the gain of the LNA (LNAGAIN), and the transconductance (gm) of the feedback transconductance amplifier. The gm value is programmed in Register 0x120, Bits[4:3]. CS must be equal to CLG for proper operation. 7.5 SHUNT TERMINATION 6.0 4.5 3.0 ACTIVE TERMINATION UNTERMINATED 10 100 RS (Ω) 1k 11041-025 1.5 0 4 2 LNA Noise The short-circuit noise voltage (input referred noise) is an important limit on system performance. The short-circuit noise voltage for the LNA is 0.78 nV/√Hz at a gain of 21.6 dB, including the VGA noise at a VGA postamplifier gain of 27 dB. These measurements, taken without a feedback resistor, provide the basis for calculating the input noise and noise figure (NF) performance. Figure 35 and Figure 36 are simulations of noise figure vs. RS results with different input configurations and an input referred noise voltage of 2.5 nV/√Hz for the VGA. Unterminated (RFB = ∞) operation exhibits the lowest equivalent input noise and noise figure. Figure 36 shows the noise figure vs. source resistance rising at low RS—where the LNA voltage noise is large compared to the source noise—and at high RS due to the noise contribution from RFB. The lowest NF is achieved when RS matches RIN. 5 11041-026 RIN (Ω) 50 50 50 100 100 100 200 200 200 NOISE FIGURE (dB) LNA Gain (dB) 15.6 17.9 21.6 15.6 17.9 21.6 15.6 17.9 21.6 RIN = 50Ω RIN = 75Ω RIN = 100Ω RIN = 200Ω UNTERMINATED 7 Table 9. Active Termination External Component Values 11041-035 Table 9 lists the recommended values for RFB and CSH in terms of RIN. CFB is needed in series with RFB because the dc levels at the LO-x pin and the LI-x pin are unequal. Figure 35. Noise Figure vs. RS for Shunt Termination, Active Termination Matched, and Unterminated Inputs, VGAIN = 1.6 V Rev. A | Page 22 of 52 Data Sheet AD9670 gm (mS) 0.5 1.0 1.5 2.0 LNAGAIN = 15.6 dB (kHz) 41 83 133 167 LNAGAIN = 17.9 dB (kHz) 55 110 178 220 AD9670 LNAGAIN = 21.6 dB (kHz) 83 167 267 330 0.01µF GAIN– 100Ω 0.01µF 249Ω ADA4938-1/ ADA4938-2 31.3kΩ ±1.6V 0.8V CM 249Ω 10kΩ ±0.8V DC AT 0.8V CM 249Ω Figure 38. Differential GAIN± Pin Configuration Disable the analog gain control and digitally control the attenuator using SPI Register 0x011, Bits[7:4]. The control range is 45 dB, and the step size is 3.5 dB. For other values of CLG, determine the high-pass filter cutoff frequency by scaling the values from Table 10 or calculating based on CLG, LNAGAIN, and gm, as shown in Equation 6. fHP (CLG) = 10 nF g 1 × LNAGAIN × m = fHP (see Table 10) × 2 C LG C LG GAIN+ ±0.8V DC 100Ω AT 0.8V CM 11041-027 Reg. 0x120, Bits[4:3] 00 (default) 01 10 11 AVDD2 249Ω Table 10. High-Pass Filter Cutoff Frequency, fHP, for CLG = 10 nF VGA Noise (6) Variable Gain Amplifier (VGA) The differential X-AMP VGA provides precise input attenuation and interpolation. It has a low input referred noise of 2.5 nV/√Hz and excellent gain linearity. The VGA is driven by a fully differential input signal from the LNA. The X-AMP architecture produces a linear in dB gain law conformance and low distortion levels—deviating by only ±0.5 dB or less from the ideal. The gain slope is monotonic with respect to the control voltage and is stable with variations in process, temperature, and supply. The resulting total gain range is 45 dB, which allows range loss at the endpoints. The X-AMP inputs are part of a PGA that completes the VGA. The PGA in the VGA is programmable to a gain of 21 dB, 24 dB, 27 dB, or 30 dB. This allows the optimization of channel gain for different imaging modes in the ultrasound system. The VGA bandwidth is greater than 100 MHz. The input stage is designed to ensure excellent frequency response uniformity across the gain setting. For TGC mode, this uniformity minimizes time delay variation across the gain range. In a typical application, a VGA compresses a wide dynamic range input signal to within the input span of an ADC. The input referred noise of the LNA limits the minimum resolvable input signal, whereas the output referred noise, which depends primarily on the VGA, limits the maximum instantaneous dynamic range that can be processed at any one particular gain control voltage. This latter limit is set in accordance with the total noise floor of the ADC. The output referred noise is a flat 40 nV/√Hz (postamplifier gain = 24 dB) over most of the gain range because it is dominated by the fixed output referred noise of the VGA. At the high end of the gain control range, the noise of the LNA and of the source prevail. The input referred noise reaches its minimum value near the maximum gain control voltage, where the input referred contribution of the VGA is miniscule. Gain Control At lower gains, the input referred noise and, therefore, the noise figure, increases as the gain decreases. The instantaneous dynamic range of the system is not lost, however, because the input capacity increases as the input referred noise increases. The contribution of the ADC noise floor has the same dependence. The important relationship is the magnitude of the VGA output noise floor relative to that of the ADC. The analog gain control interface, GAIN±, is a differential input. VGAIN varies the gain of all VGAs through the interpolator by selecting the appropriate input stages connected to the input attenuator. The nominal VGAIN range is 14 dB/V from −1.6 V to +1.6 V, with the best gain linearity from approximately −1.44 V to +1.44 V, where the error is typically less than ±0.5 dB. For VGAIN voltages of greater than +1.44 V and less than −1.44 V, the error increases. The value of GAIN± can exceed the supply voltage by 1 V without gain foldover. Gain control noise is a concern in very low noise applications. Thermal noise in the gain control interface can modulate the channel gain. The resulting noise is proportional to the output signal level and is usually evident only when a large signal is present. Take care to minimize noise impinging at the GAIN± inputs. Use an external RC filter to remove VGAIN source noise. The filter bandwidth must be sufficient to accommodate the desired control bandwidth and attenuate unwanted switching noise from the external DACs used to drive the gain control. Gain control response time is less than 750 ns to settle within 10% of the final value for a change from minimum to maximum gain. The AD9670 can bypass the GAIN± inputs and control the gain of the attenuator digitally (see the Gain Control section). This mode removes any external noise contributions when active gain control is not needed. The differential input pins, GAIN+ and GAIN−, can be interfaced as shown in Figure 38. DC couple the GAIN+ and GAIN− pins, and drive them to accommodate a 3.2 V full-scale input. Rev. A | Page 23 of 52 AD9670 Data Sheet Antialiasing Filter The filter that the signal reaches prior to the ADC is used to reject dc signals and to band limit the signal for antialiasing. The antialiasing filter is a combination of a single-pole highpass filter and a second-order low-pass filter. The high-pass filter can be configured at a ratio of the low-pass filter cutoff. This is selectable through Register 0x02B. The filter uses on-chip tuning to trim the capacitors and, in turn, to set the desired low-pass cutoff frequency and reduce variations. The default −3 dB low-pass filter cutoff is 1/3, 1/4.5, or 1/6 of the ADC sample clock rate. The cutoff can be scaled to 0.75, 0.8, 0.9, 1.0, 1.13, 1.25, or 1.45 times this frequency through Register 0x00F. The cutoff tolerance (±10%) is maintained from 8 MHz to 18 MHz for low band mode and 13.5 MHz to 30 MHz for high band mode. Table 11 and Table 12 calculate the valid SPI-selectable low-pass filter settings and expected cutoff frequencies for the low band and high band mode at the minimum sample frequency and the maximum sample frequency in each speed mode. Rev. A | Page 24 of 52 AD9670 Data Sheet Table 11. SPI-Selectable Low-Pass Filter Cutoff Options for Low Band Mode at Example Sampling Frequencies Address 0x00F, Bits[7:3] 0 0000 LPF Cutoff Frequency (MHz) 1.45 × (1/3) × fSAMPLE Sampling Frequency (MHz) 20.5 9.91 0 0001 1.25 × (1/3) × fSAMPLE 8.54 0 0010 1.13 × (1/3) × fSAMPLE 0 0011 1.0 × (1/3) × fSAMPLE 0 0100 0.9 × (1/3) × fSAMPLE 0 0101 0.8 × (1/3) × fSAMPLE 0 0110 0.75 × (1/3) × fSAMPLE 0 1000 1.45 × (1/4.5) × fSAMPLE 0 1001 1.25 × (1/4.5) × fSAMPLE 0 1010 1.13 × (1/4.5) × fSAMPLE 0 1011 1.0 × (1/4.5) × fSAMPLE 0 1100 0.9 × (1/4.5) × fSAMPLE 0 1101 0.8 × (1/4.5) × fSAMPLE 0 1110 0.75 × (1/4.5) × fSAMPLE 1 0000 1.45 × (1/6) × fSAMPLE 1 0001 1.25 × (1/6) × fSAMPLE 1 0010 1.13 × (1/6) × fSAMPLE 1 0011 1.0 × (1/6) × fSAMPLE 1 0100 0.9 × (1/6) × fSAMPLE 1 0101 0.8 × (1/6) × fSAMPLE 1 0110 0.75 × (1/6) × fSAMPLE Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range 40 Out of tunable filter range 16.67 10.67 65 Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range 17.33 10.00 16.25 12.89 20.94 11.11 18.06 10.00 16.25 8.89 14.44 Out of tunable filter range Out of tunable filter range Out of tunable filter range 17.78 8.00 13.00 16.00 Out of tunable filter range Out of tunable filter range 9.67 11.56 14.22 10.83 13.33 15.71 8.33 13.54 Out of tunable filter range 16.67 Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range 12.19 15.00 10.83 13.33 9.75 12.00 8.67 10.67 Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range 16.67 8.13 10.00 15.63 15.00 13.33 12.00 Rev. A | Page 25 of 52 80 Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range 16.82 125 Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range 17.50 AD9670 Data Sheet Table 12. SPI-Selectable Low-Pass Filter Cutoff Options for High Band Mode at Example Sampling Frequencies Address 0x00F, Bits[7:3] 0 0000 LPF Cutoff Frequency (MHz) 1.45 × (1/3) × fSAMPLE 0 0001 1.25 × (1/3) × fSAMPLE 0 0010 1.13 × (1/3) × fSAMPLE 0 0011 1.0 × (1/3) × fSAMPLE 0 0100 0.9 × (1/3) × fSAMPLE 0 0101 0.8 × (1/3) × fSAMPLE 0 0110 0.75 × (1/3) × fSAMPLE 0 1000 1.45 × (1/4.5) × fSAMPLE 0 1001 1.25 × (1/4.5) × fSAMPLE 0 1010 1.13 × (1/4.5) × fSAMPLE 0 1011 1.0 × (1/4.5) × fSAMPLE 0 1100 0.9 × (1/4.5) × fSAMPLE 0 1101 0.8 × (1/4.5) × fSAMPLE 0 1110 0.75 × (1/4.5) × fSAMPLE 1 0000 1.45 × (1/6) × fSAMPLE 1 0001 1.25 × (1/6) × fSAMPLE 1 0010 1.13 × (1/6) × fSAMPLE 1 0011 1.0 × (1/6) × fSAMPLE 1 0100 0.9 × (1/6) × fSAMPLE 1 0101 0.8 × (1/6) × fSAMPLE 1 0110 0.75 × (1/6) × fSAMPLE 20.5 Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range 40 19.33 16.67 15.00 Sampling Frequency (MHz) 65 80 Out of tunable Out of tunable filter range filter range 27.08 Out of tunable filter range 24.38 30.00 Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Rev. A | Page 26 of 52 21.67 26.67 19.50 24.00 17.33 21.33 16.25 20.00 20.94 25.78 18.06 22.22 16.25 20.00 14.44 17.78 125 Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range 27.78 Out of tunable filter range Out of tunable filter range Out of tunable filter range 15.71 16.00 25.00 14.22 22.22 Out of tunable filter range 19.33 20.83 13.54 16.67 Out of tunable filter range 26.04 Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range 15.00 23.44 Out of tunable filter range Out of tunable filter range Out of tunable filter range Out of tunable filter range 20.83 18.75 16.67 15.63 Data Sheet AD9670 For optimum performance, clock the AD9670 sample clock inputs (CLK+ and CLK−) with a differential signal. This signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or capacitors. These pins are biased internally and require no additional bias. Figure 39 shows the preferred method for clocking the AD9670. A low jitter clock source, such as the Valpey Fisher oscillator, VFAC3BHL-50 MHz, is converted from single-ended to differential using an RF transformer. The back to back Schottky diodes across the secondary transformer limit clock excursions into the AD9670 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9670, and it preserves the fast rise and fall times of the signal, which are critical to low jitter performance. 3.3V 0.1µF Table 13. High-Pass Filter Cutoff Options 1 Ratio1 12.00 9.00 6.00 3.00 High-Pass Cutoff Frequency Low-Pass Low-Pass Cutoff = 8 MHz Cutoff = 18 MHz 670 kHz 1.5 MHz 890 kHz 2.0 MHz 1.33 MHz 3.0 MHz 2.67 MHz 6.0 MHz Ratio is the low-pass filter cutoff frequency/high-pass filter cutoff frequency. Antialiasing Filter/VGA Test Mode For debug and testing, there is a bypass switch to view the antialiasing filter output on the GPO2 and GPO3 pins. Enable this mode using SPI Register 0x109, Bit 4. The differential antialiasing filter output of only one channel can be accessed at a time. The dc output voltage is 1.5 V (or AVDD2/2) and the maximum ac output voltage is 2 V p-p. 50Ω 100Ω CLK+ AD9670 0.1µF VFAC3 CLK– 0.1µF SCHOTTKY DIODES: HSM2812 Figure 39. Transformer-Coupled Differential Clock If a low jitter clock is available, another option is to ac-couple a differential PECL signal to the sample clock input pins, as shown in Figure 40. Analog Devices, Inc., offers a family of clock drivers with excellent jitter performance, including the AD9516-0, AD9516-1, AD9516-2, AD9516-3, and AD9516-5 (these five devices are represented by AD9516-x in Figure 40, Figure 41, and Figure 42), as well as the AD9524. 3.3V AD9516-x OR AD9524 VFAC3 0.1µF 0.1µF CLK+ CLK OUT 50Ω* 0.1µF ADC AD9670 100Ω PECL DRIVER 0.1µF CLK– CLK The AD9670 uses a pipelined ADC architecture. The quantized output from each stage is combined into a 14-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample and the remaining stages to operate on preceding samples. Sampling occurs on the rising edge of the clock. 240Ω 240Ω 11041-029 Reg. 0x02B[1:0] High-Pass Filter Cutoff 00 (default) 01 10 11 OUT MINI-CIRCUITS® ADT1-1WT, 1:1Z 0.1µF XFMR 11041-028 A total of four SPI-programmable settings allow the user to vary the high-pass filter cutoff frequency as a function of the lowpass cutoff frequency. Two examples are shown in Table 13: one example is for an 8 MHz low-pass cutoff frequency, and the other example is for an 18 MHz low-pass cutoff frequency. In both examples, as the ratio decreases, the amount of rejection on the low-end frequencies increases. Therefore, making the entire antialiasing filter frequency pass band narrow can reduce low frequency noise or maximize dynamic range for harmonic processing. Clock Input Considerations *50Ω RESISTOR IS OPTIONAL. Figure 40. Differential PECL Sample Clock A third option is to ac couple a differential LVDS signal to the sample clock input pins, as shown in Figure 41. 3.3V The output staging block aligns the data, corrects errors, and passes the data to the output buffers. The data is then serialized and aligned to the frame and output clocks. VFAC3 AD9516-x OR AD9524 0.1µF 0.1µF CLK+ CLK OUT 50Ω* 0.1µF LVDS DRIVER CLK 100Ω AD9670 0.1µF CLK– *50Ω RESISTOR IS OPTIONAL. Figure 41. Differential LVDS Sample Clock Rev. A | Page 27 of 52 11041-030 Tuning is normally off to avoid changing the capacitor settings during critical times. The tuning circuit is enabled through the SPI. It is disabled automatically after 512 cycles of the ADC sample clock. Initializing the tuning of the filter must be performed after initial power-up and after reprogramming the filter cutoff scaling or ADC sample rate. The tuning is initiated in Register 0x02B, Bit 6. AD9670 Data Sheet 130 In some applications, it is acceptable to drive the sample clock inputs with a single-ended CMOS signal. In such applications, drive CLK+ directly from a CMOS gate, and bypass the CLK− pin to ground with a 0.1 μF capacitor (see Figure 42). AD9516-x OR AD9524 0.1µF CLK 50Ω* CMOS DRIVER OPTIONAL 0.1µF 100Ω SNR (dB) VFAC3 OUT 110 CLK+ 90 14 BITS 80 CLK– 12 BITS 70 50 10 BITS 8 BITS 40 11041-031 0.1µF *50Ω RESISTOR IS OPTIONAL. 30 Figure 42. Single-Ended, 1.8 V CMOS Sample Clock 1 0.125ps 0.25ps 0.5ps 1.0ps 2.0ps 10 100 ANALOG INPUT FREQUENCY (MHz) 1000 Figure 43. Ideal SNR vs. Analog Input Frequency and Jitter Clock Duty Cycle Considerations Power Dissipation and Power-Down Mode Typical high speed ADCs use both clock edges to generate a variety of internal timing signals. As a result, these ADCs may be sensitive to the clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9670 contains a duty cycle stabilizer (DCS) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of the AD9670. When the DCS is on, noise and distortion performance are nearly flat for a wide range of duty cycles. However, some applications may require the DCS function to be off. If so, keep in mind that the dynamic range performance may be affected when operated in this mode. The duty cycle stabilizer uses a delay-locked loop (DLL) to create the nonsampling edge. As a result, any changes to the sampling frequency require approximately eight clock cycles to allow the DLL to acquire and lock to the new rate. Clock Jitter Considerations High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fA) due only to aperture jitter (tJ) can be calculated as follows: SNR Degradation = 20 × log10(1/2 × π × fA × tJ) 16 BITS 60 AD9670 CLK 0.1µF 100 11041-033 3.3V RMS CLOCK JITTER REQUIREMENT 120 (7) In this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and ADC aperture jitter (see Figure 43). Treat the clock input as an analog signal when aperture jitter may affect the dynamic range of the AD9670. Separate power supplies for clock drivers from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystalcontrolled oscillators make the best clock sources, such as the Valpey Fisher VFAC3 series. If the clock is generated from another type of source (by gating, dividing, or other methods), retime it by the original clock during the last step. For more information about how jitter performance relates to ADCs, refer to the AN-501 Application Note and the AN-756 Application Note. The power dissipated by the AD9670 is proportional to its sample rate. The digital power dissipation does not vary significantly because it is determined primarily by the DRVDD supply and the bias current of the LVDS output drivers. The AD9670 features scalable LNA bias currents (see Table 27, Register 0x012). The default LNA bias current settings are high. By asserting the PDWN pin high, the AD9670 is placed into power-down mode. In this state, the device typically dissipates 5 mW. During power-down, the LVDS output drivers are placed into a high impedance state. The AD9670 returns to normal operating mode when the PDWN pin is pulled low. This pin is only 1.8 V tolerant. To drive the PDWN pin from a 3.3 V logic level, insert a 1 kΩ resistor in series with this pin to limit the current. By asserting the STBY pin high, the AD9670 is placed into a standby mode. In this state, the device typically dissipates 630 mW. During standby, the entire device, except the internal references, is powered down. The LVDS output drivers are placed into a high impedance state. This mode is well suited for applications that require power savings because it allows the device to power down when not in use, and then be quickly powered up. The time to power the device back up is also greatly reduced. The AD9670 returns to normal operating mode when the STBY pin is pulled low. This pin is only 1.8 V tolerant. To drive the STBY pin from a 3.3 V logic level, insert a 1 kΩ resistor in series with this pin to limit the current. In power-down mode, low power dissipation is achieved by shutting down the reference, reference buffer, PLL, and biasing networks. The decoupling capacitors on VREF are discharged when entering power-down mode and must be recharged when returning to normal operation. As a result, the wake-up time is related to the time spent in the power-down mode: shorter cycles result in proportionally shorter wake-up times. To restore the device to full operation, approximately 375 μs is required when using the recommended 1 μF and 0.1 μF decoupling capacitors on the VREF pin and the 0.01 μF decoupling capacitors on the GAIN± pins. Most of this time is dependent on the gain decoupling: Rev. A | Page 28 of 52 Data Sheet AD9670 A number of other power-down options are available when using the SPI port interface. The user can individually power down each channel or put the entire device into standby mode. This allows the user to keep the internal PLL powered up when fast wake-up times are required. The wake-up time is slightly dependent on gain. To achieve a 2 μs wake-up time when the device is in standby mode, 0.8 V must be applied to the GAIN± pins. Power and Ground Connection Recommendations When connecting power to the AD9670, it is recommended that two separate 1.8 V supplies be used: one for analog supply (AVDD1) and one for digital supply (DRVDD). If only one 1.8 V supply is available, route this supply to the AVDD1 pin first, and then tap the supply off and isolate it with a ferrite bead or a filter choke preceded by decoupling capacitors for the DRVDD pin. If the user does not use the digital demodulator and decimator functions for post ADC processing, the DVDD pin can be tied to the 1.8 V DRVDD supply. If this is the case, route the DVDD supply first, tapped the supply off, and isolated it with a ferrite bead or filter choke preceded by decoupling capacitors for the DRVDD pin. It is not recommended to use the same supply for AVDD1, DVDD, and DRVDD. Use several decoupling capacitors on all supplies to cover both high and low frequencies. Locate these capacitors close to the point of entry at the PCB level and close to the device, with minimal trace lengths. A single PCB ground plane is sufficient when using the AD9670. With proper decoupling and smart partitioning of the analog, digital, and clock sections of the PCB, optimum performance is easily achieved. Advanced Power Control Not all channels are required during all periods of scanning in an ultrasound system. Use the POWER_START and POWER_ STOP values in the vector profile to delay the channel startup and to turn the channel off after a certain number of samples. These counters are relative to TX_TRIG±. The analog circuitry must power up before the digital circuitry, and the advance time (POWER_SETUP) for powering up the analog circuitry, before POWER_START, is set up in Register 0x112, Bits[4:0] (see Table 27). TX_TRIG± DIGITAL POWER ANALOG POWER POWER_STOP (PROFILE SPECIFIC) POWER_START (PROFILE SPECIFIC) POWER_SETUP (SPI SET) 11041-034 higher value decoupling capacitors on the GAIN± pins result in longer wake-up times. Figure 44. Power Sequencing Digital Outputs and Timing The AD9670 differential outputs conform to the ANSI-644 LVDS standard on default power-up. This standard can be changed to a low power, reduced signal option similar to the IEEE 1596.3 standard via the SPI using Register 0x015, Bit 7. This LVDS standard can further reduce the overall power dissipation of the device by approximately 36 mW. The LVDS driver current is derived on chip and sets the output current at each output equal to a nominal 3.5 mA. A 100 Ω differential termination resistor placed at the LVDS receiver inputs results in a nominal 350 mV swing at the receiver. The AD9670 LVDS outputs facilitate interfacing with LVDS receivers in custom ASICs and FPGAs that have LVDS capability for superior switching performance in noisy environments. Single point-to-point network topologies are recommended with a 100 Ω termination resistor placed as close to the receiver as possible. No far-end receiver termination and poor differential trace routing may result in timing errors. The trace length must be no longer than 24 inches. Keep the differential output traces close together and at equal lengths. Rev. A | Page 29 of 52 AD9670 Data Sheet 300 200 100 0 –100 –200 –300 –400 ULS: 11197/11197 –1.5 –1.0 –0.5 300 0 TIME (ns) 0.5 1.0 1.5 Figure 47. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths of Greater Than 24 Inches on Standard FR-4 Material 200 100 80 0 –100 70 –200 –300 –1.0 –0.5 0 TIME (ns) 0.5 1.0 1.5 Figure 45. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths of Less Than 24 Inches on Standard FR-4 Material 50 40 30 20 10 70 0 –300 60 50 –200 –100 0 TIME (ps) 100 200 300 Figure 48. TIE Jitter Histogram for LVDS Outputs in ANSI-644 Mode with Trace Lengths of Greater Than 24 Inches on Standard FR-4 Material 40 Additional SPI options allow the user to further increase the internal current of all eight outputs to drive longer trace lengths. Even though this produces sharper rise and fall times on the data edges, it is less prone to bit errors and improves frequency distribution. The power dissipation of the DRVDD supply increases when this option is used. 30 20 –100 –50 0 TIME (ps) 50 100 150 11041-144 10 0 –150 60 11041-145 –1.5 11041-044 –400 TIE JITTER HISTOGRAM (Hits) EYE DIAGRAM VOLTAGE (mV) 400 TIE JITTER HISTOGRAM (Hits) ULS: 11199/11199 11041-045 EYE: ALL BITS EYE: ALL BITS 400 EYE DIAGRAM VOLTAGE (mV) An example of the LVDS output using the ANSI-644 standard (default) data eye and a time interval error (TIE) jitter histogram with trace lengths of less than 24 inches on regular FR-4 material is shown in Figure 45 and Figure 46. Figure 47 and Figure 48 show examples of the trace lengths exceeding 24 inches on regular FR-4 material. Notice that the TIE jitter histogram reflects the decrease of the data eye opening as the edge deviates from the ideal position; therefore, the user must determine whether the waveforms meet the timing budget of the design when the trace lengths exceed 24 inches. Figure 46. TIE Jitter Histogram for LVDS Outputs in ANSI-644 Mode with Trace Lengths of Less Than 24 Inches on Standard FR-4 Material In cases that require increased drive current, Register 0x015 allows the user to adjust the drivers from 2.0 mA to 3.72 mA. Note that this feature requires Bit 3 of Register 0x015 to be enabled. The drive current can be adjusted for both ANSI-644 and IEEE (low power) mode. See Table 27 for more details. Rev. A | Page 30 of 52 Data Sheet AD9670 The format of the output data is twos complement by default. Table 14 provides an example of the output coding format. To change the output data format to twos complement, see the Memory Map section. Table 14. Digital Output Coding with RF Decimator Bypassed, Demodulator Bypassed, and Baseband Decimator Bypassed Code 16384 8192 8191 0 (VIN+) − (VIN−), Input Span = 2 V p-p (V) +1.00 0.00 −0.000488 −1.00 Digital Output Mode: Twos Complement (D13 to D0) 01 1111 1111 1111 00 0000 0000 0000 11 1111 1111 1111 10 0000 0000 0000 Digital data from each channel is serialized based on the number of lanes that are enabled (see Table 27). The maximum data rate for each serial output lane is 1 Gbps. For 1 channel/ lane with a 14-bit data stream and an ADC sample clock of 70 MHz, the output data rate is 980 Mbps (14 bits × 70 MHz = 980 Mbps) with the RF decimator bypassed, the demodulator bypassed, and the baseband decimator bypassed. For higher sample rates, enabling the RF decimator is required. Two output clocks are provided to assist in capturing data from the AD9670. DCO± clocks the output data and is equal to seven times the sampling clock rate in 14-bit mode with the RF decimator bypassed, the demodulator bypassed, and the baseband decimator bypassed. Data is clocked out of the AD9670 and must be captured on the rising and falling edges of DCO±, which support double data rate (DDR) capturing. The frame clock output (FCO±) signals the start of a new output byte and is equal to the sampling clock rate. A 12-, 14-, or 16-bit serial stream can also be initiated from SPI Register 0x021, Bits[1:0]. The user can implement different serial streams and test device compatibility with lower and higher resolution systems using these modes. When using the SPI, all the data outputs can also be inverted from their nominal state by setting Bit 2 in the output mode register (Register 0x014). This is not to be confused with inverting the serial stream to an LSB first mode. In default mode, as shown in Figure 2, the MSB is represented first in the data output serial stream. However, this order this can be inverted so that the LSB is represented first in the data output serial stream. Output Zero Stuffing A zero stuffing feature handles the various decimation rates and complex (IQ) vs. real samples. As the decimation rates increase, relatively large amounts of zero stuffing can occur in the output data stream. Rev. A | Page 31 of 52 AD9670 Data Sheet Table 15. Flexible Output Test Modes Output Test Mode Bit Sequence 0000 0001 0010 0011 0100 0101 0110 0111 1000 Pattern Name Off (default) Midscale short +Full-scale short −Full-scale short Checkerboard PN sequence long PN sequence short One-/zero-word toggle User input Digital Output Word 1 Not applicable 10 0000 0000 0000 11 1111 1111 1111 00 0000 0000 0000 10 1010 1010 1010 Not applicable Not applicable 11 1111 1111 1111 Register 0x019 and Register 0x01A There are nine digital output test pattern options available that can be initiated through the SPI. The test pattern options are useful when validating receiver capture and timing. See Table 15 for the available output bit sequencing options. Some test patterns have two serial sequential words and can be alternated in various ways, depending on the test pattern chosen. Note that some patterns may not adhere to the data format select option. In addition, custom user defined test patterns can be assigned in the user pattern registers (Address 0x019 through Address 0x01C). All test mode options except pseudorandom number (PN) sequence short and PN sequence long can support 8- to 14-bit word lengths to verify data capture to the receiver. The PN sequence short pattern produces a pseudorandom bit sequence that repeats itself every 29 − 1 bits, or 511 bits. A description of the PN sequence short and how it is generated can be found in Section 5.1 of the ITU-T O.150 (05/96) standard. The only difference from the standard is that the starting value is a specific value instead of all 1s (see Table 16 for the initial values). The PN sequence long pattern produces a pseudorandom bit sequence that repeats itself every 223 − 1 bits, or 8,388,607 bits. A description of the PN sequence long and how it generates is found in Section 5.6 of the ITU-T O.150 (05/96) standard. The only differences from the standard are that the starting value is a specific value instead of all 1s, and that the AD9670 inverts the bit stream (see Table 16 for the initial values). The output sample size depends on the selected bit length. Table 16. PN Sequence PN Sequence Short Long Initial Value 0x092 0x003 First Three Output Samples (MSB First, 16-Bit) 0x496F, 0xC9A9, 0x980C 0xFF5C, 0x0029, 0xB80A See the Memory Map section for information on how to change these additional digital output timing features via the SPI. SDIO Pin The SDIO pin is required to operate the SPI. It has an internal 30 kΩ pull-down resistor that pulls this pin low and is only 1.79 V tolerant. If applications require that SDIO be driven from a 3.3 V logic level, insert a 1 kΩ resistor in series with this pin to limit the current. Digital Output Word 2 Not applicable Same Same Same 01 0101 0101 0101 Not applicable Not applicable 00 0000 0000 0000 Register 0x01B and Register 0x01C Subject to Resolution Select Not applicable Yes Yes Yes No Yes Yes No No SCLK Pin The SCLK pin is required to operate the SPI port interface. It has an internal 30 kΩ pull-down resistor that pulls this pin low and is only 1.8 V tolerant. To drive the SCLK pin from a 3.3 V logic level, insert a 1 kΩ resistor in series with this pin to limit the current. CSB Pin The CSB pin is required to operate the SPI port interface. CSB has an internal 70 kΩ pull-up resistor that pulls this pin high and is only 1.8 V tolerant. To drive the CSB pin from a 3.3 V logic level, insert a 1 kΩ resistor in series with this pin to limit the current. RBIAS Pin To set the internal core bias current of the ADC, place a resistor nominally equal to 10.0 kΩ to ground at the RBIAS pin. Using a resistor other than the recommended 10.0 kΩ resistor for RBIAS degrades the performance of the device. Therefore, it is imperative that at least a 1% tolerance on this resistor be used to achieve consistent performance. VREF Pin A stable and accurate 0.5 V voltage reference is built in to the AD9670. This reference is gained up internally by a factor of 2, setting VREF to 1.0 V, which results in a full-scale differential input span of 2.0 V p-p for the ADC. VREF is set internally by default, but the VREF pin can be driven externally with a 1.0 V reference to achieve more accuracy. However, the AD9670 does not support ADC full-scale ranges below 2.0 V p-p. When applying the decoupling capacitors to the VREF pin, use ceramic, low ESR capacitors. Place these capacitors close to the reference pin and on the same layer of the PCB as the AD9670. It is recommended that the VREF pin have both a 0.1 μF capacitor and a 1 μF capacitor that are connected in parallel to the analog ground. These capacitor values are recommended for the ADC to properly settle and acquire the next valid sample. General-Purpose Output Pins The general-purpose output pins, GPO0, GPO1, GPO2, and GPO3, can be used in a system to provide programmable inputs to other chips in the system. The value of each pin is set via SPI Register 0x00E to either Logic 0 or Logic 1 (see Table 27). Rev. A | Page 32 of 52 Data Sheet AD9670 Chip Address Pins CW DOPPLER OPERATION The chip address pins can be used to SPI address individual AD9670 devices in a system. When chip address mode is enabled in Register 0x115, Bit 5 (see Table 27), if the value written to Bits[4:0] matches the value on the chip address bit pins (ADDR0 to ADDR4), the device is selected and any subsequent SPI writes or reads to registers indicated as chip registers are written only to that device. If chip address mode is disabled, all registers can be written to, regardless of the value on the address pins. Each channel of the AD9670 includes a I/Q demodulator. Each demodulator has an individual programmable phase shifter. The I/Q demodulator is ideal for phased array beamforming applications used in medical ultrasound. Each channel can be programmed for 16 delay states/360° (or 22.5°/step), selectable via the SPI port. The device has a RESET± input that synchronizes the LO dividers of each channel. If multiple AD9670 devices are used, a common reset across the array ensures a synchronized phase for all channels. Internal to the AD9670, the individual Channel I and Channel Q outputs are current summed. If multiple AD9670 devices are used, the I and Q outputs from each AD9670 can be current summed and converted to a voltage using an external transimpedance amplifier. ANALOG TEST SIGNAL GENERATION The AD9670 generates analog test signals that can be switched to the input of the LNA of each channel to be used for channel gain calibration. The test signal amplitude at the LNA output is dependent on LNA gain, as shown in Table 17. Table 17. Test Signal Fundamental Amplitude at the LNA Output Reg. 0x116, Bits[3:2], Analog Test Tones 00 (Default) 01 10 At 15.6 dB (mV p-p) 80 160 320 LNA Gain At 17.9 dB (mV p-p) 98 196 391 At 21.6 dB (mV p-p) 119 238 476 Calculate the test signal amplitude at the input to the ADC given the LNA gain, attenuator control voltage, and the PGA gain. Table 18 and Table 19 show example calculations. Table 18. Test Signal Fundamental Amplitude at the ADC Input, VGAIN = 0 V, PGA Gain = 21 dB Register 0x116, Bits[3:2], Analog Test Tones 00 (Default) 01 10 At 15.6 dB (dBFS) −29 −23 −17 LNA Gain At 17.9 dB (dBFS) −28 −22 −16 At 21.6 dB (dBFS) −26 −20 −14 Table 19. Test Signal Fundamental Amplitude at the ADC Input, VGAIN = 0 V, PGA Gain = 30 dB Register 0x116, Bits[1:0], Analog Test Tones 00 (Default) 01 10 At 15.6 dB (dBFS) −20 −14 −8 LNA Gain At 17.9 dB (dBFS) −19 −13 −7 At 21.6 dB (dBFS) −17 −11 −5 Quadrature Generation The internal 0° and 90° LO phases are digitally generated by a divide-by-M logic circuit, where M = 4, 8, or 16. The internal divider is selected via SPI Register 0x02E, Bits[2:0] (see Table 27). The divider is dc-coupled and inherently broadband; the maximum LO frequency is limited only by its switching speed. The duty cycle of the quadrature LO signals must be as close to 50% as possible for the 4LO and 8LO modes. The 16LO mode does not require a 50% duty cycle. Furthermore, the divider is implemented such that the MLO signal reclocks the final flip-flops that generate the internal LO signals and, thereby, minimizes noise introduced by the divide circuitry. For optimum performance, the MLO input is driven differentially, as on the AD9670 evaluation board. The common-mode voltage on each pin is approximately 1.5 V with the nominal 3 V supply. It is important to ensure that the MLO source has very low phase noise (jitter), a fast slew rate, and an adequate input level to obtain optimum performance of the CW signal chain. Beamforming applications require a precise channel to channel phase relationship for coherence among multiple channels. A RESET± input is provided to synchronize the LO divider circuits in different AD9670 devices when they are used in arrays. The RESET± input is a synchronous edge triggered input that resets the dividers to a known state after power is applied to multiple AD9670 devices. The RESET± signal can be either a continuous signal or a single pulse, and it can be either synchronized with the MLO± clock edge (recommended) or it can be asynchronous. If a continuous signal is used for the RESET± signal, it must be at the LO rate. For a synchronous RESET±, the device can be configured to sample the RESET± signal with either the falling or rising edge of the MLO± clock, which makes it easier to align the RESET± signal with the opposite MLO± clock edge. Use Register 0x02E to configure the RESET signal behavior. Synchronize the RESET± input to the MLO input. Accurate channel-to-channel phase matching can be achieved via a common clock on the RESET± input when using more than one AD9670. Rev. A | Page 33 of 52 AD9670 Data Sheet I/Q Demodulator and Phase Shifter Table 20. Phase Select Code for Channel-to-Channel Phase Shift The I/Q demodulators consist of double-balanced, harmonic rejection, passive mixers. The RF input signals are converted into currents by transconductance stages that have a maximum differential input signal capability matching the LNA output full scale. These currents are then presented to the mixers, which convert them to baseband (RF − LO) and 2× RF (RF + LO). The signals are phase shifted according to the codes programmed into the SPI latch (see Table 27). The phase shift function is an integral part of the overall circuit. The phase shift listed in Table 20 is defined as being between the baseband I or Q channel outputs. As an example, for a common signal applied to a pair of RF inputs to an AD9670, the baseband outputs are in phase for matching phase codes. However, if the phase code for Channel 1 is 0000 and that of Channel 2 is 0001, Channel 2 leads Channel 1 by 22.5°. Φ Shift 0° 22.5° 45° 67.5° 90° 112.5° 135° 157.5° 180° 202.5° 225° 247.5° 270° 292.5° 315° 337.5° Rev. A | Page 34 of 52 I/Q Demodulator Phase (SPI Register 0x02D, Bits[3:0]) 0000 0001 (not valid in 4LO mode) 0010 0011 (not valid in 4LO mode) 0100 0101 (not valid in 4LO mode) 0110 0111 (not valid in 4LO mode) 1000 1001 (not valid in 4LO mode) 1010 1011 (not valid in 4LO mode) 1100 1101 (not valid in 4LO mode) 1110 1111 (not valid in 4LO mode) AD9670 Data Sheet DIGITAL DEMODULATOR/DECIMATOR The AD9670 contains digital processing capability. Each channel has three stages of processing available: the RF decimator, the baseband demodulator, and the baseband decimator. For test purposes, the input to the demodulator/decimator can be a test waveform. Normally, this input is the output of the ADC. The output of the demodulator/decimator is sent to the framer/ serializer for output formatting. The maximum data rate of the baseband demodulator and decimator is 65 MSPS. Therefore, if the sample of the ADC is greater than 65 MSPS, the RF decimator (with a fixed rate of 2) must be enabled. The ADC resolution is 14 bits. The maximum resolution at the output of the digital processing is 16 bits. Saturation of the ADC is determined after the dc offset calibration to ensure maximum dynamic range. Depending on the decimation rate, the loss in output SNR due to truncation to 16 bits is negligible. VECTOR PROFILE To minimize time needed to reconfigure device settings during operation, the device supports configuration profiles. Up to 32 profiles can be stored in the device. A profile is selected by a 5-bit index. A profile consists of a 64-bit vector, as described in Table 21. Each parameter is concatenated to form the 64-bit profile vector. The profile memory starts at Register 0xF00 and ends at Register 0xFFF. The memory can be written in either stream or address selected data mode. However, the memory must be read using stream mode. When writing or reading in stream mode while the SPI configuration is set to MSB first mode (the default setting for Register 0x000), the write/read address must refer to the last register address, not the first. For example, when writing or reading the first profile that spans the address space between Register 0xF00 and Register 0xF07, with the SPI port configured as MSB first, the referenced address must be Register 0xF07 to allow reading or writing the 64 profile bits in MSB mode. For more information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. A buffer stores the current profile data. When the profile index is written in Register 0x10C, the selected profile is read from memory and stored in the current profile buffer. The profile memory is read/written in the SPI clock domain. After the SPI writes the profile index value, the SPI takes 4 SPI clock cycles to read the profile from RAM and store it in the current profile buffer. If the SPI is in LSB mode, these additional SPI clock cycles are provided when the profile index register is written. If the SPI is in MSB mode, an additional byte must be read or written to update the profile buffer. Updating the profile memory does not affect the data in the profile buffer. The profile index register must be written to cause a refresh of the current profile data, even if the profile index register is written with the same value. NUMERICALLY CONTROLLED OSCILLATOR ADC OUTPUT OR TEST WAVEFORM MULTIBAND AAF DECIMATE BY 2 DC OFFSET CALIBRATION Cos HIGH-PASS FILTER BB DECIMATOR I Q RF DECIMATOR LOW-PASS FILTER DECIMATOR LOW-PASS FILTER DECIMATOR FRAMER SERIALIZER BB DEMODULATOR Figure 49. Simplified Block Diagram of a Single Channel of the Demodulator/Decimator Table 21. Profile Definition Field f Bits 16 P 8 Description Demodulation frequency (fD) fD = f × fSAMPLE/216, where f = [0,(216 − 1)] and fSAMPLE is the effective sample rate 0x0000: fD = 0 (dc, I = cos(0) = 1, Q = sin(0) = 0) 0x0001: fD = fSAMPLE/216 … 0x8000: fD = fSAMPLE/2 … 0xFFFF (216 − 1): fD = fSAMPLE (216 − 1)/ 216 =−fSAMPLE/216 Pointer to coefficient block; the coefficients used begin at coefficient P × 8 and continue for M × 8 coefficients, for example, 0000 0000: points to coefficient 0 and continues M × 8 coefficients 0000 0001: points to coefficient 8 and continues M × 8 coefficients Rev. A | Page 35 of 52 11041-038 –Sin AD9670 Data Sheet Field M Bits 5 g 3 HPF Bypass 1 POWER_START Reserved POWER_STOP 15 1 15 TX_TRIG indicates the differential signal created via the TX_TRIG− pin and the TX_TRIG+ pin. 10 RF DECIMATOR Reduce dc offset through a manual system calibration process. Measure the dc offset of every channel in the system and then set a calibration value in Register 0x110 and Register 0x111. Note that these registers are both chip and local registers, meaning that they are accessed using the chip address and device index. Bypass the dc offset calibration in Register 0x10F, Bits[2:0]. LOW BAND FILTER –10 HIGH BAND FILTER –20 –30 –40 –50 –60 0 2 4 6 8 10 12 14 16 18 20 FREQUENCY (MHz) Multiband Antialiasing Filter and Decimate by 2 Figure 50. Antialiasing Filter Frequency Response (Frequency Scale Assumes fADC = 2 × fDEC = 40 MHz) 2 1 0 AMPLITUDE (dBFS) The multiband filter is a finite pulse response (FIR). It is programmable with low or high band filtering. The filter requires 11 input samples to populate. The decimation rate is fixed at 2×. Therefore, the decimation frequency is fDEC = fSAMPLE/2. Figure 50 and Figure 51 show the frequency response of the filter, depending on the mode. Figure 50 shows the attenuation amplitude over the Nyquist frequency range. Figure 51 shows the pass band response as nearly flat. 11041-039 DC Offset Calibration 0 AMPLITUDE (dBFS) The input to the RF decimator is either the ADC output data or a test waveform described in the Digital Test Waveforms section. The test waveforms are enabled per channel in Register 0x11A (see Table 27). –1 LOW BAND FILTER HIGH BAND FILTER –2 –3 –4 –5 –6 –7 –8 0 2 4 6 8 10 12 FREQUENCY (MHz) 14 16 18 20 11041-040 1 Description Decimation factor M = N − 1, where N = decimation factor 0x00: decimate by 1 (no decimation, filtering only) 0x01: decimate by 2 0x02: decimate by 3 … 0x1F: decimate by 32 Digital gain compensation Gain = 2 000: gain = 1 (no shift) 001: gain = 2 (shift by 1) 010: gain = 4 (shift by 2) … 111: gain = 128 (shift by 7) Digital high-pass filter (HPF) bypass 0 = disable (filter enabled) 1 = enable (filter bypassed) ADC clock counted from TX_TRIG1 signal assertion when the active channels are powered up Reserved ADC clock counted from TX_TRIG1 signal assertion when the active channels are powered down Figure 51. Antialiasing Filter Frequency Response (Frequency Scale Assumes fADC = 2 × fDEC = 40 MHz) Rev. A | Page 36 of 52 Data Sheet AD9670 High-Pass Filter Table 22. Coefficient Memory for M = 4 A second-order Butterworth, high-pass infinite impulse response (IIR) filter can be applied after the RF decimator. The filter has a settling time of 2.5 μs and a cutoff of 700 kHz for an encode clock of 50 MHz. Therefore, if the ADC clock is 50 MHz, the first 125 samples (2.5 μs/0.02 μs) must be ignored. The filter can be bypassed or enabled in the vector profile if the filter is enabled in Register 0x113, Bit 5. If the filter is bypassed by setting Register 0x113, Bits[5:1], the filter cannot be enabled from the vector profile. j\i 0 1 2 3 BASEBAND DEMODULATOR AND DECIMATOR The demodulator downconverts the RF signal to a baseband quadrature signal. The decimator reduces the excess oversampling. Numerically Controlled Oscillator The numerically controlled oscillator (NCO) generates I and Q signals (cos and −sin) for the demodulator. A division of the effective sample clock generates the oscillator frequency. If the RF decimator is bypassed, the effective sample clock is the same as the ADC clock. If the RF decimator is enabled, the effective clock rate is ½ the ADC sample clock frequency. The divider is set in the vector profile. The oscillator has a frequency resolution of 1 kHz. To synchronize different devices, the NCO is reset upon assertion of the TX_TRIG signal. Decimation Filter The purpose of the decimation filter is to band limit the demodulated signal prior to decimation. The filter is a polyphase FIR filter that uses 16 taps per decimation with symmetrical coefficients. Therefore, there are eight unique, 14-bit coefficients per decimation. The decimation rate and a pointer to the coefficients used by the filter are set in the vector profile. Digital gain from 1 to 128 is applied to the filter response. The digital gain compensation is set in the vector profile. The filter is reset upon assertion of the TX_TRIG signal. The decimation filter takes 32× the decimation input samples or 32 output samples to populate. Coefficient Memory The coefficient memory stores the eight coefficients per decimation, with a maximum decimation of 32, in a coefficient memory block. At a maximum decimation of 32, 32 × 8 = 256 coefficients are needed. The coefficient memory is available at Address 0x1000 to Address 0x1FFF. This is sufficient space to store up to 2048 coefficients. Each vector profile has a pointer, P, to the coefficient block within coefficient memory. Coefficients are written using the SPI in stream mode during startup. Coefficients are written in 14-bit × 8-word = 112-bit blocks. There are 256 coefficient blocks. The 14-bit × 8-word coefficients are packed into 14 bytes × 8 bits, as shown in Table 22. 7 28 29 30 31 6 27 26 25 24 5 20 21 22 23 4 19 18 17 16 3 12 13 14 15 2 11 10 9 8 1 4 5 6 7 0 3 2 1 0 Writes and reads from a coefficient block must begin on a coefficient block boundary, and an entire coefficient block must be written or read. After a coefficient block is written, the coefficient block address automatically increments/decrements (depending on the LSB/MSB SPI setting in Register 0x000) to the next coefficient block. Having a direct map between the SPI memory address and coefficient block address requires a divide by 7, which is not simple to do in hardware (the address must be mapped within a single cycle). Therefore, each block is padded to a 16-byte boundary, but the SPI does not need to shift in these extra 2 bytes when loading coefficient memory sequentially. If the SPI is configured LSB first, the SPI address bits, Bits[3:0], are all 0s. If the SPI is configured MSB first, the SPI address bits are all 1s. In other words, in LSB mode, the referenced addresses for the coefficient memory blocks are 0x1000, 0x2000, and so on, while in MSB SPI mode, the referenced block addresses are 0x100F, 0x200F, and so on. The coefficient block order and how words/bytes are split across each other are shown in Table 23. When the SPI is configured LSB first, C0[0] = B0[0] is written first, and C7[13] = B13[7] is written last. When the SPI is configured MSB first, C7[13] = B13[7] is written first, and C0[0] = B0[0] is written last. The position of a coefficient, Cn, in memory is determined from its index (i, j) by n = M(1 + i) − (1 + j), if i is even (8) n = M × i + j, if i is odd (9) where: M is the decimation factor. i is the index within the coefficient block from 0 to 7. j is the decimation phase from 0 to M − 1. Due to symmetry, Coefficient C0 is multiplied by the newest and oldest samples. As an example, the coefficient memory for a decimation factor of M = 4 is shown in Table 22. The upper 16 bits of the filter output are used as the data output of the channel. The filter output may have gain applied according to g, from the vector profile. Additionally, a gain of 4× can be applied using the filter output gain in Register 0x113, Bit 4. Rev. A | Page 37 of 52 AD9670 Data Sheet Table 23. Coefficient Block Mapping into SPI Memory Location C7[13:0] 111:98 B13[7:0] 111:104 C6[13:0] 97:84 B12[7:0] 103:96 B11[7:0] 95:88 C5[13:0] 83:70 B10[7:0] 87:80 B9[7:0] 79:72 Coefficients (8 Words × 14 Bits) C4[13:0] C3[13:0] 69:56 55:42 SPI Memory (14 Bytes) B8[7:0] B7[7:0] B6[7:0] B5[7:0] B4[7:0] 71:64 63:56 55:48 47:40 39:32 C2[13:0] 41:28 B3[7:0] 31:24 B2[7:0] 23:16 C1[13:0] 27:14 C0[13:0] 13:0 B1[7:0] 15:8 B0[7:0] 7:0 DIGITAL TEST WAVEFORMS DIGITAL BLOCK POWER SAVING SCHEME Digital test waveforms can be used in the digital processing block instead of the ADC output. The digital test waveforms enable is set in Register 0x11B. Each channel can be individually enabled in Register 0x11A. To reduce power consumption in the digital block, the demodulator and decimation filter start in an idle state after running the chip (Register 0x008, Bits[2:0] = 000). The digital block only switches to a running state when the negative edge of the TX_TRIG pulse is detected, or with a software TX_TRIG write (Register 0x10C, Bit 5 = 1). Waveform Generator For testing and debugging, use the programmable waveform generator instead of ADC data. The waveform generator varies offset, amplitude, and frequency. The generator uses the ADC sample frequency, fSAMPLE, and ADC full-scale amplitude, AFULL SCALE, as references. The values are set in Register 0x117, Register 0x118, and Register 0x119 (see Table 27). x = C + A × sin(2 × π × N) A= 64 AFULL 2 (see Register 0x117) (10) CHIP IN POWER-DOWN, STANDBY, OR CW MODE (11) RUN CHIP SCALE x (see Register 0x118) C = AFULL SCALE × a × 2−(13 − b) (see Register 0x119) (12) DIGITAL DEMODULATOR IDLE (13) Channel ID and Ramp Generator In Channel ID test mode, the output is a concatenated value. Output Data Bits[6:0] are a ramp. Output Data Bit 7 is 0 in real data mode or I channel and 1 for Q channel in complex data mode. Output Data Bits[10:8] are the channel ID such that Channel A is coded as 000 and Channel B is 001. Output Data Bits[15:11] are the chip address. TX_TRIG IS HIGH, PROFILE INDEX WRITE, OR POWER STOP EXPIRES Filter Coefficients To check the filter coefficients, the input to the decimating FIR filter must be a sequence of 1 followed by 0s. The number of zeros is the decimation rate times the number of taps (16). The output shifter outputs the LSBs of the filter. Rev. A | Page 38 of 52 NEGATIVE EDGE TX_TRIG OR S/W TX_TRIG DIGITAL DEMODULATOR RUNNING Figure 52. Digital Block Power Saving Scheme 11041-048 N= f SAMPLE n To put the digital block back into the idle state while the rest of the chip is still running and to save power, enact one of the following three events: raise the TX_TRIG signal high, write to the profile index (Register 0x10C, Bits[4:0]), or the power stop expires if the advanced power control feature is used. Figure 52 illustrates the digital block power saving scheme. Data Sheet AD9670 SERIAL PORT INTERFACE (SPI) Table 24. Serial Port Pins Pin SCLK SDIO CSB Function Serial clock. Serial shift clock input. SCLK synchronizes serial interface reads and writes. Serial data input/output. SDIO is a dual-purpose pin that typically serves as an input or an output, depending on the instruction sent and the relative position in the timing frame. Chip select bar (active low). This control gates the read and write cycles. The falling edge of CSB, in conjunction with the rising edge of SCLK, determines the start of the framing sequence. During an instruction phase, a 16-bit instruction is transmitted, followed by one or more data bytes, which is determined by Bit Field W0 and Bit Field W1. An example of the serial timing and its definitions are shown in Figure 54 and Table 25. During normal operation, CSB signals to the device that SPI commands are to be received and processed. When CSB is brought low, the device processes SCLK and SDIO to execute instructions. Normally, CSB remains low until the communication cycle is complete. However, if connected to a slow device, CSB can be brought high between bytes, allowing older microcontrollers enough time to transfer data into shift registers. CSB can be stalled when transferring one, two, or three bytes of data. When W0 and W1 are set to 11, the device enters streaming mode and continues to process data, either reading or writing, until CSB is taken high to end the communication cycle. This allows complete memory transfers without the need for additional instructions. Regardless of the mode, if CSB is taken high in the middle of a byte transfer, the SPI state machine is reset and the device waits for a new instruction. In addition to the operation modes, the SPI port can be configured to operate in different manners. CSB can also be tied low to enable 2-wire mode. When CSB is tied low, SCLK and SDIO are In addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on-chip memory. If the instruction is a readback operation, performing a readback causes the serial data input/output (SDIO) pin to change direction from an input to an output at the appropriate point in the serial frame. Data can be sent in MSB first mode or LSB first mode. MSB first mode is the default at power-up and can be changed by adjusting the configuration register. For more information about this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. HARDWARE INTERFACE The pins described in Table 24 constitute the physical interface between the user programming device and the serial port of the AD9670. The SCLK and CSB pins function as inputs when using the SPI. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. If multiple SDIO pins share a common connection, ensure that proper VOH levels are met. Figure 53 shows the number of SDIO pins that can be connected together and the resulting VOH level, assuming the same load for each AD9670. 1.800 1.795 1.790 1.785 1.780 1.775 1.770 1.765 1.760 1.755 1.750 1.745 1.740 1.735 1.730 1.725 1.720 1.715 0 10 20 30 40 50 60 70 80 90 NUMBER OF SDIO PINS CONNECTED TOGETHER 100 11041-041 Three pins define the serial port interface, or SPI: SCLK, SDIO, and CSB (see Table 24). The SCLK (serial clock) pin synchronizes the read and write data presented to the device. The SDIO (serial data input/output) pin is a dual-purpose pin that allows data to be sent to and read from the internal memory map registers of the device. The CSB (chip select bar) pin is an active low control that enables or disables the read and write cycles. the only pins required for communication. Although the device is synchronized during power-up, caution must be exercised when using this mode to ensure that the serial port remains synchronized with the CSB line. When operating in 2-wire mode, it is recommended that a 1-, 2-, or 3-byte transfer be used exclusively. Without an active CSB line, streaming mode can be entered but not exited. VOH (V) The AD9670 serial port interface allows the user to configure the signal chain for specific functions or operations through a structured register space provided inside the chip. The SPI offers the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided into fields, as documented in the Memory Map section. For detailed operational information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Figure 53. SDIO Pin Loading This interface is flexible enough to be controlled either by serial PROMs or by PIC microcontrollers, which provides the user with an alternative to a full SPI controller for programming the device (see the AN-812 Application Note, Microcontroller-Based Serial Port Interface (SPI®) Boot Circuit). Rev. A | Page 39 of 52 AD9670 Data Sheet tDS tS tHIGH tCLK tH tDH tLOW CSB DON’T CARE SDIO DON’T CARE DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE 11041-042 SCLK Figure 54. Serial Timing Diagram Table 25. Serial Timing Definitions Parameter tDS tDH tCLK tS tH tHIGH tLOW tEN_SDIO Timing (ns min) 12.5 5 40 5 2 16 16 15 tDIS_SDIO 15 Description Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the clock Setup time between CSB and SCLK Hold time between CSB and SCLK Minimum period that SCLK must be in a logic high state Minimum period that SCLK must be in a logic low state Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Figure 54) Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 54) Rev. A | Page 40 of 52 Data Sheet AD9670 MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS Each row in the memory map register table has eight bit locations. The memory map is roughly divided into three sections: the chip configuration register map (Address 0x000 to Address 0x1A1), the profile register map (Address 0xF00 to Address 0xFFF), and the coefficient register map (Address 0x1000 to Address 0x1FFF). Registers that are designated as local registers utilize the device index in Address 0x004 and Address 0x005 to determine to which channels of a device the command is applied. Registers that are designated as chip registers utilize the chip address mode in Address 0x115 to determine if the device is selected to be updated by writing to the chip register. Undefined memory locations must not be written to except when writing the default values suggested in this data sheet. Consider addresses that have values marked as 0 reserved and write a 0 into their registers during power-up. The leftmost column of the memory map indicates the register address, and the default value is shown in the second rightmost column. The Bit 7 (MSB) column is the start of the default hexadecimal value given. For example, Address 0x009, the global clock register, has a default value of 0x01, meaning that Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001 in binary. This setting is the default for the duty cycle stabilizer in the on condition. For more information on the SPI memory map and other functions, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. DEFAULT VALUES After a reset, critical registers are automatically loaded with default values. These values are indicated in Table 27, where an X refers to an undefined feature. LOGIC LEVELS An explanation of various registers follows: “bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit.” Similarly, “bit is cleared” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit.” RECOMMENDED STARTUP SEQUENCE To save system power during programming, the AD9670 powers up in power-down mode. To start up the device and initialize the data interface, the SPI commands listed in Table 26 are recommended. At a minimum, the profile memory for an index of 0 must be written (Registers 0xF00 to Register 0xF07). If additional profiles and coefficient memory are required, these can be written after Profile File Memory 0. Rev. A | Page 41 of 52 AD9670 Data Sheet Table 26. SPI Write Start-Up Sequence Example Register 0x000 0x002 0x0FF 0x004 0x005 0x113 Write Value 0x3C 0x0X (default) 0x01 0x0F 0x3F 0x03 Description Initiates an SPI reset Sets the speed mode to 40 MHz Enables speed mode change (required after Register 0x002 writes) Sets local registers to all channels Sets local registers to all channels Bypasses the demodulator and decimator; bypasses the RF decimator; enables the digital high-pass filter Sets LNA gain= 21.6 dB, sets VGA gain = external, and sets PGA gain = 24 dB Enables continuous run mode; do not power down channels (POWER_STOP LSB) Enables continuous run mode; do not power down channels (POWER_STOP MSB) Powers up all channels, 0 clock cycles after TX_TRIG signal assertion (POWER_START LSB) Bypasses the digital high-pass filter (POWER_START MSB) Decimates by 2 (M = 00001); digital gain = 16 (g = 100) Points to Coefficient Block 00 Demodulation frequency = fSAMPLE/8 0x011 0x06 (default) 0xF00 0xFF 0xF01 0x7F 0xF02 0x00 0xF03 0x80 0xF04 0x0C 0xF05 0x00 0xF06 0x00 0xF07 0x20 Additional profile memory and coefficient memory can be written here 0x10C1 0x00 (default) Sets index profile (required after profile memory writes) 0x014 0x00 Sets the output data format 0x008 0x00 TGC run mode2 0x021 0x05 14 bits, 8 lanes, FCO covers the entire frame 0x199 0x80 Enables automatic clocks per sample calculation 0x19B 0x50 Serial format 0x188 0x01 Enables the start code 0x18B 0x27 Sets the start code MSB 0x18C 0x72 Sets the start code LSB 0x182 0x82 Autoconfigures the PLL 0x10C3 0x20 Sets SPI TX_TRIG and index profile2 0x00F 0x18 Sets the low-pass filter cutoff frequency, and mode 0x02B 0x40 Sets the analog LPF and HPF to defaults, tune filters4 1 Setting the profile index requires an additional SPI write in SPI MSB mode before the chip is run to complete the current profile buffer update. Running the chip from full power-down mode requires 375 μs wake-up time, as listed in Table 3. Soft TX_TRIG switches the demodulator/decimator digital block to a running state. The soft TX_TRIG may not be needed if a hardware TX_TRIG signal is used to run the digital block. 4 Tuning the filters requires 512 ADC clock cycles. 2 3 Rev. A | Page 42 of 52 Data Sheet AD9670 Table 27. Memory Map Registers Addr. Register Name (Hex) Chip Configuration Registers 0x000 CHIP_PORT_CONFIG Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value 0 LSB first 0 = off (default) 1 = on SPI reset 0 = off (default) 1 = on 1 1 SPI reset 0 = off (default) 1 = on LSB first 0 = off (default) 1 = on 0 0x18 0x001 CHIP_ID 0x002 CHIP_GRADE X X 0x0FF DEVICE_UPDATE X X Speed mode, Bits[5:4] (identify device variants of chip ID) 00: Mode I (40 MSPS) (default) 01: Mode II (65 MSPS) 10: Mode III (80 MSPS) 11: Mode III (125 MSPS) X X 0x004 DEVICE_INDEX_2 X X X X 0x005 DEVICE_INDEX_1 X X 0x008 GLOBAL_MODES X Clock channel FCO± 0 = off 1 = on (default) 0 0x009 GLOBAL_CLOCK X LNA input impedance 0 = 6 kΩ (default) 1 = 3 kΩ X Clock channel DCO± 0 = off 1 = on (default) X X X X 0x00A PLL_STATUS PLL lock status 0 = not locked 1 = locked X X X X 0x7C Chip ID, Bits[7:0] (AD9670 = 0xA6) (default) Comments Mirror nibbles so that LSB or MSB first mode is set correctly, regardless of shift mode. An SPI reset reverts all registers (including the LVDS registers), except Register 0x000, to their default values, and Register 0x000, Bits[2:5] are automatically cleared. Default is unique chip ID, different for each device; read-only register. Speed mode is used to differentiate the ADC speed power modes (the user must update Reg. 0x0FF to initiate the mode setting). A write to Reg. 0x0FF (the write value does not matter) resets all default register values (analog and ADC registers only, not LVDS registers and not Reg. 0x000 or Reg. 0x002, Bits[5:4]) if Register 0x002 has been previously written since the last reset/load of defaults. Bits are set to determine which on-chip device receives the next write command. Bits are set to determine which on-chip device receives the next write command. X X X X 0x0X X X X X 0x00 Data Channel H 0 = off 1 = on (default) Data Channel D 0 = off 1 = on (default) Data Channel G 0 = off 1 = on (default) Data Channel C 0 = off 1 = on (default) Data Channel F 0 = off 1 = on (default) Data Channel B 0 = off 1 = on (default) Data Channel E 0 = off 1 = on (default) Data Channel A 0 = off 1 = on (default) 0x0F 0 Internal power-down mode 000 = chip run (TGC mode) 001 = full power-down (default) 010 = standby 011 = reset all LVDS registers 100 = CW mode (TGC power-down) X X DCS 0 = off 1 = on (default) X X X 0x01 Determines the generic modes of chip operation (global). 0x01 Turns the internal DCS on and off (global). 0x00 Monitors the PLL lock status (read only, global). Rev. A | Page 43 of 52 0x3F AD9670 Addr. (Hex) 0x00D Register Name TEST_IO 0x00E GPO 0x00F FLEX_CHANNEL_ INPUT 0x010 0x011 FLEX_OFFSET FLEX_GAIN 0x012 0x013 0x014 Data Sheet Bit 7 (MSB) User test mode 0 = continuous, repeat user patterns (1, 2, 3, 4, 1, 2, 3, 4 …) (default) 1 = single clock cycle user patterns, then zeros (1, 2, 3, 4, 0, 0 …) X Bit 6 X Bit 5 Reset PN long generation 0 = on, PN long running (default) 1 = off, PN long held in reset Bit 4 Reset PN short generation 0 = on, PN short running (default) 1 = off, PN short held in reset X X X Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Output test mode 0000 = off (default) 0001 = midscale short 0010 = +FS short 0011 = −FS short 0100 = checkerboard output 0101 = PN sequence long 0110 = PN sequence short 0111 = one-/zero-word toggle 1000 = user input 1001:1110 = reserved 1111 = ramp output General-purpose digital outputs 0 0 PGA gain 00 = 21 dB 01 = 24 dB (default) 10 = 27 dB 11 = 30 dB BIAS_CURRENT Filter cutoff frequency control 0 0000 = 1.45 × (1/3) × fSAMPLE 0 0001 = 1.25 × (1/3) × fSAMPLE 0 0010 = 1.13 × (1/3) × fSAMPLE 0 0011 = 1.0 × (1/3) × fSAMPLE (default) 0 0100 = 0.9 × (1/3) × fSAMPLE 0 0101 = 0.8 × (1/3) × fSAMPLE 0 0110 = 0.75 × (1/3) × fSAMPLE 0 0111 = reserved 0 1000 = 1.45 × (1/4.5) × fSAMPLE 0 1001 = 1.25 × (1/4.5) × fSAMPLE 0 1010 = 1.13 × (1/4.5) × fSAMPLE 0 1011 = 1.0 × (1/4.5) × fSAMPLE 0 1100 = 0.9 × (1/4.5) × fSAMPLE 0 1101 = 0.8 × (1/4.5) × fSAMPLE 0 1110 = 0.75 × (1/4.5) × fSAMPLE 0 1111 = reserved 1 0000 = 1.45 × (1/6) × fSAMPLE 1 0001 = 1.25 × (1/6) × fSAMPLE 1 0010 = 1.13 × (1/6) × fSAMPLE 1 0011 = 1.0 × (1/6) × fSAMPLE 1 0100 = 0.9 × (1/6) × fSAMPLE 1 0101 = 0.8 × (1/6) × fSAMPLE 1 0110 = 0.75 × (1/6) × fSAMPLE 1 0111 = reserved X X 1 0 Digital VGA gain control 0000 = GAIN± pins enabled (default) 0001 = 0.0 dB (maximum gain, GAIN± pins disabled) 0010 = −3.5 dB 0011 = −7.0 dB … 1110 = −45.5 dB 1111 = −45.5 dB X X X X 1 PGA bias 0 =100% (default) 1 = 60% RESERVED_13 OUTPUT_MODE 0 X 0 X 0 Output data invert 0 = disable (default) 1 = enable 0 X 0 X 0 Output data enable 0 = enable (default) 1= disable BW mode 0 = low (default, 8 MHz to 18 MHz) 1 = high (13.5 MHz to 30 MHz) Rev. A | Page 44 of 52 X 0 X Default Value 0x00 0x00 0x18 Comments When this register is set, the test data is placed on the output pins in place of normal data (local). Values placed on the GPO0 to GPO3 pins (global). Antialiasing filter cutoff (global). 0 LNA gain 00 = 15.6 dB 01 = 17.9 dB 10 = 21.6 dB (default) 0x20 0x06 Reserved. LNA and PGA gain adjustment (global). LNA bias 00 = high 01 = midhigh (default) 10 = midlow 11 = low 0 0 Output data format 00 = offset binary 01 = twos complement (default) 10 = gray code 11 = reserved 0x09 LNA bias current adjustment (global). 0x00 0x01 Reserved. Data output modes (local). Data Sheet Addr. (Hex) 0x015 AD9670 Bit 7 (MSB) LVDS output standard 0 = ANSI (default) 1 = IEEE (low power) Bit 6 1 Bit 5 1 Bit 4 0 Bit 3 LVDS drive strength enable 0 = disable (default) 1 = enable 0x016 FLEX_OUTPUT_ PHASE X X 0 DCO invert 0= disable (default) 1= enable X 0x017 FLEX_OUTPUT_ DELAY DCO delay enable 0 = disable (default) 1 = enable X X 0x018 0x019 FLEX_VREF USER_PATT1_LSB X B7 X B6 X B5 X B4 X B3 0x01A USER_PATT1_MSB B15 B14 B13 B12 B11 B10 B9 B8 0x00 0x01B USER_PATT2_LSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 0x01C USER_PATT2_MSB B15 B14 B13 B12 B11 B10 B9 B8 0x00 0x01D USER_PATT3_LSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 0x01E USER_PATT3_MSB B15 B14 B13 B12 B11 B10 B9 B8 0x00 0x01F USER_PATT4_LSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 0x020 USER_PATT4_MSB B15 B14 B13 B12 B11 B10 B9 B8 0x00 0x021 FLEX_SERIAL_CTRL 0 FCO invert 0 = not inverted (default) 1= inverted Lane low rate 0 = normal (default) 1 = low sample frequency (<32 MHz) 0x022 SERIAL_CH_STAT X X FCO rate with demodulator enabled 0 = FCO per I/Q (default) 1 = FCO per sample (I and Q) X Lane mode 00 = 1 channel/lane (8 lanes) (default) 01 = 2 channels/lane (4 lanes) 10 = 4 channels/lane (2 lanes) 11 = 8 channels/lane (1 lane) X X Bit 1 Bit 0 (LSB) LVDS drive current 000 = 3.72 mA 001 = 3.5 mA (default) 010 = 3.30 mA 011 = 2.96 mA 100 = 2.82 mA 101 = 2.57 mA 110 = 2.27 mA 111 = 2.0 mA (reduced range) X DCO phase adjust with respect to DOUT 00 = +90° (default) 01 = 0° 10 = 0° 11 = −90° DCO clock delay 00000: 100 ps (default) 00001 = 200 ps 00010 = 300 ps … 11101 = 3.0 ns 11110 = 3.1 ns 11111 = 3.2 ns 1 0 0 B2 B1 B0 X Rev. A | Page 45 of 52 Bit 2 Default Value 0x61 Register Name OUTPUT_ADJUST Output word length 00 = 12 bits (default) 01 = 14 bits 10 = 16 bits 11 = reserved X Channel powerdown 1 = on 0 = off (default) Comments Data output levels (global). 0x00 DCO inversion and course phase adjustment (global). 0x00 DCO delay (global). 0x04 0x00 Reserved (global). User Defined Pattern 1, LSB (global). User Defined Pattern 1, MSB (global). User Defined Pattern 2, LSB (global). User Defined Pattern 2, MSB (global). User Defined Pattern 3, LSB (global). User Defined Pattern 3, MSB (global). User Defined Pattern 4, LSB (global). User Defined Pattern 4, MSB (global). LVDS control (global). 0x00 0x00 Used to power down individual channels (local). AD9670 Data Sheet Addr. (Hex) 0x02B Register Name FLEX_FILTER Bit 7 (MSB) X 0x02C LNA_TERM 0x02D Bit 5 X Bit 4 X Bit 3 Bypass analog HPF 0 = off (default) 1 = on Bit 2 X X Bit 6 Enable automatic low-pass tuning 1 = on (self clearing) X X X X X CW_ENABLE_ PHASE X X X CW Doppler channel enable 0 = off (default) 0 = on 0x02E CW_LO_MODE RESET with MLO clock edge 0 = synchronous (default) 1 = asynchronous Synchronous RESET sampling MLO± clock edge 0 = falling (default) 1 = rising RESET signal polarity 0 = active high (default) 1 = active low 0x02F CW_OUTPUT 0 0 0x102 0x103 0x104 0x105 0x106 0x107 RESERVED_102 RESERVED_103 RESERVED_104 RESERVED_105 RESERVED_106 RESERVED_107 Partially enables LVDS during CW 0: LVDS link disabled during CW (default) 1: LVDS link partially enabled during CW. PLL, FCO, and DCO are enabled, while LVDS data drivers are disabled (switching activity can degrade CW performance) CW output dc bias voltage 0 = bypass 1 = enable (default) 0 0 0 0 0 0 0 0 0 0 0 0 0x108 RESERVED_108 0 0 Bit 1 Bit 0 (LSB) Analog high-pass filter cutoff 00 = fLP/12.00 (default) 01 = fLP/9.00 10 = fLP/6.00 11 = fLP/3.00 Default Value 0x00 Comments Filter cutoff (global); (fLP = lowpass filter cutoff frequency). LO-x, LOSW-x connection 00 = RFB1 (default) 01 = (RFB1 || RFB2) 10 = RFB2 11 = ∞ I/Q demodulator phase 0000 = 0° (default) 0001 = 22.5° (not valid for 4LO mode) 0010 = 45° 0011 = 67.5° (not valid for 4LO mode) 0100 = 90° 0101 = 112.5° (not valid for 4LO mode) 0110 = 135° 0111 = 157.5° (not valid for 4LO mode) 1000 = 180° 1001 = 202.5° (not valid for 4LO mode) 1010 = 225° 1011 = 247.5° (not valid for 4LO mode) 1100 = 270° 1101 = 292.5° (not valid for 4LO mode) 1110 = 315° 1111 = 337.5° (not valid for 4LO mode) MLO and LO mode RESET 00X = 4LO, 3rd to 5th odd harmonic buffer rejection (default) enable (in 010 = 8LO, 3rd to 5th odd harmonic all modes rejection except CW 011 = 8LO, 3rd to 13th odd harmonic mode) rejection 0 = power100 = 16LO, 3rd to 5th odd harmonic down rejection (default) 101 = 16LO, 3rd to 13th odd harmonic 1 = enable rejection 11X = reserved 0x00 LNA active termination/input impedance (global). 0x00 Phase of demodulators (local, chip). 0x00 CW mode functions (global). 0 0 0 0 0 0x80 Global. 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 X 0 0 1 0 0 X Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. 0 0 0 0 0 0 0X00 0X00 0x3F 0x00 0x00 Read only 0x00 Rev. A | Page 46 of 52 Reserved. Data Sheet AD9670 Addr. (Hex) 0x109 Register Name VGA_TEST Bit 7 (MSB) X Bit 6 X Bit 5 X 0x10C PROFILE_INDEX X X 0x10D 0x10E 0x10F RESERVED_10D RESERVED_10E DIG_OFFSET_CAL 1 1 0 1 1 0 Manual TX_TRIG 0 = off, use pin (default) 1 = on, autogenerate TX_TRIG (self clears) 1 1 0 1 1 0 0x110 DIG_OFFSET_ CORR1 DIG_OFFSET_ CORR2 D7 D6 D5 D4 0x111 0x112 POWER_MASK_ CONFIG 0x113 DIG_DEMOD_ CONFIG 0x115 CHIP_ADDR_EN Bit 4 VGA/ antialiasing filter test mode enable 0 = off (default) 1 = on Bit 3 X Bit 2 Bit 1 Bit 0 (LSB) VGA/ antialiasing filter output test mode 000 = Channel A (default) 001 = Channel B 010 = Channel C 011 = Channel D 100 = Channel E 101 = Channel F 110 = Channel G 111 = Channel H Profile Index[4:0] 1 1 Digital offset calibration status 0 = not complete (default) 1= complete D3 1 1 D2 1 1 1 1 Digital offset calibration 000 = disable correction, reset correction value (default) 001 = average 210 samples 010 = average 211 samples … 111 = average 216 samples D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 Digital offset calibration (read back if auto calibration is enabled with Register 0x10F; otherwise, force correction value Offset correction = [D15:D0] × AFULL SCALE/216 0111 1111 1111 1111 (215 − 1) = +1/2 × AFULL SCALE − 1/216 × AFULL SCALE 0111 1111 1111 1110 (215 − 2) = +1/2 × AFULL SCALE − 2/216 × AFULL SCALE … 0000 0000 0000 0001 (+1) = 1/216 × AFULL SCALE 0000 0000 0000 0000 = no correction (default) 1111 1111 1111 1111 (−1) = −1/216 × AFULL SCALE … 1000 0000 0000 0000 (−215) = −1/2 full scale X X X Power up set-up time (POWER_SETUP) 0 0000 = 0 0 0001 = 1 × 40/fSAMPLE 0 0010 = 2 × 40/fSAMPLE (default) 0 0011 = 3 × 40/fSAMPLE … 1 1111 = 31 × 40/fSAMPLE X X Digital Decimator Decimator and filter Baseband Demodhigh-pass gain scale enable decimator ulator filter 0 = no 00 = RF 2× decimator 0 = enable 0 = enable 0 = enable gain bypassed (default) (default) (default) (default) (default) 01 = RF 2× decimator 1 = bypass 1 = bypass 1 = bypass 1 = 4× enabled and low band gain (shift filter decimator 1X = RF 2× decimator output by enabled and high band 2) filter X X Chip Chip address qualifier address 0 0000 (default) mode (If read, returns the state of ADDR0 to ADDR4 pins) 0 = disable (default) 1 = enable Rev. A | Page 47 of 52 Default Value 0x00 Comments VGA/ antialiasing filter test mode enables antialiasing filter output to the GPO2 and GPO3 pins (global). 0x00 Index for profile memory selects active profile (global). 0xFF 0xFF Reserved. Reserved. Controls digital offset calibration enable and the number of samples used (global). 0x00 Offset correction LSB (local, chip). Offset correction MSB (local, chip). 0x00 0x02 Power setup time is used to set the power-up time (global). 0x00 Enable stages of the digital processing (global). 0x00 Chip address mode enables the addressing of devices if the value of the chip address qualifier equals the state on the ADDR0 to ADDR4 pins (global). AD9670 Addr. (Hex) 0x116 Data Sheet Register Name ANALOG_TEST_ TONE Bit 7 (MSB) X Bit 6 X Bit 5 X 0x117 DIG_SINE_TEST_ FREQ X X X 0x118 DIG_SINE_TEST_ AMP X X X 0x119 DIG_SINE_TEST_ OFFSET 0x11A TEST_MODE_ CH_ENABLE 0x11B TEST_MODE_ CONFIG 0x11C 0x11D 0x11E 0x11F 0x120 RESERVED_11C RESERVED_11D RESERVED_11E RESERVED_11F CW_TEST_TONE 0 0 0 0 0 0x180 0x181 0x182 RESERVED_180 RESERVED_181 PLL_STARTUP 0x183 0x184 0x186 RESERVED_183 RESERVED_184 RESERVED_186 1 0 PLL auto configure 0 = disable (default) 1 = enable 0 0 1 Channel H enable 0 = off (default) 1 = on X Bit 4 X Bit 3 Bit 2 Analog test signal amplitude (see Table 17 to Table 19) Bit 1 Bit 0 (LSB) Analog test signal frequency 00 = fSAMPLE/4 (default) 01 = fSAMPLE/8 10 = fSAMPLE/16 11 = fSAMPLE/32 Digital test tone frequency 0 0000 = 1 × fSAMPLE/64 0 0001 = 2 × fSAMPLE/64 … 1 1111 = 32 × fSAMPLE/64 Digital test tone amplitude 0000 = AFULL SCALE (default) 0001 = AFULL SCALE/2 0010 = AFULL SCALE/22 … 1111 = AFULL SCALE/215 Offset exponent (b) 000 = 0 (default) 001 = 1 … 111 = 7 Default Value 0x00 Comments Analog test tone amplitude and frequency (global). 0x00 Digital sine test tone frequency (global). 0x00 Digital sine test tone amplitude (global). Offset multiplier (a) 0 1111 = +15 0 1110 =+14 … 0 0000 = 0 (default) 1 1111 = −1 … 1 0000 = −16 Offset = AFULL-SCALE × a × 2 − (13 − b) Offset range is ~0.5 dB Maximum positive offset = 15 × 2 − (13 − 7) = +0.25 × AFULL SCALE Maximum negative offset = –16 × 2 − (13 − 7) ≈ –0.25 × AFULL SCALE Channel G Channel F Channel E Channel D Channel C Channel B Channel A enable enable enable enable enable enable enable 0 = off 0 = off 0 = off 0 = off 0 = off 0 = off 0 = off (default) (default) (default) (default) (default) (default) (default) 1 = on 1 = on 1 = on 1 = on 1 = on 1 = on 1 = on X X X X Test mode selection 000 = disable test modes (default) 001 = enable digital sine test mode 010 = enable decimator filter test (output of decimator is the sequence of filter coefficients) 011 = enable channel ID test mode 16-bit data = digital ramp (7 bits) + I/Q bit + Channel ID (3 bits) + Chip Address (5 bits) 100 = enable analog test tone 101 = reserved 110 = reserved 111 = reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CW I/Q LNA offset LNA offset cancellation CW analog test tone output canceltransconductance override for Reg. 0x116, swap lation 00 = 0.5 mS (default) Bits[1:0] 0= 0 = enable 01 = 1.0 mS 00 = disable override disable (default) 10 = 1.5 mS (default) (default) 1 = disable 11 = 2.0 mS 01 = set analog test 1= tone frequency to fLO enable 1X = set analog test tone frequency to dc 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0x00 Digital sine test tone offset (global). 0x00 Enable channels for test mode (global). 0x00 Enable digital test modes (global). 0x00 0x00 0x00 0x00 0x00 Reserved. Reserved. Reserved. Reserved. Sets the frequency of the analog test tone to fLO in CW Doppler mode. Enables I/Q output swap. LNA offset cancellation control (global). 0x87 0x00 0x02 Reserved. Reserved. PLL control (global). 0 0 0 0x07 0x00 0xAE Reserved. Reserved. Reserved. 0 0 1 X 0 0 0 0 1 0 0 1 1 Rev. A | Page 48 of 52 1 0 1 1 0 0 Data Sheet AD9670 Addr. (Hex) 0x187 0x188 Register Name RESERVED_187 START_CODE_EN Bit 7 (MSB) 0 0 Bit 6 0 0 Bit 5 1 0 Bit 4 0 0 Bit 3 0 0 Bit 2 0 0 Bit 1 0 0 0x189 0x18A 0x18B RESERVED_189 RESERVED_18A START_CODE_MSB 0 0 B15 0 0 B14 0 0 B13 0 0 B12 0 0 B11 0 0 B10 0x18C START_CODE_LSB B7 B6 B5 B4 B3 B2 0x190 0x191 0x192 0x193 0x194 0x195 0x196 0x197 0x198 RESERVED_190 RESERVED_191 RESERVED_192 RESERVED_193 RESERVED_194 RESERVED_195 RESERVED_196 RESERVED_197 CLOCK_DOUBLING 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 0 1 0 1 0 1 0 0x199 SAMPLE_CLOCK_ COUNTER 0 0 0 0 0x19A DATA_OUTPUT_ INVERT Enable clocks per sample auto calculation 0 = off (default) 1 = on X X X X X 0x19B SERIAL_FORMAT X 0x19C 0x19D 0x19E 0x19F RESERVED_19C RESERVED_19D RESERVED_19E RESERVED_19F 0 0 0 0 Enable FCO for start code sample 0= disable 1= enable (default) 0 0 0 0 Enable FCO for extra sample at end of burst 0 = disable 1 = enable (default) 0 0 0 0 Enable FCO continuously 0 = only during burst 1 = continuous (default) 1 0 1 0 0 0 B9 0x00 0x00 0x27 B1 B0 0x72 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 DCO frequency doubling/divider 1011 = 1/32 1010 = 1/64 1001 = 1/128 1000 = 1/256 0000 = 1 (default) 0001 = 2 0010 = 4 0011 = 8 0100 = 16 0101 = 32 0110 = 64 0111 = 128 1000 = 1/256 1001 = 1/128 1010 = 1/64 1011 = 1/32 1100 = 1/16 1101 = 1/8 1110 = ¼ 1111 = ½ 0 0 0 X X Invert data output 0 = noninverted (default) 1= inverted FCO rotate 0000 = FCO aligned with DOUT 0001 = FCO 1 bit before DOUT 0010 = FCO 2 bits before DOUT … 1101 = FCO 3 bits after DOUT 1110 = FCO 2 bits after DOUT 1111 = FCO 1 bit after DOUT 0 0 0 0 Rev. A | Page 49 of 52 0 0 0 0 Default Value 0x20 0x01 Bit 0 (LSB) 0 Start code identifier 0 = disable 1 = enable (default) 0 0 B8 0 0 0 0 0 0 0 0 0x10 0x00 0x18 0x00 0x1C 0x00 0x18 0x00 0x00 Comments Reserved. Enables start code identifier (global). Reserved. Reserved. Start code MSB (global). Start code LSB (global). Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. DCO frequency control (global). 0x00 Enables automatic clocks per sample calculation (global). 0x00 Inverts DOUT outputs (global). 0x70 FCO controls (global). 0x10 0x00 0x10 0x00 Reserved. Reserved. Reserved. Reserved. AD9670 Addr. (Hex) Register Name 0x1A0 RESERVED_1A0 0x1A1 RESERVED_1A1 Profile Memory Registers 0x1000 Coefficient memory to 0x1FFF Coefficient Memory Registers 0xF00 Profile memory to 0xFFF Data Sheet Bit 7 (MSB) 0 0 Bit 6 0 0 Bit 5 0 0 Bit 4 0 0 Default Value 0x00 0x00 Comments Reserved. Reserved. 32 × 64 bits 0x00 Global. 256 × 112 bits 0x00 Global. Bit 3 0 0 Rev. A | Page 50 of 52 Bit 2 0 0 Bit 1 0 0 Bit 0 (LSB) 0 0 AD9670 Data Sheet MEMORY MAP REGISTER DESCRIPTIONS Profile Index and Manual TX_TRIG (Register 0x10C) For more information on the SPI memory map and other functions, consult the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. The vector profile is selected using the profile index in Register 0x10C, Bits[4:0]. The manual TX_TRIG control in Bit 5 generates a TX_TRIG signal internal to the device. This signal is asynchronous to the ADC sample clock. Therefore, it cannot be used to align the data output, advanced power mode, or NCO reset across multiple devices in the system. The external pin-driven TX_TRIG control is recommended for systems that require synchronization of these features across multiple AD9670 devices. Transfer (Register 0x0FF) All registers except Register 0x002 are updated the moment they are written. Setting Bit 0 of Register 0x0FF high initializes and updates the speed mode (Address 0x002) and resets all other registers to their default values. Bit 0 is self clearing. It is recommended that Register 0x002 and Regoster 0x0FF, Bit 0, be set at the beginning of the setup SPI writes after the device is powered up. This avoids rewriting other registers after Register 0x0FF is set. Rev. A | Page 51 of 52 AD9670 Data Sheet OUTLINE DIMENSIONS A1 BALL CORNER 10.10 10.00 SQ 9.90 A1 BALL CORNER 12 11 10 9 8 7 6 5 4 3 2 1 A B C D 8.80 BSC SQ E F G H 0.80 J K L M TOP VIEW 0.60 REF BOTTOM VIEW DETAIL A *1.40 MAX DETAIL A 0.65 MIN 0.25 MIN 0.50 COPLANARITY 0.45 0.20 0.40 BALL DIAMETER *COMPLIANT WITH JEDEC STANDARDS MO-275-EEAB-1 WITH THE EXCEPTION OF PACKAGE HEIGHT. 01-30-2014-B PKG-003538 SEATING PLANE Figure 55. 144-Ball Chip Scale Package, Ball Grid Array [CSP_BGA] (BC-144-1) Dimensions shown in millimeters ORDERING GUIDE Model1 AD9670BBCZ AD9670EBZ 1 Temperature Range 0°C to +85°C Package Description 144-Ball Chip Scale Package, Ball Grid Array [CSP_BGA] Evaluation Board Z = RoHS Compliant Part. ©2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11041-0-2/16(A) Rev. A | Page 52 of 52 Package Option BC-144-1