ADS8484 SLAS511 – NOVEMBER 2007 18-BIT, 1.25-MSPS, PSEUDO-BIPOLAR, FULLY DIFFERENTIAL INPUT, MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE, REFERENCE • 48-Pin 7x7 QFN Package 1.25-MHz Sample Rate APPLICATIONS ±1.5 LSB Typ, ±2.5 LSB Max INL • Medical Instruments +0.8/-0.6 LSB Typ, +1.5/-1 LSB Max DNL • Optical Networking 18-Bit NMC Ensured Over Temperature • Transducer Interface ±0.5-mV Offset Error • High Accuracy Data Acquisition Systems ±0.05-PPM/°C Offset Error Drift • Magnetometers ±0.1 %FSR Gain Error DESCRIPTION ±0.5-PPM/°C Gain Error Drift 98.5dB SNR, –120db THD, 121dB SFDR The ADS8484 is an 18-bit, 1.25-MSPS A/C converter with an internal 4.096-V reference and a Zero Latency pseudo-bipolar, fully differential input. The device Low Power: 235 mW Typ at 1.25 MSPS includes a 18-bit capacitor-based SAR A/D converter Pseudo-Bipolar Fully Differential Input Range: with inherent sample and hold. The ADS8484 offers a Vref to –Vref full 18-bit interface, a 16-bit option where data is read using two read cycles, or an 8-bit bus option using Onboard Reference with 6 PPM/°C Drift three read cycles. Onboard Reference Buffer The ADS8484 is available in a 48-lead 7x7 QFN High-Speed Parallel Interface package and is characterized over the industrial Wide Digital Supply 2.7 V to 5.25 V –40°C to 85°C temperature range. 8-/16-/18-Bit Bus Transfer HIGH SPEED SAR CONVERTER FAMILY FEATURES 1 • • • • • • • • • • • • • • • • • TYPE/SPEED 500 kHz ~600 kHz ADS8383 ADS8381 750 kHz 1 MHz 1.25 MHz 2 MHz 3 MHz 4MHz ADS8481 18-Bit Pseudo-Diff ADS8380 (s) 18-Bit Pseudo-Bipolar, Fully Diff ADS8382 (s) ADS8327 ADS8370 (s) ADS8328 ADS8472 (s) ADS8371 ADS8482 ADS8484 ADS8471 ADS8401 ADS8411 ADS8405 ADS8410 (s) 16-Bit Pseudo-Diff ADS8472 ADS8402 ADS8412 ADS8406 ADS8413 (s) ADS8422 16-Bit Pseudo-Bipolar, Fully Diff 14-Bit Pseudo-Diff ADS7890 (s) 12-Bit Pseudo-Diff ADS7891 ADS7886 SAR +IN −IN + _ CDAC ADS7881 Output Latches and 3-State Drivers BYTE 16-/8-Bit Parallel DA TA Output Bus BUS 18/16 Comparator REFIN REFOUT 4.096-V Internal Reference Clock Conversion and Control Logic CONVST BUSY CS RD 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated ADS8484 www.ti.com SLAS511 – NOVEMBER 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) MODEL MAXIMUM INTEGRAL LINEARITY (LSB) MAXIMUM DIFFERENTIAL LINEARITY (LSB) NO MISSING CODES RESOLUTION (BIT) PACKAGE TYPE PACKAGE DESIGNATOR TEMPERATURE RANGE ADS8484I ±4 –1 to +2 18 7x7 48 Pin QFN RGZ -40°C to 85°C ADS8484IB (1) ±2.5 –1 to +1.5 18 7x7 48 Pin QFN RGZ ORDERING INFORMATION TRANSPORT MEDIA QTY. ADS8484IRGZT Tape and reel 250 ADS8484IRGZR Tape and reel 1000 ADS8484IBRGZT Tape and reel 250 ADS8484IBRGZR Tape and reel 1000 -40°C to 85°C For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VALUE UNIT +IN to AGND –0.4 to +VA + 0.1 V –IN to AGND –0.4 to +VA + 0.1 V +VA to AGND –0.3 to 7 V +VBD to BDGND –0.3 to 7 V –0.3 to 2.55 V Digital input voltage to BDGND –0.3 to +VBD + 0.3 V Digital output voltage to BDGND –0.3 to +VBD + 0.3 V Voltage +VA to +VBD TA Operating free-air temperature range –40 to 85 °C Tstg Storage temperature range –65 to 150 °C 150 °C Junction temperature (TJ max) QFN package Lead temperature, soldering (1) 2 Power dissipation (TJMax – TA)/θJA θJA thermal impedance 22 °C/W Vapor phase (60 sec) 215 °C Infrared (15 sec) 220 °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8484 ADS8484 www.ti.com SLAS511 – NOVEMBER 2007 SPECIFICATIONS TA = –40°C to 85°C, +VA = 5 V, +VBD = 3 V or 5 V, Vref = 4.096 V, fSAMPLE = 1.25 MSPS (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT Full-scale input voltage (1) Absolute input voltage +IN – (–IN) –Vref Vref +IN –0.2 Vref + 0.2 –IN –0.2 Vref + 0.2 (Vref)/2 – 0.2 (Vref)/2 (Vref)/2 + 0.2 Common-mode input range Input capacitance Input leakage current V V V 65 pF 1 nA 18 Bits SYSTEM PERFORMANCE Resolution No missing codes (2) INL Integral linearity DNL Differential linearity Offset error (4) Offset error temperature drift Gain error (4) EG (5) Gain error temperature drift CMRR ADS8484I 18 ADS8484IB 18 ADS8484I Bits –4 ±1.5 –2.5 ±1.5 ADS8484I –1 –0.6/0.8 2 ADS8484IB –1 –0.6/0.8 1.5 ADS8484IB ADS8484I ADS8484IB 4 LSB (3) 2.5 (18 bit) –2 ±1 2 –0.5 ±0.1 0.5 ADS8484I ±0.05 ADS8484IB ±0.05 LSB (18 bit) mV ppm/°C ADS8484I Vref = 4.096 V –0.1 ±0.035 0.1 %FS ADS8484IB Vref = 4.096 V –0.1 ±0.035 0.1 %FS ADS8484I ±0.5 ADS8484IB ±0.5 Common-mode rejection ratio At dc (±0.2 V around Vref/2) 60 +IN – (–IN) = 1 Vpp at 1.25 MHz 55 Noise Power supply rejection ratio At 1FFFFh output code ppm/°C dB 30 µV RMS 60 dB SAMPLING DYNAMICS Conversion time 575 Acquisition time 175 Throughput rate (1) (2) (3) (4) (5) 610 ns 1.25 MHz 200 ns Aperture delay 4 ns Aperture jitter 5 ps Step response 150 ns Over voltage recovery 150 ns Ideal input span, does not include gain or offset error. This is endpoint INL, not best fit. LSB means least significant bit Measured relative to an ideal full-scale input [+IN – (–IN)] of 8.192 V This specification does not include the internal reference voltage error and drift. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8484 3 ADS8484 www.ti.com SLAS511 – NOVEMBER 2007 SPECIFICATIONS (Continued) TA = –40°C to 85°C, +VA = 5 V, +VBD = 3 V or 5 V, Vref = 4.096 V, fSAMPLE = 1.25 MSPS (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DYNAMIC CHARACTERISTICS ADS8484I ADS8484IB THD Total harmonic distortion ADS8484I (1) ADS8484IB ADS8484I ADS8484IB ADS8484I ADS8484IB SNR Signal-to-noise ratio ADS8484I (1) ADS8484IB ADS8484I ADS8484IB ADS8484I ADS8484IB SINAD Signal-to-noise + distortion ADS8484I (1) ADS8484IB ADS8484I ADS8484IB ADS8484I ADS8484IB SFDR Spurious free dynamic range (1) ADS8484I ADS8484IB ADS8484I ADS8484IB 4 –120 –105 VIN = 8 Vpp at 20 kHz –110 VIN = 8 Vpp at 2 kHz –103 96 97 97 98.5 96 VIN = 8 Vpp at 20 kHz 98 VIN = 8 Vpp at 20 kHz VIN = 8 Vpp at 100 kHz VIN = 8 Vpp at 2 kHz VIN = 8 Vpp at 20 kHz VIN = 8 Vpp at 100 kHz dB 95 VIN = 8 Vpp at 100 kHz VIN = 8 Vpp at 2 kHz dB –100 VIN = 8 Vpp at 100 kHz –3dB Small signal bandwidth (1) –115 VIN = 8 Vpp at 2 kHz 97 96 96 97 98.5 95 97 dB 93 95 117 121 107 113 dB 102 105 15 MHz Calculated on the first nine harmonics of the input frequency. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8484 ADS8484 www.ti.com SLAS511 – NOVEMBER 2007 SPECIFICATIONS (Continued) TA = –40°C to 85°C, +VA = 5 V, +VBD = 3 V or 5 V, Vref = 4.096 V, fSAMPLE = 1.25 MSPS (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 3.0 4.096 +VA – 0.8 UNIT VOLTAGE REFERENCE INPUT Vref Reference voltage at REFIN Reference resistance (1) 500 Reference current drain fs = 1.25 MHz V kΩ 1 mA 120 ms INTERNAL REFERENCE OUTPUT Vref Internal reference start-up time From 95% (+VA), with 1-µF storage capacitor Reference voltage range IO = 0 Source current Static load Line regulation +VA = 4.75 V ~ 5.25 V 60 µV Drift IO = 0 ±6 PPM/°C 4.081 4.096 4.111 V 10 µA DIGITAL INPUT/OUTPUT Logic family – CMOS VIH High-level input voltage IIH = 5 µA +VBD – 1 +VBD + 0.3 VIL Low-level input voltage IIL = 5 µA –0.3 0.8 VOH High-level output voltage IOH = 2 TTL loads VOL Low-level output voltage IOL = 2 TTL loads +VBD – 0.6 V 0.4 Data format – Two's Complement POWER SUPPLY REQUIREMENTS Power supply voltage +VBD +VA 2.7 3.3 5.25 4.75 5 5.25 V V Supply current (2) fs = 1.25 MHz 47 52 mA Power dissipation (2) fs = 1.25 MHz 235 260 mW 85 °C TEMPERATURE RANGE Operating free-air (1) (2) –40 Can vary ±20% This includes only +VA current. +VBD current is typical 1 mA with 5-pF load capacitance on all output pins. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8484 5 ADS8484 www.ti.com SLAS511 – NOVEMBER 2007 TIMING CHARACTERISTICS All specifications typical at –40°C to 85°C, +VA =+VBD = 5 V (1) (2) (3) PARAMETER MIN TYP MAX UNIT 610 ns t(CONV) Conversion time t(ACQ) Acquisition time t(HOLD) Sample capacitor hold time 15 ns tpd1 CONVST low to BUSY high 40 ns tpd2 Propagation delay time, end of conversion to BUSY low 15 ns tpd3 Propagation delay time, start of convert state to rising edge of BUSY 25 ns tw1 Pulse duration, CONVST low 40 ns tsu1 Setup time, CS low to CONVST low 20 ns tw2 Pulse duration, CONVST high 20 175 CONVST falling edge jitter ns ns 10 t(ACQ)min ps tw3 Pulse duration, BUSY signal low tw4 Pulse duration, BUSY signal high th1 Hold time, first data bus transition (RD low, or CS low for read cycle, or BYTE or BUS18/16 input changes) after CONVST low td1 Delay time, CS low to RD low tsu2 Setup time, RD high to CS high tw5 Pulse duration, RD low ten Enable time, RD low (or CS low for read cycle) to data valid td2 Delay time, data hold from RD high td3 Delay time, BUS18/16 or BYTE rising edge or falling edge to data valid 10 tw6 Pulse duration, RD high 20 ns tw7 Pulse duration, CS high 20 ns th2 Hold time, last RD (or CS for read cycle ) rising edge to CONVST falling edge 50 ns tpd4 Propagation delay time, BUSY falling edge to next RD (or CS for read cycle) falling edge 0 ns td4 Delay time, BYTE edge to BUS18/16 edge skew 0 ns tsu3 Setup time, BYTE or BUS18/16 transition to RD falling edge 10 ns th3 Hold time, BYTE or BUS18/16 transition to RD falling edge 10 tdis Disable time, RD high (CS high for read cycle) to 3-stated data bus td5 Delay time, BUSY low to MSB data valid delay td6 Delay time, CS rising edge to BUSY falling edge 50 ns td7 Delay time, BUSY falling edge to CS rising edge 50 ns tsu5 BYTE transition setup time, from BYTE transition to next BYTE transition, or BUS18/16 transition setup time, from BUS18/16 to next BUS18/16. 50 ns 6 ns 40 ns 0 ns 0 ns 50 ns 20 5 tsu(ABORT) Setup time from the falling edge of CONVST (used to start the valid conversion) to the next falling edge of CONVST (when CS = 0 and CONVST are used to abort) or to the next falling edge of CS (when CS is used to abort). (1) (2) (3) ns 610 60 ns ns 20 ns ns 20 ns 0 ns 480 ns All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2. See timing diagrams. All timing are measured with 20-pF equivalent loads on all data bits and BUSY pins. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8484 ADS8484 www.ti.com SLAS511 – NOVEMBER 2007 TIMING CHARACTERISTICS All specifications typical at –40°C to 85°C, +VA = 5 V +VBD = 3 V (1) (2) (3) PARAMETER MIN TYP MAX UNIT 610 ns t(CONV) Conversion time t(ACQ) Acquisition time t(HOLD) Sample capacitor hold time 15 ns tpd1 CONVST low to BUSY high 40 ns tpd2 Propagation delay time, end of conversion to BUSY low 15 ns tpd3 Propagation delay time, start of convert state to rising edge of BUSY 25 ns tw1 Pulse duration, CONVST low 40 ns tsu1 Setup time, CS low to CONVST low 20 ns tw2 Pulse duration, CONVST high 20 175 CONVST falling edge jitter ns ns 10 t(ACQ)min ps tw3 Pulse duration, BUSY signal low tw4 Pulse duration, BUSY signal high th1 Hold time, first data bus transition (RD low, or CS low for read cycle, or BYTE or BUS18/16 input changes) after CONVST low td1 Delay time, CS low to RD low tsu2 Setup time, RD high to CS high tw5 Pulse duration, RD low ten Enable time, RD low (or CS low for read cycle) to data valid td2 Delay time, data hold from RD high td3 Delay time, BUS18/16 or BYTE rising edge or falling edge to data valid 10 tw6 Pulse duration, RD high 20 ns tw7 Pulse duration, CS high 20 ns th2 Hold time, last RD (or CS for read cycle ) rising edge to CONVST falling edge 50 ns tpd4 Propagation delay time, BUSY falling edge to next RD (or CS for read cycle) falling edge 0 ns td4 Delay time, BYTE edge to BUS18/16 edge skew 0 ns tsu3 Setup time, BYTE or BUS18/16 transition to RD falling edge 10 ns th3 Hold time, BYTE or BUS18/16 transition to RD falling edge 10 tdis Disable time, RD high (CS high for read cycle) to 3-stated data bus td5 Delay time, BUSY low to MSB data valid delay td6 Delay time, CS rising edge to BUSY falling edge 50 ns td7 Delay time, BUSY falling edge to CS rising edge 50 ns tsu5 BYTE transition setup time, from BYTE transition to next BYTE transition, or BUS18/16 transition setup time, from BUS18/16 to next BUS18/16. 50 ns ns 40 ns 0 ns 0 ns 50 ns 30 5 tsu(ABORT) Setup time from the falling edge of CONVST (used to start the valid conversion) to the next falling edge of CONVST (when CS = 0 and CONVST are used to abort) or to the next falling edge of CS (when CS is used to abort). (1) (2) (3) ns 610 70 ns ns 30 ns ns 30 ns 0 ns 480 ns All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2. See timing diagrams. All timing are measured with 20-pF equivalent loads on all data bits and BUSY pins. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8484 7 ADS8484 www.ti.com SLAS511 – NOVEMBER 2007 PIN ASSIGNMENTS BUSY DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 BDGND RGZ PACKAGE (TOP VIEW) +VBD DB10 DB11 DB12 DB13 DB14 DB15 DB16 DB17 AGND AGND +VA AGND AGND AGND +VA +VA −IN +IN AGND NC +VA REFIN 48 47 46 45 44 43 42 41 40 39 38 37 36 1 35 2 3 34 4 33 32 5 31 6 30 7 29 8 9 28 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 REFOUT +VBD BUS18/16 BYTE CONVST RD CS +VA AGND AGND +VA REFM REFM NC − No internal connection NOTE: The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. TERMINAL FUNCTIONS NAME NO I/O AGND 8, 9, 17, 20, 23, 24, 26, 27 DESCRIPTION – Analog ground BDGND 37 – Digital ground for bus interface digital supply BUSY 48 O Status output. High when a conversion is in progress. BUS18/16 2 I Bus size select input. Used for selecting 18-bit or 16-bit wide bus transfer. 0: Data bits output on the 18-bit data bus pins DB[17:0]. 1: Last two data bits D[1:0] from 18-bit wide bus output on: a) the low byte pins DB[9:2] if BYTE = 0 b) the high byte pins DB[17:10] if BYTE = 1 BYTE 3 I Byte select input. Used for 8-bit bus reading. 0: No fold back 1: Low byte D[9:2] of the 16 most significant bits is folded back to high byte of the 16 most significant pins DB[17:10]. CONVST 4 I Convert start. The falling edge of this input ends the acquisition period and starts the hold period. CS 6 I Chip select. The falling edge of this input starts the acquisition period. 8-BIT BUS Data Bus 16-BIT BUS 18-BIT BUS BYTE = 0 BYTE = 1 BYTE = 1 BYTE = 0 BYTE = 0 BYTE = 0 BUS18/16 = 0 BUS18/16 = 0 BUS18/16 = 1 BUS18/16 = 0 BUS18/16 = 1 BUS18/16 = 0 DB17 28 O D17 (MSB) D9 All ones D17 (MSB) All ones D17 (MSB) DB16 29 O D16 D8 All ones D16 All ones D16 DB15 30 O D15 D7 All ones D15 All ones D15 DB14 31 O D14 D6 All ones D14 All ones D14 DB13 32 O D13 D5 All ones D13 All ones D13 DB12 33 O D12 D4 All ones D12 All ones D12 DB11 34 O D11 D3 D1 D11 All ones D11 DB10 35 O D10 D2 D0 (LSB) D10 All ones D10 8 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8484 ADS8484 www.ti.com SLAS511 – NOVEMBER 2007 TERMINAL FUNCTIONS (continued) NAME NO I/O DB9 38 O D9 All ones All ones D9 All ones D9 DB8 39 O D8 All ones All ones D8 All ones D8 DB7 40 O D7 All ones All ones D7 All ones D7 DB6 41 O D6 All ones All ones D6 All ones D6 DB5 42 O D5 All ones All ones D5 All ones D5 DB4 43 O D4 All ones All ones D4 All ones D4 DB3 44 O D3 All ones All ones D3 D1 D3 DB2 45 O D2 All ones All ones D2 D0 (LSB) D2 DB1 46 O D1 All ones All ones D1 All ones D1 DB0 47 O D0 (LSB) All ones All ones D0 (LSB) All ones D0 (LSB) –IN 19 I Inverting input channel +IN 18 I Noninverting input channel NC 15 REFIN 13 I Reference input REFOUT 14 O Reference output. Add 1-µF capacitor between the REFOUT pin and REFM pin when internal reference is used. 11, 12 I Reference ground RD 5 I Synchronization pulse for the parallel output. When CS is low, this serves as output enable and puts the previous conversion results on the bus. +VA 7, 10, 16, 21, 22, 25 – Analog power supplies, 5-V DC 1, 36 – Digital power supply for bus REFM +VBD DESCRIPTION No connection TYPICAL CHARACTERISTICS INTERNAL REFERENCE VOLTAGE vs FREE-AIR TEMPERATURE DC HISTOGRAM (8192 Conversion Outputs) 4.098 3615 +VA = 5 V, 3500 +VBD = 5 V, TA = 25°C, 3000 f = 1.25 MSPS, Vref = 4.096 V, 2383 2500 Input = Midscale 1474 1500 1000 481 0 0 6 -4 -3 TA = 25°C 4.09719 196 -2 -1 0 1 2 Output Code Reference Voltage - V 2000 500 4.0972 +VA = 5 V, +VBD = 5 V 4.0975 Reference Voltage - V Frequency 4000 INTERNAL REFERENCE VOLTAGE vs SUPPLY VOLTAGE 4.097 4.0965 4.096 4.0955 36 1 0 3 4 5 Figure 1. 4.095 -40 4.09718 4.09717 4.09716 4.09715 4.09714 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C Figure 2. 80 4.09713 4.75 4.85 4.95 5.05 5.15 Supply Voltage - V Figure 3. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8484 5.25 9 ADS8484 www.ti.com SLAS511 – NOVEMBER 2007 TYPICAL CHARACTERISTICS (continued) SUPPLY CURRENT vs FREE-AIR TEM PERATURE SUPPLY CURRENT vs SUPPLY VOLTAGE 48 47.6 +VA = 5 V, +VBD = 5 V, fi = 1.25 MSPS, Vref = 4.096 V 47 TA = 25°C, fi = 1.25 MSPS, Vref = 4.096 V 47.2 47.2 46.8 46.8 46.4 46 45.6 45.2 44.8 46.4 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C 44 4.75 80 45 44 43 42 41 40 44.4 46 -40 TA = 25°C, +VA = 5 V, +VBD = 5 V, Vref = 4.096 V 46 Supply Current - mA Supply Current - mA 47.6 Supply Current - mA SUPPLY CURRENT vs SAMPLE RATE 4.85 4.95 5.05 5.15 39 250 5.25 500 750 1000 Sample Rate - KSPS Supply Voltage - V Figure 4. Figure 5. Figure 6. DIFFERENTIAL NONLINEARITY vs FREE-AIR TEMPERATURE INTEGRAL NONLINEARITY vs FREE-AIR TEMPERATURE DIFFERENTIAL NONLINEARITY vs SUPPLY VOLTAGE 1.5 +VA = 5 V, +VBD = 5 V, fi = 1.25 MSPS, Vref = 4.096 V 1 1.5 2.5 TA = 25°C, fi = 1.25 MSPS, Vref = 4.096 V 2 Max 1.5 Max 1 Max 0.5 0 0.5 0 -0.5 -1 Min Min -0.5 DNL - LSBs INL - LSBs 1 DNL - LSBs 1250 +VA = 5 V, +VBD = 5 V, fi = 1.25 MSPS, Vref = 4.096 V 0.5 0 Min -0.5 -1.5 -2 -1 -40 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C -2.5 -40 80 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C INTEGRAL NONLINEARITY vs SUPPLY VOLTAGE DIFFERENTIAL NONLINEARITY vs REFERENCE VOLTAGE INTEGRAL NONLINEARITY vs REFERENCE VOLTAGE 1.5 2.5 VDD = 5 V, TA = 25°C, fi = 1.25 MSPS 1 1.5 1.5 Max -0.5 0.5 0 -1 Min 0.5 0 -0.5 -1 Min -1.5 Max 1 INL - LSBs DNL - LSBs TA = 25°C, fi = 1.25 MSPS, Vref = 4.096 V VDD = 5 V, TA = 25°C, fi = 1.25 MSPS 2 1 INL - LSBs 5.25 Figure 9. Max -0.5 -1.5 -1 -2.5 -2 Min -2 -2.5 4.75 4.85 4.95 5.05 5.15 Supply Voltage - V 5.25 Figure 10. 10 4.95 5.05 5.15 Supply Voltage - V Figure 8. 2 0 4.85 Figure 7. 2.5 0.5 -1 4.75 80 3 3.2 3.4 3.6 3.8 Reference Voltage - V 4 Figure 11. Submit Documentation Feedback 4.2 3 3.2 3.4 3.6 3.8 Reference Voltage - V 4 4.2 Figure 12. Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8484 ADS8484 www.ti.com SLAS511 – NOVEMBER 2007 TYPICAL CHARACTERISTICS (continued) OFFSET ERROR vs FREE-AIR TEMPERATURE OFFSET ERROR vs SUPPLY VOLTAGE 0.04 0.06 0.1 TA = 25°C, fi = 1.25 MSPS, Vref = 4.096 V 0.08 0.02 -0.04 -0.06 0.02 0 -0.02 -0.04 +VA = 5 V, +VBD = 5 V, fi = 1.25 MSPS, Vref = 4.096 V -0.08 -0.1 -40 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C -0.02 -0.04 -0.08 -0.08 -0.1 4.75 80 4.85 4.95 5.05 5.15 Supply Voltage - V -0.1 3 5.25 3.2 3.4 3.6 3.8 Reference Voltage - V 4 Figure 13. Figure 14. Figure 15. GAIN ERROR vs SUPPLY VOLTAGE GAIN ERROR vs FREE-AIR TEMPERATURE GAIN ERROR vs REFERENCE VOLTAGE -0.025 -0.03 -0.04 -0.05 -0.06 -0.07 4.85 4.95 5.05 5.15 Supply Voltage - V 5.25 +VA = 5 V, +VBD = 5 V, fi = 1.25 MSPS, Vref = 4.096 V 0.08 0.06 -0.035 Gain Error - %FS Gain Error - %FS -0.03 4.2 0.1 -0.02 -0.08 4.75 0 -0.06 TA = 25°C, fi = 1.25 MSPS, Vref = 4.096 V -0.02 VDD = 5 V, TA = 25°C, fi = 1.25 MSPS -0.06 -0.01 -0.04 -0.045 -0.05 -0.055 0.02 0 -0.02 -0.04 -0.06 -0.065 -0.08 -0.07 -40 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C -0.1 3 80 VDD = 5 V, TA = 25°C, fi = 1.25 MSPS 0.04 -0.06 3.2 3.4 3.6 3.8 Reference Voltage - V 4 4.2 Figure 16. Figure 17. Figure 18. OFFSET ERROR TEMPERATURE DRIFT DISTRIBUTION (35 Samples) GAIN ERROR TEMPERATURE DRIFT DISTRIBUTION (35 Samples) TOTAL HARMONIC DISTORTION vs REFERENCE VOLTAGE 14 9 9 8 11 8 +VA = 5 V, +VBD = 5 V, fi = 1.25 MSPS, 7 Vref = 4.096 V +VA = 5 V, +VBD = 5 V, fs = 1.25 MSPS, TA = 25°C, fi = 2 kHz -120 7 8 6 4 4 -119 10 Frequency 13 +VA = 5 V, +VBD = 5 V, 12 f = 1.25 MSPS, i Vref = 4.096 V 10 4 6 6 THD - dB Gain Error - %FS 0.02 Offset Error - mV -0.02 0.04 0.04 Offset Error - mV Offset Error - mV 0.06 0 Frequency OFFSET ERROR vs REFERENCE VOLTAGE 5 4 4 -121 3 3 -122 2 2 1 0 0 1 0 0.01 0.03 0.04 0.05 0.07 Offset Drift - ppm/°C 0.08 Figure 19. -123 0.03 0.19 0.35 0.50 0.66 Gain Error Drift - ppm/°C 0.90 Figure 20. 3 3.2 3.6 3.8 3.4 4 Vref - Reference Voltage - V Figure 21. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8484 4.2 11 ADS8484 www.ti.com SLAS511 – NOVEMBER 2007 TYPICAL CHARACTERISTICS (continued) SIGNAL-TO-NOISE + DISTORTION vs REFERENCE VOLTAGE 98 97.5 97 96.5 96 3 3.2 3.4 3.6 3.8 4 Vref - Reference Voltage - V 4.2 99 98.5 98 -115 +VA = 5 V, +VBD = 5 V, fs = 1.25 MSPS, TA = 25°C, fi = 2 kHz 97.5 97 96.5 96 3 3.2 3.4 3.6 3.8 4 -116 -117 +VA = 5 V, +VBD = 5 V, fs = 1.25 MSPS, Vref = 4.096 V, fi = 2 kHz -118 -119 -120 -121 -122 -40 4.2 Vref - Reference Voltage - V -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C 80 Figure 22. Figure 23. Figure 24. SPURIOUS FREE DYNAMIC RANGE vs FREE-AIR TEMPERATURE SIGNAL-TO-NOISE RATIO vs FREE-AIR TEMPERATURE SIGNAL-TO-NOISE + DISTORTION vs FREE-AIR TEMPERATURE 123.5 98.8 98.8 +VA = 5 V, +VBD = 5 V, fs = 1.25 MSPS, Vref = 4.096 V, fi = 2 kHz 123 122.5 122 121.5 121 120.5 120 119.5 119 118.5 -40 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C 98.7 98.6 98.5 98.4 98.3 98.2 98.1 -40 -25 80 Figure 25. +VA = 5 V, +VBD = 5 V, fs = 1.25 MSPS, Vref = 4.096 V, fi = 2 kHz SNR - Signal-to-Noise Ratio - dB SFDR - Spurious Free Dynamic Range - dB SINAD - Signal-to-Noise + Distortion - dB 98.5 +VA = 5 V, +VBD = 5 V, fs = 1.25 MSPS, TA = 25°C, fi = 2 kHz SNR - Signal-to-Noise Ratio - dB SNR - Signal-to-Noise Ratio - dB 99 TOTAL HARMONIC DISTORTION vs FREE-AIR TEMPERATURE THD - Total Harmonic Distortion - dB SIGNAL-TO-NOISE RATIO vs REFERENCE VOLTAGE 98.7 98.6 98.5 98.4 98.3 98.2 98.1 -40 -10 5 20 35 50 65 80 TA - Free-Air Temperature - °C Figure 26. DNL +VA = 5 V, +VBD = 5 V, fs = 1.25 MSPS, Vref = 4.096 V, fi = 2 kHz -25 -10 5 20 35 50 65 80 TA - Free-Air Temperature - °C Figure 27. 1.5 +VA = 5 V, +VBD = 5 V, TA = 25°C, fs = 1.25 MSPS, Vref = 4.096 V DNL - LSBs 1 0.5 0 -0.5 -1 -1.5 -131072 12 -65536 0 Output Code Figure 28. Submit Documentation Feedback 65536 131072 Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8484 ADS8484 www.ti.com SLAS511 – NOVEMBER 2007 TYPICAL CHARACTERISTICS (continued) INL INL - LSBs 2.5 2 1.5 +VA = 5 V, +VBD = 5 V, TA = 25°C, fs = 1.25 MSPS, Vref = 4.096 V 1 0.5 0 -0.5 -1 -1.5 -2 -2.5 -131072 -65536 0 Output Code Figure 29. 65536 131072 FFT Power - dB 0 -20 -40 +VA = 5 V, +VBD = 5 V, TA = 25°C, fs = 1.25 MSPS, fi = 1.9 kHz, Vref = 4.096 V -60 -80 -100 -120 -140 -160 -180 -200 0 100 200 300 f - Frequency - kHz Figure 30. 400 500 600 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8484 13 ADS8484 www.ti.com SLAS511 – NOVEMBER 2007 TYPICAL CHARACTERISTICS (continued) TIMING DIAGRAMS tw2 tw1 CONVST tpd1 tpd2 tw4 tw3 BUSY tsu1 CS tpd3 tw7 td7 td6 CONVERT† t(CONV) t(CONV) t(HOLD) SAMPLING† (When CS Toggle) t(ACQ) tsu(ABORT) tsu(ABORT) BYTE tsu5 th1 BUS 18/16 tsu5 tsu2 tpd4 th2 td1 RD tdis ten DB[17:12] Hi−Z D[17:12] Hi−Z D[9:4] MSB DB[11:10] DB[9:0] †Signal Hi−Z Hi−Z D[11:10] D[3:2] D[1:0] Hi−Z Hi−Z D[9:0] internal to device Figure 31. Timing for Conversion and Acquisition Cycles With CS and RD Toggling 14 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8484 ADS8484 www.ti.com SLAS511 – NOVEMBER 2007 TYPICAL CHARACTERISTICS (continued) tw1 tw2 CONVST tpd1 tpd2 tw4 tw3 BUSY tsu1 tw7 td7 CS tpd3 td6 CONVERT† t(CONV) t(CONV) t(HOLD) SAMPLING† (When CS Toggle) t(ACQ) tsu(ABORT) tsu(ABORT) BYTE tsu5 th1 BUS 18/16 tpd4 th2 RD = 0 ten DB[17:12] DB[11:10] DB[9:0] †Signal ten tdis Previous Hi−Z D[17:12] Hi−Z Hi−Z Previous D[11:10] Previous D [9:0] Hi−Z Hi−Z Hi−Z tdis ten MSB D[17:12] D[11:10] D[9:0] Hi−Z D[9:4] D[3:2] D[1:0] Hi−Z Hi−Z Repeated D[17:12] Repeated D[11:10] Repeated D [9:0] internal to device Figure 32. Timing for Conversion and Acquisition Cycles With CS Toggling, RD Tied to BDGND Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8484 15 ADS8484 www.ti.com SLAS511 – NOVEMBER 2007 TYPICAL CHARACTERISTICS (continued) tw1 tw2 CONVST tpd1 tpd2 tw4 tw3 BUSY CS = 0 CONVERT† t(CONV) t(CONV) t(HOLD) t(ACQ) SAMPLING† (When CS = 0) tsu(ABORT) tsu(ABORT) BYTE tsu5 th1 BUS 18/16 tsu5 tpd4 th2 RD tdis ten MSB DB[17:12] DB[11:10] DB[9:0] †Signal Hi−Z Hi−Z Hi−Z D[17:12] D[9:4] D[11:10] D[3:2] D[9:0] Hi−Z D[1:0] Hi−Z Hi−Z internal to device Figure 33. Timing for Conversion and Acquisition Cycles With CS Tied to BDGND, RD Toggling 16 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8484 ADS8484 www.ti.com SLAS511 – NOVEMBER 2007 TYPICAL CHARACTERISTICS (continued) tw2 tw1 CONVST tpd1 tw4 tpd2 tw3 BUSY CS = 0 CONVERT† t(CONV) t(CONV) tpd3 tpd3 t(HOLD) t(HOLD) t(ACQ) SAMPLING† (When CS = 0) tsu(ABORT) tsu(ABORT) BYTE tsu5 tsu5 BUS 18/16 tsu5 tsu5 th1 th1 RD = 0 td5 DB[17:12] DB[11:10] D[17:12] Previous LSB DB[9:0] †Signal D[11:10] D[9:4] D[3:2] D[9:0] Next D[17:12] D[1:0] Next D[11:10] Next D[9:0] internal to device Figure 34. Timing for Conversion and Acquisition Cycles With CS and RD Tied to BDGND - Auto Read Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8484 17 ADS8484 www.ti.com SLAS511 – NOVEMBER 2007 TYPICAL CHARACTERISTICS (continued) CS RD BYTE tsu5 BUS 18/16 ten ten DB[17:0] Hi−Z tdis Valid Hi−Z td3 tdis td3 Valid Valid Hi−Z Figure 35. Detailed Timing for Read Cycles 18 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8484 ADS8484 www.ti.com SLAS511 – NOVEMBER 2007 APPLICATION INFORMATION MICROCONTROLLER INTERFACING ADS8484 to 8-Bit Microcontroller Interface Figure 36 shows a parallel interface between the ADS8484 and a typical microcontroller using the 8-bit data bus. The BUSY signal is used as a falling-edge interrupt to the microcontroller. Analog 5 V 0.1 µF AGND 10 µF Ext Ref Input 0.1 µF Micro Controller GPIO GPIO GPIO GPIO RD AD[7:0] −IN +IN +VA REFIN REFM AGND Analog Input Digital 3 V Data Bus D[17:0] CS ADS8484 BYTE BDGND BUS18/16 CONVST RD +VBD DB[17:10] 0.1 µF BDGND Figure 36. ADS8484 Application Circuitry Analog 5 V 0.1 µF AGND 10 µF 0.1 µF AGND AGND REFM REFIN REFOUT +VA 1 µF ADS8484 Figure 37. ADS8484 Using Internal Reference Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8484 19 ADS8484 www.ti.com SLAS511 – NOVEMBER 2007 PRINCIPLES OF OPERATION The ADS8484 is a high-speed successive approximation register (SAR) analog-to-digital converter (ADC). The architecture is based on charge redistribution which inherently includes a sample/hold function. See Figure 36 for the application circuit for the ADS8484. The conversion clock is generated internally. The conversion time of 610 ns is capable of sustaining a 1.25-MHz throughput. The analog input is provided to two input pins: +IN and –IN. When a conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are disconnected from any internal function. REFERENCE The ADS8484 can operate with an external reference with a range from 3.0 V to 4.2 V. The reference voltage on the input pin 13 (REFIN) of the converter is internally buffered. A clean, low noise, well-decoupled reference voltage on this pin is required to ensure good performance of the converter. A low noise band-gap reference like the REF3240 can be used to drive this pin. A 0.1-µF decoupling capacitor is required between REFIN and REFM pins (pin 13 and pin 12) of the converter. This capacitor should be placed as close as possible to the pins of the device. Designers should strive to minimize the routing length of the traces that connect the terminals of the capacitor to the pins of the converter. An RC network can also be used to filter the reference voltage. A 100-Ω series resistor and a 0.1-µF capacitor, which can also serve as the decoupling capacitor can be used to filter the reference voltage. REFM 0.1 mF 100 W ADS8484 REFIN REF3240 Figure 38. ADS8484 Using External Reference The ADS8484 also has limited low pass filtering capability built into the converter. The equivalent circuitry on the REFIN input ia as shown in Figure 39. 10 kW REFIN + _ 300 pF REFM To CDAC 830 pF To CDAC Figure 39. Simplified Reference Input Circuit The REFM input of the ADS8484 should always be shorted to AGND. A 4.096-V internal reference is included. When internal reference is used, pin 14 (REFOUT) is connected to pin 13 (REFIN) with an 0.1-µF decoupling capacitor and 1-µF storage capacitor between pin 14 (REFOUT) and pins 11 and 12 (REFM) (see Figure 37). The internal reference of the converter is double buffered. If an external reference is used, the second buffer provides isolation between the external reference and the CDAC. This buffer is also used to recharge all of the capacitors of the CDAC during conversion. Pin 14 (REFOUT) can be left unconnected (floating) if external reference is used. 20 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8484 ADS8484 www.ti.com SLAS511 – NOVEMBER 2007 ANALOG INPUT When the converter enters the hold mode, the voltage difference between the +IN and –IN inputs is captured on the internal capacitor array. Both +IN and –IN input has a range of –0.2 V to Vref + 0.2 V. The input span [+IN – (–IN)] is limited to –Vref to Vref. The input current on the analog inputs depends upon a number of factors: sample rate, input voltage, and source impedance. Essentially, the current into the ADS8484 charges the internal capacitor array during the sample period. After this capacitance has been fully charged, there is no further input current. The source of the analog input must be able to charge the input capacitance (65 pF) to an 18-bit settling level within the acquisition time (175 ns) of the device. When the converter goes into the hold mode, the input impedance is greater than 1 GΩ. Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, the +IN and –IN inputs and the span [+IN – (–IN)] must be within the limits specified. Outside of these ranges, the converter's linearity may not meet specifications. To minimize noise, low bandwidth input signals with low-pass filters are used. Care must be taken to ensure that the output impedance of the sources driving the +IN and –IN inputs are matched. If this is not observed, the two inputs could have different setting times. This may result in offset error, gain error, and linearity error which varies with temperature and input voltage. The analog input to the converter needs to be driven with a low noise, high-speed op-amp like the THS4031. An RC filter is recommended at the input pins to low-pass filter the noise from the source. The input to the converter is a uni-polar input voltage in the range 0 to Vref. The THS4031 can be used in the source follower configuration to drive the converter. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8484 21 ADS8484 www.ti.com SLAS511 – NOVEMBER 2007 +12 V 1 mF R +VIN 5W +0V to +4V C THS4031 1 mF (+)IN 1 mF -12 V 75 W 2200 pF 300 W +12 V 1 mF 300 W 5W THS4031 (-)IN +2.048 V 1 mF 1 mF -12 V Figure 40. Single-Ended Input, Differential Output Configuration In systems, where the input is differential, the THS4031 can be used in the inverting configuration with an additional DC bias applied to its + input so as to keep the input to the ADS8484 within its rated operating voltage range. The DC bias can be derived from the REF3220 or the REF3240 reference voltage ICs. The input configuration shown below is capable of delivering better than 97dB SNR and -103db THD at an input frequency of 100 kHz. In case band-pass filters are used to filter the input, care should be taken to ensure that the signal swing at the input of the band-pass filter is small so as to keep the distortion introduced by the filter minimal. In such cases, the gain of the circuit shown below can be increased to keep the input to the ADS8484 large to keep the SNR of the system high. Note that the gain of the system from the + input to the output of the THS4031 in such a configuration is a function of the gain of the AC signal. A resistor divider can be used to scale the output of the REF3220 or REF3240 to reduce the voltage at the DC input to THS4031 to keep the voltage at the input of the converter within its rated operating range. 22 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8484 ADS8484 www.ti.com SLAS511 – NOVEMBER 2007 +12 V 1 mF +1.024 V ... (Vref/4) 5W 300 W THS4031 (+)IN -2.048 V to +2.048 V 1 mF 1 mF -12V AP Cascade Two System 2200 pF 300 W AP Cascade Two System Pattern Generator Platform fi = 1 kHz SNR: 98.5 dB SINAD: 98.5 dB THD: -117 dB SFDR: 120 dB ENOB(SINAD): 16 +2.048 V to -2.048 V 300 W +12V 1 mF 300 W 5W THS4031 (-)IN +1.024 V ... (Vref/4) 1 mF 1 mF -12 V Figure 41. Differential Input, Differential Output Configuration DIGITAL INTERFACE Timing and Control See the timing diagrams in the specifications section for detailed information on timing signals and their requirements. The ADS8484 uses an internal oscillator generated clock which controls the conversion rate and in turn the throughput of the converter. No external clock input is required. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8484 23 ADS8484 www.ti.com SLAS511 – NOVEMBER 2007 Conversions are initiated by bringing the CONVST pin low for a minimum of 20 ns (after the 20 ns minimum requirement has been met, the CONVST pin can be brought high), while CS is low. The ADS8484 switches from the sample to the hold mode on the falling edge of the CONVST command. A clean and low jitter falling edge of this signal is important to the performance of the converter. The BUSY output is brought high immediately following CONVST going low. BUSY stays high throughout the conversion process and returns low when the conversion has ended. Sampling starts tpd ns before the falling edge of the BUSY signal when CS is tied low or starts with the falling edge of CS when BUSY is low. Both RD and CS can be high during and before a conversion with one exception (CS must be low when CONVST goes low to initiate a conversion). Both the RD and CS pins are brought low in order to enable the parallel output bus with the conversion. Reading Data The ADS8484 outputs full parallel data in two's complement format as shown in Table 1. The parallel output is active when CS and RD are both low. There is a minimal quiet zone requirement around the falling edge of CONVST. This is 50 ns prior to the falling edge of CONVST and 40 ns after the falling edge. No data read should attempted within this zone. Any other combination of CS and RD sets the parallel output to 3-state. BYTE and BUS18/16 are used for multiword read operations. BYTE is used whenever lower bits on the bus are output on the higher byte of the bus. BUS18/16 is used whenever the last two bits on the 18-bit bus is output on either bytes of the higher 16-bit bus. Refer to Table 1 for ideal output codes. Table 1. Ideal Input Voltages and Output Codes DESCRIPTION ANALOG VALUE Full scale range +Vref Least significant bit (LSB) +Full scale DIGITAL OUTPUT TWO'S COMPLEMENT 2 × (+Vref)/262144 BINARY CODE HEX CODE (+Vref) – 1 LSB 01 1111 1111 1111 1111 1FFFF 0V 00 0000 0000 0000 0000 00000 0 V – 1 LSB 11 1111 1111 1111 1111 3FFFF –Vref 10 0000 0000 0000 0000 20000 Midscale Midscale – 1 LSB Zero The output data is a full 18-bit word (D17–D0) on DB17–DB0 pins (MSB–LSB) if both BUS18/16 and BYTE are low. The result may also be read on an 16-bit bus by using only pins DB17–DB2. In this case two reads are necessary: the first as before, leaving both BUS18/16 and BYTE low and reading the 16 most significant bits (D17–D2) on pins DB17–DB2, then bringing BUS18/16 high while holding BYTE low. When BUS18/16 is high, the lower two bits (D1–D0) appear on pins DB3–DB2. The result may also be read on an 8-bit bus for convenience. This is done by using only pins DB17–DB10. In this case three reads are necessary: the first as before, leaving both BUS18/16 and BYTE low and reading the 8 most significant bits on pins DB17–DB10, then bringing BYTE high while holding BUS18/16 low. When BYTE is high, the medium bits (D9–D2) appear on pins DB17–DB10. The last read is done by bringing BUS18/16 high while holding BYTE high. When BUS18/16 is high, the lower two bits (D1–D0) appear on pins DB11–DB10. The last read cycle is not necessary if only the first 16 most significant bits are of interest. All of these multiword read operations can be performed with multiple active RD (toggling) or with RD held low for simplicity. This is referred to as the AUTO READ operation. Table 2. Conversion Data Read Out DATA READ OUT 24 BYTE BUS18/16 PINS DB17–DB12 High High Low High High Low Low Low PINS DB11–DB10 PINS DB9–DB4 PINS DB3–DB2 PINS DB1–DB0 All One's D1–D0 All One's All One's All One's All One's All One's All One's D1–D0 All One's D9–D4 D3–D2 All One's All One's All One's D17–D12 D11–D10 D9–D4 D3–D2 D1–D0 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8484 ADS8484 www.ti.com SLAS511 – NOVEMBER 2007 RESET On power-up, internal POWER-ON RESET circuitry generates the reset required for the device. The first three conversions after power-up are used to load factory trimming data for a specific device to assure high accuracy of the converter. The results of the first three conversions are invalid and should be discarded. The device can also be reset through the use of the combination fo CS and CONVST. Since the BUSY signal is held at high during the conversion, either one of these conditions triggers an internal self-clear reset to the converter. • Issue a CONVST when CS is low and the internal convert state is high. The falling edge of CONVST starts a reset. • Issue a CS (select the device) while the internal convert state is high. The falling edge of CS causes a reset. Once the device is reset, all output latches are cleared (set to zeroes) and the BUSY signal is brought low. A new sampling period is started at the falling edge of the BUSY signal immediately after the instant of the internal reset. LAYOUT For optimum performance, care must be taken with the physical layout of the ADS8484 circuitry. As the ADS8484 offers single-supply operation, it is often used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more difficult it is to achieve good performance from the converter. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections and digital inputs that occur just prior to latching the output of the analog comparator. Thus, driving any single conversion for an n-bit SAR converter, there are at least n windows in which large external transient voltages can affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic, or high power devices. The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. On average, the ADS8484 draws very little current from an external reference as the reference voltage is internally buffered. If the reference voltage is external and originates from an op amp, make sure that it can drive the bypass capacitor or capacitors without oscillation. A 0.1-µF capacitor is recommended from pin 13 (REFIN) directly to pin 12 (REFM). REFM and AGND must be shorted on the same ground plane under the device. The AGND and BDGND pins should be connected to a clean ground point. In all cases, this should be the analog ground. Avoid connections which are too close to the grounding point of a microcontroller or digital signal processor. If required, run a ground trace directly from the converter to the power supply entry point. The ideal layout consists of an analog ground plane dedicated to the converter and associated analog circuitry. As with the AGND connections, +VA should be connected to a 5-V power supply plane or trace that is separate from the connection for digital logic until they are connected at the power entry point. Power to the ADS8484 should be clean and well bypassed. A 0.1-µF ceramic bypass capacitor should be placed as close to the device as possible. See Table 3 for the placement of the capacitor. In addition, a 1-µF to 10-µF capacitor is recommended. In some situations, additional bypassing may be required, such as a 100-µF electrolytic capacitor or even a Pi filter made up of inductors and capacitors-all designed to essentially low-pass filter the 5-V supply, removing the high frequency noise. Table 3. Power Supply Decoupling Capacitor Placement POWER SUPPLY PLANE CONVERTER DIGITAL SIDE CONVERTER ANALOG SIDE SUPPLY PINS Pin pairs that require shortest path to decoupling capacitors (7,8), (9,10), (16,17), (20,21), (22,23), (25,26) (36,37) Pins that require no decoupling 24, 26 1 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS8484 25 PACKAGE OPTION ADDENDUM www.ti.com 8-Dec-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty ADS8484IBRGZR ACTIVE VQFN RGZ 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8484IBRGZRG4 ACTIVE VQFN RGZ 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8484IBRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8484IBRGZTG4 ACTIVE VQFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8484IRGZR ACTIVE VQFN RGZ 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8484IRGZRG4 ACTIVE VQFN RGZ 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8484IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8484IRGZTG4 ACTIVE VQFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing ADS8484IBRGZR VQFN RGZ 48 ADS8484IBRGZT VQFN RGZ ADS8484IRGZR VQFN RGZ ADS8484IRGZT VQFN RGZ SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 48 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 48 1000 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 48 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS8484IBRGZR VQFN RGZ 48 1000 336.6 336.6 28.6 ADS8484IBRGZT VQFN RGZ 48 250 336.6 336.6 28.6 ADS8484IRGZR VQFN RGZ 48 1000 336.6 336.6 28.6 ADS8484IRGZT VQFN RGZ 48 250 336.6 336.6 28.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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