Order Now Product Folder Support & Community Tools & Software Technical Documents ADS8168 SBAS817 – NOVEMBER 2017 ADS8168 8-Channel, 16-Bit, 1-MSPS SAR ADC With Easy to Drive Analog Inputs 1 Features 2 Applications • • • • • • • • • • • Compact Low Power Data Acquisition System: – MUX Breakout Enables Single External Amplifier – Single 5-V Supply Operation – 16-Bit SAR ADC – Low Drift Integrated Reference and Buffer – 0.5 × VREF Output for Analog Input DC Biasing Excellent AC and DC Performance: – SNR: 92-dB, THD: –110-dB – INL: ±0.3-LSB, 16-Bit No Missing Codes Low Leakage Multiplexer with Sequencer: – Multiple Channel Sequencing Options: – Manual Mode, On-the-Fly Mode, Auto Sequence Mode, Lookup Based Channel Sequencing – Early Switching Enables Direct Sensor Interface – Fast Response Time with On-the-Fly Mode System Monitoring Features: – Per Channel Programmable Window Comparator – Alert Output for MCU Interrupt – False Trigger Avoidance With Programmable Hysteresis Enhanced-SPI Digital Interface: – 1-MSPS Throughput With 16-MHz SCLK – Wide Read Cycle Enables Lowest Cost Isolation Wide Temperature Range: –40°C to +125°C Optical Line Cards Optical Modules Test and Measurement Patient Monitoring PLC Universal Analog Input Module 3 Description The ADS8168 device is a 16-bit, 8-channel, highprecision successive-approximation-register (SAR) analog-to-digital converter (ADC) operating from a single 5-V supply with a 1-MSPS aggregate throughput. The early switching feature of the multiplexer supports extended settling time for analog inputs, making the device ideal for direct sensor interface. The output of the multiplexer and ADC analog inputs are available as device pins. This feature enables using a single ADC driver op-amp for all 8 analog inputs of the multiplexer. The ADS8168 features a digital window comparator with programmable high and low alarm thresholds with hysteresis per analog input channel. The ADS8168 simplifies processing of data with an enhanced channel sequencer, which reduces software complexity. The single op-amp solution with programmable alarm thresholds enables low power, low cost, and smallest form factor applications. Device Information PART NUMBER ADS8168 PACKAGE BODY SIZE (NOM) VQFN (32) 5.00 mm × 5.00 mm (1) For all package options refer to mechanical drawing section at the end of the datasheet. ADS8168 Application Topologies Single external op-amp (optional) Lowest Clock Speeds at 1-MSPS using 4-Wire Enhanced-SPI + VTH ISO ADS8168 AIN0 AIN1 User Code AINX Data User Code Data CS ADC CS SDO + + ± ALERT Parity AINX Data MISO MOSI SDI AIN7 MUX MCU 16-MHz SCK SCLK SPI Quiet time VREF ADC Conversion Small Form Factor Solution for Multiple Input Types Data Read ADC Conversion Data Read SPI Enhanced SPI 52-MHz 16-MHz 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. ADVANCE INFORMATION 1 ADS8168 SBAS817 – NOVEMBER 2017 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 5 6.1 6.2 6.3 6.4 6.5 6.6 6.7 5 5 5 5 6 8 9 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Timing Requirements ................................................ Switching Characteristics .......................................... 7.5 Programming........................................................... 31 7.6 Register Maps ......................................................... 36 8 8.1 Application Information............................................ 61 8.2 Typical Applications ................................................ 65 9 Power Supply Recommendations...................... 71 10 Layout................................................................... 72 10.1 Layout Guidelines ................................................. 72 10.2 Layout Example .................................................... 73 11 Device and Documentation Support ................. 75 11.1 11.2 11.3 11.4 11.5 11.6 Detailed Description ............................................ 12 ADVANCE INFORMATION 7.1 7.2 7.3 7.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ Application and Implementation ........................ 61 12 12 13 22 Documentation Support ........................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 75 75 75 75 75 75 12 Mechanical, Packaging, and Orderable Information ........................................................... 75 4 Revision History 2 DATE REVISION NOTES November 2017 * Initial release. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 ADS8168 www.ti.com SBAS817 – NOVEMBER 2017 5 Pin Configuration and Functions GND DVDD RST READY SDO-1/SEQSTS SDO-0 SCLK 31 30 29 28 27 26 25 GND 1 24 SDI DECAP 2 23 CS REFIO 3 22 ALERT REFM 4 21 GND REFP 5 20 ADC-INM REFP 6 19 MUXOUT-M REF/2 7 18 MUXOUT-P AIN-COM 8 17 ADC-INP Thermal 9 10 11 12 13 14 15 16 AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 Pad ADVANCE INFORMATION AVDD 32 RHB Package 32-Pin VQFN Top View Not to scale Pin Functions PIN NAME NO. FUNCTION ADC-INM 20 Analog input Negative ADC analog input DESCRIPTION ADC-INP 17 Analog input Positive ADC analog input AIN0 9 Analog input Analog input channel 0 AIN1 10 Analog input Analog input channel 1 AIN2 11 Analog input Analog input channel 2 AIN3 12 Analog input Analog input channel 3 AIN4 13 Analog input Analog input channel 4 AIN5 14 Analog input Analog input channel 5 AIN6 15 Analog input Analog input channel 6 AIN7 16 Analog input Analog input channel 7 AIN-COM 8 Analog input Common analog input ALERT 22 Digital output Digital ALERT output; active high. This pin is the output of the logical OR of the enabled channel ALERTs. AVDD 32 Power supply Analog power supply pin Chip-select input pin; active low. The device starts conversion of the active input channel on the CS rising edge. The device takes control of the data bus when CS is low. The SDO-x pins go to Hi-Z when CS is high. CS 23 Digital input DECAP 2 Power supply Place decoupling capacitor here for internal power supply DVDD 30 Power supply Interface power supply pin Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 3 ADS8168 SBAS817 – NOVEMBER 2017 www.ti.com Pin Functions (continued) PIN NAME GND NO. FUNCTION DESCRIPTION ADVANCE INFORMATION 1, 21, 31 Power supply Ground MUXOUT-M 19 Analog output MUX negative analog output MUXOUT-P 18 Analog output MUX positive analog output READY 28 Digital output Multifunction output pin. With CS held high, READY reflects the device conversion status. READY is low when a conversion is on-going. With CS low, the status of READY depends on the output protocol selection. REF/2 7 Analog output The output voltage on this pin is equal to half the voltage on REFP REFIO 3 REFM 4 REFP 5, 6 RST 29 Digital input Asynchronous reset input pin. A low pulse on the RST pin resets the device. All register bits return to the default state. SCLK 25 Digital input Clock input pin for the serial interface. All system-synchronous data transfer protocols are timed with respect to the SCLK signal. SDI 24 Digital input Serial data input pin. This pin is used to feed data or commands into the device. SDO-0 26 Digital output Serial communication pin: data output 0 SDO1/SEQSTS 27 Digital output Multifunction output pin. By default, this pin indicates the channel scanning status in the AUTO or PROGRAM sequence modes. In dual SDO data transfer mode this pin acts as a serial communication pin: data output 1. Thermal pad 4 Analog input/output Reference voltage input; internal reference 4.096-V output Analog input Reference ground potential short to GND externally Analog input/output Reference buffer output, ADC reference input. Short pins 5 and 6 together. Supply Exposed thermal pad; connect to GND Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 ADS8168 www.ti.com SBAS817 – NOVEMBER 2017 6 Specifications 6.1 Absolute Maximum Ratings MIN MAX UNIT AVDD -0.3 7 V DVDD -0.3 7 V AIN0, AIN1, AIN2, AIN3, AIN4, AIN5, AIN6, AIN7 to GND -0.3 AVDD + 0.3 V REFP to REFM -0.3 AVDD + 0.3 V REFIO to REFM -0.3 AVDD + 0.3 V REFM to GND -0.1 0.1 V Digital input pins to GND -0.3 DVDD + 0.3 V Digital output pins to GND -0.3 DVDD + 0.3 V Input current to any pin except supply pins -10 10 mA Operating temperature, TJ -40 125 °C Storage temperature, Tstg -65 150 °C (1) Input current to any pin except supply pins Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) ±2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) AVDD DVDD TA MIN NOM MAX 3 5 5.5 V Operating 1.65 3 5.5 V Specified throughput 2.35 3 5.5 V Ambient temperature -40 25 125 °C Supply voltage UNIT 6.4 Thermal Information DEVICE THERMAL METRIC (1) PKG DES (PKG FAM) UNIT PINS RθJA Junction-to-ambient thermal resistance 29.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 18.6 °C/W RθJB Junction-to-board thermal resistance 10.2 °C/W ΨJT Junction-to-top characterization parameter 0.2 °C/W ΨJB Junction-to-board characterization parameter 10.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 1.3 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 5 ADVANCE INFORMATION over operating free-air temperature range (unless otherwise noted) (1) ADS8168 SBAS817 – NOVEMBER 2017 www.ti.com 6.5 Electrical Characteristics At AVDD = 5-V, DVDD = 2.35-V to 5.5-V, REFIO configured as output pin, and maximum throughput (unless otherwise noted). Minimum and maximum values at TA = -40°C to +125°C; typical values at TA = 25°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 0 VREF V -0.1 VREF + 0.1 V -0.1 0.1 V -0.1 0.1 V ANALOG INPUTS - SINGLE-ENDED CONFIGURATION Full-scale input range for selected input pair FSR Absolute input voltage (AINx (1) to REFM) CHX_CHY_CFG (2) = 00b VIN Absolute input voltage (AINY REFM) (3) to CHX_CHY_CFG = 01b or 10b Absolute input voltage (AIN-COM) CINADC ADC Input capacitance 60 CINMUX MUX Input capacitance 13 pF ILMUX MUX input leakge ±10 nA REFM < VIN < REFP pF ANALOG INPUTS - PSEUDO-DIFFERENTIAL CONFIGURATION Full-scale input range for selected input pair FSR ADVANCE INFORMATION VIN Absolute input voltage (AINx to REFM) CHX_CHY_CFG = 00b Absolute input voltage (AINODD to REFM) CHX_CHY_CFG = 01b or 10b Absolute input voltage (AIN-COM) -VREF/2 VREF/2 V -0.1 VREF+0.1 V VREF/2 0.1 VREF/2 VREF/2+0 .1 V VREF/2 0.1 VREF/2 VREF/2+0 .1 V CINADC ADC Input capacitance 60 CINMUX MUX Input capacitance 13 pF ILMUX MUX input leakage ±10 nA 16 Bits REFM < VIN < REFP pF DC PERFORMANCE Resolution NMC No Missing Codes 16 INL Integral nonlinearity TBD ±0.3 TBD LSB DNL Differential nonlinearity TBD ±0.2 TBD LSB E(IO) Input offset error TBD ±0.5 TBD dVOS/dT Input offset thermal drift GE Gain error dGE/dT Gain error thermal drift TNS Transition noise 1 TBD ±0.005 LSB µV/°C TBD 3 %FSR ppm/°C TBD LSB AC PERFORMANCE SINAD fIN = 2-kHz TBD 92 dB SNR fIN = 2-kHz TBD 92 dB THD fIN = 2-kHz -110 dB SFDR fIN = 2-kHz 125 dB Crosstalk fIN = 10-kHz -110 dB -3-dB small signal bandwidth MUXOUT-P connected to ADC-INP and MUXOUT-M connected to ADC-INM 20 MHz REFERENCE BUFFER V(RO) Reference buffer offset voltage CREFBUF Decoupling capacitor on REFP RESR External series resistance ISHRT Short-circuit current (1) (2) (3) 6 V(RO) = VREFP - VREFIO, TA = 25°C -250 20 0 250 µV 250 µF Ω 1.3 30 mA AINX refers to analog inputs AIN0, AIN1, AIN2, AIN3, AIN4, AIN5, AIN6, and AIN7 CHX_CHY_CFG bits set the analog input configuration as single ended or pseudo-differential. Refer to AIN_CFG for more details. AINODD refers to analog inputs AIN1, AIN3, AIN5, and AIN7 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 ADS8168 www.ti.com SBAS817 – NOVEMBER 2017 Electrical Characteristics (continued) At AVDD = 5-V, DVDD = 2.35-V to 5.5-V, REFIO configured as output pin, and maximum throughput (unless otherwise noted). Minimum and maximum values at TA = -40°C to +125°C; typical values at TA = 25°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT REFby2 BUFFER VREFby2 REFby2 output voltage IREFby2 Sourcing current from REFby2 VREFP/2 V 2 mA INTERNAL REFERENCE OUTPUT VREFIO REFIO output voltage (4) dVREFIO/ dT Internal reference temperature drift CREFIO Decoupling capacitor on REFIO TA = 25°C, REFIO configured as output pin TBD 4.096 TBD 5 REFIO configured as output V ppm/°C 1 µF VREFIO REFIO input voltage REFIO configured as input pin 2.5 IREFIO REFIO input current REFIO configured as input pin 0.1 CREF Internal capacitance on REFIO pin REFIO configured as input pin 10 AVDD 0.3 V 1 µA ADVANCE INFORMATION EXTERNAL REFERENCE INPUT pF SAMPLING DYNAMICS tCONV Conversion time ADS8168 640 ADS8167 1200 ADS8166 2500 ADS8168 tACQ fCYCLE Acquisition time Maximum throughput ns 330 ADS8167 770 ADS8166 2470 ns ADS8168 1000 ADS8167 500 ADS8166 250 kSPS POWER SUPPLY REQUIREMENTS AVDD Analog power-supply voltage DVDD Digital power-supply voltage IAVDD Analog supply current REFIO configured as output pin REFIO configured as input pin (4) Digital supply current 5.5 3 5.5 2.35 5.5 ADS8168, AVDD = 5 V 6 TBD ADS8167, AVDD = 5 V 5 TBD ADS8166, AVDD = 5 V 4.5 TBD Static, no conversion Static, EN_REFBUF = 0 IDVDD 4.5 V V mA 2 1 Static, EN_REFIO = 0 970 µA Static, EN_REFBUF and EN_REFIO = 0 120 µA 1 uA DVDD = 3 V, CLOAD = 10 pF, no conversion Does not include the variation in voltage resulting from solder shift effects. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 7 ADS8168 SBAS817 – NOVEMBER 2017 www.ti.com 6.6 Timing Requirements At AVDD = 5-V, DVDD = 2.35-V to 5.5-V, and maximum throughput (unless otherwise noted). Minimum and maximum values at TA = -40°C to +125°C; typical values at TA = 25°C. MIN NOM MAX UNIT CONVERSION CYCLE twh_CSZ Pulse duration: CS high 30 ns twl_CSZ Pulse duration: CS low 30 ns tACQ Acquisition time 300 ns tqt_ACQ Quite acquisition time 30 ns td_CNVCA Quiet aperture time 20 ns 100 ns P ASYNCHRONOUS RESET AND LOW POWER MODES twl_RST Pulse duration: RST low SPI-COMPATIBLE SERIAL INTERFACE fCLK Serial clock frequency ADVANCE INFORMATION 2.35-V ≤ DVDD ≤ 3.6-V, VIH ≥ 0.7 DVDD, VIL ≤ 0.3 DVDD 70 MHz 1.65-V ≤ DVDD < 2.35-V, VIH ≥ 0.7 DVDD, VIL ≤ 0.3 DVDD 60 MHz tCLK Serial clock time period 1/fCLK ns tph_CK SCLK high time 0.45 0.55 tCLK tpl_CK SCLK low time 0.45 0.55 tCLK tph_CSCK Setup time: CS falling to the first SCLK capture edge 12 ns tsu_CKDI Setup time: SDI data valid to the SCLK capture edge 1.5 ns tht_CKDI Hold time: SCLK capture edge to (previous) data valid on SDI 1 ns tht_CKCS Delay time: last SCLK falling to CS rising 7 ns SOURCE-SYNCHRONOUS SERIAL INTERFACE fCLK tCLK 8 Serial clock frequency 2.35-V ≤ DVDD ≤ 3.6-V, SDR (DATA_RATE = 0b) 70 MHz 2.35-V ≤ DVDD ≤ 3.6-V, DDR (DATA_RATE = 1b) 35 MHz Serial clock time period 1/fCLK Submit Documentation Feedback ns Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 ADS8168 www.ti.com SBAS817 – NOVEMBER 2017 6.7 Switching Characteristics At AVDD = 5-V, DVDD = 2.35-V to 5.5-V, and maximum throughput (unless otherwise noted). Minimum and maximum values at TA = -40°C to +125°C; typical values at TA= 25°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ASYNCHRONOUS RESET, AND LOW POWER MODES td_RST Delay time: RST rising to RVS rising tPU_ADC Power-up time for converter module Change PD_ADC = 1b to 0b 1 ms tPU_REFIO Power-up time for internal reference Change PD_REF = 1b to 0b 5 ms tPU_REFB Change PD_REFBUF = 1b to 0b 10 ms 10 ms UF Power-up time for internal reference buffer 3 tPU_Device Power-up time for device ms tden_CSDO Delay time: CS falling to data enable 9 ns tdz_CSDO Delay time: CS rising to SDO going to Hi-Z 10 ns td_CKDO Delay time: SCLK launch edge to (next) data valid on SDO 13 ns td_CSRDY_ Delay time: CS falling to RVS falling 12 ns td_CKSTR_ Delay time: SCLK launch edge to RVS rising r 13 ns td_CKSTR_ Delay time: SCLK launch edge to RVS falling f 13 ns ADVANCE INFORMATION SPI-COMPATIBLE SERIAL INTERFACE t SOURCE-SYNCHRONOUS SERIAL INTERFACE (External Clock) toff_STRDO Time offset: RVS falling to (next) data valid on SDO _f -2 2 ns toff_STRDO Time offset: RVS rising to (next) data valid on SDO _r -2 2 ns tph_STR Strobe output high time 2.35-V ≤ DVDD ≤ 5.5-V 0.45 0.55 tSTR tpl_STR Strobe output low time 2.35-V ≤ DVDD ≤ 5.5-V 0.45 0.55 tSTR Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 9 ADS8168 SBAS817 – NOVEMBER 2017 www.ti.com Sample S Sample S+1 CS tcycle tconv_max tconv tacq tconv_min ADCST (Internal) CNV (C) ACQ (C + 1) tdCS_RVS ADVANCE INFORMATION READY Figure 1. Conversion Cycle Timing trst twl_RST RST td_rst CS SCLK READY SDO-x Figure 2. Asynchronous Reset Timing 10 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 ADS8168 www.ti.com SBAS817 – NOVEMBER 2017 tCLK tph_CK CS tpl_CK (1) SCLK tsu_CKDI tsu_CSCK tht_CKCS tht_CKDI SCLK(1) SDI tden_CSDO tdz_CSDO td_CKDO (1) SDO-x ADVANCE INFORMATION SDO-x The SCLK polarity, launch edge, and capture edge depend on the SPI protocol selected. Figure 3. SPI-Compatible Serial Interface Timing tCLK tph_CK CS tpl_CK SCLK td_CKSTR_f tsu_CSCK tht_CKCS SCLK td_CKSTR_r RVS tden_CSDO tdz_CSDO toff_STRDO_f toff_STRDO_r SDO-x (DDR) SDO-x td_CSRDY_f td_CSRDY_r toff_STRDO_r SDO-x (SDR) RVS Figure 4. Source-Synchronous Serial Interface Timing Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 11 ADS8168 SBAS817 – NOVEMBER 2017 www.ti.com 7 Detailed Description 7.1 Overview The ADS8168 is a successive approximation register (SAR), analog-to-digital converter (ADC) based on charge redistribution architecture with an analog multiplexer. This device integrates a reference, reference buffer, REFby2, and LDO, and features high performance at a high throughput rate at low power consumption. This ADS8168 supports unipolar, single-ended and pseudo-differential, analog input signals. The internal reference generates low-drift 4.096-V reference output. The integrated reference buffer supports the burst mode of data acquisition for external reference voltages in the range 2.5-V to 5-V, and offers a wide selection of input ranges without additional input scaling. For DC level shifting of the analog signals, the device has a REFby2 output. The REFby2 output is derived from the output of the integrated reference buffer. When a conversion is initiated, the differential input between the ADC-INP and ADC-INM pins is sampled on the internal capacitor array. The device uses an internal clock to perform conversions. During the conversion process, both analog inputs of the ADC are disconnected from the internal circuit. At the end of conversion process, the device reconnects the sampling capacitors to the ADC-INP and ADC-INM pins and enters an acquisition phase. ADVANCE INFORMATION The integrated LDO allows the device to operate on a single supply, AVDD. The device consumes only 25-mW, 20-mW, or 18-mW of power when operating at the rated maximum throughput of 1-MSPS, with the internal reference buffer and LDO enabled. The ADS8168 features a SPI compatible enhanced-SPI digital interface that can boost analog performance and simplify board layout, timing, and firmware, and support high throughput at lower clock speeds. This makes it easy to use with variety of microcontrollers as well as digital signal processors (DSPs), and field-programmable gate arrays (FPGAs). The ADS8168 enables optical line cards, optical modules, test and measurement, medical, and industrial applications to achieve fast, low-noise, low-distortion, low-power data acquisition in small form factors. 7.2 Functional Block Diagram MUXOUT-P ADC-INP AVDD DECAP MUX Control DVDD LDO ALERT AIN0 RVS AIN1 SDO-1/SEQ_ACTIVE Digital AIN2 4-WIRE SPI AIN3 AIN4 MUX ADC RST AIN5 AIN6 4.096-V AIN7 ÷2 AIN-COM MUXOUT-N ADC-INM REFP REFby2 REFIO 12 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 ADS8168 www.ti.com SBAS817 – NOVEMBER 2017 7.3 Feature Description From a functional perspective, the device comprises of five modules: the converter (SAR ADC), multiplexer (MUX), the reference module, and the Enhanced-SPI interface, and the low-dropout regulator (LDO), as shown in the Functional Block Diagram section. The LDO module is powered by the AVDD supply, and generates the bias voltage for internal circuit blocks of the device. The reference buffer drives the capacitive switching load present at the reference pins during the conversion process. The multiplexer selects among 8 analog input channels as input for the converter module. The converter module samples and converts the analog input into an equivalent digital output code. The enhanced-SPI interface module facilitates communication and data transfer between the device and the host controller. 7.3.1 Analog Multiplexer Figure 5 shows the small-signal equivalent circuit of the sample-and-hold circuit. Each sampling switch is represented by resistance (RS1 and RS2, typically 50-Ω) in series with an ideal switch (SW). The sampling capacitors, CS1 and CS2, are typically 60-pF. AVDD AVDD MUX SW RMUX 40 AINx MUXOUT-P OR ADVANCE INFORMATION The multiplexer ON-resistance (RMUX), typically 40-Ω is seen in series between the ON channel and MUXOUT-P or MUXOUT-M. Analog input of the multiplexer has typically 13-pF ON-channel capacitance (CMUX). ADC SW RS1 50 ADC-INP CMUX 13pF CS1 60pF AVDD AINy, AIN-COM AVDD SW RMUX 40 SW MUXOUT-M OR RS2 50 CS2 60pF ADC-INM CMUX 13pF Figure 5. Input Sampling Stage Equivalent Circuit During the input signal acquisition phase, the ADC-INP and ADC-INM inputs are individually sampled on CS1 and CS2, respectively. During the conversion process, the device converts for the voltage difference between the two sampled values: VADC-INP – VADC-INM. Each analog input pin has electrostatic discharge (ESD) protection diodes to AVDD and GND. Keep the analog inputs within the specified range to avoid turning the diodes on. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 13 ADS8168 SBAS817 – NOVEMBER 2017 www.ti.com Feature Description (continued) 7.3.1.1 Multiplexer Configurations The ADS8168 supports single-ended and pseudo-differential analog input signals. The flexible analog input channel configuration supports various sensor types. The analog inputs can be configured as shown in Figure 6. 8-channel MUX With Sense Input 4-channel MUX with Remote Ground Sense Inputs CHX_CHY_CFG = 00b AIN0 Input Pair 1 AIN0 AIN1 AIN1 AIN2 Input Pair 2 AIN2 AIN3 AIN3 AIN4 Pseudo-differential AIN-COM = REFby2 AIN5 COM_CFG bit = 1 AIN4 Input Pair 3 AIN5 AIN6 Input Pair 4 ADVANCE INFORMATION AIN6 REFby2 REFby2 AIN7 AIN-COM AIN7 AIN-COM AIN-COM not used Single-ended AIN-COM = GND Single-ended CHX_CHY_CFG = 01b COM_CFG bit = 0 GND or REFby2 Pseudo-differential CHX_CHY_CFG = 01b Configuration - 1 AINX AINY Configuration - 2 6-channel MUX with Remote Ground Sense Inputs Single-ended CHX_CHY_CFG = 01b GND or REFby2 AIN0 Input Pair 1 Pseudo-differential CHX_CHY_CFG = 01b AIN1 AIN2 Input Pair 2 AINX AIN3 AINY Pseudo-differential AIN-COM = REFby2 AIN4 Selectable Channel Configuration AIN5 4 single inputs referred to AIN-COM AIN6 CHX_CHY_CFG = 00b Channels Input Pairs Single Inputs 8 0 8 7 1 6 6 2 4 5 3 2 4 4 0 REFby2 AIN7 AIN-COM Single-ended AIN-COM = GND Configuration - 3 Figure 6. Analog Input Configurations 14 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 ADS8168 www.ti.com SBAS817 – NOVEMBER 2017 Feature Description (continued) The analog inputs can be configured as: • Configuration 1: Eight-channel MUX with sense input (AIN-COM); AIN_CFG register = 00h. The AIN-COM input range is decided by COM_CFG register. – Single-ended inputs with AIN-COM input as GND (COM_CFG register = 00h). – Pseudo-differential inputs with AIN-COM input as VREF / 2 (COM_CFG register = 01h). • Configuration 2: Four-channel MUX with remote ground sense inputs. – AIN_CFG register selects the analog input range of individual pairs. (1) (2). • Configuration 3: MUX with local sense (AIN-COM) and remote ground sense inputs. – Among the eight analog inputs of the MUX, some can be configured as pairs while the others are configured as individual channels. See Table 1 for options with channel configuration. – For channels configured as pairs, AIN_CFG register selects the analog input range of individual pairs. – For individual channels, COM_CFG register decides the input range. (1) (2) SR. NO. TOTAL CHANNELS INPUT PAIRS SINGLE CHANNELS 1 8 0 8 2 7 1 6 3 6 2 4 4 5 3 2 5 4 4 0 Channel pairs can be formed as [AIN0 - AIN1], [AIN2 - AIN3], [AIN4 - AIN5], and [AIN6 - AIN7]. When channels are configured as pairs, AIN0, AIN2, AIN4, and AIN6 are positive inputs. NOTE COM_CFG register register sets the input voltage range of the AIN-COM pin. AIN-COM pin must be connected to GND (COM_CFG register = 0b) or REFby2 (COM_CFG register = 1b) externally on the PCB. When using all channels in the Remote Sense configuration, the COM_CFG register register has no effect; connect the AIN-COM pin to GND to avoid noise pick-up. 7.3.1.2 Optimized for Minimum Crosstalk For precision measurement in a multi-channel system, coupling from one channel to another, i.e. crosstalk, can distort the measurement. When averaging few samples of a particular channel before switching over to the next channel, as described in Figure 20 and Figure 18, conventional multiplexers can have significant errors due to crosstalk. In conventional multiplexers, as shown in Figure 7, the OFF channel parasitic capacitance CDSY couples the OFF channel signal on to the ON channel. The ADS8168 uses a T switch structure, as shown in Figure 7. In this switch architecture, the off channel parasitic capacitance is connected to ground which significantly reduces coupling. Care must be taken to avoid signal coupling on the printed-circuit-board as described in the Layout section. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 15 ADVANCE INFORMATION Table 1. Channel Configuration Options ADS8168 SBAS817 – NOVEMBER 2017 www.ti.com ADS816x MUX Conventional MUX CDSX MUXOUT CS CHX CD CHY SW CS SW CS CDSY CHY SW CD MUXOUT CD SW SW CDSX CDSY CDSY SW SW CS CD SW CHX CDSX ADVANCE INFORMATION Figure 7. Isolation Crosstalk in Conventional MUX versus the ADS8168 7.3.1.3 Early Switching for Direct Sensor Interface Special care must be taken to minimize the driving requirements at the analog inputs of the multiplexer. Figure 8 shows the small signal equivalent model of the ADS8168 analog inputs. The multiplexer input has a switch resistance (RMUX) and parasitic capacitance (CMUX). This parasitic capacitance causes a charge kick-back on the MUX analog input just as the ADC sampling capacitor causes a charge kick-back on ADC inputs. In conventional multi-channel SAR ADCs, the acquisition time of the ADC is also the settling time available at the analog inputs of the multiplexer. Hence high-bandwidth op-amps are required at the analog inputs of the multiplexer to settle the charge kick-back. Multiple high bandwidth op-amps would significantly increase power dissipation, cost and size of the solution. The analog inputs of the ADS8168 provide a tCYCLE - 100-ns settling time resulting in long acquisition phase. At 1-MSPS, the multiplexer analog inputs get a 900-ns settling time. The low parasitic capacitance together with enhanced settling time eliminate the need to use an op-amp at the multiplexer input in most applications. In applications where the source impedance is significantly high, an op-amp such as the TLV314 can be used. SWMUX RMUX 40 CMUX 13pF AINx SWMUX CS1 60pF AINP MUXOUT-P AINy, AIN-COM RS1 50 SWADC OR RMUX 40 RS2 50 SWADC MUXOUT-M CMUX 13pF OR AINM CS2 60pF ADC MUX Figure 8. Synchronous and Timed Switching of the MUX and ADC Input Switches 16 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 ADS8168 www.ti.com SBAS817 – NOVEMBER 2017 tCYCLE CS SWADC 100-ns tACQ SWMUX CHX Input Settling Time To achieve better accuracy and noise performance, it is desirable to gather an average of multiple samples on the same channel without switching the MUX. As shown in Figure 20 and Figure 18, the output of the multiplexer does not create a charge kick-back as long as SDI = 0 i.e. the NOP command. Multiplexer does not switch during subsequent conversions except for the first time when a channel is selected. Hence high impedance sources such as voltage from resistor dividers can be connected to analog inputs of the multiplexer without an op-amp. 7.3.2 Reference The ADS8168 has a precision, low-drift reference internal to the device. See the Internal Reference section for details about using the internal reference. For best ENOB performance, the input signal range must be equal to the full-scale input range of the ADC. To maximize ENOB, an external reference voltage source can be used as described in the External Reference section. 7.3.2.1 Internal Reference The device features an internal reference source with a nominal output value of 4.096 V. In order to select the internal reference, the PD_REF bit of the PD_CNTL register must be programmed to logic 0. When the internal reference is used, the REFIO pin becomes an output with the internal reference value. A 1-µF (minimum) decoupling capacitor is recommended to be placed between the REFIO pin and REFM, as shown in Figure 10. The capacitor must be placed as close to the REFIO pin as possible. The output impedance of the internal bandgap circuit creates a low-pass filter with this capacitor to band-limit the noise of the reference. The internal reference is also temperature compensated to provide excellent temperature drift over an extended industrial temperature range of –40°-C to +125°-C. Short the two REFP pins externally. Short the REFM pin to GND externally. As shown in Figure 10, place a decoupling capacitor CREFBUF between the REFP pins and the REFM pin as close to the device as possible. The initial accuracy specification for the internal reference can be degraded if the die is exposed to any mechanical or thermal stress. Heating the device when being soldered to a printed circuit board (PCB) and any subsequent solder reflow is a primary cause for shifts in the VREF value. The main cause of thermal hysteresis is a change in die stress and is therefore a function of the package, die-attach material, and molding compound, as well as the layout of the device itself. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 17 ADVANCE INFORMATION Figure 9. Early Switching of the MUX Enables a Long Acquisition Phase ADS8168 SBAS817 – NOVEMBER 2017 www.ti.com AVDD 1-k 4.096-V PD_CNTL[3] = 0 (PD_REF) REFIO 1 F REFP REFP 10 F 10 F REFM ADC GND ADVANCE INFORMATION Figure 10. Device Connections for Using Internal 4.096-V Reference 7.3.2.2 External Reference Figure 11 shows the connections for using the device with external reference. A reference without low impedance output buffer can be used because the input leakage current of the internal reference buffer is less than 1 µA. AVDD 1-k 4.096-V AVDD PD_CNTL[3] = 1 (PD_REF) OUT REFIO REF5040 1 …F REFP REFP 10 …F 10 …F REFM ADC GND Figure 11. Device Connections for Using External Reference 18 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 ADS8168 www.ti.com SBAS817 – NOVEMBER 2017 7.3.3 Reference Buffer On the CS rising edge, the ADC starts converting the sampled analog input channel, and the internal capacitors are switched to the REFP pins as per the successive approximation algorithm. Most of the switching charge required during the conversion process is provided by external decoupling capacitor CREFBUF. If the charge lost from the CREFBUF is not replenished before the next CS rising edge, the voltage on REFP pins is less than VREFP. The subsequent conversion occurs with this different reference voltage, and causes a proportional error in the output code. The internal reference buffer of the device maintains the voltage on REFP pins within 0.5-LSB of VREFP. All the performance characteristics of the device are specified with the internal reference buffer and specified value of CREFBUF. Figure 12 shows the block diagram of the internal reference and reference buffer. ADS816x AVDD Margin ± BUF REFIO REFP + REFP DIS_REF 4.096-V GND REFM Figure 12. Internal Reference and Reference Buffer Block Diagram The input range for the device is set by the voltage (VREF) at the REFIO pin; by default the internal reference is ON and voltage at REFIO is 4.096 V. The REFIO pin has ESD protection diodes to the AVDD and GND pins. For minimum input offset error (E(IO)), set the REF_SEL[2:0] bits to the value closest to VREF. The internal reference buffer has a typical gain of 1 V/V with minimal offset error (V(RO)), and the output of the buffer is available between the REFP pins and the REFM pin. Set the REF_OFST[4:0] bits to add or subtract an intentional offset voltage (see the Table 21). Short the two REFP pins externally. Short the REFM pin to GND externally. As shown in Figure 11, place a decoupling capacitor CREFBUF between the REFP pins and the REFM pins as close to the device as possible. See the Layout section for layout recommendations. 7.3.4 REFby2 Buffer To use the maximum dynamic range of an ADC, the input signal must be centered around the mid-scale of the ADC's input range. In an unipolar ADC, where absolute input range is ground to reference voltage (VREF), midscale is VREF / 2. The REFby2 buffer generates the VREF / 2 signal for mid-scale shifting of the input signal. REFBy2 can be used in various types of sensor signal conditioning circuits, as shown in Figure 13. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 19 ADVANCE INFORMATION In burst-mode of operation, the ADC samples the selected analog input channel for a long duration of time and then performs a burst of conversions. During the sampling time, the sampling capacitor (CS) is connected to the differential input pins and no charge is drawn from the REFP pins. However, during the very first conversion cycle, there is a step change in the current drawn from the REFP pins. This sudden change in load triggers a transient settling response in the reference buffer. For a fixed input voltage, any transient settling error at the end of the conversion cycle results in a change in output codes over the subsequent conversions, as shown in . The internal reference buffer of the ADS8168, when used with the recommended value of CREFBUF, keeps the transient settling error at the end of each conversion cycle within 0.5 LSB. Therefore, the device supports burstmode of operation with every conversion result being as per the datasheet specifications. ADS8168 SBAS817 – NOVEMBER 2017 www.ti.com VCC VCC Current Sense Amplifier AC coupled sensor VLOAD ADS816x ADC Ref ADC + Load ADS816x + REFby2 REFby2 REF Configuration 2: AC Coupled Sensor Interface Configuration 1: High-side / Low-side Current sensing VCC VCC VBRIDGE ADVANCE INFORMATION INA ADS816x ADS816x - ADC ADC Ref + + REFby2 R REF REFby2 REF REF R Configuration 4: High Impedance Sensor Interface with INA Configuration 3: Unity Gain Sensor Interface Figure 13. Signal Conditioning with REFby2 Buffer A resistor divider at the output of reference buffer generates the reference-by-2 output as illustrated in Figure 14. When not using the internal reference buffer (see the PD_CNTL register), voltage applied at the REFP pin is applied to resistor divider. The output of the resistor divider is buffered and available at the REFby2 pin. REFP ADS816x AVDD ADC Reference ± ± BUF REFIO BUF + REFby2 + 100-k 100-k Margin GND Figure 14. REFby2 Buffer Model The REFby2 buffer is capable of sourcing up to 3-mA current (see Absolute Maximum Ratings). The REFby2 pin has ESD diode connections to AVDD and GND. 20 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 ADS8168 www.ti.com SBAS817 – NOVEMBER 2017 7.3.5 Converter Module The converter module samples the analog input signal (provided between the ADC-INP and ADC-INM pins), compares this signal with the reference voltage (between the REFP pins and REFM pin), and generates an equivalent digital output code. The converter module receives RST and CS inputs from the interface module, and outputs the ADCST signal and the conversion result back to the interface module. 7.3.5.1 Internal Oscillator The device features an internal oscillator (OSC) that provides the conversion clock. Conversion duration varies, but is bounded by the minimum and maximum value of tconv. The interface module uses this internal clock (OSC), an external clock (provided by the host controller on the SCLK pin), or a combination of both the internal and external clocks, to execute the data transfer operations between the device and host controller; see the Register Read/Write Operation section for more details. 7.3.5.2 ADC Transfer Function The least significant bit (LSB) for the ADC is given by Equation 1: 1 LSB = VREF / 216 (1) ADC Code (Hex) FFFF 8000 7FFF 1 0 -FSR VIN -FSR + 1 LSB MID ± 1 LSB MID FSR ± 1 LSB Analog Input (AINP AINM) Figure 15. Converter Transfer Characteristics Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 21 ADVANCE INFORMATION The device supports single-ended and pseudo-differential analog inputs. The device output is in straight binary format. Figure 15 and Table 2 show the ideal transfer characteristics for the device. ADS8168 SBAS817 – NOVEMBER 2017 www.ti.com Table 2. Transfer Characteristics DESCRIPTION SINGLE-ENDED INPUT VOLTAGE VREF = 4.096V PSEUDO-DIFFERENTIAL INPUT VOLTAGE VREF = 4.096V OUTPUT CODE (HEX) FSR – 1 LSB 4.0959375 V 2.0479375 V FFFF MID + 1 LSB 2.0480625 V 0.0000625 V 8001 MID 2.048 V 0V 8000 MID – 1 LSB 2.0479375 V –0.0000625 V 7FFF –FSR + 1 LSB 0.0000625 V –2.0479375 V 0001 –FSR 0V –2.048 V 0000 7.3.6 LDO To enable single-supply operation, the device features an internal low-dropout regulator (LDO). The LDO is powered by the AVDD supply, and the output is available on the DECAP pin. This LDO output powers the critical analog blocks within the device, and must not be used for any other external purposes. ADVANCE INFORMATION Decouple the DECAP pin with the GND pin by placing a 1-μF, X7R-grade, ceramic capacitor with a 10-V rating, as shown in Figure 16. There is no upper limit on the value of the decoupling capacitor; however, a larger decoupling capacitor results in higher power-up time for the device. See the Layout section for layout recommendations. AVDD DECAP LDO CLDO GND 1 F Figure 16. Internal LDO Connections 7.4 Device Functional Modes The multiplexer includes a sequence control logic that supports various features, thus making averaging data points easier and minimizing the components required to drive the multiplexer as described in the Channel Selection Using Internal Multiplexer section. The multiplexer scanning features are further enhanced by a Digital Window Comparator that enables optimized system power by minimizing communication between the host and the ADS8168. 7.4.1 Channel Selection Using Internal Multiplexer The ADS8168 includes an eight channel, linear, and low leakage current analog multiplexer. The multiplexer performs break-before-make operation when switching channels. There are four modes of switching the multiplexer input channels: • Manual mode • On-The-Fly Mode • Auto Channel Sequence mode • Custom Channel Sequencing Mode These modes can be selected by configuring the SEQ_MODE[1:0] bits in the DEVICE_CFG register. On powerup the default mode is Manual Mode; SEQ_MODE[1:0] = 00b, and default input channel is AIN0. The multiplexer configuration registers can be accessed over SPI as shown in Figure 25. The SPI interface eliminates the need for separate MUX control lines and reduces system cost. 22 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 ADS8168 www.ti.com SBAS817 – NOVEMBER 2017 Device Functional Modes (continued) 7.4.1.1 Manual Mode In Manual Mode of operation, the channel ID of desired analog input is configured in the CHANNEL_ID[2:0] register. On power-up or after device reset, AIN0 is selected; CHANNEL_ID[2:0] = 000b. Manual mode can be enabled, from any other sequencing mode, by programming the CHANNEL_ID[2:0] register. The timing information for changing channels in manual mode is shown in Figure 17. The channel information can be updated in a MCU friendly 3-byte access. As the 24-bits of channel configuration are sent over SDI, conversion data is clocked out over SDO. The data on SDO is MSB aligned and the first 16clocks correspond to 16-bits of conversion data. The last 8-bits of SDO an be ignored by the MCU. Sample CHA Sample CHA tCONV Sample CHB Sample CHC tCYCLE SCLK SDI Switch to CHB Switch to CHC Switch to CHD Data CHA Data CHA Data CHB SDO 24 clocks 100-ns MUX MUX OUT = CHA Cycle N MUX OUT = CHB MUX OUT = CHC Cycle (N + 1) Cycle (N + 2) Figure 17. Manual Mode Timing Diagram As can be inferred from Figure 17, the command to switch to CHB is sent in the Nth cycle and the data corresponding to channel CHB is available in the (N + 2)th cycle. This is because, on the rising edge of CS, the SDI commands are processed and ADC starts conversion. This causes the conversion to be done on the previous channel (CHA) and not on the updated channel ID (CHB). Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 23 ADVANCE INFORMATION CS ADS8168 SBAS817 – NOVEMBER 2017 www.ti.com Device Functional Modes (continued) Sample CHA Sample CHA Sample CHB tCONV Sample CHB Sample CHB tCYCLE CS SCLK SDI Switch to CHB SDO ADVANCE INFORMATION Data CHA Data CHA 24 clocks 16 clocks Data CHB MUX OUT = CHB MUX OUT = CHA MUX Data CHB 100-ns No MUX switching with SDI = 0 (NOP) Figure 18. Manual Mode With No Switching Timing Diagram 7.4.1.2 On-The-Fly Mode There is a latency of 1 cycle when switching channels using register access, as in Manual Mode. The newly selected channel data is available 2 cycles after selecting the desired channel. The ADS8168 supports on-the-fly switching of analog input channels of the multiplexer. This mode can be enabled by programming SEQ_MODE[1:0] = 01b in the DEVICE_CFG register. When enabled, the analog input channel for next conversion is determined by the first 5-bits sent over SDI. Desired analog input channel can be selected by setting MSB = 1 and the following 4-bits as channel ID. If the MSB = 0 then the SDI bit stream is decoded as a normal frame on the rising edge of CS. Table 3. On-the-Fly Mode Channel Selection Commands 24 SDI BITS [15:11] SDI BITS [10:0] DESCRIPTION 1 0000 Don't care Select analog input 0 1 0001 Don't care Select analog input 1 1 0010 Don't care Select analog input 2 1 0011 Don't care Select analog input 3 1 0100 Don't care Select analog input 4 1 0101 Don't care Select analog input 5 1 0110 Don't care Select analog input 6 1 0111 Don't care Select analog input 7 1 1000 to 1 1111 Don't care Error bit is set; select analog input 0 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 ADS8168 www.ti.com SBAS817 – NOVEMBER 2017 To set the device in on-the-fly mode, configure EN_ON_THE_FLY = 1b in ON_THE_FLY_CFG register using a 3-byte register access as shown in Figure 19. Once in this mode, 16-bit data transfer can be used thereby reducing the required clock speed. Sample CHA Sample CHA Sample CHB tCONV Sample CHC tCYCLE CS SCLK 1 24 1 2 3 4 5 16 1 2 3 4 5 16 5 clocks Set MODE = 1 SDO 1 4-bit CHB ID Data CHA 1 4-bit CHC ID 16 clocks 16 clocks Data CHA Data CHB 24 clocks MUX MUX OUT = CHA 100-ns MUX OUT = CHB MUX OUT = CHA MUX OUT = CHC No Cycle Latency Figure 19. On-the-Fly Mode With No MUX Channel Selection Latency To achieve better accuracy and noise performance, it is desirable to gather multiple samples on the same channel without switching the MUX. As shown in Figure 20 after selecting CHB the output of the multiplexer does not create a charge kick-back as long as SDI = 0 i.e. the NOP command. There multiplexer does not switch during subsequent conversions except for the first time when a channel is selected. Hence high impedance sources such as voltage from resistor dividers can be connected to analog inputs of the multiplexer without an op-amp. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 25 ADVANCE INFORMATION SDI ADS8168 SBAS817 – NOVEMBER 2017 www.ti.com Sample CHA Sample CHB Sample CHA tCONV Sample CHB tCYCLE CS SCLK 1 24 1 2 3 4 5 16 1 2 3 4 5 16 5 clocks SDI Set MODE = 1 SDO 1 4-bit CHB ID Data CHA 16 clocks 16 clocks Data CHA Data CHB 24 clocks ADVANCE INFORMATION MUX MUX OUT = CHA MUX OUT = CHA 100-ns MUX OUT = CHB No MUX switching with SDI = 0 (NOP) Figure 20. On-the-Fly Mode With No Switching Timing Diagram 7.4.1.3 Auto Sequence Mode In auto sequence mode the internal channel sequencer can selectively scan channels from AIN0 through AIN7 in ascending order. The device can be configured to scan channels in an ascending order by setting SEQ_MODE[1:0] = 10b in the DEVICE_CFG register using a 3-byte register access. In this mode, one or more channels among AIN[7:0] can be enabled by configuring the AUTO_SEQ_CFG1[7:0] register. By default all analog input channels are enabled. After enabling the desired channels, the sequence can be started by setting SEQ_START = 1b. The ADC auto-increments through the enabled channels after every CS rising edge. Upon setting SEQ_START = 1b, the SDO-1/SEQSTS pin will be pulled high until the last channel conversion frame is complete as shown in Figure 21. After the last enabled channel conversion is complete, channel AIN0 is selected and SDO-1/SEQSTS is in tristate as shown in Figure 22. 26 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 ADS8168 www.ti.com SBAS817 – NOVEMBER 2017 Sample CHA Sample CHA tCONV Sample CHA Sample CH0 Sample CH0 tCYCLE CS SCLK SDO MUX AUTO_SEQ_CH SEQ_START Data CHA Data CHA Data CHA 24 clocks 24 clocks 16 clocks MUX OUT = CHA MUX OUT = CH0 Data CH0 MUX OUT = CH1 Data CH7 MUX OUT = CH0 Scan channels AIN0 to AIN7 SEQSTS Figure 21. Starting a sequence in Auto Sequence Mode As an example, Figure 22 shows the timing diagram when the device is scanning AIN2 and AIN6 in Auto Sequence mode. At the end of conversion of AIN6, SDO-1/SEQSTS is tristate and AIN0 is selected as the active channel. At the end of sequence, if more conversion frames are launched the device will return valid data corresponding to AIN0. To • • • use the device in auto sequence mode follow these steps Set SEQ_MODE[1:0] = 10b. Configure the AUTO_SEQ_CH[7:0] register. In Figure 22, AUTO_SEQ_CH = 0x84. SEQ_START = 1b to start executing the sequence. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 27 ADVANCE INFORMATION SDI ADS8168 SBAS817 – NOVEMBER 2017 www.ti.com Sample CHA Sample CH2 Sample CH6 Sample CH0 tCYCLE CS SCLK SDI SDO MUX SEQ_START Data CHA Data CHA Data CH2 Data CH6 24 clocks 24 clocks 16 clocks 16 clocks MUX OUT = CHA MUX OUT = CH2 MUX OUT = CH6 MUX OUT = CH6 MUX OUT = CH0 ADVANCE INFORMATION SEQSTS Scan channels AIN2 and AIN6 Figure 22. Example: Scanning Channels 2 and 6 in Auto Sequence Mode To repeat a channel sequence indefinitely, set AUTO_REPEAT = 1b. When AUTO_REPEAT bit is enabled, the MUX will scan through the channels enabled in the AUTO_SEQ_CH[7:0] register and repeat the sequence after the last channel data has been converted as shown in Figure 23. After converting last channel in the sequence, the multiplexer does not automatically default to AIN0 unless AIN0 is enabled in AUTO_SEQ_CH[7:0]. As an example, Figure 23 shows the timing diagram when the device is scanning AIN2 and AIN6 in Auto Sequence mode with AUTO_REPEAT = 1b. At the end of conversion of AIN6, AIN2 is selected as the active channel and the device continues scanning through the enabled channels again. To • • • • 28 use the device in auto sequence with the repeat mode enabled follow these steps Set SEQ_MODE[1:0] = 10b. Configure the AUTO_SEQ_CH[7:0] register. In Figure 22, AUTO_SEQ_CH = 0x84. AUTO_REPEAT = 1b. SEQ_START = 1b to start executing the sequence. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 ADS8168 www.ti.com SBAS817 – NOVEMBER 2017 Sample CHA Sample CH2 Sample CH6 Sample CH2 Sample CH6 tCYCLE CS SCLK SDO MUX SEQ_START Data CHA Data CHA Data CH2 Data CH6 Data CH2 24 clocks 24 clocks 16 clocks 16 clocks 16 clocks MUX OUT = CHA MUX OUT = CH2 MUX OUT = CH2 MUX OUT = CH6 MUX OUT = CH6 SEQSTS Scan channels AIN2 and AIN6 and repeat Figure 23. Example: Scanning Channels 2 and 6 in Auto Sequence Mode With AUTO_REPEAT = 1 To terminate an on-going channel sequence set SEQ_ABORT = 1. When SEQ_ABORT is set, the auto sequence stops and AIN0 is selected as the active input channel. 7.4.1.4 Custom Channel Sequencing Mode In lookup based sequencing mode the internal channel sequencer can selectively scan channels from AIN0 through AIN7 in an order as defined by the user programmable illustrated in Table 4. The device can be configured in custom channel sequencing mode by programming SEQ_MODE[1:0] = 11b in the DEVICE_CFG register using a 3-byte register access. The channel scanning sequence is programmed by configuring the channel IDs in the register as space as shown in Table 4. Associated with every channel ID, a channel sample count can also be programmed. By default the channel sample count is 1 which means the sequence executes in the order of programmed channel IDs. If channel sample count is > 1 the corresponding channel is sampled and converted programmed number of times before switching to the next channel. Table 4. Custom Channel Sequencing Configuration Space Register Address Channel ID [2:0] Register Address Channel Sample Count [7:0] 0x000C Index 0 : 3-bit Channel ID 0x000D Index 0 : 8-bit Sample Count (default = 1) 0x000E Index 1 : 3-bit Channel ID 0x000F Index 1 : 8-bit Sample Count (default = 1) 0x0010 Index 2 : 3-bit Channel ID 0x0011 Index 2 : 8-bit Sample Count (default = 1) 0x0012 Index 3 : 3-bit Channel ID 0x0013 Index 3 : 8-bit Sample Count (default = 1) 0x0014 Index 4 : 3-bit Channel ID 0x0015 Index 4 : 8-bit Sample Count (default = 1) 0x0016 Index 5 : 3-bit Channel ID 0x0017 Index 5 : 8-bit Sample Count (default = 1) 0x0018 Index 6 : 3-bit Channel ID 0x0019 Index 6 : 8-bit Sample Count (default = 1) 0x001A Index 7 : 3-bit Channel ID 0x001B Index 7 : 8-bit Sample Count (default = 1) 0x001C Index 8 : 3-bit Channel ID 0x001D Index 8 : 8-bit Sample Count (default = 1) 0x001E Index 9 : 3-bit Channel ID 0x001F Index 9 : 8-bit Sample Count (default = 1) 0x0020 Index 10 : 3-bit Channel ID 0x0021 Index 10 : 8-bit Sample Count (default = 1) 0x0022 Index 11 : 3-bit Channel ID 0x0023 Index 11 : 8-bit Sample Count (default = 1) 0x0024 Index 12 : 3-bit Channel ID 0x0025 Index 12 : 8-bit Sample Count (default = 1) Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 29 ADVANCE INFORMATION SDI ADS8168 SBAS817 – NOVEMBER 2017 www.ti.com Table 4. Custom Channel Sequencing Configuration Space (continued) Register Address Channel ID [2:0] Register Address Channel Sample Count [7:0] 0x0026 Index 13 : 3-bit Channel ID 0x0027 Index 13: 8-bit Sample Count (default = 1) 0x0028 Index 14 : 3-bit Channel ID 0x0029 Index 14 : 8-bit Sample Count (default = 1) 0x002A Index 15: 3-bit Channel ID 0x002B Index 15 : 8-bit Sample Count (default = 1) For application specific scanning requirements, start and stop pointers can be used to define the channel scanning sequence. Start index can be programmed in CCS_START_INDEX[3:0] and stop index can be programmed in CCS_STOP_INDEX[3:0]. The 4-bit index corresponds to the configuration index as shown in Table 4. The sequence starts executing from the index programmed in CCS_START_INDEX (default 0) and stop or loop-back from CCS_STOP_INDEX (default 15). The channel scanning sequence can be looped-back to the start index from stop index by setting the CCS_SEQ_LOOP register = 1b. After configuring the channel scanning order, start index, and stop index the scanning can be initiated by setting the SEQ_START bit = 1b. The ADC scans through the enabled channels after every CS rising edge as defined by the channel scanning order. Upon setting SEQ_START = 1b, the SDO-1/SEQSTS pin is pulled high until the last channel conversion frame is complete as shown in Figure 21. After the last enabled channel conversion is complete, channel AIN0 is selected and SEQSTS/SDO-1 goes to tristate as shown in Figure 22. ADVANCE INFORMATION As an example, Figure 22 shows the timing diagram when the channel configuration is set as in Table 5. At the end of conversion of AIN6, SEQSTS/SDO-1 is tristate and AIN0 is selected as the active channel. At the end of sequence, if more conversion frames are launched the device will return valid data corresponding to AIN0. To • • • • • use the device in easy capture mode follow these steps: Set SEQ_MODE[1:0] = 3. Configure the channel sequence by setting up registers 0x000C - 0x002B. Configure CCS_START_INDEX and SEQ_STOP_INDEX. In Figure 22, CCS_START_INDEX = 0 and CCS_STOP_INDEX = 1. CCS_SEQ_LOOP register = 1 for indefinitely looping the sequence. In Figure 22, CCS_SEQ_LOOP register = 0b. SEQ_START = 1b to start executing the sequence. Table 5. Custom Channel Sequencing Configuration Example REGISTER ADDRESS CHANNEL ID [2:0] REGISTER ADDRESS CHANNEL SAMPLE COUNT [7:0] 0x000C 010b (Channel 2) 0x000D 1 0x000E 110b (Channel 6) 0x000F 1 7.4.2 Digital Window Comparator The ADS8168 has a programmable digital window comparator per analog input channel. The integrated window comparator enables the host not to read ADC data over serial interface for comparison purposes. In monitoring applications, the ADC can compare channel data with the set thresholds and alert the system host using ALERT pin. Also, it saves processing cycles by not requiring the high and low comparison in software. The window comparison is achieved by comparing the channel output code with a programmable high and low digital threshold. Each analog input channel has a programable hysteresis which is applicable to both the high and low thresholds of the corresponding channel as shown in Figure 24. Hence the following configurations are available per analog input channel: • Low threshold • High threshold • Hysteresis 30 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 ADS8168 www.ti.com SBAS817 – NOVEMBER 2017 AIN7 AIN1 High High Th + Hysteresis + AIN0 AIN7 + Latch Logical OR of All Analog Input Alerts Low Low Low Th - Hysteresis VIN Alert AIN0 ADC Data ADC The thresholds and hysteresis can be configured independently for every analog input channel. The ALERT output of the device is a logical OR of all the enabled alert outputs corresponding to the analog inputs. It is possible to selectively enable the window comparator for the analog inputs by configuring the ALERT_CFG register. By writing 1 to the register bits enables the window comparator for the corresponding analog input channel. The status of alert of individual analog input channel can be read from the ALERT_STATUS register. Further information about high or low threshold ALERT can be read by reading the ALERT_HI_STATUS register and ALERT_LO_STATUS register, respectively. When monitoring only a low threshold, the high threshold can be set to ADC positive full-scale code. Similarly, when monitoring only a high threshold, the low threshold can be set to negative full-scale code. 7.5 Programming 7.5.1 Data Transfer Protocols 7.5.1.1 Enhanced-SPI Interface • • The device features an enhanced-SPI interface that allows the host controller to operate at slower SCLK speeds and still achieve the required cycle time with a faster response time. For any data write operation, the host controller can use any of the four legacy, SPI-compatible protocols to configure the device, as described in the Protocols for Configuring the Device section. See the Register Read/Write Operation section for details about register read or write operation. For reading ADC conversion data or register data from the device, the enhanced-SPI interface module offers the following options: – SPI protocol with a single data output line; for example, SDO-0 (see the SPI Protocols with a Single SDO section) – SPI protocol with dual data output lines; for example SDO-1 and SDO-0 (see the SPI Protocols With Dual SDO section) – Clock re-timer data transfer (see the section) 7.5.1.1.1 Protocols for Configuring the Device As described in Table 6, the host controller can use any of the four SPI protocols i.e SPI-00, SPI-01, SPI-10, or SPI-11 to write data into the device. Table 6. SPI Protocols for Configuring the Device PROTOCOL SCLK POLARITY (At CS Falling Edge) SCLK PHASE (Capture Edge) SDI_CTL SD0_CTL1 DIAGRAM SPI-00 Low Rising 00h 00h Figure 26 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 31 ADVANCE INFORMATION Figure 24. Digital Window Comparator ADS8168 SBAS817 – NOVEMBER 2017 www.ti.com Programming (continued) Table 6. SPI Protocols for Configuring the Device (continued) PROTOCOL SCLK POLARITY (At CS Falling Edge) SCLK PHASE (Capture Edge) SDI_CTL SD0_CTL1 DIAGRAM SPI-01 Low Falling 01h 00h Figure 26 SPI-10 High Falling 02h 00h Figure 27 SPI-11 High Rising 03h 00h Figure 27 On power-up or after coming out of any asynchronous reset, the device supports the SPI-00-S protocol for data read and data write operations. To select a different SPI-compatible protocol, program the SDI_MODE[1:0] bits in the SDI_CTL register. This first write operation must adhere to the SPI-00-S protocol. Any subsequent data transfer frames must adhere to the newly-selected protocol. Note that the SPI protocol selected by the configuration of the SDI_MODE[1:0] is applicable to both read and write operations. 5-V ADVANCE INFORMATION AVDD VDD DVDD CS CS SDI SDO SDO SDI SCLK SCK ADS8168 GND MCU GND GND GND Figure 25. 4-Wire SPI Interface Connection Diagram Figure 26 and Figure 27 detail the four protocols using an optimal data frame. NOTE As explained in the Register Read/Write Operation section, a valid register read or write operation to the device requires 24 SCLKs to be provided within a data transfer frame. When reading ADC conversion data, minimum 16 SCLKs are required within a data transfer frame. CS CS RVS RVS CPOL = 0 CPOL = 0 SCLK SCLK CPOL = 1 CPOL = 1 SDI MSB MSB-1 LSB+1 LSB SDI Figure 26. Standard SPI Timing Protocol (CPHA = 0) 32 Submit Documentation Feedback MSB MSB-1 LSB+1 LSB Figure 27. Standard SPI Timing Protocol (CPHA = 1) Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 ADS8168 www.ti.com SBAS817 – NOVEMBER 2017 7.5.1.1.2 Protocols for Reading From the Device The protocols for the data read operation can be broadly classified into three categories: 1. SPI protocols (SPI-00, SPI-01, SPI-10, and SPI-11) with Single SDO; for example, SDO-0 2. SPI protocols (SPI-00, SPI-01, SPI-10, and SPI-11)with Dual SDO; for example, SDO-1 and SDO-0 3. Source-synchronous protocol for data transfer 7.5.1.1.2.1 SPI Protocols with a Single SDO As shown in Table 7, the host controller can use any of the four legacy, SPI-compatible protocols (SPI-00, SPI01, SPI-10, or SPI-11) to read data from the device. PROTOCOL SCLK POLARITY (At CS Falling Edge) SPI-00 Low SPI-01 Low SPI-10 High SPI-11 High SCLK PHASE (Capture Edge) MSB BIT LAUNCH EDGE SDI_CTL SD0_CTL1 DIAGRAM Rising CS falling 00h 00h Figure 28 Falling 1st SCLK rising 01h 00h Figure 28 Falling CS falling 02h 00h Figure 29 Rising 1st SCLK falling 03h 00h Figure 29 On power-up or after coming out of any asynchronous reset, the device supports the SPI-00 protocol for data read and data write operations. To select a different SPI-compatible protocol for both the data transfer operations: 1. Program the SDI_MODE[1:0] bits in the SDI_CTL register. This first write operation must adhere to the SPI00 protocol. Any subsequent data transfer frames must adhere to the newly-selected protocol. 2. Set the SDO_MODE[1:0] bits = 00b in the SD0_CTL1 register. NOTE The SPI transfer protocol selected by configuring the SDI_MODE[1:0] bits in the SDI_CTL register determines the data transfer protocol for both write and read operations. Either data can be read from the device using the selected SPI protocol by configuring the SDO_MODE[1:0] bits = 00b in the SD0_CTL1 register, or one of the SRC protocols can be selected for data read, as explained in the section. When using any of the SPI-compatible protocols, the READY output remains low throughout the data transfer frame. CS CS RVS RVS CPOL = 0 CPOL = 0 SCLK SCLK CPOL = 1 CPOL = 1 SDO-0 MSB MSB-1 MSB-2 LSB+1 LSB SDO-0 Figure 28. Standard SPI Timing Protocol (CPHA = 0, Single SDO-0) 0 MSB MSB-1 LSB+1 LSB Figure 29. Standard SPI Timing Protocol (CPHA = 1, Single SDO-0) Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 33 ADVANCE INFORMATION Table 7. SPI Protocols for Reading From the Device ADS8168 SBAS817 – NOVEMBER 2017 www.ti.com 7.5.1.1.2.2 SPI Protocols With Dual SDO The device provides an option to increase the SDO bus width from one bit (default, single SDO-0) to two bits (dual SDO) when operating with any of the data transfer protocols. In order to operate the device in dual SDO mode, the SDO_WIDTH bit in the SD0_CTL1 register must be set to 1b. In this mode, the SDO-1/SEQSTS pin functions as SDO-1. In dual SDO mode, two bits of data are launched on the two SDO pins (SDO-0 and SDO-1) on every SCLK launch edge, as shown in Figure 30 and Figure 31. CS CS RVS RVS CPOL = 0 CPOL = 0 SCLK SCLK CPOL = 1 CPOL = 1 ADVANCE INFORMATION SDO-1 MSB MSB-2 MSB-4 LSB+3 LSB+1 SDO-0 MSB-1 MSB-3 MSB-5 LSB+2 LSB SDO-1 0 MSB MSB-2 LSB+3 LSB+1 SDO-0 0 MSB-1 MSB-3 LSB+2 LSB Figure 30. Standard SPI Timing Protocol (CPHA = 0, Dual SDO) 34 Submit Documentation Feedback Figure 31. Standard SPI Timing Protocol (CPHA = 1, Dual SDO) Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 ADS8168 www.ti.com SBAS817 – NOVEMBER 2017 7.5.1.1.2.3 Clock Re-Timer Data Transfer In clock re-timer data transfer mode, the device provides an output clock that is synchronous with the output data. Furthermore, the host controller can also select the data bus width in this mode of operation. In all modes of operation, the READY pin provides the output clock, synchronous to the device data output. The clock re-timer data transfer allows the width of the output bus to be configured, similar to the SPI protocols. 7.5.1.1.2.3.1 Output Bus Width Options The device provides an option to increase the SDO-x bus width from one bit (default, single SDO-x) to two bits (dual SDO-x) when operating with clock re-timer data transfer. In order to operate the device in dual SDO mode, the SDO_WIDTH bit in the SD0_CTL1 must be set to 1b. In this mode, the SDO-1/SEQSTS pin functions as SDO-1. 7.5.2 Register Read/Write Operation This device features configuration registers (as described in the Device Module Configuration Registers section). To access the internal configuration registers, these devices support the commands listed in Table 8. Table 8. Supported Commands B[23:19] B[18:8] B[7:0] COMMAND ACRONYM 00000 00000000000 00000000 NOP 00001 <11-bit address> <8-bit data> WR_REG Write <8-bit data> to the <11-bit address> 00010 <11-bit address> 00000000 RD_REG Read contents from the <11-bit address> 00011 <11-bit address> <8-bit unmasked bits> SET_BITS Set <8-bit unmasked bits> from <11-bit address> 00100 <11-bit address> <8-bit unmasked bits> CLR_BITS Clear <8-bit unmasked bits> from <11-bit address> Remaining combinations of 0xxxx xxxxxxxxx xxxxxxxx Reserved These commands are reserved and treated by the device as no operation COMMAND DESCRIPTION No operation This device supports two types of data transfer operations: data write (the host controller configures the device), and data read (the host controller reads data from the device). Any data write to the device is always synchronous to the external clock provided on the SCLK pin. The WR_REG command writes the 8-bit data into the 11-bit address specified in the command string. The CLR_BITS command clears the specified bits (identified by 1) at the 11-bit address (without affecting the other bits), and the SET_BITS command sets the specified bits (identified by 1) at the 11-bit address (without affecting the other bits). Figure 32 shows the digital waveform for register read operation. Register read operation consists of two frames: one frame to initiate a register read and second frame to read data from register address provided in the first frame. As shown in Figure 32, during the first 24-bit frame, read command (00010b), 11-bit register address and 8-bit dummy data are sent over SDI. When CS goes from low to high, this read command is decoded and the requested register data is available for reading during the next frame. During the second frame, the first 8 bits on SDO correspond to the requested register read. During the second frame SDI can be used to initiate another operation or can be set to 0. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 35 ADVANCE INFORMATION NOTE For any particular data transfer, SPI or Clock Re-timer, the device follows the same timing specifications for single and dual SDO modes. The only difference is that in the dual SDO mode the device requires half as many clock cycles to output the same number of bits when in single SDO mode, thus reducing the minimum required clock frequency for a certain sampling rate of the ADC. ADS8168 SBAS817 – NOVEMBER 2017 www.ti.com CS SCLK 1 2 5 6 0 0010b (RD_REG) SDI 7 16 18 17 11-bit Address 24 1 0000 0000b 2 5 Command 6 7 11-bit A Optional; Can SDO 8-bit Register Data Figure 32. Register Read Operation ADVANCE INFORMATION For writing data to the register one 24-bit frame is required as shown in Figure 33. The 24-bit data on SDI consists of 5-bit write command (00001b), 11-bit register address and 8-bit data. On CS rising edge the write command is decoded and the specified register is updated with the 8-bit data specified during register write operation. CS SCLK 1 2 5 0 0001b (WR_REG) SDI 6 7 16 17 11-bit Address 18 24 8-bit Data Figure 33. Register Write Operation Table 9 lists the access codes for the ADS8168 registers. Table 9. ADS8168 Access Type Codes Access Type Code Description R R Read R-W R/W Read or write W W Write -n Value after reset or the default value 7.6 Register Maps 7.6.1 Device Module Configuration Registers The device features following hardware configuration registers, mapped as described in Table 10. Table 10. Configuration Registers Mapping 36 ADDRESS REGISTER NAME REGISTER DESCRIPTION 000h REG_ACCESS 004h PD_CNTL Low-power modes control 008h SDI_CNTL SDI input protocol selection Enables read/write access to device hardware configuration registers. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 ADS8168 www.ti.com SBAS817 – NOVEMBER 2017 Register Maps (continued) Table 10. Configuration Registers Mapping (continued) ADDRESS REGISTER NAME 00Ch SDO_CNTL1 SDO output protocol selection REGISTER DESCRIPTION 00Dh SDO_CNTL2 Output data rate selection 00Eh SDO_CNTL3 SDO-1 pin configuration 010h DATA_CNTL Output data word configuration 011h PARITY_CNTL Parity configuration register 7.6.1.1 REG_ACCESS Register (address = 00h) [reset = 00h] This register controls write access to the device hardware configuration registers. Figure 34. REG_ACCESS Register 6 5 4 3 REG_ACCESS_BITS R/W-0000 0000b 2 1 0 Table 11. REG_ACCESS Register Field Descriptions Bit Field Type Reset Description 7-0 REG_ACCESS_BITS R/W 0000 0000b Controls write access to . Write 1010 1010b to this register to enable write access to . Write access to is disabled for all values other than REG_ACCESS_BITS = 1010 1010b. 7.6.1.2 PD_CNTL Register (address = 04h) [reset = 00h] This register controls the low-power modes offered by the device. Write access to this register are disabled on power-up. To enable write access, configure the REG_ACCESS register. Figure 35. PD_CNTL Register 7 0 R-0b 6 0 R-0b 5 0 R-0b 4 PD_REFby2 R/W-0b 3 PD_REF R/W-0b 2 PD_REFBUF R/W-0b 1 PD_ADC R/W-0b 0 0 R-0b Table 12. PD_CNTL Register Field Descriptions Bit Field Type Reset Description 7-5 0 R 0000b Reserved bits. Reads return 0000b. 4 PD_REFby2 R/W 0b This bit powers down the internal reference-by-2 buffer. 0b = Internal reference-by-2 buffer is powered up 1b = Internal reference-by-2 buffer is powered down 3 PD_REF R/W 0b This bit powers down the internal reference. 0b = Internal reference is powered up 1b = Internal reference is powered down 2 PD_REFBUF R/W 0b This bit powers down the internal reference buffer. 0b = Internal reference buffer is powered up 1b = Internal reference buffer is powered down 1 PD_ADC R/W 0b This bit powers down the converter module. 0b = converter module is powered up 1b = converter module is powered down 0 0 R 0b Reserved bits. Do not write. Reads return 0b. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 37 ADVANCE INFORMATION 7 ADS8168 SBAS817 – NOVEMBER 2017 www.ti.com To power-down the converter module, set the PD_ADC bit in the PD_CNTL register. The converter module powers down on the rising edge of CS. To power-up the converter module, reset the PD_ADC bit in the PD_CNTL register. The converter module starts to power-up on the rising edge of CS. Wait for tPU_ADC before initiating any conversion or data transfer operation. To power-down the internal reference buffer, clear the EN_REFBUF bit in the PD_CNTL register. The internal reference buffer powers down on the rising edge of CS. To power-up the internal reference buffer, set the EN_REFBUF bit in the PD_CNTL register. The internal reference buffer starts to power-up on the rising edge of CS. Hold CS high for tPU_REFBUF to allow for reference buffer power-up time. To power-down the internal reference, clear the EN_REF bit in the PD_CNTL register. The internal reference powers down on the rising edge of CS. To power-up the internal reference, set the EN_REF bit in the PD_CNTL register. The internal reference starts to power-up on the rising edge of CS. Hold CS high for tPU_REF before initiating any conversion. 7.6.1.3 SDI_CNTL Register (address = 008h) [reset = 00h] This register selects the SPI protocol for writing data to the device. Write access to this register are disabled on power-up. To enable write access, configure the REG_ACCESS register. Figure 36. SDI_CNTL Register ADVANCE INFORMATION 7 0 R-0b 6 0 R-0b 5 0 R-0b 4 0 R-0b 3 0 R-0b 2 0 R-0b 1 0 SDI_MODE[1:0] R/W-00b Table 13. SDI_CNTL Register Field Descriptions Bit Field Type Reset Description 7-2 0 R 000000b Reserved bits. Do not write. Reads return 000000b. 1-0 SDI_MODE[1:0] R/W 00b These bits select the protocol for writing data into the device. 00b = Standard SPI with CPOL = 0 and CPHASE = 0 01b = Standard SPI with CPOL = 0 and CPHASE = 1 10b = Standard SPI with CPOL = 1 and CPHASE = 0 11b = Standard SPI with CPOL = 1 and CPHASE = 1 7.6.1.4 SDO_CNTL1 Register (address = 0Ch) [reset = 00h] This register configures the protocol for reading data from the device. Write access to this register are disabled on power-up. To enable write access, configure the REG_ACCESS register. Figure 37. SDO_CNTL1 Register 7 0 6 OUTDATA_uC _MODE R/W-0b R-0b 5 DATA_RIGHT_ ALIGNED R/W-0b 4 BYTE_INTERL EAVE R/W-0b 3 0 2 SDO_WIDTH 1 0 SDO_MODE[1:0] R-0b R/W-0b R/W-00b Table 14. SDO_CNTL1 Register Field Descriptions Bit 38 Field Type Reset Description 7 0 R 0b Reserved bit. Do not write. Read returns 0b. 6 OUTDATA_uC_MODE R/W 0b Enables MCU/Processor friendly data interface. 0b = Device will output N data bits. 1b = Device will output 16 bits if N ≤ 16; Device will output 32 bits if N > 16. 5 DATA_RIGHT_ALIGNED R/W 0b This bit is ignored if uC_MODE = 0b. When uC_MODE = 1b: 0b = Data frame left aligned. The SDOs will output device data followed by SDI data bits. 1b = Data frame right aligned. The SDOs will output 0s followed by device data bits. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 ADS8168 www.ti.com SBAS817 – NOVEMBER 2017 Bit Field Type Reset Description 4 BYTE_INTERLEAVE R/W 0b This bit is ignored if uC_MODE = 0b or SDO_WIDTH = 0b. When uC_MODE = 1b and SDO_WIDTH = 1b: 0b = Bit mode. SDO-0 will output (MSB, MSB-2 ..., 1) and SDO-1 will output (MSB-1, MSB-3, ..., 0) 1b = Byte mode. Say data output bits = N; if N ≤16: SDO-0 will output 8 MSB bits and SDO-1 will output (N-8) bits if 16< N ≤ 32: SDO-0 will output 16 MSB bits and SDO-1 will output (N16) bits 3 0 R 0b Reserved bit. Do not write. Read returns 0b. 2 SDO_WIDTH R/W 0b This bits set the width of the output bus. 0b = Data are output only on SDO-0 1b = Data are output on SDO-0 and SDO-1 SDO_MODE[1:0] R/W 00b These bits select the protocol for reading data from the device. 00b = SDO follows the SPI protocol selected in the SDI_CNTL register 01b = SDO follows the SPI protocol selected in the SDI_CNTL register but with Early Data Launch feature enabled. See . 10b = Invalid configuration, not supported by the device 11b = SDO follows the Clock Re-Timer Data Transfer 1-0 7.6.1.5 SDO_CNTL2 Register (address = 0Dh) [reset = 00h] This register configures the protocol for reading data from the device. Write access to this register are disabled on power-up. To enable write access, configure the REG_ACCESS register. Figure 38. SDO_CNTL2 Register 7 0 R-0b 6 0 R-0b 5 0 R-0b 4 0 R-0b 3 0 R-0b 2 0 R-0b 1 0 R-0b 0 DATA_RATE R/W-0b Table 15. SDO_CNTL2 Register Field Descriptions Bit Field Type Reset Description 7-1 000 0000 R 000 0000b Reserved bit. Do not write. Reads return 000 0000b. DATA_RATE R/W 0b This bit is ignored if SDO_MODE[1:0] = 00b. When SDO_MODE[1:0] = 11b: 0b = SDOs are updated at single data rate (SDR) with respect to the output clock 1b = SDOs are updated at double data rate (DDR) with respect to the output clock 0 7.6.1.6 SDO_CNTL3 Register (address = 0Dh) [reset = 00h] This register configures the protocol for reading data from the device. Write access to this register are disabled on power-up. To enable write access, configure the REG_ACCESS register. Figure 39. SDO_CNTL3 Register 7 0 R-0b 6 0 R-0b 5 0 R-0b 4 0 R-0b 3 0 R-0b 2 0 R-0b 1 0 R-0b 0 SEQSTS_CFG R/W-0b Table 16. SDO_CNTL3 Register Field Descriptions Bit Field Type Reset Description 7-1 000 0000 R 000 0000b Reserved bits. Do not write. Reads return 000 0000b. SEQSTS_CFG R/W 0b This pin decides the behaviour of SDO-1 when SDO_WIDTH = 0b. 0b = SDO-1 is tristate. 1b = SDO-1 will indicate sequence active status. 0 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 39 ADVANCE INFORMATION Table 14. SDO_CNTL1 Register Field Descriptions (continued) ADS8168 SBAS817 – NOVEMBER 2017 www.ti.com 7.6.1.7 DATA_CNTL Register (address = 010h) [reset = 00h] This register configures the contents of the output data word. Write access to this register are disabled on powerup. To enable write access, configure the REG_ACCESS register. Figure 40. DATA_CNTL Register 7 0 R-0b 6 0 R-0b 5 4 DATA_OUT_FORMAT[1:0] R/W-00b 3 0 R-0b 2 0 R-0b 1 0 R-0b 0 DATA_VAL R/W-0b Table 17. DATA_CNTL Register Field Descriptions ADVANCE INFORMATION Bit Field Type Reset Description 7-6 00 R 000b Reserved bits. Reads return 00b. 5-4 DATA_OUT_FORMAT[1:0] R/W 00b These bits control the composition of the output data frame. 00b = ADC conversion result. 01b = ADC conversion result + 4-bit channel ID. 10b = ADC conversion result + 4-bit channel ID + 4-bit device status + 2bit channel configuration. 11b = ADC conversion result + 4-bit channel ID + 4-bit device status + 3bit device ID. Parity bits can be appended to data output frame. Refer to PARITY_CNTL register for details. 3-1 000 R 000b Reserved bits. Reads return 00b. DATA_VAL R/W 0b Setting this bit enables SDO capture debug mode. 0b = Normal operation. Device data output on SDO. 1b = Fixed 0101 output. 0 7.6.1.8 PARITY_CNTL Register (address = 11h) [reset = 00h] This register configures the parity output from the device. Write access to this register are disabled on power-up. To enable write access, configure the REG_ACCESS register. Figure 41. PARITY_CNTL Register 7 0 R-0b 6 0 R-0b 5 0 R-0b 4 0 R-0b 3 0 R-0b 2 PARITY_EN R/W-0b 1 0 R-0b 0 0 R-0b Table 18. PARITY_CNTL Register Field Descriptions Bit Field Type Reset Description 7-3 0 0000 R 0 0000b Reserved bits. Do not write. Reads return 0 0000b. PARITY_EN R/W 0b Enables parity computation on the data output bits. 0b = Parity disabled. 1b = 1-bit parity appended to data output frame. Length of data is 1-bit more than length specified by DATA_OUT_FORMAT. 00 R 00b Reserved bits. Do not write. Reads return 00b. 2 1-0 40 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 ADS8168 www.ti.com SBAS817 – NOVEMBER 2017 7.6.2 Device Calibration Registers The device features following calibration registers, mapped as described in Table 19. Table 19. Calibration Registers Mapping ADDRESS REGISTER NAME 018h OFST_CAL Offset calibration REGISTER DESCRIPTION 019h REF_MRG1 Reference margin 01Ah REF_MRG2 Reference margin enable 01Bh REFby2_MRG REFby2 buffer margin configuration 7.6.2.1 OFST_CAL Register (address = 018h) [reset = 00h] This register selects the external reference range for optimal offset calibration. Figure 42. OFST_CAL Register 6 0 R-0b 5 0 R-0b 4 0 R-0b 3 0 R-0b 2 1 REF_SEL[2:0] R/W-000b 0 Table 20. OFST_CAL Register Field Descriptions Bit Field Type Reset Description 7-3 0 R 00000b Reserved bits. Reads return 00000b. 2-0 REF_SEL[2:0] R/W 000b These bits select the external reference range for optimal offset. 000b = Optimum offset calibration for VREF = 5.0 V 001b = Optimum offset calibration for VREF = 4.5 V 010b = Optimum offset calibration for VREF = 4.096 V 011b = Optimum offset calibration for VREF = 3.3 V 100b = Optimum offset calibration for VREF = 3.0 V 101b = Optimum offset calibration for VREF = 2.5 V 110b = Optimum offset calibration for VREF = 5.0 V 111b = Optimum offset calibration for VREF = 5.0 V 7.6.2.2 REF_MRG1 Register (address = 019h) [reset = 00h] This register selects the margining to be added to or subtracted from the reference buffer output; see the Reference Buffer section. Figure 43. REF_MRG1 Register 7 0 R-0b 6 0 R-0b 5 0 R-0b 4 3 2 REF_OFST[4:0] R/W-00000b 1 0 Table 21. REF_MRG1 Register Field Descriptions Bit Field Type Reset Description 7-5 0 R 000b Reserved bits. Reads return 000b. 4-0 REF_OFST[4:0] R/W 00000b These bits select the reference offset value as per Table 22. Table 22. REF_OFST[4:0] settings REF_OFST[4:0] ΔVREFBUFOUT (typical) 00000b 0 mV 00001b 280 µV 00010b 580 µV 00011b 840 µV 00100b 1.12 mV Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 41 ADVANCE INFORMATION 7 0 R-0b ADS8168 SBAS817 – NOVEMBER 2017 www.ti.com Table 22. REF_OFST[4:0] settings (continued) REF_OFST[4:0] ΔVREFBUFOUT (typical) 00101b 1.4 mV 00110b 1.68 mV 00111b 1.96 mV 01000b 2.24 mV 01001b 2.52 mV 01010b 2.8 mV 01011b 3.08 mV 01100b 3.36 mV 01101b 3.64 mV 01110b 3.92 mV 01111b 4.2 mV ADVANCE INFORMATION 10000b –4.5 mV 10001b –4.22 mV 10010b –3.94 mV 10011b –3.66 mV 10100b –3.38 mV 10101b –3.1 mV 10110b –2.82 mV 10111b –2.54 mV 11000b –2.26 mV 11001b –1.98 mV 11010b –1.7 mV 11011b –1.42 mV 11100b –1.14 mV 11101b –860 µV 11110b –580 µV 11111b –280 µV 7.6.2.3 REF_MRG2 Register (address = 01Ah) [reset = 00h] This register selects the external reference range for optimal offset calibration. Figure 44. REF_MRG2 Register 7 0 R-0b 6 0 R-0b 5 0 R-0b 4 0 R-0b 3 0 R-0b 2 0 R-0b 1 0 R-0b 0 EN_MARG R/W-0b Table 23. REF_MRG2 Register Field Descriptions Bit Field Type Reset Description 7-1 0 R 000 0000b Reserved bits. Reads return 000 0000b. EN_MARG R/W 0b This bit enables reference buffer margining feature. 0b = Margining is disabled 1b = Margining is enabled 0 7.6.2.4 REFby2_MRG Register (address = 01Bh) [reset = 00h] This register selects the margining to be added to or subtracted from the REFFby2 buffer output; see the Reference Buffer section. 42 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 ADS8168 www.ti.com SBAS817 – NOVEMBER 2017 Figure 45. REFby2_MRG Register 7 0 6 R-0b 5 REF_OFST[2:0] 4 R/W-000b 3 0 2 0 1 0 R-0b R-0b R-0b 0 EN_REFby2_M ARG R/W-0b Table 24. REFby2_MRG Register Field Descriptions Bit Field Type Reset Description 0 R 0b Reserved bit. Do not write. Reads return 0b. 6-4 REFBY2_OFST[2:0] R/W 00000b These bits select the REFby2 offset value as per . 3-1 0 R 000b Reserved bits. Do not write. Reads return 000b. EN_REF/2_MARG R/W 0b This bit enables REFby2 buffer margining feature. 0b = Margining is disabled 1b = Margining is enabled 7 0 REF/2_OFST[2:0] ΔVREFby2 (typical) 000b TBD 001b TBD 010b TBD 011b TBD 100b TBD 101b TBD 110b TBD 111b TBD ADVANCE INFORMATION Table 25. REFby2_OFST[2:0] settings Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 43 ADS8168 SBAS817 – NOVEMBER 2017 www.ti.com 7.6.3 Analog Input Configuration Registers The device features following channel configuration registers, mapped as described in Table 19. Table 26. Analog Input Configuration Registers Mapping ADDRESS REGISTER NAME 024h AIN_CFG 027h COM_CFG REGISTER DESCRIPTION Selects the analog input signal modes AIN-COM pin configuration 7.6.3.1 AIN_CFG Register (address = 024h) [reset = 00h] This register configures the analog input channels. Figure 46. AIN_CFG Register 7 6 CH7_CH6_CFG[1:0] R/W-00b 5 4 CH5_CH4_CFG[1:0] R/W-00b 3 2 CH3_CH2_CFG[1:0] R/W-00b 1 0 CH1_CH0_CFG[1:0] R/W-00b ADVANCE INFORMATION Table 27. AIN_CFG Register Field Descriptions 44 Bit Field Type Reset Description 7-6 CH1_CH0_CFG[1:0] R/W 00b 00b = AIN0 and AIN1 will be 2 separate channels. MUXOUT-M pin connected to AIN-COM pin. Refer to COM_CFG for selecting singleended or pseudo-differential operation. 01b = AIN0 and AIN1 will be a single-ended pair. AIN0will connect to MUXOUT-P and AIN1will connect to MUXOUT-M. 10b = AIN0 and AIN1 will be a pseudo-differential pair. AIN0will connect to MUXOUT-P and AIN1will connect to MUXOUT-M. 11b = Same as 00b. AIN0 and AIN1 will be 2 separate channels. MUXOUT-M pin connected to AIN-COM pin. Refer to COM_CFG for selecting single-ended or pseudo-differential operation. 5-4 CH3_CH2_CFG[1:0] R/W 00b 00b = AIN2 and AIN3 will be 2 separate channels. MUXOUT-M pin connected to AIN-COM pin. Refer to COM_CFG for selecting singleended or pseudo-differential operation. 01b = AIN2 and AIN3 will be a single-ended pair. AIN2will connect to MUXOUT-P and AIN3will connect to MUXOUT-M. 10b = AIN2 and AIN3 will be a pseudo-differential pair. AIN2will connect to MUXOUT-P and AIN3will connect to MUXOUT-M. 11b = Same as 00b. AIN2 and AIN3 will be 2 separate channels. MUXOUT-M pin connected to AIN-COM pin. Refer to COM_CFG for selecting single-ended or pseudo-differential operation. 3-2 CH5_CH4_CFG[1:0] R/W 00b 00b = AIN4 and AIN5 will be 2 separate channels. MUXOUT-M pin connected to AIN-COM pin. Refer to COM_CFG for selecting singleended or pseudo-differential operation. 01b = AIN4 and AIN5 will be a single-ended pair. AIN4will connect to MUXOUT-P and AIN5will connect to MUXOUT-M. 10b = AIN4 and AIN5 will be a pseudo-differential pair. AIN4will connect to MUXOUT-P and AIN5will connect to MUXOUT-M. 11b = Same as 00b. AIN4 and AIN5 will be 2 separate channels. MUXOUT-M pin connected to AIN-COM pin. Refer to COM_CFG for selecting single-ended or pseudo-differential operation. 1-0 CH7_CH6_CFG[1:0] R/W 00b 00b = AIN6 and AIN7 will be 2 separate channels. MUXOUT-M pin connected to AIN-COM pin. Refer to COM_CFG for selecting singleended or pseudo-differential operation. 01b = AIN6 and AIN7 will be a single-ended pair. AIN6will connect to MUXOUT-P and AIN7will connect to MUXOUT-M. 10b = AIN6 and AIN7 will be a pseudo-differential pair. AIN6will connect to MUXOUT-P and AIN7will connect to MUXOUT-M. 11b = Same as 00b. AIN6 and AIN7 will be 2 separate channels. MUXOUT-M pin connected to AIN-COM pin. Refer to COM_CFG for selecting single-ended or pseudo-differential operation. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 ADS8168 www.ti.com SBAS817 – NOVEMBER 2017 7.6.3.2 COM_CFG Register (address = 027h) [reset = 00h] This register selects single-ended or pseudo-differential operation of analog input channels which are not configured as pairs (see the AIN_CFG register). Depending on the contents of this register, AIN-COM must be connected to either GND or REFby2 on the printed-circuit-board. Figure 47. COM_CFG Register 7 0 R-0b 6 0 R-0b 5 0 R-0b 4 0 R-0b 3 0 R-0b 2 0 R-0b 1 0 R-0b 0 COM_CFG R/W-0b Table 28. COM_CFG Register Field Descriptions Bit Field Type Reset Description 7-1 0 R 000 0000b Reserved bits. Reads return 000 0000b. COM_CFG R/W 0b These bits select the analog input channel configuration when CHx_CHy_CFG = 00b or 11b: 0b = AIN[7:0]are single-ended inputs. Connect AIN-COM pin to GND. 1b = AIN[7:0]are pseudo differential input. Connect AIN-COM pin to REFby2. ADVANCE INFORMATION 0 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 45 ADS8168 SBAS817 – NOVEMBER 2017 www.ti.com 7.6.4 Channel Sequence Configuration Registers Map The device features following channel configuration registers, mapped as described in Table 19. Table 29. Channel Sequence Configuration Registers Mapping ADDRESS REGISTER NAME 01Ch DEVICE_CFG Device mode and status REGISTER DESCRIPTION 01Dh CHANNEL_ID Manual channel selection 01Eh SEQ_START Start sequence control 01Fh SEQ_STOP Abort sequence control 02A ON_THE_FLY_CFG Enable/Disable On-The-Fly Mode 080h AUTO_SEQ_CFG1 Auto Sequence mode channel selection 082h AUTO_SEQ_CFG2 Auto Sequence mode loop control 7.6.4.1 DEVICE_CFG Register (address = 01Ch) [reset = 00h] This register selects the mode of channel sequencing and read back returns device status information. Figure 48. DEVICE_CFG Register ADVANCE INFORMATION 7 0 6 0 5 0 4 0 R-0b R-0b R-0b R-0b 3 ALERT_STATU S R-0b 2 ERROR_STAT US R-0b 1 0 SEQ_MODE[1:0] R/W-00b Table 30. DEVICE_CFG Register Field Descriptions Bit Field Type Reset Description 7-4 0 R 0000b Reserved bits. Do not write. Reads return 0000b. 3 ALERT_STATUS R 0b Read only. This bit reflects the ALERT pin logic level. 2 ERROR_STATUS R 0b Read only. Indicates device configuration error: 0b = No error. 1b = Error in configuration. . 1-0 SEQ_MODE[1:0] R/W 00b Sets the MUX channel selection operation: 00b = Manual mode. 01b = On-The-Fly mode. 10b = Auto Sequence mode. 11b = Lookup Based Sequencing mode. The ALERT_STATUS, ERROR_STATUS and SEQ_MODE[1:0] bits can be collectively decoded to indicate events as shown in Table 31. Table 31. Decoding DEVICE_CFG Read Value 46 ALERT_STATUS ERROR_STATUS SEQ_MODE[1:0] EVENT DESCRIPTION 0 0 00 No ALERT, No error, Manual mode. 0 0 01 No ALERT, No error, On-The-Fly mode. 0 0 10 No ALERT, No error, Auto Sequence mode. 0 0 11 No ALERT, No error, Lookup Based Sequencing mode. 0 1 00 No ALERT, Error, Manual mode. 0 1 01 No ALERT, Error, On-The-Fly mode. 0 1 10 No ALERT, Error, Auto Sequence mode. 0 1 11 No ALERT, Error, Lookup Based Sequencing mode. 1 0 00 ALERT, No error, Manual mode. 1 0 01 ALERT, No error, On-The-Fly mode. 1 0 10 ALERT, No error, Auto Sequence mode. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 ADS8168 www.ti.com SBAS817 – NOVEMBER 2017 Table 31. Decoding DEVICE_CFG Read Value (continued) ALERT_STATUS ERROR_STATUS SEQ_MODE[1:0] EVENT DESCRIPTION ALERT, No error, Lookup Based Sequencing mode. 1 0 11 1 1 00 ALERT, Error, Manual mode. 1 1 01 ALERT, Error, On-The-Fly mode. 1 1 10 ALERT, Error, Auto Sequence mode. 11 ALERT, Error, Lookup Based Sequencing mode. 1 1 7.6.4.2 CHANNEL_ID Register (address = 01Dh) [reset = 00h] This register selects the analog input channel; see the Manual Mode section. Figure 49. CHANNEL_ID Register 6 0 R-0b 5 0 R-0b 4 0 R-0b 3 0 R-0b 2 1 CHANNEL_ID[2:0] R/W-000b 0 ADVANCE INFORMATION 7 0 R-0b Table 32. CHANNEL_ID Register Field Descriptions Bit Field Type Reset Description 7-3 0 R 0 0000b Reserved bits. Reads return 0 0000b. 2-0 CHANNEL_ID[2:0] R/W 00000b These bits select the analog input channel as per Table 33. Table 33. Analog input channel selection settings CHANNEL_ID[2:0] ANALOG INPUT SELECTED 000b AIN0 001b AIN1 010b AIN2 011b AIN3 100b AIN4 101b AIN5 110b AIN6 111b AIN7 NOTE Writing to CHANNEL_ID Register (address = 01Dh) [reset = 00h] register, when SEQ_MODE[1:0] = Auto Sequence mode. or SEQ_MODE[1:0] = Lookup Based Sequencing mode, will reset abort the on-going sequence and SEQ_MODE[1:0] will be set to Manual mode.. 7.6.4.3 SEQ_START Register (address = 01Eh) [reset = 00h] This register starts the channel selection sequence when in Auto Channel Sequence mode or Lookup Based Sequencing mode. Writing to this register has no effect when in Manual mode or On-The-Fly mode. Figure 50. SEQ_START Register 7 0 R-0b 6 0 R-0b 5 0 R-0b 4 0 R-0b 3 0 R-0b 2 0 R-0b 1 0 R-0b 0 SEQ_START W-0b Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 47 ADS8168 SBAS817 – NOVEMBER 2017 www.ti.com Table 34. SEQ_START Register Field Descriptions Bit Field Type Reset Description 7-1 0 - - Reserved bits. Do not write. SEQ_START W 0b This bit starts channel scanning sequence when SEQ_MODE[1:0] = Auto Channel Sequence mode or SEQ_MODE[1:0] = Lookup Based Sequencing mode. 0b = No effect. This does not stop an on-going sequence. 1b = Start channel sequence. Refer to Auto Channel Sequence mode and Lookup Based Sequencing mode. 0 7.6.4.4 SEQ_ABORT Register (address = 01Fh) [reset = 00h] This register stops the channel selection sequence when in auto channel sequence mode or lookup based sequencing mode. Writing to this register has no effect when in manual mode or on-the-fly mode. Figure 51. SEQ_ABORT Register 7 0 R-0b 6 0 R-0b 5 0 R-0b 4 0 R-0b 3 0 R-0b 2 0 R-0b 1 0 R-0b 0 SEQ_ABORT W-0b ADVANCE INFORMATION Table 35. SEQ_ABORT Register Field Descriptions Bit Field Type Reset Description 7-1 0 - - Reserved bits. Do not write. SEQ_ABORT W 0b This bit stops channel scanning sequence when SEQ_MODE[1:0] = Auto Channel Sequence mode or SEQ_MODE[1:0] = Lookup Based Sequencing mode. 0b = No effect. 1b = Stop channel sequence. See the Auto Sequence Mode and Custom Channel Sequencing Mode sections. 0 7.6.4.5 ON_THE_FLY_CFG Register (address = 029h) [reset = 00h] This register selects the analog input channel; see the On-The-Fly Mode section. Figure 52. ON_THE_FLY_CFG Register 7 0 6 0 5 0 4 0 3 0 2 0 1 0 R-0b R-0b R-0b R-0b R-0b R-0b R-0b 0 EN_ON_THE_ FLY R/W-0b Table 36. ON_THE_FLY_CFG Register Field Descriptions Bit Field Type Reset Description 7-1 0 R 000 0000b Reserved bits. Reads return 000 0000b. EN_ON_THE_FLY R/W 0b This bit enables the On-The-Fly mode. 0b = On-The-Fly mode disabled. 1b = On-The-Fly mode enabled. First five bits on SDI control the MUX channel ID, Figure 19. 0 7.6.4.6 AUTO_SEQ_CFG1 Register (address = 080h) [reset = 00h] This register selects the channels enabled for auto channel sequence mode. Figure 53. AUTO_SEQ_CFG1 Register 7 EN_AIN7 R/W-0b 48 6 EN_AIN6 R/W-0b 5 EN_AIN5 R/W-0b 4 EN_AIN4 R/W-0b 3 EN_AIN3 R/W-0b Submit Documentation Feedback 2 EN_AIN2 R/W-0b 1 EN_AIN1 R/W-0b 0 EN_AIN0 R/W-0b Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 ADS8168 www.ti.com SBAS817 – NOVEMBER 2017 Bit Field Type Reset Description 7 EN_AIN7 R/W 0b Enable analog input channel 7 in sequence in the auto channel sequence mode, see the Auto Sequence Mode section. 0b = AIN7 not enabled in scanning sequence. 1b = AIN7 enabled in scanning sequence. 6 EN_AIN6 R/W 0b Enable analog input channel 6 in sequence in the auto channel sequence mode. 0b = AIN6 not enabled in scanning sequence. 1b = AIN6 enabled in scanning sequence. 5 EN_AIN5 R/W 0b Enable analog input channel 5 in sequence in the auto channel sequence mode. 0b = AIN5 not enabled in scanning sequence. 1b = AIN5 enabled in scanning sequence. 4 EN_AIN4 R/W 0b Enable analog input channel 4 in sequence in the auto channel sequence mode. 0b = AIN4 not enabled in scanning sequence. 1b = AIN4 enabled in scanning sequence. 3 EN_AIN3 R/W 0b Enable analog input channel 3 in sequence in the auto channel sequence mode. 0b = AIN3 not enabled in scanning sequence. 1b = AIN3 enabled in scanning sequence. 2 EN_AIN2 R/W 0b Enable analog input channel 2 in sequence in the auto channel sequence mode. 0b = AIN2 not enabled in scanning sequence. 1b = AIN2 enabled in scanning sequence. 1 EN_AIN1 R/W 0b Enable analog input channel 1 in sequence in the auto channel sequence mode. 0b = AIN1 not enabled in scanning sequence. 1b = AIN1 enabled in scanning sequence. 0 EN_AIN0 R/W 0b Enable analog input channel 0 in sequence in the auto channel sequence mode. 0b = AIN0 not enabled in scanning sequence. 1b = AIN0 enabled in scanning sequence. 7.6.4.7 AUTO_SEQ_CFG2 Register (address = 082h) [reset = 00h] This register enables sequence loop for Auto Channel Sequence mode. Figure 54. AUTO_SEQ_CFG2 Register 7 0 6 0 5 0 4 0 3 0 2 0 1 0 R-0b R-0b R-0b R-0b R-0b R-0b R-0b 0 AUTO_REPEA T R/W-0b Table 38. AUTO_SEQ_CFG2 Register Field Descriptions Bit Field Type Reset Description 7-1 0 R 000 0000b Reserved bits. Reads return 000 0000b. AUTO_REPEAT R/W 0b Enables looping the sequence indefinitely in Auto Channel Sequence mode. 0b = Sequence will terminate after all enabled channels have been scanned. 1b = Sequence will repeat from the lowest enabled channel after scanning all enabled channels. 0 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 49 ADVANCE INFORMATION Table 37. AUTO_SEQ_CFG1 Register Field Descriptions ADS8168 SBAS817 – NOVEMBER 2017 www.ti.com 7.6.4.8 Custom Channel Sequencing Mode Registers The device features following registers for Custom Channel Sequencing mode, mapped as described in Table 19. Table 39. Custom Channel Sequencing Registers ADDRESS REGISTER NAME REGISTER DESCRIPTION 088h CCS_START_INDEX Start index for Custom Channel Sequencing mode sequence. 089h CCS_STOP_INDEX End index for Custom Channel Sequencing mode sequence. 08Ah CCS_SEQ_LOOP 08Ch CCS_CHID_INDEX_0 08Dh REPEAT_INDEX_0 08Eh CCS_CHID_INDEX_1 08Fh REPEAT_INDEX_1 090h CCS_CHID_INDEX_2 091h REPEAT_INDEX_2 092h CCS_CHID_INDEX_3 Custom Channel Sequencing mode loop control. Channel ID configuration register index 0. Repeat count register index 0. Channel ID configuration register index 1. Repeat count register index 1. Channel ID configuration register index 2. Repeat count register index 2. ADVANCE INFORMATION 093h REPEAT_INDEX_3 094h CCS_CHID_INDEX_4 095h REPEAT_INDEX_4 096h CCS_CHID_INDEX_5 097h REPEAT_INDEX_5 098h CCS_CHID_INDEX_6 099h REPEAT_INDEX_6 09Ah CCS_CHID_INDEX_7 09Bh REPEAT_INDEX_7 09Ch CCS_CHID_INDEX_8 Channel ID configuration register index 3. Repeat count register index 3. Channel ID configuration register index 4. Repeat count register index 4. Channel ID configuration register index 5. Repeat count register index 5. Channel ID configuration register index 6. Repeat count register index 6. Channel ID configuration register index 7. Repeat count register index 7. 09Dh REPEAT_INDEX_8 09Eh CCS_CHID_INDEX_9 09Fh REPEAT_INDEX_9 0A0h CCS_CHID_INDEX_10 0A1h REPEAT_INDEX_10 0A2h CCS_CHID_INDEX_11 0A3h REPEAT_INDEX_11 0A4h CCS_CHID_INDEX_12 0A5h REPEAT_INDEX_12 0A6h CCS_CHID_INDEX_13 Channel ID configuration register index 8. Repeat count register index 8. Channel ID configuration register index 9. Repeat count register index 9. 0A7h REPEAT_INDEX_13 0A8h CCS_CHID_INDEX_14 0A9h REPEAT_INDEX_14 0AAh CCS_CHID_INDEX_15 0ABh REPEAT_INDEX_15 Channel ID configuration register index 10. Repeat count register index 10. Channel ID configuration register index 11. Repeat count register index 11. Channel ID configuration register index 12. Repeat count register index 12. Channel ID configuration register index 13. Repeat count register index 13. Channel ID configuration register index 14. Repeat count register index 13. Channel ID configuration register index 15. Repeat count register index 15. 7.6.4.8.1 CCS_START_INDEX Register (address = 088h) [reset = 00h] This register sets the relative sequence index from which the Lookup Based Sequencing mode starts execution. Figure 55. CCS_START_INDEX Register 7 0 R-0b 50 6 0 R-0b 5 0 R-0b 4 0 R-0b 3 Submit Documentation Feedback 2 1 SEQ_START_INDEX[3:0] R/W-0000b 0 Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 ADS8168 www.ti.com SBAS817 – NOVEMBER 2017 Table 40. CCS_START_INDEX Register Field Descriptions Bit Field Type Reset Description 7-4 0 R 0000b Reserved bits. Reads return 0000b. 3-0 SEQ_START_INDEX[3:0] R/W 0000b Relative pointer to the start index sequence in Lookup Based Sequencing mode. 7.6.4.8.2 CCS_END_INDEX Register (address = 089h) [reset = 00h] This register sets the relative sequence index from which the Lookup Based Sequencing mode starts execution. Figure 56. CCS_END_INDEX Register 7 0 R-0b 6 0 R-0b 5 0 R-0b 4 0 R-0b 3 2 1 SEQ_END_INDEX[3:0] R/W-0000b 0 Field Type Reset Description 7-4 0 R 0000b Reserved bits. Reads return 0000b. 3-0 SEQ_END_INDEX[3:0] R/W 0000b Relative pointer to the end index sequence in Lookup Based Sequencing mode. 7.6.4.8.3 CCS_SEQ_LOOP Register (address = 08Bh) [reset = 00h] This register control the looping of sequence in Custom Channel Sequencing mode. Figure 57. CCS_SEQ_LOOP Register 7 0 R-0b 6 0 R-0b 5 0 R-0b 4 0 R-0b 3 0 R-0b 2 0 R-0b 1 0 R-0b 0 SEQ_LOOP R/W-0b Table 42. CCS_SEQ_LOOP Register Field Descriptions Bit Field Type Reset Description 7-1 0 R 000 0000b Reserved bits. Reads return 000 0000b. SEQ_LOOP R/W 0b Configures the looping of sequence in Lookup Based Sequencing mode. 0b = Sequence will end at index location configured in CCS_END_INDEX[3:0]. 1b = Sequence will resume from CCS_START_INDEX[3:0] after executing CCS_END_INDEX[3:0]. 0 7.6.4.8.4 CCS_CHID_INDEX_m Registers (address = 08C, 08E, 090, 092, 094, 096, 098, 09A, 09C, 09E, 0A0, 0A2, 0A4, 0A6, 0A8, and 0AAh) [reset = 00h] In Lookup Based Sequencing mode, the intended sequence of analog input channels can be programmed in these 16 registers. Refer to REPEAT_INDEX_m for details about repeating a particular channel before switching to the next index. Figure 58. CCS_CHID_INDEX_m Register 7 0 R-0b 6 0 R-0b 5 0 R-0b 4 0 R-0b 3 0 R-0b 2 1 CHID[2:0] R/W-000b 0 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 51 ADVANCE INFORMATION Table 41. CCS_END_INDEX Register Field Descriptions Bit ADS8168 SBAS817 – NOVEMBER 2017 www.ti.com Table 43. CCS_CHID_INDEX_m Register Field Descriptions Bit Field Type Reset Description 7-3 0 R 0 0000b Reserved bits. Reads return 000 0000b. 2-0 CHID[2:0] R/W 000b Configures the analog input channel associated with the index in Lookup Based Sequencing mode. 000b = AIN0 001b = AIN1 010b = AIN2 011b = AIN3 100b = AIN4 101b = AIN5 110b = AIN6 111b = AIN7 7.6.4.8.5 REPEAT_INDEX_m Registers (address = 08D, 08F, 091, 093, 095, 097, 099, 09B, 09D, 09F, 0A1, 0A3, 0A5, 0A7, 0A9, and 0ABh) [reset = 00h] In Lookup Based Sequencing mode, the analog input selected in corresponding CCS_CHID_INDEX can be repeated Refer to REPEAT_INDEX_m for details about repeating a particular channel before switching to the next index. ADVANCE INFORMATION Figure 59. REPEAT_INDEX_m Register 7 6 5 4 3 REPEAT[7:0] R/W-0000 0001b 2 1 0 Table 44. REPEAT_INDEX_m Register Field Descriptions 52 Bit Field Type Reset Description 7-0 REPEAT[7:0] R/W 0000 0001b Configures the number of times the analog input configured in corresponding CCS_CHID_INDEX will be repeated. Configuring 0000 0000b in this register will result in an Error. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 ADS8168 www.ti.com SBAS817 – NOVEMBER 2017 7.6.5 Digital Window Comparator Configuration Registers Map The device features following configuration registers for Digital Window Comparator, mapped as described in Table 45. Table 45. Digital Window Comparator Configuration Registers Mapping REGISTER NAME REGISTER DESCRIPTION 02Eh ALERT_CFG 031h and 030h HI_TRIG_AIN7 ALERT enable control for individual channels. High threshold input for AIN7 Digital Window Comparator. 035h and 034h HI_TRIG_AIN6 High threshold input for AIN6 Digital Window Comparator. 039h and 038h HI_TRIG_AIN5 High threshold input for AIN5 Digital Window Comparator. 03Dh and 03Ch HI_TRIG_AIN4 High threshold input for AIN4 Digital Window Comparator. 041h and 040h HI_TRIG_AIN3 High threshold input for AIN3 Digital Window Comparator. 045h and 044h HI_TRIG_AIN2 High threshold input for AIN2 Digital Window Comparator. 049h and 048h HI_TRIG_AIN1 High threshold input for AIN1 Digital Window Comparator. 04Dh and 04Ch HI_TRIG_AIN0 High threshold input for AIN0 Digital Window Comparator. 055h and 054h LO_TRIG_AIN7 Low threshold input for AIN7 Digital Window Comparator. 059h and 058h LO_TRIG_AIN6 Low threshold input for AIN6 Digital Window Comparator. 05Dh and 05Ch LO_TRIG_AIN5 Low threshold input for AIN5 Digital Window Comparator. 061h and 060h LO_TRIG_AIN4 Low threshold input for AIN4 Digital Window Comparator. 065h and 064h LO_TRIG_AIN3 Low threshold input for AIN3 Digital Window Comparator. 069h and 068h LO_TRIG_AIN2 Low threshold input for AIN2 Digital Window Comparator. 06Dh and 06Ch LO_TRIG_AIN1 Low threshold input for AIN1 Digital Window Comparator. 071h and 070h LO_TRIG_AIN0 Low threshold input for AIN0 Digital Window Comparator. 033h HYSTERESIS_AIN7 Threshold hysteresis for AIN7 Digital Window Comparator. 037h HYSTERESIS_AIN6 Threshold hysteresis for AIN6 Digital Window Comparator. 03Bh HYSTERESIS_AIN5 Threshold hysteresis for AIN5 Digital Window Comparator. 03Fh HYSTERESIS_AIN4 Threshold hysteresis for AIN4 Digital Window Comparator. 043h HYSTERESIS_AIN3 Threshold hysteresis for AIN3 Digital Window Comparator. 047h HYSTERESIS_AIN2 Threshold hysteresis for AIN2 Digital Window Comparator. 04Bh HYSTERESIS_AIN1 Threshold hysteresis for AIN1 Digital Window Comparator. 04Fh HYSTERESIS_AIN0 Threshold hysteresis for AIN0 Digital Window Comparator. 078h ALERT_STATUS 079h ALERT_HI_STATUS Indicates analog input channel-wise ALERT due to high threshold. Indicates analog input channel-wise ALERT due to low threshold. ADVANCE INFORMATION ADDRESS Indicates analog input channel-wise ALERT status. 07Ah ALERT_LO_STATUS 07Ch CURR_ALARM_STATUS Indicates analog input channel-wise ALERT status for last conversion data. 07Dh CURR_ALERT_STATUS Indicates analog input channel-wise ALERT due to high threshold for last conversion data. 07Eh CURR_ALERT_LO_STATUS Indicates analog input channel-wise ALERT due to low threshold for last conversion data. 7.6.5.1 ALERT_CFG Register (address = 02Eh) [reset = 00h] This register enables/disables the ALERT module for individual analog input channels. Figure 60. ALERT_CFG Register 7 ALERT_EN_AI N7 R/W-0b 6 ALERT_EN_AI N6 R/W-0b 5 ALERT_EN_AI N5 R/W-0b 4 ALERT_EN_AI N4 R/W-0b 3 ALERT_EN_AI N3 R/W-0b 2 ALERT_EN_AI N2 R/W-0b 1 ALERT_EN_AI N1 R/W-0b 0 ALERT_EN_AI N0 R/W-0b Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 53 ADS8168 SBAS817 – NOVEMBER 2017 www.ti.com Table 46. ALERT_CFG Register Field Descriptions Bit ADVANCE INFORMATION Field Type Reset Description 7 ALERT_EN_AIN7 R/W 0b Digital Window Comparator control for AIN7. 0b = Digital Window Comparator disabled. 1b = Digital Window Comparator enabled. 6 ALERT_EN_AIN6 R/W 0b Digital Window Comparator control for AIN6. 0b = Digital Window Comparator disabled. 1b = Digital Window Comparator enabled. 5 ALERT_EN_AIN5 R/W 0b Digital Window Comparator control for AIN5. 0b = Digital Window Comparator disabled. 1b = Digital Window Comparator enabled. 4 ALERT_EN_AIN4 R/W 0b Digital Window Comparator control for AIN4. 0b = Digital Window Comparator disabled. 1b = Digital Window Comparator enabled. 3 ALERT_EN_AIN3 R/W 0b Digital Window Comparator control for AIN3. 0b = Digital Window Comparator disabled. 1b = Digital Window Comparator enabled. 2 ALERT_EN_AIN2 R/W 0b Digital Window Comparator control for AIN2. 0b = Digital Window Comparator disabled. 1b = Digital Window Comparator enabled. 1 ALERT_EN_AIN1 R/W 0b Digital Window Comparator control for AIN1. 0b = Digital Window Comparator disabled. 1b = Digital Window Comparator enabled. 0 ALERT_EN_AIN0 R/W 0b Digital Window Comparator control for AIN0. 0b = Digital Window Comparator disabled. 1b = Digital Window Comparator enabled. When Digital Window Comparator is disabled, the bits corresponding to the disabled Digital Window Comparator will not be updated inALARM_STATUS, ALARM_HI_STATUS, ALARM_LO_STATUS, CURR_ALARM_STATUS, CURR_ALARM_HI_STATUS, and CURR_ALARM_LO_STATUS registers. 7.6.5.2 HI_TRIG_AIN[7:0] Register (address = 04Dh to 030h) [reset = 0000h] This bank of registers configures high threshold for Digital Window Comparator. For 16-bit ADC data output, the comparator thresholds are 16-bits wide. Hence the 16-bit high threshold is spread over two 8-bit registers for every analog input channel as shown in register address map. Table 47. Register Address Map For HI_TRIG_AIN[7:0] ANALOG INPUT REGISTER ADDRESS FOR HI_TRIG[15:8] REGISTER ADDRESS FOR HI_TRIG[7:0] AIN7 031h 030h AIN6 035h 034h AIN5 039h 038h AIN4 03Dh 03Ch AIN3 041h 040h AIN2 045h 044h AIN1 049h 048h AIN0 04Dh 04Ch Figure 61. MSB Byte Register for HI_TRIG_AIN[7:0] 7 54 6 5 4 3 HI_TRIG[15:8] R/W-0000 0000b Submit Documentation Feedback 2 1 0 Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 ADS8168 www.ti.com SBAS817 – NOVEMBER 2017 Figure 62. LSB Byte Register for HI_TRIG_AIN[7:0] 7 6 5 4 3 HI_TRIG[7:0] R/W-0000 0000b 2 1 0 Table 48. HI_TRIG_AIN[7:0] Registers Field Descriptions Bit 15:0 Field Type Reset Description HI_TRIG[15:0] R/W 0000 0000 0000 0000b High threshold for Digital Window Comparator. 7.6.5.3 LO_TRIG_AIN[7:0] Register (address = 071h to 054h) [reset = 0000h] This bank of registers configures low threshold for Digital Comparator. For 16-bit ADC data output, the comparator thresholds are 16-bits wide. Hence the 16-bit low threshold is spread over 2 registers for every analog input channel as shown in register address map. ANALOG INPUT REGISTER ADDRESS FOR LO_TRIG[15:8] REGISTER ADDRESS FOR LO_TRIG[7:0] AIN7 051h 054h AIN6 059h 058h AIN5 05Dh 05Ch AIN4 061h 060h AIN3 065h 064h AIN2 069h 068h AIN1 06Dh 06Ch AIN0 071h 070h ADVANCE INFORMATION Table 49. Register Address Map For LO_TRIG_AIN[7:0] Figure 63. MSB Byte Register for LO_TRIG_AIN[7:0] 7 6 5 4 3 LO_TRIG[15:8] R/W-0000 0000b 2 1 0 1 0 Figure 64. LSB Byte Register for LO_TRIG_AIN[7:0] 7 6 5 4 3 LO_TRIG[7:0] R/W-0000 0000b 2 Table 50. LO_TRIG_AIN[7:0] Registers Field Descriptions Bit 15:0 Field Type Reset Description LO_TRIG[15:0] R/W 0000 0000 0000 0000b Low threshold for Digital Window Comparator. 7.6.5.4 HYSTERESIS_AIN[7:0] Register (address = 04Fh to 033h) [reset = 00h] This bank of registers configures hysteresis around threshold for Digital Window Comparator. For 16-bit ADC data output, the hysteresis is 6-bit wide. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 55 ADS8168 SBAS817 – NOVEMBER 2017 www.ti.com Figure 65. HYSTERESIS_AIN[7:0] Registers 7 6 5 4 HYSTERESIS[5:0] R/W-00 0000b 3 2 1 0 R-0b 0 0 R-0b Table 51. HYSTERESIS_AIN[7:0] Registers Field Descriptions Bit Field Type Reset Description 7:2 HYSTERESIS[5:0] R/W 000 0000b Low threshold for Digital Window Comparator. 7.6.5.5 ALERT_STATUS Register (address = 078h) [reset = 00h] This register reflects the ALERT status for the analog input channels. Figure 66. ALERT_STATUS Register 7 ALERT_AIN7 R-0b 6 ALERT_AIN6 R-0b 5 ALERT_AIN5 R-0b 4 ALERT_AIN4 R-0b 3 ALERT_AIN3 R-0b 2 ALERT_AIN2 R-0b 1 ALERT_AIN1 R-0b 0 ALERT_AIN0 R-0b ADVANCE INFORMATION Table 52. ALERT_STATUS Register Field Descriptions Bit Field Type Reset Description 7 ALERT_AIN7 R 0b This bit indicates either high or low threshold for AIN7 was exceeded. 0b = Both high threshold and low threshold not exceeded. 1b = High threshold or low threshold or both have been exceeded. 6 ALERT_AIN6 R 0b This bit indicates either high or low threshold for AIN6 was exceeded. 0b = Both high threshold and low threshold not exceeded. 1b = High threshold or low threshold or both have been exceeded. 5 ALERT_AIN5 R 0b This bit indicates either high or low threshold for AIN5 was exceeded. 0b = Both high threshold and low threshold not exceeded. 1b = High threshold or low threshold or both have been exceeded. 4 ALERT_AIN4 R 0b This bit indicates either high or low threshold for AIN4 was exceeded. 0b = Both high threshold and low threshold not exceeded. 1b = High threshold or low threshold or both have been exceeded. 3 ALERT_AIN3 R 0b This bit indicates either high or low threshold for AIN3 was exceeded. 0b = Both high threshold and low threshold not exceeded. 1b = High threshold or low threshold or both have been exceeded. 2 ALERT_AIN2 R 0b This bit indicates either high or low threshold for AIN2 was exceeded. 0b = Both high threshold and low threshold not exceeded. 1b = High threshold or low threshold or both have been exceeded. 1 ALERT_AIN1 R 0b This bit indicates either high or low threshold for AIN1 was exceeded. 0b = Both high threshold and low threshold not exceeded. 1b = High threshold or low threshold or both have been exceeded. 0 ALERT_AIN0 R 0b This bit indicates either high or low threshold for AIN0 was exceeded. 0b = Both high threshold and low threshold not exceeded. 1b = High threshold or low threshold or both have been exceeded. If the ALERT bit for a particular channel is set in, it can be cleared by writing 1b to the corresponding bit in ALARM_HI_STATUS or ALARM_LO_STATUS registers. If both high and low thresholds were exceeded, corresponding channel bit in both ALARM_HI_STATUS and ALARM_LO_STATUS registers must be set to 1b to clear the ALERT. 7.6.5.6 ALERT_HI_STATUS Register (address = 079h) [reset = 00h] This register reflects the high threshold ALERT status for the analog input channels. 56 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 ADS8168 www.ti.com SBAS817 – NOVEMBER 2017 Figure 67. ALERT_HI_STATUS Register 7 6 5 4 3 2 1 0 ALERT_HI_AIN ALERT_HI_AIN ALERT_HI_AIN ALERT_HI_AIN ALERT_HI_AIN ALERT_HI_AIN ALERT_HI_AIN ALERT_HI_AIN 7 6 5 4 3 2 1 0 R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b Bit Field Type Reset Description 7 ALERT_HI_AIN7 R/W 0b This bit indicates high threshold for AIN7 was exceeded. 0b = High threshold not exceeded. 1b = High exceeded. This bit can be cleared by writing 1b to it. 6 ALERT_HI_AIN6 R/W 0b This bit indicates high threshold for AIN6 was exceeded. 0b = High threshold not exceeded. 1b = High exceeded. This bit can be cleared by writing 1b to it. 5 ALERT_HI_AIN5 R/W 0b This bit indicates high threshold for AIN5 was exceeded. 0b = High threshold not exceeded. 1b = High exceeded. This bit can be cleared by writing 1b to it. 4 ALERT_HI_AIN4 R/W 0b This bit indicates high threshold for AIN4 was exceeded. 0b = High threshold not exceeded. 1b = High exceeded. This bit can be cleared by writing 1b to it. 3 ALERT_HI_AIN3 R/W 0b This bit indicates high threshold for AIN3 was exceeded. 0b = High threshold not exceeded. 1b = High exceeded. This bit can be cleared by writing 1b to it. 2 ALERT_HI_AIN2 R/W 0b This bit indicates high threshold for AIN2 was exceeded. 0b = High threshold not exceeded. 1b = High exceeded. This bit can be cleared by writing 1b to it. 1 ALERT_HI_AIN1 R/W 0b This bit indicates high threshold for AIN1 was exceeded. 0b = High threshold not exceeded. 1b = High exceeded. This bit can be cleared by writing 1b to it. 0 ALERT_HI_AIN0 R/W 0b This bit indicates high threshold for AIN0 was exceeded. 0b = High threshold not exceeded. 1b = High exceeded. This bit can be cleared by writing 1b to it. If the ALERT bit for a particular channel is set in, it can be cleared by writing 1b to the corresponding bit in ALARM_HI_STATUS or ALARM_LO_STATUS registers. If both high and low thresholds were exceeded, corresponding channel bit in both ALARM_HI_STATUS and ALARM_LO_STATUS registers must be set to 1b to clear the ALERT. 7.6.5.7 ALERT_LO_STATUS Register (address = 07Ah) [reset = 00h] This register reflects the low threshold ALERT status for the analog input channels. Figure 68. ALERT_LO_STATUS Register 7 ALERT_LO_AI N7 R/W-0b 6 ALERT_LO_AI N6 R/W-0b 5 ALERT_LO_AI N5 R/W-0b 4 ALERT_LO_AI N4 R/W-0b 3 ALERT_LO_AI N3 R/W-0b 2 ALERT_LO_AI N2 R/W-0b 1 ALERT_LO_AI N1 R/W-0b 0 ALERT_LO_AI N0 R/W-0b Table 54. ALERT_LO_STATUS Register Field Descriptions Bit Field Type Reset Description 7 ALERT_LO_AIN7 R/W 0b This bit indicates high threshold for AIN7 was exceeded. 0b = High threshold not exceeded. 1b = High exceeded. This bit can be cleared by writing 1b to it. 6 ALERT_LO_AIN6 R/W 0b This bit indicates high threshold for AIN6 was exceeded. 0b = High threshold not exceeded. 1b = High exceeded. This bit can be cleared by writing 1b to it. 5 ALERT_LO_AIN5 R/W 0b This bit indicates high threshold for AIN5 was exceeded. 0b = High threshold not exceeded. 1b = High exceeded. This bit can be cleared by writing 1b to it. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 57 ADVANCE INFORMATION Table 53. ALERT_HI_STATUS Register Field Descriptions ADS8168 SBAS817 – NOVEMBER 2017 www.ti.com Table 54. ALERT_LO_STATUS Register Field Descriptions (continued) Bit Field Type Reset Description 4 ALERT_LO_AIN4 R/W 0b This bit indicates high threshold for AIN4 was exceeded. 0b = High threshold not exceeded. 1b = High exceeded. This bit can be cleared by writing 1b to it. 3 ALERT_LO_AIN3 R/W 0b This bit indicates high threshold for AIN3 was exceeded. 0b = High threshold not exceeded. 1b = High exceeded. This bit can be cleared by writing 1b to it. 2 ALERT_LO_AIN2 R/W 0b This bit indicates high threshold for AIN2 was exceeded. 0b = High threshold not exceeded. 1b = High exceeded. This bit can be cleared by writing 1b to it. 1 ALERT_LO_AIN1 R/W 0b This bit indicates high threshold for AIN1 was exceeded. 0b = High threshold not exceeded. 1b = High exceeded. This bit can be cleared by writing 1b to it. 0 ALERT_LO_AIN0 R/W 0b This bit indicates high threshold for AIN0 was exceeded. 0b = High threshold not exceeded. 1b = High exceeded. This bit can be cleared by writing 1b to it. ADVANCE INFORMATION If the ALERT bit for a particular channel is set in, it can be cleared by writing 1b to the corresponding bit in ALARM_HI_STATUS or ALARM_LO_STATUS registers. If both high and low thresholds were exceeded, corresponding channel bit in both ALARM_HI_STATUS and ALARM_LO_STATUS registers must be set to 1b to clear the ALERT. 7.6.5.8 CURR_ALERT_STATUS Register (address = 07Ch) [reset = 00h] This register reflects the ALERT status for the analog input channels. Figure 69. CURR_ALERT_STATUS Register 7 ALERT_AIN7 R-0b 6 ALERT_AIN6 R-0b 5 ALERT_AIN5 R-0b 4 ALERT_AIN4 R-0b 3 ALERT_AIN3 R-0b 2 ALERT_AIN2 R-0b 1 ALERT_AIN1 R-0b 0 ALERT_AIN0 R-0b Table 55. CURR_ALERT_STATUS Register Field Descriptions Bit 58 Field Type Reset Description 7 ALERT_AIN7 R 0b This bit indicates either high or low threshold for AIN7 was exceeded by the last converted data from channel AIN7. 0b = Both high threshold and low threshold not exceeded. 1b = High threshold or low threshold or both have been exceeded. 6 ALERT_AIN6 R 0b This bit indicates either high or low threshold for AIN6 was exceeded by the last converted data from channel AIN6. 0b = Both high threshold and low threshold not exceeded. 1b = High threshold or low threshold or both have been exceeded. 5 ALERT_AIN5 R 0b This bit indicates either high or low threshold for AIN5 was exceeded by the last converted data from channel AIN5. 0b = Both high threshold and low threshold not exceeded. 1b = High threshold or low threshold or both have been exceeded. 4 ALERT_AIN4 R 0b This bit indicates either high or low threshold for AIN4 was exceeded by the last converted data from channel AIN4. 0b = Both high threshold and low threshold not exceeded. 1b = High threshold or low threshold or both have been exceeded. 3 ALERT_AIN3 R 0b This bit indicates either high or low threshold for AIN3 was exceeded by the last converted data from channel AIN3. 0b = Both high threshold and low threshold not exceeded. 1b = High threshold or low threshold or both have been exceeded. 2 ALERT_AIN2 R 0b This bit indicates either high or low threshold for AIN2 was exceeded by the last converted data from channel AIN2. 0b = Both high threshold and low threshold not exceeded. 1b = High threshold or low threshold or both have been exceeded. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 ADS8168 www.ti.com SBAS817 – NOVEMBER 2017 Table 55. CURR_ALERT_STATUS Register Field Descriptions (continued) Bit Field Type Reset Description 1 ALERT_AIN1 R 0b This bit indicates either high or low threshold for AIN1 was exceeded by the last converted data from channel AIN1. 0b = Both high threshold and low threshold not exceeded. 1b = High threshold or low threshold or both have been exceeded. 0 ALERT_AIN0 R 0b This bit indicates either high or low threshold for AIN0 was exceeded by the last converted data from channel AIN0. 0b = Both high threshold and low threshold not exceeded. 1b = High threshold or low threshold or both have been exceeded. Bits in this register are a logical OR of the corresponding channel bits in CURR_ALARM_HI_STATUS and CURR_ALARM_LO_STATUS. The status of individual bits is evaluated on every conversion. These bits indicate the ALERT status of the latest conversion data from the corresponding analog input channels. 7.6.5.9 CURR_ALERT_HI_STATUS Register (address = 07Dh) [reset = 00h] This register reflects the high threshold ALERT status for the analog input channels. 7 6 5 4 3 2 1 0 ALERT_HI_AIN ALERT_HI_AIN ALERT_HI_AIN ALERT_HI_AIN ALERT_HI_AIN ALERT_HI_AIN ALERT_HI_AIN ALERT_HI_AIN 7 6 5 4 3 2 1 0 R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b Table 56. CURR_ALERT_HI_STATUS Register Field Descriptions Bit Field Type Reset Description 7 ALERT_HI_AIN7 R 0b This bit indicates high threshold for AIN7 was exceeded by the last converted data from channel AIN7. 0b = High threshold not exceeded. 1b = High exceeded. 6 ALERT_HI_AIN6 R 0b This bit indicates high threshold for AIN6 was exceeded by the last converted data from channel AIN6. 0b = High threshold not exceeded. 1b = High exceeded. 5 ALERT_HI_AIN5 R 0b This bit indicates high threshold for AIN5 was exceeded by the last converted data from channel AIN5. 0b = High threshold not exceeded. 1b = High exceeded. 4 ALERT_HI_AIN4 R 0b This bit indicates high threshold for AIN4 was exceeded by the last converted data from channel AIN4. 0b = High threshold not exceeded. 1b = High exceeded. 3 ALERT_HI_AIN3 R 0b This bit indicates high threshold for AIN3 was exceeded by the last converted data from channel AIN3. 0b = High threshold not exceeded. 1b = High exceeded. 2 ALERT_HI_AIN2 R 0b This bit indicates high threshold for AIN2 was exceeded by the last converted data from channel AIN2. 0b = High threshold not exceeded. 1b = High exceeded. 1 ALERT_HI_AIN1 R 0b This bit indicates high threshold for AIN1 was exceeded by the last converted data from channel AIN1. 0b = High threshold not exceeded. 1b = High exceeded. 0 ALERT_HI_AIN0 R 0b This bit indicates high threshold for AIN0 was exceeded by the last converted data from channel AIN0. 0b = High threshold not exceeded. 1b = High exceeded. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 59 ADVANCE INFORMATION Figure 70. CURR_ALERT_HI_STATUS Register ADS8168 SBAS817 – NOVEMBER 2017 www.ti.com The status of individual bits is evaluated on every conversion. These bits indicate the ALERT status of the latest conversion data from the corresponding analog input channels. 7.6.5.10 CURR_ALERT_LO_STATUS Register (address = 07Eh) [reset = 00h] This register reflects the low threshold ALERT status for the analog input channels. Figure 71. CURR_ALERT_LO_STATUS Register 7 ALERT_LO_AI N7 R-0b 6 ALERT_LO_AI N6 R-0b 5 ALERT_LO_AI N5 R-0b 4 ALERT_LO_AI N4 R-0b 3 ALERT_LO_AI N3 R-0b 2 ALERT_LO_AI N2 R-0b 1 ALERT_LO_AI N1 R-0b 0 ALERT_LO_AI N0 R-0b Table 57. CURR_ALERT_LO_STATUS Register Field Descriptions Bit ADVANCE INFORMATION Field Type Reset Description 7 ALERT_LO_AIN7 R 0b This bit indicates high threshold for AIN7 was exceeded by the last converted data from channel AIN7. 0b = High threshold not exceeded. 1b = High exceeded. 6 ALERT_LO_AIN6 R 0b This bit indicates high threshold for AIN6 was exceeded by the last converted data from channel AIN6. 0b = High threshold not exceeded. 1b = High exceeded. 5 ALERT_LO_AIN5 R 0b This bit indicates high threshold for AIN5 was exceeded by the last converted data from channel AIN5. 0b = High threshold not exceeded. 1b = High exceeded. 4 ALERT_LO_AIN4 R 0b This bit indicates high threshold for AIN4 was exceeded by the last converted data from channel AIN4. 0b = High threshold not exceeded. 1b = High exceeded. 3 ALERT_LO_AIN3 R 0b This bit indicates high threshold for AIN3 was exceeded by the last converted data from channel AIN3. 0b = High threshold not exceeded. 1b = High exceeded. 2 ALERT_LO_AIN2 R 0b This bit indicates high threshold for AIN2 was exceeded by the last converted data from channel AIN2. 0b = High threshold not exceeded. 1b = High exceeded. 1 ALERT_LO_AIN1 R 0b This bit indicates high threshold for AIN1 was exceeded by the last converted data from channel AIN1. 0b = High threshold not exceeded. 1b = High exceeded. 0 ALERT_LO_AIN0 R 0b This bit indicates high threshold for AIN0 was exceeded by the last converted data from channel AIN0. 0b = High threshold not exceeded. 1b = High exceeded. The status of individual bits is evaluated on every conversion. These bits indicate the ALERT status of the latest conversion data from the corresponding analog input channels. 60 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 ADS8168 www.ti.com SBAS817 – NOVEMBER 2017 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information Conventional multi-channel ADC solutions internally connect the multiplexer output directly to the switched capacitor input of the ADC. In this case, a wide bandwidth amplifier is required for each channel, whereas the ADS8168 only requires one for many applications. The ADS8168 solution shown in Figure 72 has lower power, smaller PCB area, and lower cost compared to the comparative solution. Furthermore, from a calibration perspective, the offset error is the same in each channel and is set by the multiplexer output amplifier. The offset error in the conventional solution, on the other hand, is different for each channel. To calibrate the offset error for the conventional solution would require a separate calibration for each channel. High Bandwidth Amplifier OPA320 VIN0 AIN0 VIN1 AIN1 ADC-INP AIN0 ADC VIN2 AIN2 VIN0 + AIN1 + AIN2 ADC MUXOUT-P VIN7 AIN7 AIN7 VIN7 + Sequencer ADS8168 Solution ± Single Wide Bandwidth Amplifier Conventional Solution ± Eight Wide Bandwidth Amplifiers Figure 72. Small Size and Low Power 8-Channel DAQ System Using the ADS8168 When connecting the sensor directly to the input of the ADS8168, the maximum switching speed of the multiplexer is limited by multiplexer ON-resistance and parasitic capacitance. Figure 73 shows the source resistance (RS0, RS1…), multiplexer impedance (RMUX), multiplexer capacitance (CMUX), op amp input capacitance (COPA), and the stray PCB capacitance at the output of the multiplexer (CSTRAY). In this example, the total at the output capacitance is the combination of the multiplexer output capacitance, the op amp input capacitance and the stray capacitance (CMUX + COPA + CSTRAY) = 15-pF). When switching to a channel, this capacitance needs to be charged to the sensor output voltage via the source resistance and the multiplexer resistance (RS0 + RMUX). Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 61 ADVANCE INFORMATION 8.1.1 Multiplexer Input Connection ADS8168 SBAS817 – NOVEMBER 2017 www.ti.com Application Information (continued) OPA320 RS0 1000 AIN0 RMUX 40 SW RFLT 50 ADC-INP RS1 50 SW MUXOUT-P + AIN1 CMUX 13pF SW CFLT 1.2nF CS1 60pF COPA + CSTRAY Sensor 0 RS7 1000 AIN2 SW AIN7 SW ADC-INM RS2 50 SW CS2 60pF MUXOUT-M AIN-COM RFLT 50 MUX CFLT 1.2nF ADC Sensor 7 ADVANCE INFORMATION Figure 73. Direct Sensor Interface With ADS8168 in an 8-Channel, Single-Ended Configuration NTC = lnM (2N ) = lnM (216) = 11.09 (2) Equation 2 can be used to estimate the number of time constants required for N-bits of settling. For this example, to achieve 16-bit settling, 11.09 time constants are required. Thus, for channel 0 the required settling time is 167ns, as computed in Equation 3 and Equation 4. Settling time required = (RS0 + RMUX) × (CMUX + COPA + CSTRAY) × NTC Settling time required = (1kΩ) × (15pF) × 11.09 = 167ns (3) (4) When operating at 1-MSPS in either manual mode, auto channel sequence mode, or custom channel sequencing mode, 900-ns settling time is available at the analog inputs of the multiplexer as shown in Early Switching for Direct Sensor Interface. Using Equation 4, the maximum sensor output impedance for direct connection is 5.4-kΩ. In some applications, such as temperature sensing, the sensor output impedance can be greater than 10-kΩ. When scanning the multiplexer channels at high throughput, the relatively higher driving impedance results in settling error. In such cases, the multiplexer inputs can be driven using an amplifier as shown in Figure 74. The multiplexer outputs can be connected to ADC inputs directly. For best distortion performance, an amplifier can be used between multiplexer and ADC as described in Selecting ADC Input Buffer. 62 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 ADS8168 www.ti.com SBAS817 – NOVEMBER 2017 Application Information (continued) MUXOUT-P ADC-INP RFLT_MUX 55 RS0 >10 k AIN0 + OPA320 ADS8168 AIN1 CFLT_MUX 1 nF AIN2 ADC Sensor 0 RFLT_MUX 55 RS7 >10 k AIN7 OPA320 CFLT_MUX 1 nF MUXOUT-M ADC-INM Sensor 7 Figure 74. High Output Impedance Sensor Interface 8.1.2 Selecting ADC Input Buffer Figure 75 shows the external amplifier, charge bucket filter, and sample-and-hold circuit at the ADC input for the ADS8168. To understand the design procedure for selecting the amplifier and RC filter, it is helpful to have a short background on the conversion process. The conversion process is broken up into two phases: the acquisition phase and the conversion phase. During the acquisition phase the switches SW are closed, and the input signal is stored on the sample and hold capacitors, CS1 and CS2. After the acquisition phase, the switches will open and the voltage stored on the capacitors is converted to digital code by the SAR algorithm. This conversion process will deplete the charge on the sample and hold capacitors. During subsequent acquisition cycles, the sample and hold capacitor will have to be charged to ADC input voltage which may make step changes in value as each input may be from a different multiplexer channel. For example, if AIN0 is connected to 4 V and AIN1 is connected to 0.5 V, the sample and hold will have to charge to 4-V for the first acquisition cycle and 0.5 V for the second acquisition cycle. When running at high throughput, the acquisition time will be small and a wide bandwidth amplifier is required for proper settling at ADC inputs (minimum acquisition time for ADS8168 is tACQ = 330 ns). The RC filter (RFLT and CFLT) is designed to provide a reservoir of charge that will help charge the internal sample and hold capacitor rapidly at the start of the acquisition period. For this reason, the RC filter is sometimes called a “charge bucket” or “charge kickback” filter. In this section we will provide a method for determining the required amplifier bandwidth and the values of the RC charge bucket filter. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 63 ADVANCE INFORMATION + ADS8168 SBAS817 – NOVEMBER 2017 www.ti.com Application Information (continued) OPA320 RFLT 50 ADC-INP RS1 50 SW + MUXOUT-P CFLT 1.2nF CS1 60pF ADC-INM RS2 50 SW CS2 60pF MUXOUT-M ADVANCE INFORMATION RFLT 50 CFLT 1.2nF ADC Figure 75. Driving ADC Inputs (ADC-INP and ADC-INM) A summary of the equations and an example calculation is provided to determine the amplifier bandwidth and RC charge bucket circuit for the ADS8168 assuming minimum ADC acquisition time. Equation 8 finds the amplifier time constant and Equation 9 uses this to computer the amplifiers required unity gain bandwidth. CSH 60pF,t ACQ 330ns,N 16bits,VREF 4.096V (5) LSB VREF 4.096V N 216 2 WC (6) t ACQ § 0.5 u LSB · In ¨ ¸ © 100mV ¹ WAMP UGBW 330ns § 0.5 u (62.5PV) · In ¨ ¸ 100mV © ¹ WC 40.9ns 17 17 1 2S u WAMP 62.5PV 40.9ns (7) 9.917ns (8) 1 2S u (9.917ns) 16MHz (9) The value of CFLT is computed in Equation 10 by taking twenty times the internal sample and hold capacitance. The factor of twenty is a rule of thumb that is intended to minimize the droop in voltage on the charge bucket capacitor, CFLT, after the start of the acquisition period. The filter resistor, RFLT, is computed in Equation 11 using the op amp time constant and CFLT. Note that these equations model the system as a first order system, and in reality the system is a higher order. Consequently, the values may need to be adjusted to optimize performance. This optimization and more details on the math behind the component selection are covered in ADC Precision Labs. CFLT 20 u CFLT 20 u (60pF) 1.2nF (10) 4 u WAMP CFLT RFLT RFLTMin RFLTMax 64 4 u (9.917ns) 1.2nF 0.25 u RFLT 2 u RFLT 33.05: (11) 0.25 u (33:) 2 u (33:) 8.3: (12) 66.1: (13) Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 ADS8168 www.ti.com SBAS817 – NOVEMBER 2017 8.2 Typical Applications 8.2.1 1-MSPS DAQ Circuit With Lowest Distortion and Noise Performance An 8-channel and 1-MSPS solution with minimum external components is shown in Figure 76. This solution significantly reduces solution size and power by not requiring amplifiers on every analog input. OPA320 50 + 1.2 nF 107 ADVANCE INFORMATION ADS8168 AIN0 AIN1 560 pF AIN2 MUXOUT-P ADC-INP Interface ADC 107 ADC-INM AIN7 MUXOUT-M REFP 560 pF 20 µF 107 AIN-COM REFby2 ÷2 560 pF 1 µF REFIO Sequencer 4.096 V 1 µF 50 1.2 nF Figure 76. 1-MSPS DAQ Circuit With Lowest Distortion and Noise Performance 8.2.1.1 Design Requirements For this example, the design parameters are listed in Table 58. Table 58. Design Parameters DESIGN PARAMETER EXAMPLE VALUE SNR ≥ 92-dB THD ≤ -108-dB Throughput 1-MSPS Input signal frequency ≤100-kSPS Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 65 ADS8168 SBAS817 – NOVEMBER 2017 www.ti.com 8.2.1.2 Detailed Design Procedure The general design procedure below can be used for any ADS8168 application circuit. The final design for this example is shown in Example Schematic. • All ADS8168 applications require the supply and reference decoupling as given in the Example Schematic and Layout sections. • Select the buffer amplifier and associated charge bucket filter between the multiplexer output and ADC input using the method described in the Selecting ADC Input Buffer. The values given in this section meet the maximum throughput and input signal frequency design requirements given. A lower bandwidth solution could be used in cases where lower power is required. • Select an input amplifier for rapid settling when the multiplexer switches channels. This selection is covered in the Multiplexer Input Connection. The OPA320 buffer and associated RC filter shown in Figure 74 meet these requirements. 8.2.1.3 Application Curve 0 -36 Amplitude (dB) ADVANCE INFORMATION -72 -108 -144 -180 0 100 200 300 fIN, Input Frequency (kHz) 400 500 D001 fIN = 2-kHz, 92-dB SNR, -109-dB THD Figure 77. FFT Plot: ADS8168 66 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 ADS8168 www.ti.com SBAS817 – NOVEMBER 2017 8.2.2 1-MSPS DAQ Circuit for Factory Automation The circuit in Figure 8 shows an example of how the ADS8168 can be used for a factory automation application. AVDD +5V Supply Current Sensor 1 Supply Wiring Impedance VSUP_DROP T GND1 -80mV VGND_DROP AVDD Sensor 2 AIN0 ADS8168 VSUP_DROP ADVANCE INFORMATION AIN1 AIN2 T AIN3 GND2 -60mV VGND_DROP ADC AIN4 AIN5 AIN6 Sensor 3 GND VSUP_DROP Ground Wiring Impedance AIN7 T GND3 -40mV VGND_DROP ADC GND 0V Sensor 4 T GND4 -20mV VGND_DROP Ground return current Figure 78. Remote Ground Sense With the ADS8168 in Factory Automation 8.2.2.1 Design Requirements The goal of this design to sense outputs from four sensors, each sensor being at different ground potentials. 8.2.2.2 Detailed Design Procedure In Figure 78, the sensors are connected over long leads to the supply, ground, and ADC inputs. Voltage drop due to ground wiring impedance will cause the ground connections to be at different potentials for each sensor. The ADS8168 can be configured into four single-ended pairs with remote ground sense as described in Multiplexer Configurations. In this input configuration, the error in ground potential is sensed and accounted for in the measurement. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 67 ADS8168 SBAS817 – NOVEMBER 2017 www.ti.com The ADC negative input can sense ground voltages of ±100-mV. The ADC has digital window comparators that can be programed to set an alarm if the sensor output is out of range. Many industrial applications require isolation. When scanning all the channels at 1Msps, the serial clock rate can be as low as 16-MHz. This clock rate is suitable for most isolators. Using a common amplifier to drive the ADC input simplifies calibration as all channels have a common error. ADVANCE INFORMATION 68 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 ADS8168 www.ti.com SBAS817 – NOVEMBER 2017 8.2.3 8-Channel Photodiode Detector With Smallest Size and Lowest Number of Components The circuit in Figure 79 shows an 8-channel photodiode detector using the ADS8168. In this example, one common amplifier is used for eight photodiodes. A detailed description of the transimpedance amplifier is given in TI Precision Designs. 3.6pF 43.2k 5V 0µA to 90µA 49.9 + OPA320 VB = 0.1V 3.6pF 0µA to 90µA ADC-INP AIN0 ADC AIN1 AIN1 MUXOUT-P AIN7 VREF VB = 0.1V 10k AIN7 4.096V ÷2 SFH213 REFby2 Sequencer 500 ADS8168 ADS8168 Solution ± Single Wide Bandwidth Amplifier Figure 79. Small Size, 8-channel Photo Detector 8.2.3.1 Design Requirements The objective of this design is to achieve: • Smallest solution size. • Transimpedance output of 0.1-V to 4-V for a 0-µA to 90-µA input with a bandwidth of 1-MHz. • The voltage divider is designed to provide a minimum amplifier output of 0.1-V when the photodiode current is zero (dark current). This prevents the amplifier from saturating to the negative rail. 8.2.3.2 Detailed Design Procedure In Figure 79, the photodiodes are connected to the multiplexer input in photovoltaic mode. Depending on the application requirements, either photovoltaic mode or photoconductive mode can be used. The multiplexer in the ADS8168 is used as a current multiplexer in this example. One common amplifier for all photodiodes reduces cost, complexity, PCB area, and power consumption. It also simplifies system calibration as the gain and offset error is the same for all channels. Finally, the low leakage current of the multiplexer is ideal for photodiode applications OPA320 is used as a transimpedance amplifier that can also drive the ADC inputs. In order to set the output voltage of OPA320 to 0.1-V in dark conditions, an equivalent bias voltage (VB) is applied at the non-inverting terminal. This bias voltage is derived using a resistive voltage divider on REFby2 output (2.048V), as shown in Equation 14. VB 500: § · (VREFby2 V) u ¨ ¸ © 10k: 500: ¹ 97.5mV (14) The feedback resistor for the transimpedance amplifier can be selected by designing for 4-V output for a 90-µA input, as shown in Equation 15. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 69 ADVANCE INFORMATION AIN0 ADS8168 SBAS817 – NOVEMBER 2017 RF VOUT _ MAX VOUT _ MIN IIN _ MAX www.ti.com 4V 0.1V 90PA 43.3k: (15) Equation 16 computed the value of feedback capacitance to limit the bandwidth of transimpedance circuit to 1MHz. 1 1 CF 3.6pF 2S u fC u RF 2S u (1MHz) u (43.3k:) (16) Transimpedance amplifiers can have potential stability concerns. Stability is a function of the feedback capacitance, the capacitance on the inverting input of the amplifier, and the amplifier gain bandwidth. In this case the capacitance on the inverting amplifier input (CIN) includes, Equation 17, the photodiode junction capacitance (CJ), the multiplexer capacitance (CMUX), the trace capacitance, and the op amp input differential (CD) and common-mode (CCM2) capacitances. Minimum gain bandwidth of the amplifier for stability given CIN can be computed by Equation 19. The minimum required gain bandwidth is 10.9MHz and the gain bandwidth for the OPA320 is 20MHz, so the stability test passes. CIN CJ CD CCM2 CMUX (17) CIN 11pF 5pF 4pF 15pF ADVANCE INFORMATION FGBW ! FGBW ! 70 CIN 35pF (18) CF 2S u RF u (CF )2 35pF 3.6pF 2S u 43.3k: u (3.6pF)2 (19) 10.9MHz (20) Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 ADS8168 www.ti.com SBAS817 – NOVEMBER 2017 9 Power Supply Recommendations The ADS8168 has two separate power supplies: AVDD and DVDD. The internal reference, reference buffer, multiplexer and the internal LDO operate on AVDD. The ADC core operates on the LDO output (available on the DECAP pin). DVDD is used for the setting the logic levels on digital interface. AVDD and DVDD can be independently set to any value within their permissible ranges. During normal operation, if voltage on AVDD supply drops below AVDD minimum specification, it is recommended to ramp AVDD supply down to ≤ 0.7-V before power-up. Also, during power-up, AVDD must monotonously rise to desired operating voltage above minimum AVDD specification. When using internal reference, set AVDD so that: 4.5-V ≤ AVDD ≤ 5.5-V (21) The AVDD supply voltage value defines the permissible range for the external reference voltage VREF on REFIO pin as: 2.5-V ≤ VREF ≤ (AVDD – 0.3) V (22) In other words, to use the external reference voltage of VREF, set AVDD so that: 3-V ≤ AVDD ≤ (AVDD + 0.3) V Place minimum 1-µF decoupling capacitor between the RVDD and GND pins, and between the DVDD and GND pins, as shown in Figure 80. Use minimum 1-µF decoupling capacitor between the DECAP pins and the GND pin. AVDD 1 …F 1 …F GND GND AVDD DECAP DVDD DVDD MUX Control LDO 1 …F ALERT RVS Digital SDO-1/SEQ_ACTIVE GND 4-WIRE SPI MUX ADC RST 4.096-V ÷2 Figure 80. Power-Supply Decoupling Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 71 ADVANCE INFORMATION (23) ADS8168 SBAS817 – NOVEMBER 2017 www.ti.com 10 Layout 10.1 Layout Guidelines This section provides some layout guidelines for achieving optimum performance with the ADS8168. 10.1.1 Analog Signal Path As illustrated in Figure 81, the analog input signals are routed in opposite directions to the digital connections. The reference decoupling components are kept away from the switching digital signals. This arrangement prevents noise generated by digital switching activity from coupling to sensitive analog signals. 10.1.2 Grounding and PCB Stack-Up Low inductance grounding is critical for achieving optimum performance. Place all critical components of the signal chain on the same PCB layer as the ADS8168. For lowest inductance grounding, connect the GND pins of the ADS8168 (pins 1, 21, and 31) and reference ground REFM (pin 4) directly to the device thermal pad. Connect the device thermal pad to PCB ground using four vias, as shown in Figure 81. ADVANCE INFORMATION 10.1.3 Decoupling of Power Supplies Use wide traces or a dedicated power supply plane to minimize trace inductance. Place 1-µF, X7R grade, ceramic decoupling capacitors in close proximity on AVDD (pin 32), the DECAP (pin 2), DVDD (pin 30), and REFby2 (pin 7). Avoid placing vias between any supply pin and the respective decoupling capacitor. 10.1.4 Reference Decoupling When using the internal reference, as discussed in External Reference, the REFIO (pin 3) should have a 1-μF, X7R-grade, ceramic capacitor with at least 10-V rating. This capacitor must be placed close to the REFIO pin, as illustrated in Figure 81. In cases where external reference is used, refer to the reference datasheet for filtering capacitor requirements. 10.1.5 Reference Buffer Decoupling Dynamic currents are present at the REFP and REFM pins during the conversion phase, and excellent decoupling is required to achieve optimum performance. Place a 22-μF, X7R-grade, ceramic capacitor with at least 10-V rating between the REFP and the REFM pins, as illustrated in Figure 81. Select 0603- or 0805-size capacitors to keep equivalent series inductance (ESL) low. Connect the REFM pins to the decoupling capacitor before a ground via. 10.1.6 Multiplexer Input Decoupling Minimizing channel-to-channel parasitic capacitance will reduce the cross-talk induced on the PCB. This can be achieved by increasing the spacing between the analog traces to multiplexer input. In Figure 81, each multiplexer input has a RC filter. Use C0G- or NPO-type capacitors in the RC filter. The purpose of this filter is to aid in settling when switching between multiplexer channels. When not switching the multiplexer, as discussed in Figure 18 and Figure 19, the RC filter may be omitted. 10.1.7 ADC Input Decoupling Dynamic currents are also present at the ADC analog inputs of the ADS8168 (pins 18 and 19). Use C0G- or NPO-type capacitors to decouple these inputs. With these type of capacitors, capacitance stays almost constant over the full input voltage range. Lower-quality capacitors (such as X5R and X7R) have large capacitance changes over the full input-voltage range that may cause degradation in the performance of the device. In Figure 81, each multiplexer input has a RC filter. The purpose of this filter is to aid in settling when switching between multiplexer channels. When not switching the multiplexer, as discussed in Figure 18 and Figure 19, the RC filter may be omitted. 72 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 ADS8168 www.ti.com SBAS817 – NOVEMBER 2017 10.2 Layout Example GND REFby2 GND CREF1 CREF_IO CREFby2 Rcom Ccom GND CREF2 R0 CREG C0 AVDD GND R1 C1 32 9 C2 CDVDD R3 DVDD GND C3 Digital I/O UU11 R4 C4 25 1 7 16 R5 2 24 4 Analog In 1 8 R2 CAVDD ADVANCE INFORMATION C5 R6 C6 R7 C7 CFLT+ CFLT- RFLT+ RFLT- GND GND U2 GND AVDD CC Figure 81. Recommended Layout 10.2.1 Example Schematic The schematic for Layout Example is shown in Figure 82. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 73 ADS8168 SBAS817 – NOVEMBER 2017 www.ti.com Layout Example (continued) DVDD CDVDD 1µF AIN0 Vref/2 CREFby2 1µF CREF2 10µF 3 5 Reference 4.096V LDO 9 REFP CREFIO 1µF 2 32 CREF1 10µF REFIO CREG 1µF CAVDD 1µF 30 R0 107Ÿ DECAP AVDD 7 ÷2 C0 560pF REFP ALARM RVS ADC Analog In 4-wire SPI INM AIN-COM Ccom 560pF 19 17 18 5.5V 20 RFLT+ 49.9Ÿ + + ADC-AINM 8 ADC-AINP C7 560pF Rcom 107Ÿ RST AIN7 MUXOUT-P ADVANCE INFORMATION 16 MUXOUT-M R7 107Ÿ SDO-1 Digital I/O INP U2 OPA320 CFLT+ 1.2nF CC 0.1µF RFLT49.9Ÿ CFLT1.2nF Figure 82. Example Schematic Used in the Recommended Layout 74 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 ADS8168 www.ti.com SBAS817 – NOVEMBER 2017 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation For related documentation see the following: • 16-Bit 1-MSPS Data Acquisition Reference Design for Single-Ended Multiplexed Applications • OPAx625 High-Bandwidth, High-Precision, Low THD+N, 16-Bit and 18-Bit Analog-to-Digital Converter (ADC) Drivers Data Sheet • THS4551 Low Noise, Precision, 150MHz, Fully Differential Amplifier 11.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 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ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADS8168 75 ADVANCE INFORMATION 11.3 Community Resources PACKAGE OPTION ADDENDUM www.ti.com 18-Jan-2018 PACKAGING INFORMATION Orderable Device Status (1) XADS8168IRHBR ACTIVE Package Type Package Pins Package Drawing Qty VQFN RHB 32 3000 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) TBD Call TI Call TI Op Temp (°C) Device Marking (4/5) -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. 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