Product Folder Order Now Support & Community Tools & Software Technical Documents ADC12D1620QML-SP SNAS717 – APRIL 2017 ADC12D1620QML-SP 12-Bit, Single Or Dual, 3200- or 1600-MSPS RF Sampling Analog-to-Digital Converter (ADC) 1 Features 3 Description • • • • • • The ADC12D1620QML device uses a package redesign to achieve better ENOB, SNR, and X-talk compared to the ADC12D1600QML. As is its predecessor, the ADC12D1620QML is a low-power, high-performance CMOS analog-to-digital converter (ADC) that digitizes signals at a 12-bit resolution at sampling rates up to 3.2 GSPS in an interleaved mode. It can also be used as a dual-channel ADC for sampling rates up to 1.6 GSPS. For sampling rates below 800 MHz, there is a low-sampling powersaving mode (LSPSM) that reduces power consumption to less than 1.4 W per channel (typical). The ADC can support conversion rates as low as 200 MSPS. 1 • • • • • • • Total Ionizing Dose (TID) to 300 krad(Si) Single Event Functional Interrupt (SEFI) Tested Single Event Latch-up (SEL) > 120 MeV-cm2/mg Cold Sparing Capable Wide Temperature Range –55°C to +125°C Power Consumption = 3.8 W or 2.7 W (1600- or 800-MHz Clock) 3-dB Input Bandwidth = 3 GHz Low-Sampling Power-Saving Mode (LSPSM) Reduces Power Consumption and Improves Performance for fCLK ≤ 800 MHz Auto-Sync Function for Multi-Chip Systems Time Stamp Feature to Capture External Trigger Test Patterns at Output for System Debug 1:1 Non-Demuxed or 1:2 or 1:4 Parallel Demuxed LVDS Outputs Single 1.9-V Power Supply 2 Applications • • • Direct RF Down Conversion Satellite Wideband Communications Synthetic Aperture RADAR and LIDAR Device Information(1) PART NUMBER GRADE PACKAGE ADC12D1620CCMLS Flight 300 krad CCGA (376) ADC12D1620CCMPR Pre-flight engineering prototype CCGA (376) ADC10D1000DAISY Daisy chain, mechanical sample, no die CCGA (376) ADC12D1620LGMLS Flight 300 krad CLGA (256) ADC12D1620LGMPR Pre-flight engineering prototype CLGA (256) ADC10D1000LDAZ Daisy chain, mechanical sample, no die CLGA (256) (1) For all available packages, see the package orderable addendum (POA) at the end of the data sheet. space Functional Block Diagram 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ADC12D1620QML-SP SNAS717 – APRIL 2017 www.ti.com Table of Contents 1 2 3 4 5 6 6.18 Timing Diagrams ................................................... 27 6.19 Typical Characteristics .......................................... 32 Features .................................................................. 1 Applications ........................................................... 1 Description ............................................................. 1 Revision History..................................................... 2 Pin Configuration and Functions ......................... 3 Specifications....................................................... 12 7 Detailed Description ............................................ 37 7.1 7.2 7.3 7.4 7.5 7.6 6.1 6.2 6.3 6.4 6.5 Absolute Maximum Ratings .................................... 12 ESD Ratings............................................................ 12 Recommended Operating Conditions..................... 12 Thermal Information ................................................ 13 Converter Electrical Characteristics: Static Converter Characteristics ......................................................... 13 6.6 Converter Electrical Characteristics: Dynamic Converter Characteristics......................................... 15 6.7 Converter Electrical Characteristics: Analog Input/Output and Reference Characteristics............ 17 6.8 Converter Electrical Characteristic: Channel-toChannel Characteristics........................................... 18 6.9 Converter Electrical Characteristics: LVDS CLK Input Characteristics ........................................................ 18 6.10 Electrical Characteristics: AutoSync Feature........ 19 6.11 Converter Electrical Characteristics: Digital Control and Output Pin Characteristics ................................ 19 6.12 Converter Electrical Characteristics: Power Supply Characteristics ........................................................ 21 6.13 Converter Electrical Characteristics: AC Electrical Characteristics ......................................................... 23 6.14 Electrical Characteristics: Delta Parameters......... 24 6.15 Timing Requirements: Serial Port Interface .......... 25 6.16 Timing Requirements: Calibration......................... 26 6.17 Quality Conformance Inspection ........................... 26 8 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ Programming .......................................................... Register Maps ......................................................... 37 37 38 46 47 52 Application and Implementation ........................ 59 8.1 Application Information............................................ 59 8.2 Radiation Environments .......................................... 66 8.3 Cold Sparing ........................................................... 66 9 Power Supply Recommendations...................... 68 9.1 System Power-On Considerations.......................... 68 10 Layout................................................................... 69 10.1 10.2 10.3 10.4 Layout Guidelines ................................................. Layout Example .................................................... Thermal Considerations ........................................ Board Mounting Recommendation ....................... 69 71 73 73 11 Device and Documentation Support ................. 75 11.1 11.2 11.3 11.4 11.5 11.6 Device Support .................................................... Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 75 77 77 77 77 77 12 Mechanical, Packaging, and Orderable Information ........................................................... 77 12.1 Engineering Samples ............................................ 78 4 Revision History 2 DATE REVISION NOTES April 2017 * Initial release Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP ADC12D1620QML-SP www.ti.com SNAS717 – APRIL 2017 5 Pin Configuration and Functions The center ground pins are for thermal dissipation and must be soldered to a ground plane to ensure rated performance. See Layout Guidelines for more information. NAA Package 376-Pin CCGA and CLGA Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A G ND V _A S DO T PM NDM V _A G ND V _E G ND_E DId 0+ V _DR DId 3+ G ND_DR DId 6+ V _DR DId 9+ G ND_DR DId 11+ DId 11- G ND_DR A B V bg G ND E CE b S DI CalRu n V _A G ND G ND_E V _E DId 0- DId 2+ DId 3- DId 5+ DId 6- DId 8+ DId 9- DId 10+ DI0+ DI1+ DI1- B C Rtrim + V cm o Rext+ S CS b S CL K G ND V _A V _E G ND_E DId 1+ DId 2- DId 4+ DId 5- DId 7+ DId 8- DId 10- DI0- V _DR DI2+ DI2- C D V _A Rtrim - Rext- G ND G ND CAL V b iasI V _A V _A DId 1- V _DR DId 4- G ND_DR DId 7- V _DR G ND_DR V _DR DI3+ DI4+ DI4- D E V _A T d iod e+ RS V 1 G ND G ND_DR DI3- DI5+ DI5- 1 2 3 4 5 6 7 8 9 10 11 E F V _A G ND_T C T d iod e- RS V 2 AA GND GND GND GND GND GND GND GND GND GND G ND_DR DI6+ DI6- G ND_DR F G V _T C G ND_T C V _T C V _T C AB GND GND GND GND GND GND GND GND GND GND GND DI7+ DI7- DI8+ DI8- G H V in I+ V _T C G ND_T C V _A AC GND GND GND GND GND GND GND GND GND GND GND DI9+ DI9- DI10+ DI10- H J AD GND GND GND GND GND GND GND GND GND GND GND V in I- G ND_T C V _T C V b iasI V _DR DI11+ DI11- V _DR J O RI+ O RI- DCL KI+ DCL KI- K O RQ + O RQ - DCL KQ + DCL KQ - L G ND_DR DQ 11+ DQ 11- G ND_DR M DQ 9+ DQ 9- DQ 10+ DQ 10- N DQ 7+ DQ 7- DQ 8+ DQ 8- P V _DR DQ 6+ DQ 6- V _DR R V _DR DQ 3- DQ 5+ DQ 5- T K L M N G ND G ND V in Q - V in Q + V b iasI V b iasQ G ND_T C V _T C V _T C V _T C V _T C G ND_T C AE GND GND GND GND GND GND GND GND GND GND GND AF GND GND GND GND GND GND GND GND GND GND GND AG GND GND GND GND GND GND GND GND GND GND GND AH GND GND GND GND GND GND GND GND GND GND GND AJ GND GND GND GND GND GND GND GND GND GND GND AK GND GND GND GND GND GND GND GND GND GND GND AL GND GND GND GND GND GND GND GND GND GND GND G ND_T C G ND_T C V b iasQ V _A P V _T C R V _A G ND_T C T V _A G ND_T C G ND_T C U G ND_T C CL K+ P DI G ND G ND RCO u t1- V CL K- DCL K_R ST + P DQ LS P S M DE S RCO u t2+ RCO u t2- W DCL K_R ST - G ND RS V DDRP h RCL K- V _A Y G ND V _A FS R RCL K+ RCO u t1+ 1 2 3 4 5 G ND_T C V _T C V _T C V _T C V _T C G ND V _A V _A DQ d 1- V _DR DQ d 4- G ND_DR DQ d 7- V _DR V _DR G ND_DR DQ 3+ DQ 4+ DQ 4- U V _E G ND_E DQ d 1+ DQ d 2- DQ d 4+ DQ d 5- DQ d 7+ DQ d 8- DQ d 10- DQ 0- G ND_DR DQ 2+ DQ 2- V G ND G ND_E V _E DQ d 0- DQ d 2+ DQ d 3- DQ d 5+ DQ d 6- DQ d 8+ DQ d 9- DQ d 10+ DQ 0+ DQ 1+ DQ 1- W V _A G ND V _E G ND_E DQ d 0+ V _DR DQ d 3+ G ND_DR DQ d 6+ V _DR DQ d 9+ G ND_DR DQ d 11+ DQ d 11- G ND_DR Y 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 V b iasQ The center ground pins are for thermal dissipation and must be soldered to a ground plane to ensure rated performance. See Layout Guidelines for more information. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP 3 ADC12D1620QML-SP SNAS717 – APRIL 2017 www.ti.com Pin Functions: Analog Front-End and Clock Pins PIN NAME NO. TYPE DESCRIPTION EQUIVALENT CIRCUIT ANALOG FRONT-END AND CLOCK PINS VA CLK+ CLK– U2/V1 I Differential converter sampling clock. In the nonDES mode, the analog inputs are sampled on the positive transitions of this clock signal. In the DES mode, the selected input is sampled on both transitions of this clock. This clock must be ACcoupled. 50k AGND VA 100 VBIAS 50k AGND VA DCLK_RST+ DCLK_RST– V2/W1 I Differential DCLK reset. A positive pulse on this input is used to reset the DCLKI and DCLKQ outputs of two or more ADC12D1620 devices in order to synchronize them with other ADC12D1620 devices in the system. DCLKI and DCLKQ are always in phase with each other, unless one channel is powered down, and do not require a pulse from DCLK_RST to become synchronized. The pulse applied here must meet timing relationships with respect to the CLK input. Although supported, this feature has been superseded by AutoSync. AGND 100 VA AGND VA RCLK+ RCLK– Y4/W5 I Reference clock input. When the AutoSync feature is active, and the ADC12D1620 is in slave mode, the internal divided clocks are synchronized with respect to this input clock. The delay on this clock may be adjusted when synchronizing multiple ADCs. This feature is available in ECM with the DRC bits of the AutoSync Control Register (Addr: Eh, Bits: 15:7). 50k AGND VA 100 VBIAS 50k AGND RCOut1+, RCOut1– RCOut2+, RCOut2– Y5/U6 V6/V7 O Reference clock output 1 and 2. These signals, when enabled, provide a reference clock. The RCOut rates for all of the available modes can be found in Table 8; the rates displayed in the table are independent of whether the ADC is in master or slave mode. RCOut1 and RCOut2 are used to drive the RCLK of ADC12D1620 to enable automatic synchronization for multiple ADCs (AutoSync feature). The impedance of each trace from RCOut1 and RCOut2 to the RCLK of ADC12D1620 should be 100-Ω differential. Having two clock outputs allows the auto-synchronization to propagate as a binary tree. Use the DOC bit of the AutoSync Control Register (Addr: Eh; Bit: 1) to enable or disable this feature; default is disabled. VA 100: 100: - + A GND 4 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP ADC12D1620QML-SP www.ti.com SNAS717 – APRIL 2017 Pin Functions: Analog Front-End and Clock Pins (continued) PIN NAME NO. TYPE DESCRIPTION EQUIVALENT CIRCUIT VA Rext+ Rext– C3/D3 I/O External reference resistor terminals. Connect a 3.3kΩ, ±0.1% resistor between Rext+, Rext–. The Rext resistor is used as a reference to trim internal circuits that affect the linearity of the converter; the value and precision of this resistor must not be compromised. V GND Rtrim+ Rtrim– C1/D2 I/O VA Input termination trim resistor terminals. Connect a 3.3-kΩ, ±0.1%resistor between Rtrim+/ Rtrim–. The Rtrim resistor is used to establish the calibrated 100-Ω input impedance of Vinl, VinQ, and CLK. These impedances may be fine-tuned by varying the value of the resistor by a corresponding percentage; however, the tuning range and performance is not tested for such an alternative values. V GND VA Tdiode_P Tdiode+ Tdiode– E2/F3 O Temperature sensor diode positive (anode) and negative (cathode) terminals. This set of pins is used for die temperature measurements. It has not been fully characterized. GND VA Tdiode_N GND VBG B1 I/O VA Bandgap voltage output or LVDS common-mode voltage select. This pin provides a buffered version of the bandgap output voltage; it is capable of sourcing/sinking 100 μA and driving a load of up to 80 pF. Alternately, this pin may be used to select the LVDS digital output common-mode voltage. If tied to logic-high, the 1.2-V LVDS common-mode voltage is selected; 0.8 V is the default. GND VCMO C2 I/O Common-mode voltage. This pin is the commonmode output in DC-coupling mode and also serves as the AC-coupling mode select pin. When DCcoupling is used at the analog inputs, the voltage output at this pin is required to be the commonmode input voltage at VIN+ and VIN−. When ACcoupling is used, this pin must be grounded. This pin is capable of sourcing or sinking 100 μA. VA VCMO 200k Enable AC Coupling 8 pF GND Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP 5 ADC12D1620QML-SP SNAS717 – APRIL 2017 www.ti.com Pin Functions: Analog Front-End and Clock Pins (continued) PIN NAME NO. TYPE DESCRIPTION EQUIVALENT CIRCUIT Differential signal I and Q inputs. In the non-dual edge sampling (non-DES) mode, each I and Q input is sampled and converted by its respective channel with each positive transition of the CLK input. In non-ECM (non-extended control mode) and DES mode, both channels sample the I input. In Extended Control mode (ECM), the Q input may optionally be selected for conversion in DES mode by the DEQ Bit of the Configuration Register (Addr: 0h; Bit: 6). VinI+, VinI– VinQ+, VinQ– H1/J1 N1/M1 I Each I- and Q-channel input has an internal common mode bias that is disabled when DCcoupled mode is selected. Both inputs must be either AC- or DC-coupled. The coupling mode is selected by the VCMO pin. In non-ECM, the full-scale range of these inputs is determined by the FSR pin; both I and Q channels have the same full-scale input range. In ECM, the full-scale input range of the I- and Q-channel inputs may be independently set with the I- and Q-channel Full-Scale Range Adjust Registers (Addr: 3h and Addr: Bh, respectively). The high and low full-scale input range setting in non-ECM corresponds to the mid and minimum full-scale input range in ECM. VA 50k AGND VCMO 100 Control from VCMO VA 50k AGND The input offset may also be adjusted in ECM with the I- and Q-channel Offset Adjust Registers (Addr: 2h and Addr: Ah, respectively). CONTROL AND STATUS PINS CAL D6 I Calibration cycle initiate. The user can command the device to execute a self-calibration cycle by holding this input high for a minimum of tCAL_H after having held it low for a minimum of tCAL_L. This pin is active in both ECM and non-ECM. In ECM, this pin is logically OR'd with the CAL Bit of the Configuration Register (Addr: 0h, Bit 15). Therefore, both the pin and bit must be set low and then either can be set high to execute an on-command calibration. TI recommends holding the CAL pin high during normal usage to reduce the chance that an SEU causes a calibration cycle. VA GND VA CalRun B5 O Calibration running indication. This output is logichigh while the calibration sequence is executing; otherwise, this output is logic-low. GND 6 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP ADC12D1620QML-SP www.ti.com SNAS717 – APRIL 2017 Pin Functions: Analog Front-End and Clock Pins (continued) PIN NAME NO. TYPE DESCRIPTION EQUIVALENT CIRCUIT DDR phase select. In DDR, when this input is logiclow, it selects the 0° data-to-DCLK phase relationship. When this input is logic-high, it selects the 90° data-to-DCLK phase relationship; that is, the DCLK transition indicates the middle of the valid data outputs. DDRPh W4 I In SDR, when this input is logic-low, the output transitions on the rising edge of DCLK. When this input is logic-high, output transition is on the falling edge of DCLK. This pin only has an effect when the chip is in 1:2 demuxed mode; that is, the NDM pin is set to logiclow. In ECM, this input is ignored and the DDR phase is selected through the Control Register by the DPS bit (Addr: 0h, Bit 14); the default is 0° mode. Dual edge sampling (DES) mode select. In the nonextended control mode (Non-ECM), when this input is set to logic-high, the DES mode of operation is selected; this means that the VinI input is sampled by both channels in a time-interleaved manner and the VinQ input is ignored. DES ECE V5 B3 I I When this input is set to logic-low, the device is in non-DES mode; that is, I and Q channels operate independently. In the extended control mode (ECM), this input is ignored and DES mode selection is controlled through the DES bit of the Configuration Register (Addr: 0h; Bit: 7); default is non-DES mode operation. Extended control enable. Extended feature control through the SPI interface is enabled and the device is in ECM when this signal is asserted (logic-low). Please reference Table 1 for information on the behavior of the control pins when the extended feature control is enabled. When this signal is de-asserted (logic-high), the SPI interface is disabled, all SPI registers are reset to their default values, and all available settings are controlled with the control pins. FSR LSPSM Y3 V4 I I VA Full-scale input range select. In non-ECM, when this input is set to logic-low or logic-high, the full-scale differential input range for both I- and Q-channel inputs is set to the lower or higher FSR value, respectively. In the ECM, this input is ignored and the full-scale range of the I- and Q-channelinputs is independently determined by the setting of the Iand Q-channel Full-Scale Range Adjust Registers (Addr: 3h and Addr: Bh, respectively). Note that the high (lower) FSR value in non-ECM corresponds to the mid (min) available selection in ECM; the FSR range in ECM is greater. Low-sampling power-saving mode (LSPSM) select. In LSPSM, the power consumption is reduced by approximately 20%, and some improvement in performance may be seen. The output is in SDR in 1:2 demux mode and DDR in 1:1 non-demux mode. DDR is not available in 1:2 demux mode in LSPSM. The maximum sampling rate in LSPSM in non-DES mode is 800 MSPS. When this input is logic-high, the device is in LSPSM and when this input is logiclow, the device is in normal mode or non-LSPSM. GND VA GND VA 50 k: GND VA GND VA GND Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP 7 ADC12D1620QML-SP SNAS717 – APRIL 2017 www.ti.com Pin Functions: Analog Front-End and Clock Pins (continued) PIN NAME NO. TYPE DESCRIPTION EQUIVALENT CIRCUIT VA NDM A5 I Non-demuxed mode select. Setting this input to logic-high causes the digital output bus to be in the 1:1 non-demuxed mode. Setting this input to logiclow causes the digital output bus to be in the 1:2 demuxed mode. This feature is pin-controlled only and remains active during both ECM and non-ECM. GND PDI PDQ U3 V3 I Power down I and Q channels. Setting either input to logic-high powers down the respective I or Q channel. Setting either input to logic-low brings the respective I or Q channel to a operational state after a finite time delay. This pin is active in both ECM and non-ECM. In ECM, each pin is logically OR'd with its respective bit. Therefore, either this pin or the PDI and PDQ bits in the Configuration Register (Addr: 0h; Bit: 11 and Bit: 10, respectively) can be used to power down the I and Q channels. NONE VA 50 k: GND RSV W3 — Reserved. This pin is used for internal purposes and must be connected to GND through a 100-kΩ resistor. RSV1 E3 — Decouple this pin with a 100-nF capacitor with a low resistance, low inductance path to GND. NONE RSV2 F4 — Decouple this pin with a 100-nF capacitor with a low resistance, low inductance path to GND. NONE VA SCLK C5 I Serial clock. In ECM, serial data is shifted into and out of the device synchronously to this clock signal. This clock may be disabled and held logic-low, as long as timing specifications are not violated when the clock is enabled or disabled. 100 k: GND VA SCS C4 I Serial chip select. In ECM, when this signal is asserted (logic-low), SCLK is used to clock in serial data that is present on SDI and to source serial data on SDO. When this signal is de-asserted (logichigh), SDI is ignored and SDO is tri-state. 100 k: GND VA 100 k: SDI B4 I Serial data-in. In ECM, serial data is shifted into the device on this pin while SCS signal is asserted (logic-low). GND 8 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP ADC12D1620QML-SP www.ti.com SNAS717 – APRIL 2017 Pin Functions: Analog Front-End and Clock Pins (continued) PIN NAME NO. TYPE DESCRIPTION EQUIVALENT CIRCUIT VA SDO A3 O Serial data-out. In ECM, serial data is shifted out of the device on this pin while SCS signal is asserted (logic-low). This output is tri-state when SCS is deasserted (logic-high). GND VA TPM A4 I Test pattern mode select. With this input at logichigh, the device continuously outputs a fixed, repetitive test pattern at the digital outputs. In ECM, this input is ignored, and the test pattern mode can only be activated through the Control Register by the TPM bit (Addr: 0h, Bit: 12). GND POWER AND GROUND PINS GND A1, A7, B2, B7, C6, D4, D5, E4, K1, L1, T4, U4, U5, W2, W7, Y1, Y7, AA2:AL11 P Analog ground return NONE GNDDR A13, A17, A20, D13, D16, E17, F17, F20, M17, M20, U13, U17, V18, Y13, Y17, Y20 P Ground return for the output drivers NONE GNDE A9, B8, C9, V9, W8, Y9 P Ground return for the digital encoder NONE GNDTC F2, G2, H3, J2, K4, L4, M2, N3, P2, R2, T2, T3, U1 P Ground return for the track-and-hold and clock circuitry NONE A2, A6, B6, C7, D1, D8, D9, E1, F1, H4, N4, R1, T1, U8, U9, W6, Y2, Y6 P Analog power supply. This supply is tied to the ESD ring; therefore, it must be powered up before or with any other supply. NONE P Bias voltage I channel. This is an externally decoupled bias voltage for the I channel. Each pin must individually be decoupled with a 100-nF capacitor through a low resistance, low inductance path to GND. NONE P Bias voltage Q channel. This is an externally decoupled bias voltage for the Q channel. Each pin must individually be decoupled with a 100-nF capacitor through a low resistance, low inductance path to GND. NONE VA VbiasI VbiasQ D7, J4, K2 L2, M4, U7 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP 9 ADC12D1620QML-SP SNAS717 – APRIL 2017 www.ti.com Pin Functions: Analog Front-End and Clock Pins (continued) PIN NAME NO. TYPE DESCRIPTION EQUIVALENT CIRCUIT VDR A11, A15, C18, D11, D15, D17, J17, J20, R17, R20, T17, U11, U15, U16, Y11, Y15 P Power supply for the output drivers NONE VE A8, B9, C8, V8, W9, Y8 P Power supply for the digital encoder NONE VTC G1, G3, G4, H2, J3, K3, L3, M3, N2, P1, P3, P4, R3, R4 P Power supply for the track-and-hold and clock circuitry NONE HIGH-SPEED DIGITAL OUTPUT PINS VDR DCLKI+, DCLKI– DCLKQ+, DCLKQ– K19/K20 L19/L20 O Data clock output for the I- and Q-channel data bus. These differential clock outputs are used to latch the output data and, if used, terminate with a 100-Ω differential resistor placed as closely as possible to the differential receiver. Delayed and non-delayed data outputs are supplied synchronously to this signal. The DCLK rates for all of the available modes can be found in Table 8. DCLKI and DCLKQ are always in phase with each other, unless one channel is powered down, and do not require a pulse from DCLK_RST to become synchronized. - + + - DR GND DI11+, DI11– DI10+, DI10– DI9+, DI9– DI8+, DI8– DI7+, DI7– DI6+, DI6– DI5+, DI5– DI4+, DI4– DI3+, DI3– DI2+, DI2– DI1+,DI1 – DI0+, DI0– · DQ11+, DQ11– DQ10+, DQ10– DQ9+, DQ9– DQ8+, DQ8– DQ7+, DQ7– DQ6+, DQ6– DQ5+, DQ5– DQ4+, DQ4– DQ3+, DQ3– DQ2+, DQ2– DQ1+, DQ1– DQ0+, DQ0– 10 J18/J19 H19/H20 H17/H18 G19/G20 G17/G18 F18/F19 E19/E20 D19/D20 D18/E18 C19/C20 B19/B20 B18/C17 · M18/M19 N19/N20 N17/N18 P19/P20 P17/P18 R18/R19 T19/T20 U19/U20 U18/T18 V19/V20 W19/W20 W18/V17 VDR O I- and Q-channel digital data outputs. In non-demux mode, this LVDS data is transmitted at the sampling clock rate. In demux mode, these outputs provide ½ the data at ½ the sampling clock rate, synchronized with the delayed data; that is, the other ½ of the data which was sampled one clock cycle earlier. Compared with the DId and DQd outputs, these outputs represent the later time samples. If used, terminate each of these outputs with a 100-Ω differential resistor placed as closely as possible to the differential receiver. - + + - DR GND Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP ADC12D1620QML-SP www.ti.com SNAS717 – APRIL 2017 Pin Functions: Analog Front-End and Clock Pins (continued) PIN NAME NO. DId11+, DId11– DId10+, DId10– DId9+, DId9– DId8+, DId8– DId7+, DId7– DId6+, DId6– DId5+, DId5– DId4+, DId4– DId3+, DId3– DId2+, DId2– DId1+,DId1 – DId0+, DId0– · DQd11+, DQd11– DQd10+, DQd10– DQd9+, DQd9– DQd8+, DQd8– DQd7+, DQd7– DQd6+, DQd6– DQd5+, DQd5– DQd4+, DQd4– DQd3+, DQd3– DQd2+, DQd2– DQd1+, DQd1– DQd0+, DQd0– A18/A19 B17/C16 A16/B16 B15/C15 C14/D14 A14/B14 B13/C13 C12/D12 A12/B12 B11/C11 C10/D10 A10/B10 · Y18/Y19 W17/V16 Y16/W16 W15/V15 V14/U14 Y14/W14 W13/V13 V12/U12 Y12/W12 W11/V11 V10/U10 Y10/W10 TYPE DESCRIPTION EQUIVALENT CIRCUIT VDR O Delayed I- and Q-channel digital data outputs. In non-demux mode, these outputs are tri-state. In demux mode, these outputs provide ½ the data at ½ the sampling clock rate, synchronized with the nondelayed data; that is, the other ½ of the data which was sampled one clock cycle later. Compared with the DI and DQ outputs, these outputs represent the earlier time samples. If used, terminate each of these outputs with a 100-Ω differential resistor placed as closely as possible to the differential receiver. - + + - DR GND VDR ORI+, ORI– ORQ+, ORQ– K17/K18 L17/L18 O Out-of-range output for the I and Q channel. This differential output is asserted logic-high while the over- or under-range condition exists; that is, the differential signal at each respective analog input exceeds the full-scale value. Each OR result refers to the current data, with which it is clocked out. If used, terminate each of these outputs with a 100-Ω differential resistor placed as closely as possible to the differential receiver. - + + - DR GND Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP 11 ADC12D1620QML-SP SNAS717 – APRIL 2017 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (1) (2) MIN Supply voltage (VA, VTC, VDR, VE) Supply difference – max(VA/TC/DR/E) – min(VA/TC/DR/E) MAX UNIT 2.2 V 0 100 mV Voltage on any input pin (except VinI+, VinI–, VinQ+, VinQ–) −0.15 2.35 V VinI+, VinI–, VinQ+, VinQ– voltage (maintaining common mode) (3) −0.15 2.5 V ±50 mA 100 mV ±50 mA Input current at VinI+, VinI–, VinQ+, VinQ– (3) Ground difference – max(GNDTC/DR/E) – min(GNDTC/DR/E) 0 Input current at any pin (4) Power dissipation at TA ≤ 125°C (4) −65 Storage temperature, Tstg (1) (2) (3) (4) 4.4 W 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are measured with respect to GND = GNDDR = GNDE = GNDTC = 0 V, unless otherwise specified. Verified during product qualification high-temperature lifetime testing (HTOL) at TJ = 150°C for 1000 hours continuous operation with VA = VD = 2.2 V. When the input voltage at any pin exceeds the power supply limits, the current at that pin must be limited to 50 mA. In addition, overvoltage at a pin must adhere to maximum voltage limits. Simultaneous overvoltage at multiple pins requires adherence to the maximum package power dissipation limits, which are calculated using the JEDEC JESD51-7 thermal model. Higher dissipation may be possible based on customer-specific thermal situations and specified thermal package resistances from junction to case. 6.2 ESD Ratings V(ESD) (1) Electrostatic discharge Human-body Model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) VALUE UNIT ±2500 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) Case temperature Supply voltage (VA, VTC, VE) Voltage on any input pin (except VinI+, VinI–, VinQ+, VinQ–) Driver supply voltage (VDR) VinI+, VinI–, VinQ+, VinQ– voltage (2) DC-coupled MIN MAX UNIT −55 125 °C 1.8 2 V −0.15 2.15 V 1.8 VA V –0.4 2.4 V DC-coupled at 100% duty cycle VinI+, VinI–, VinQ+, VinQ– differential voltage (3) VinI+, VinI–, VinQ+, VinQ– current (2) VinI+, VinI–, VinQ+, VinQ– power DC-coupled at 20% duty cycle 2 DC-coupled at 10% duty cycle 2.8 AC-coupled 12 –50 50 Maintaining common-mode voltage, AC-coupled 15.3 Not maintaining common-mode voltage, AC-coupled 17.1 Ground difference – max(GNDTC/DR/E) – min(GNDTC/DR/E) (1) (2) (3) 1 V mA dBm 0 V All voltages are measured with respect to GND = GNDDR = GNDE = GNDTC = 0 V, unless otherwise specified. Proper common mode voltage must be maintained to ensure proper output code, especially during input overdrive. This rating is intended for DC-coupled applications; the voltages and duty cycles listed may be safely applied to VIN± for the lifetime of the part. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP ADC12D1620QML-SP www.ti.com SNAS717 – APRIL 2017 Recommended Operating Conditions (continued) over operating free-air temperature range (unless otherwise noted)(1) MIN Input current at any pin except VinI+, VinI–, VinQ+, or VinQ– (4) CLK+, CLK– voltage (4) UNIT ±50 mA 0 VA 0.4 2 VP-P VCMO – 150 VCMO + 150 mV Differential CLK amplitude VCMI common-mode input voltage MAX V When the input voltage at any pin exceeds the power supply limits, the current at that pin must be limited to 50 mA. In addition, overvoltage at a pin must adhere to maximum voltage limits. Simultaneous overvoltage at multiple pins requires adherence to the maximum package power dissipation limits, which are calculated using the JEDEC JESD51-7 thermal model. Higher dissipation may be possible based on customer-specific thermal situations and specified thermal package resistances from junction to case. 6.4 Thermal Information ADC12D1620QML-SP THERMAL METRIC (1) (2) NAA (CCGA) UNIT 376 PINS RθJA Junction-to-ambient thermal resistance 13.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 5.0 °C/W RθJB Junction-to-board thermal resistance 5.1 °C/W ψJT Junction-to-top characterization parameter 2.6 °C/W ψJB Junction-to-board characterization parameter 4.7 °C/W (1) (2) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics Solder process specifications in Board Mounting Recommendation. 6.5 Converter Electrical Characteristics: Static Converter Characteristics The following specifications apply after calibration for VA = VDR = VTC = VE = 1.9 V; I and Q channels AC-coupled, FSR pin = high; CL = 10-pF; differential AC-coupled sine wave input clock, fCLK = 1.6 GHz at 0.5 VP-P with 50% duty cycle; VBG = floating; non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2 demultiplex non-DES mode; I and Q channels; duty-cycle stabilizer on. (1) (2) PARAMETER TEST CONDITIONS INL Integral non-linearity DC-coupled, 1 MHz sine wave overranged DNL Differential non-linearity DC-coupled, 1 MHz sine wave overranged Resolution with no missing codes VOFF Offset error VOFF_ADJ Input offset adjustment range (1) SUB-GROUPS MIN TYP (3) MAX UNIT [1, 2, 3] –7.5 ±2.5 7.5 LSB [1, 2, 3] –1.35 ±0.5 1.35 LSB 12 bits [1, 2, 3] Extended control mode 8 LSB ±45 mV The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device. V A TO INTERNAL CIRCUITRY I/O GND (2) (3) To ensure accuracy, it is required that VA, VTC, VE and VDR be well bypassed. Each supply pin must be decoupled with separate bypass capacitors. Typical figures are at TA = 25°C, and represent most likely parametric norms. Test limits are ensured to Texas Instrument's average outgoing quality level (AOQL). Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP 13 ADC12D1620QML-SP SNAS717 – APRIL 2017 www.ti.com Converter Electrical Characteristics: Static Converter Characteristics (continued) The following specifications apply after calibration for VA = VDR = VTC = VE = 1.9 V; I and Q channels AC-coupled, FSR pin = high; CL = 10-pF; differential AC-coupled sine wave input clock, fCLK = 1.6 GHz at 0.5 VP-P with 50% duty cycle; VBG = floating; non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2 demultiplex non-DES mode; I and Q channels; duty-cycle stabilizer on.(1)(2) PARAMETER PFSE Positive full-scale error NFSE Negative full-scale error Out-of-range output code (4) 14 TEST CONDITIONS TYP (3) SUB-GROUPS MIN See (4) [1, 2, 3] –30 30 mV See (4) [1, 2, 3] –30 30 mV (VIN+) − (VIN−) > positive full scale [1, 2, 3] (VIN+) − (VIN−) < negative full scale [1, 2, 3] MAX UNIT 4095 0 Calculation of full-scale error for this device assumes that the actual reference voltage is exactly its nominal value. Full-scale error for this device, therefore, is a combination of full-scale error and reference voltage error. For relationship between gain error and full-scale error, see gain error in Device Nomenclature . Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP ADC12D1620QML-SP www.ti.com SNAS717 – APRIL 2017 6.6 Converter Electrical Characteristics: Dynamic Converter Characteristics The following specifications apply after calibration for VA = VDR = VTC = VE = 1.9 V; I and Q channels AC-coupled, FSR pin = high; CL = 10 pF; differential AC-coupled sine wave input clock, fCLK = 1.6 GHz at 0.5 VP-P with 50% duty cycle; VBG = floating; non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2 demultiplex non-DES mode; I and Q channels; duty-cycle stabilizer on. (1) (2) PARAMETER CER TEST CONDITIONS SUB-GROUPS MIN 3rd order intermodulation distortion MAX UNIT Error/ Sample 10–18 Code error rate IMD3 TYP (3) fIN = 2070 MHz ± 2.5 MHz at –13 dBFS –76 dBFS –63 dBc fIN = 2070 MHz ± 2.5 MHz at –16 dBFS –80 dBFS –64 dBc fIN = 2670 MHz ± 2.5 MHz at –13 dBFS –72 dBFS –59 dBc fIN = 2670 MHz ± 2.5 MHz at –16 dBFS –77 dBFS –61 dBc 1:2 DEMUX, NON-DES MODE, NON-ECM, NON-LSPSM, fCLK = 1.6 GHz, fIN = 248 MHz, VIN = –0.5 dBFS ENOB SINAD SNR Effective number of bits Signal-to-noise plus distortion ratio Signal-to-noise ratio [4] 8.8 [5] 8.7 [6] 8.4 [4] 54.7 [5] 54.1 [6] 52.3 [4] 56 [5] 54.6 [6] 53.5 [4, 5] 9.1 bits 56.5 dBFS 58.4 dBFS dBFS –62 –59.2 dBFS –55.5 dBFS THD Total harmonic distortion 2nd Harm Second harmonic distortion –72.2 dBFS 3rd Harm Third harmonic distortion –62.1 dBFS SFDR Spurious-free dynamic range (1) [6] [4] 58.9 [5] 58.1 [6] 56 62.1 dBFS dBFS The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device. V A TO INTERNAL CIRCUITRY I/O GND (2) (3) To ensure accuracy, it is required that VA, VTC, VE and VDR be well bypassed. Each supply pin must be decoupled with separate bypass capacitors. Typical figures are at TA = 25°C, and represent most likely parametric norms. Test limits are ensured to Texas Instrument's average outgoing quality level (AOQL). Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP 15 ADC12D1620QML-SP SNAS717 – APRIL 2017 www.ti.com Converter Electrical Characteristics: Dynamic Converter Characteristics (continued) The following specifications apply after calibration for VA = VDR = VTC = VE = 1.9 V; I and Q channels AC-coupled, FSR pin = high; CL = 10 pF; differential AC-coupled sine wave input clock, fCLK = 1.6 GHz at 0.5 VP-P with 50% duty cycle; VBG = floating; non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2 demultiplex non-DES mode; I and Q channels; duty-cycle stabilizer on.(1)(2) PARAMETER TEST CONDITIONS SUB-GROUPS MIN TYP (3) MAX UNIT 1:2 DEMUX, NON-DES MODE, NON-ECM, LSPSM, fCLK = 800 MHz, fIN = 248 MHz, VIN = –0.5 dBFS ENOB Effective number of bits [4, 5] 9.1 [6] 8.6 SINAD Signal-to-noise plus distortion ratio [4, 5] 56.5 [6] 53.5 [4, 5] 57.6 [6] 56.8 9.5 bits bits 58.6 dBFS dBFS 59.8 dBFS SNR Signal-to-noise ratio THD Total harmonic distortion 2nd Harm Second harmonic distortion –77.7 dBFS 3rd Harm Third harmonic distortion –67.5 dBFS SFDR Spurious-free dynamic range 67.4 dBFS [4, 5] dBFS –67 [6] [4, 5] 62.5 [6] 57.5 –62.3 dBFS –57 dBFS dBFS NON-DEMUX, NON-DES MODE, ECM, NON-LSPSM, fCLK = 1.6 GHz, fIN = 248 MHz, VIN = –0.5 dBFS ENOB Effective number of bits 9.1 bits SINAD Signal-to-noise plus distortion ratio 56.6 dBFS SNR Signal-to-noise ratio 58.6 dBFS THD Total harmonic distortion –63.2 dBFS 2nd Harm Second harmonic distortion –72 dBFS 3rd Harm Third harmonic distortion –63.3 dBFS SFDR Spurious-free dynamic range 63.3 dBFS 1:4 DEMUX, DES MODE, NON-LSPSM, fCLK = 1.6 GHz, fIN = 248 MHz, VIN = –0.5 dBFS ENOB Effective number of bits 8.9 bits SINAD Signal-to-noise plus distortion ratio 55.5 dB SNR Signal-to-noise ratio 56.9 dBFS THD Total harmonic distortion –62.3 dBFS 2nd Harm Second harmonic distortion –79.1 dBFS 3rd Harm Third harmonic distortion –62.3 dBFS SFDR Spurious-free dynamic range 61.7 dBFS 16 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP ADC12D1620QML-SP www.ti.com SNAS717 – APRIL 2017 6.7 Converter Electrical Characteristics: Analog Input/Output and Reference Characteristics The following specifications apply after calibration for VA = VDR = VTC = VE = 1.9 V; I and Q channels AC-coupled, FSR pin = high; CL = 10-pF; differential AC-coupled sine wave input clock, fCLK = 1.6 GHz at 0.5 VP-P with 50% duty cycle; VBG = floating; non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2 demultiplex non-DES mode; I and Q channels; duty-cycle stabilizer on. (1) (2) PARAMETER VIN_FSR Analog differential input full-scale range Analog input capacitance, Non-DES mode CIN TEST CONDITIONS (4) (5) Analog input capacitance, DES mode (4) (5) FSR pin Y3 Low [4, 5, 6] FSR pin Y3 High [4, 5, 6] MIN TYP (3) MAX 630 750 820 UNIT mVP-P 890 mVP-P EXTENDED CONTROL MODE FM(14:0) = 0000h 600 mVP-P FM(14:0) = 4000h (default) 800 mVP-P FM(14:0) = 7FFFh 1000 mVP-P Differential 0.02 pF 1.6 pF 0.02 pF 2.2 pF Each input pin to ground Differential Each input pin to ground Differential input resistance RIN SUBGROUPS [1, 2, 3] 99 103 107 Ω [1, 2, 3] 1.15 1.25 1.35 V COMMON-MODE OUTPUT Common-mode output voltage ICMO = ±100 μA Common-mode output TC_VCMO voltage temperature coefficient ICMO = ±100 μA VCMO VCMO_LVL CL_VCMO 38 VCMO input threshold to set DC-coupling mode Maximum VCMO load capacitance ppm/°C 0.63 See V (5) 80 pF 1.35 V BANDGAP REFERENCE VBG Bandgap reference output voltage IBG = ±100 µA Bandgap reference voltage temperature coefficient IBG = ±100 µA TC_VBG CLOAD VBG Maximum bandgap reference load capacitance (1) [1, 2, 3] 1.15 1.27 50 ppm/°C 80 pF The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device. V A TO INTERNAL CIRCUITRY I/O GND (2) (3) (4) (5) To ensure accuracy, it is required that VA, VTC, VE and VDR be well bypassed. Each supply pin must be decoupled with separate bypass capacitors. Typical figures are at TA = 25°C, and represent most likely parametric norms. Test limits are ensured to Texas Instrument's average outgoing quality level (AOQL). The analog and clock input capacitances are die capacitances only. Additional package capacitances of 0.22-pF differential and 1.06-pF each pin to ground are isolated from the die capacitances by lead and bond wire inductances. This parameter is specified by design and/or characterization and is not tested in production. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP 17 ADC12D1620QML-SP SNAS717 – APRIL 2017 www.ti.com 6.8 Converter Electrical Characteristic: Channel-to-Channel Characteristics The following specifications apply after calibration for VA = VDR = VTC = VE = 1.9 V; I and Q channels AC-coupled, FSR pin = high; CL = 10 pF; differential AC-coupled sine wave input clock, fCLK = 1.6 GHz at 0.5 VP-P with 50% duty cycle; VBG = floating; non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2 demultiplex non-DES mode; I and Q channels; duty-cycle stabilizer on. (1) (2) PARAMETER CONDITIONS SUBGROUPS MIN TYP (3) MAX UNIT Phase matching (I, Q) fIN = 1 GHz <1 Degree X-TALK Q-channel Crosstalk from I channel (aggressor) to Q channel (victim) Aggressor = 248 MHz –72 dBFS Aggressor = 498 MHz –75 dBFS X-TALK I-channel Crosstalk from Q channel (aggressor) to I channel (victim) Aggressor = 248 MHz –71 dBFS Aggressor = 498 MHz –79 dBFS (1) The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device. V A TO INTERNAL CIRCUITRY I/O GND (2) (3) To ensure accuracy, it is required that VA, VTC, VE and VDR be well bypassed. Each supply pin must be decoupled with separate bypass capacitors. Typical figures are at TA = 25°C, and represent most likely parametric norms. Test limits are ensured to Texas Instrument's average outgoing quality level (AOQL). 6.9 Converter Electrical Characteristics: LVDS CLK Input Characteristics The following specifications apply after calibration for VA = VDR = VTC = VE = 1.9 V; I and Q channels AC-coupled, FSR pin = high; CL = 10 pF; differential AC-coupled sine wave input clock, fCLK = 1.6 GHz at 0.5 VP-P with 50% duty cycle; VBG = floating; non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2 demultiplex non-DES mode; I and Q channels; duty-cycle stabilizer on. (1) (2) PARAMETER CONDITIONS SUBGROUPS MIN TYP (3) MAX VIN_CLK Differential clock input level (4) Sine-wave clock [1, 2, 3] 0.4 2 Square-wave clock [1, 2, 3] 0.4 2 CIN_CLK Sampling clock input capacitance (4) (5) Differential RIN_CLK Sampling clock input resistance (1) Each input to ground 0.1 1 100 UNIT VP-P pF Ω The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device. V A TO INTERNAL CIRCUITRY I/O GND (2) (3) (4) (5) 18 To ensure accuracy, it is required that VA, VTC, VE and VDR be well bypassed. Each supply pin must be decoupled with separate bypass capacitors. Typical figures are at TA = 25°C, and represent most likely parametric norms. Test limits are ensured to Texas Instrument's average outgoing quality level (AOQL). This parameter is specified by design and/or characterization and is not tested in production. The analog and clock input capacitances are die capacitances only. Additional package capacitances of 0.22-pF differential and 1.06-pF each pin to ground are isolated from the die capacitances by lead and bond wire inductances. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP ADC12D1620QML-SP www.ti.com SNAS717 – APRIL 2017 6.10 Electrical Characteristics: AutoSync Feature The following specifications apply after calibration for for VA = VDR = VTC = VE = 1.9 V; I and Q channels AC-coupled, FSR pin = High; CL = 10 pF; differential AC-coupled sine wave input clock, fCLK = 1.6 GHz at 0.5 VP-P with 50% duty cycle; VBG = floating; non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2 demultiplex non-DES mode; I and Q channels; duty-cycle stabilizer on (1) (2) PARAMETER TEST CONDITIONS SUBGROUPS MIN TYP (3) MAX UNIT VIN_RCLK Differential RCLK input level CIN_RCLK RCLK input capacitance RIN_CLK RCLK differential input resistance IIH_RCLK Input leakage current VIN = VA [1, 2, 3] 20 μA IIL_RCLK Input leakage current VIN = GND [1, 2, 3] –32 μA VO_RCOUT Differential RCOut output voltage 360 mVp-p (1) Differential peak-to-peak 360 Differential 0.1 Each input to ground mVp-p pF 1 Ω 100 The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device. V A TO INTERNAL CIRCUITRY I/O GND (2) (3) To ensure accuracy, it is required that VA, VTC, VE and VDR be well bypassed. Each supply pin must be decoupled with separate bypass capacitors. Typical figures are at TA = 25°C, and represent most likely parametric norms. Test limits are ensured to Texas Instrument's average outgoing quality level (AOQL). 6.11 Converter Electrical Characteristics: Digital Control and Output Pin Characteristics The following specifications apply after calibration for for VA = VDR = VTC = VE = 1.9 V; I and Q channels AC-coupled, FSR pin = High; CL = 10 pF; differential AC-coupled sine wave input clock, fCLK = 1.6 GHz at 0.5 VP-P with 50% duty cycle; VBG = floating; non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2 demultiplex non-DES mode; I and Q channels; duty-cycle stabilizer on. (1) (2) PARAMETER CONDITIONS SUBGROUPS MIN TYP (3) MAX UNIT DIGITAL CONTROL PINS, (DES, LSPSM, CAL, PDI, PDQ, TPM, NDM, FSR, DDRPh, ECE, SCLK, SDI, SCS— unless otherwise specified) VIH Logic high input voltage [1, 2, 3] VIL Logic low input voltage [1, 2, 3] IIH Input leakage current (1) VIN = VA [1, 2, 3] 0.7 x VA –1 V 0.3 x VA V 1 µA The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device. V A TO INTERNAL CIRCUITRY I/O GND (2) (3) To ensure accuracy, it is required that VA, VTC, VE and VDR be well bypassed. Each supply pin must be decoupled with separate bypass capacitors. Typical figures are at TA = 25°C, and represent most likely parametric norms. Test limits are ensured to Texas Instrument's average outgoing quality level (AOQL). Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP 19 ADC12D1620QML-SP SNAS717 – APRIL 2017 www.ti.com Converter Electrical Characteristics: Digital Control and Output Pin Characteristics (continued) The following specifications apply after calibration for for VA = VDR = VTC = VE = 1.9 V; I and Q channels AC-coupled, FSR pin = High; CL = 10 pF; differential AC-coupled sine wave input clock, fCLK = 1.6 GHz at 0.5 VP-P with 50% duty cycle; VBG = floating; non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2 demultiplex non-DES mode; I and Q channels; duty-cycle stabilizer on.(1)(2) PARAMETER CONDITIONS Input leakage current (DES, LSPSM, CAL, TPM, NDM, FSR, DDRPh) IIL Input leakage current (SCLK, SDI, SCS) VIN = GND Input leakage current (PDI, PDQ, ECE) CIN_DIG Input capacitance (4) SUBGROUPS MIN TYP (3) MAX [1, 2, 3] –1 [1, 2, 3] –30 µA [1, 2, 3] –55 µA Each input to ground 1 UNIT 1.5 µA pF DIGITAL OUTPUT PINS (Data, DCLKI, DCLKQ, ORI, ORQ) - see Device Nomenclature VOD LVDS differential output voltage ΔVO DIFF Change in LVDS output swing between logic levels VOS Output offset voltage ΔVOS Change in output offset voltage between logic levels IOS Output short-circuit current ZO Differential output impedance VBG = floating, OVS = High [1, 2, 3] 380 600 840 mVP-P VBG = floating, OVS = Low [1, 2, 3] 240 440 650 mVP-P VBG = VA, OVS = high [1, 2, 3] 670 mVP-P VBG = VA, OVS = low [1, 2, 3] 500 mVP-P -20 1 20 mV VBG = floating 0.8 V VBG = VA 1.2 V ±1 mV ±3.8 mA 100 Ω 1.25 V VBG = floating; D+ and D− connected to 0.8 V DIFFERENTIAL DCLK RESET PINS (DCLK_RST) VCMI_DRST DCLK_RST Common mode Input Voltage VID_DRST Differential DCLK_RST Input Voltage 0.6 VP-P RIN_DRST Differential DCLK_RST Input Resistance (5) 100 Ω DIGITAL OUTPUT PINS (CalRun, SDO) VOH Logic high output level CalRun, SDO IOH = −400 µA [1, 2, 3] VOL Logic low output level CalRun, SDO IOH = 400 µA [1, 2, 3] (4) (5) 20 1.5 1.7 0.14 V 0.3 V The digital control pin capacitances are die capacitances only. Additional package capacitance of 1.6-pF each pin to ground are isolated from the die capacitances by lead and bond wire inductances. This parameter is specified by design and/or characterization and is not tested in production. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP ADC12D1620QML-SP www.ti.com SNAS717 – APRIL 2017 6.12 Converter Electrical Characteristics: Power Supply Characteristics The following specifications apply after calibration for VA = VDR = VTC = VE = 1.9 V; I and Q channels AC-coupled, FSR pin = high; CL = 10 pF; differential AC-coupled sine wave input clock, fCLK = 1.6 GHz at 0.5 VP-P with 50% duty cycle; VBG = floating; non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2 demultiplex non-DES mode; I and Q channels; duty-cycle stabilizer on. (1) (2) PARAMETER CONDITIONS SUBGROUPS MIN TYP (3) MAX UNIT fCLK = 1.6 GHz, 1:2 DEMUX MODE, NON-LSPSM PDI = PDQ = Low IA Analog supply current [1, 2, 3] 1160 mA PDI = Low; PDQ = High 637 mA PDI = High; PDQ = Low 635 mA 2 mA PDI = PDQ = High PDI = PDQ = Low Track-and-hold and clock supply current ITC 471 mA PDI = Low; PDQ = High [1, 2, 3] 284 mA PDI = High; PDQ = Low 284 mA 1 mA PDI = PDQ = High PDI = PDQ = Low Output driver supply current IDR 281 mA PDI = Low; PDQ = High [1, 2, 3] 149 mA PDI = High; PDQ = Low 143 mA PDI = PDQ = High PDI = PDQ = Low Digital encoder supply current IE [1, 2, 3] PDI = Low; PDQ = High PDI = High; PDQ = Low PDI = PDQ = High IT Total current (1) 54 mA 42 mA µA PDI = PDQ = Low [1, 2, 3] 2020 2280 mA PDI = Low; PDQ = High [1, 2, 3] 1120 1300 mA PDI = High; PDQ = Low [1, 2, 3] 1110 1300 mA PDI = PDQ = Low Power consumption µA mA 0.04 PDI = PDQ = High PC 8 90 2.7 [1, 2, 3] 3.8 mA 4.4 W PDI = Low; PDQ = High 2.1 PDI = High; PDQ = Low 2.1 W W PDI = PDQ = High 5.2 mW The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device. V A TO INTERNAL CIRCUITRY I/O GND (2) (3) To ensure accuracy, it is required that VA, VTC, VE and VDR be well bypassed. Each supply pin must be decoupled with separate bypass capacitors. Typical figures are at TA = 25°C, and represent most likely parametric norms. Test limits are ensured to Texas Instrument's average outgoing quality level (AOQL). Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP 21 ADC12D1620QML-SP SNAS717 – APRIL 2017 www.ti.com Converter Electrical Characteristics: Power Supply Characteristics (continued) The following specifications apply after calibration for VA = VDR = VTC = VE = 1.9 V; I and Q channels AC-coupled, FSR pin = high; CL = 10 pF; differential AC-coupled sine wave input clock, fCLK = 1.6 GHz at 0.5 VP-P with 50% duty cycle; VBG = floating; non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2 demultiplex non-DES mode; I and Q channels; duty-cycle stabilizer on.(1)(2) PARAMETER CONDITIONS SUBGROUPS MIN TYP (3) MAX UNIT fCLK = 800 MHz, 1:2 DEMUX MODE, LSPSM PDI = PDQ = Low IA Analog supply current [1, 2, 3] 754 mA PDI = Low; PDQ = High 423 mA PDI = High; PDQ = Low 423 mA 2 mA PDI = PDQ = High PDI = PDQ = Low ITC Track-and-hold and clock supply current 344 mA PDI = Low; PDQ = High [1, 2, 3] 212 mA PDI = High; PDQ = Low 212 mA PDI = PDQ = High 1 mA 273 mA PDI = Low; PDQ = High 141 mA PDI = High; PDQ = Low 141 mA PDI = PDQ = Low IDR Output driver supply current [1, 2, 3] PDI = PDQ = High PDI = PDQ = Low IE Digital encoder supply current [1, 2, 3] PDI = Low; PDQ = High PDI = High; PDQ = Low PDI = PDQ = High IT Total current 22 24 mA 22 mA µA PDI = PDQ = Low [1, 2, 3] 1417 1620 mA PDI = Low; PDQ = High [1, 2, 3] 801 940 mA PDI = High; PDQ = Low [1, 2, 3] 799 940 mA PDI = PDQ = Low Power consumption µA mA 0.03 PDI = PDQ = High PC 8 46 2.7 [1, 2, 3] 2.7 mA 3.1 W PDI = Low; PDQ = High 1.5 PDI = High; PDQ = Low 1.5 W PDI = PDQ = High 5.2 mW Submit Documentation Feedback W Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP ADC12D1620QML-SP www.ti.com SNAS717 – APRIL 2017 6.13 Converter Electrical Characteristics: AC Electrical Characteristics The following specifications apply after calibration for VA = VDR = VTC = VE = 1.9 V; I and Q channels AC-coupled, FSR pin = high; CL = 10 pF; differential AC-coupled sine wave input clock, fCLK = 1.6 GHz at 0.5 VP-P with 50% duty cycle; VBG = floating; non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2 demultiplex non-DES mode; I and Q channels; duty-cycle stabilizer on. (1) (2) PARAMETER CONDITIONS SUBGROUPS MIN [9, 10, 11] 1.6 GHz [9, 10, 11] 800 MHz TYP (3) MAX UNIT INPUT CLOCK (CLK) fCLK (max) fCLK (min) Maximum input clock frequency Minimum input clock frequency Non-LSPSM LSPSM Non-LSPSM 200 [9, 10, 11] DES mode LSPSM Input clock duty cycle (4) Non-DES mode; LFS = 1b Non-DES mode MHz 250 [9, 10, 11] fCLK(min) ≤ fCLK ≤ fCLK (max) 200 20% 50% MHz 80% tCL Input clock low time (4) 200 500 ps tCH Input clock high time (4) 200 500 ps ps DCLK_RST tSR Setup time DCLK_RST± 45 tHR Hold time DCLK_RST± 45 ps 5 Input Clock Cycles Pulse width DCLK_RST± tPWR DATA CLOCK (DCLKI, DCLKQ) DCLK duty cycle 50% 90° mode 4 0° mode 5 Input Clock Cycles tSYNC_DLY DCLK synchronization delay tLHT Differential low-to-high transition time 10% to 90%, CL = 2.5-pF 200 ps tHLT Differential high-to-low transition time 10% to 90%, CL = 2.5-pF 200 ps tSU Data-to-DCLK set-up time DDR mode, 90° DCLK 500 ps tH DCLK-to-data hold time DDR mode, 90° DCLK 500 ps tOSK DCLK-to-data output skew 50% of DCLK transition to 50% of data transition ±50 ps (1) The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device. V A TO INTERNAL CIRCUITRY I/O GND (2) (3) (4) The maximum clock frequency for non-demux mode is 1 GHz. Typical figures are at TA = 25°C, and represent most likely parametric norms. Test limits are ensured to Texas Instrument's average outgoing quality level (AOQL). This parameter is specified by design and/or characterization and is not tested in production. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP 23 ADC12D1620QML-SP SNAS717 – APRIL 2017 www.ti.com Converter Electrical Characteristics: AC Electrical Characteristics (continued) The following specifications apply after calibration for VA = VDR = VTC = VE = 1.9 V; I and Q channels AC-coupled, FSR pin = high; CL = 10 pF; differential AC-coupled sine wave input clock, fCLK = 1.6 GHz at 0.5 VP-P with 50% duty cycle; VBG = floating; non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2 demultiplex non-DES mode; I and Q channels; duty-cycle stabilizer on.(1)(2) PARAMETER CONDITIONS SUBGROUPS MIN TYP (3) MAX UNIT DATA INPUT-TO-OUTPUT tAD Sampling (aperture) delay tAJ Aperture jitter tOD Input clock-to data output delay (in addition to tLAT) Latency in 1:2 demux non-DES mode (4) Input CLK+ rise to acquisition of data 50% of input clock transition to 50% of data transition 1.3 ns 0.2 ps (rms) 3.2 ns DI, DQ outputs [4, 5, 6] 34 DId, DQd outputs [4, 5, 6] 35 DI outputs [4, 5, 6] 34 DQ outputs [4, 5, 6] 34.5 DId outputs [4, 5, 6] 35 DQd outputs [4, 5, 6] 35.5 Latency in non-demux non-DES mode (4) DI outputs [4, 5, 6] 34 DQ outputs [4, 5, 6] 34 Latency in non-demux DES mode (4) DI outputs [4, 5, 6] 34 DQ outputs [4, 5, 6] 34.5 tORR Over range recovery time Differential VIN step from ±1.2 V to 0 V to get accurate conversion PD low-to-rated accuracy conversion (wake-up time) Non-DES mode tWU Latency in 1:4 demux DES mode (4) tLAT Input Clock Cycles Input Clock Cycles Input Clock Cycles Input Clock Cycle 1 DES mode Input Clock Cycles 500 ns 1 µs 6.14 Electrical Characteristics: Delta Parameters over operating free-air temperature range (unless otherwise noted) (1) (2) (3) (4) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IA Analog supply current –6 6 mA ITC Track and hold supply current –4 4 mA IDR Output driver supply current –15 15 mA IE Digital encoder supply current –30 30 mA (1) (2) (3) (4) 24 Delta parameters are measured on the automated test equipment (ATE) as part of the ATE program at both pre and post burn-in. The four delta parameter currents are measured at the beginning of the ATE program. The voltage supply is then pulsed to the absolute max and the remainder of the ATE program is executed. After the ATE program is executed, the four delta parameter currents are measured again. The differences in the measured supply currents at the beginning and end of the ATE program are the delta parameters. Delta parameters are measured at TA = 25°C prior to burn-in and at TA= –55°C, 25°C, and 125°C after burn-in. The differences between supply currents measured before and after burn-in are not included in the delta parameter analysis. For delta parameters outside of the distribution, the corresponding parts are rejected. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP ADC12D1620QML-SP www.ti.com SNAS717 – APRIL 2017 6.15 Timing Requirements: Serial Port Interface over operating free-air temperature range (unless otherwise noted) The following specifications apply after calibration for VA = VDR = VTC = VE = 1.9 V; I and Q channels AC-coupled, FSR pin = High; CL = 10 pF; differential AC-coupled sine wave input clock, fCLK = 1.6 GHz at 0.5 VP-P with 50% duty cycle; VBG = floating; non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2 demultiplex non-DES mode; I and Q channels; duty-cycle stabilizer on. (1) (2) PARAMETER fSCLK TEST CONDITIONS SUBGROUPS MIN Maximum serial clock frequency See (4) NOM (3) MAX 15 UNIT MHz (max) fSCLK (min) Minimum serial clock frequency See (4) 0 MHz Serial clock low time [9, 10, 11] 30 ns Serial clock high time [9, 10, 11] 30 ns tSSU Serial data to serial clock rising setup time See (4) 2.5 ns tSH Serial data to serial clock rising hold time See (4) 1 ns tSCS SCS to serial clock rising setup time 2.5 ns tHCS SCS to serial clock falling hold time 1.5 ns tBSU Bus turnaround time 10 ns (1) The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device. V A TO INTERNAL CIRCUITRY I/O GND (2) (3) (4) The maximum clock frequency for non-demux mode is 1 GHz. Typical figures are at TA = 25°C, and represent most likely parametric norms. Test limits are ensured to Texas Instrument's average outgoing quality level (AOQL). This parameter is specified by design and/or characterization and is not tested in production. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP 25 ADC12D1620QML-SP SNAS717 – APRIL 2017 www.ti.com 6.16 Timing Requirements: Calibration over operating free-air temperature range (unless otherwise noted) The following specifications apply after calibration for VA = VDR = VTC = VE = 1.9 V; I and Q channels AC-coupled, FSR pin = high; CL = 10 pF; differential AC-coupled sine wave input clock, fCLK = 1.6 GHz at 0.5 VP-P with 50% duty cycle; VBG = floating; non-extended control mode; Rext = Rtrim = 3300 Ω ±0.1%; analog signal source impedance = 100-Ω differential; 1:2 demultiplex non-DES mode; I and Q channels; duty-cycle stabilizer on. (1) (2) PARAMETER TEST CONDITIONS SUBGROUPS MIN NOM (3) MAX UNIT Non-ECM tCAL Calibration cycle time 4.1 × 107 ECM; CSS = 0b Clock Cycles ECM; CSS = 1b tCAL_L CAL pin low time tCAL_H CAL pin high time (1) See Figure 8, note (4) See Figure 8, note (4) [9, 10, 11] 1280 Clock Cycles [9, 10, 11] 1280 Clock Cycles The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device. V A TO INTERNAL CIRCUITRY I/O GND (2) (3) (4) The maximum clock frequency for non-demux mode is 1 GHz. Typical figures are at TA = 25°C, and represent most likely parametric norms. Test limits are ensured to Texas Instrument's average outgoing quality level (AOQL). This parameter is specified by design and/or characterization and is not tested in production. 6.17 Quality Conformance Inspection MIL-STD-883, Method 5005 - Group A 26 SUBGROUP DESCRIPTION 1 Static tests at TEMPERATURE (°C) +25 2 Static tests at +125 3 Static tests at -55 4 Dynamic tests at +25 5 Dynamic tests at +125 6 Dynamic tests at -55 7 Functional tests at +25 8A Functional tests at +125 8B Functional tests at -55 9 Switching tests at +25 10 Switching tests at +125 11 Switching tests at -55 12 Setting time at +25 13 Setting time at +125 14 Setting time at -55 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP ADC12D1620QML-SP www.ti.com SNAS717 – APRIL 2017 6.18 Timing Diagrams Sample N DI Sample N-1 DId VINI+/- Sample N+1 tAD CLK+ tOD DId, DI Sample N-39 and Sample N-38 Sample N-37 and Sample N-36 Sample N-35 and Sample N-34 tOSK DCLKI+/(0° Phase) tSU tH DCLKI+/(90° Phase) Figure 1. Clocking in Non-LSPSM, 1:2 Demux, Non-DES Mode* Sample N Sample N-1 DQ DQ VINQ+/- Sample N+1 tAD CLK+ tOD DQ Sample N-37 Sample N-36 Sample N-35 Sample N-34 Sample N-33 tOSK DCLKQ+/(0° Phase) Figure 2. Clocking in Non-LSPSM, Non-Demux, Non-DES Mode* Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP 27 ADC12D1620QML-SP SNAS717 – APRIL 2017 www.ti.com Timing Diagrams (continued) DId VINQ+/- DQd c Sample N-1.5 Sample N-1 DQ DI c c Sample N Sample N-0.5 c Sample N+1 tAD c c CLK+/tOD DQd, DId, DQ, DI Sample N-37.5, N-37, N-36.5, N-36 Sample N-39.5, N-39, N-38.5, N-38 Sample N-35.5, N-35, N-34.5, N-34 tOSK DCLKQ+/(0° Phase) tSU tH DCLKQ+/(90° Phase) Figure 3. Clocking in Non-LSPSM, 1:4 Demux DES Mode* Sample N-1 DI Sample N - 0.5 DQ Sample N DI VINQ+/- Sample N + 0.5 DQ Sample N+1 tAD CLK+ tOD DQ, DI Sample N-37.5, N-37 Sample N-36.5, N-36 Sample N-35.5, N-35 Sample N-34.5, N-34 Sample N-33.5, N-33 tOSK DCLKQ+/(0° Phase) Figure 4. Clocking in Non-LSPSM, Non-Demux Mode DES Mode* 28 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP ADC12D1620QML-SP www.ti.com SNAS717 – APRIL 2017 Timing Diagrams (continued) Sample N DI Sample N-1 DId VINI+/- Sample N+1 tAD CLK+ tOD DId, DI Sample N-22.5 and Sample N-21.5 Sample N-20.5 and Sample N-19.5 Sample N-18.5 and Sample N-17.5 tOSK DCLKI+/(SDR Rising) Figure 5. Clocking in LSPSM, 1:2 Demux Mode, Non-DES Mode* Sample N Sample N-1 DQ DQ VINQ+/- Sample N+1 tAD CLK+ tOD DQ Sample N-20 Sample N-19 Sample N-18 Sample N-17 Sample N-16 tOSK DCLKQ+/(DDR 0° Phase) tSU tH DCLKQ+/(DDR 90° Phase) tOSK DCLKI+/(SDR Rising) Figure 6. Clocking in LSPSM, Non-Demux Mode, Non-DES Mode* * The timing for Figure 1 through Figure 6 is shown for the one input only (I or Q). However, both I and Q inputs may be used. For this case, the I channel functions precisely the same as the Q channel, with VinI, DCLKI, DId, and DI instead of VinQ, DCLKQ, DQd, and DQ. Both I and Q channel use the same CLK. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP 29 ADC12D1620QML-SP SNAS717 – APRIL 2017 www.ti.com Timing Diagrams (continued) Synchronizing Edge tSYNC_DLY CLK tHR tSR DCLK_RSTtOD DCLK_RST+ tPWR DCLKI+ DCLKQ+ Figure 7. Data Clock Reset Timing (Demux Mode) tCAL CalRun tCAL_H CAL tCAL_L POWER SUPPLY Figure 8. On-Command Calibration Timing Single Register Access SCS tSCS tHCS tHCS 1 8 24 9 SCLK SDI Command Field Data Field LSB MSB tSH tSSU tBSU SDO read mode) Data Field High Z MSB High Z LSB Figure 9. Serial Interface Timing 30 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP ADC12D1620QML-SP www.ti.com SNAS717 – APRIL 2017 Timing Diagrams (continued) IDEAL POSITIVE FULL-SCALE TRANSITION Output Code ACTUAL POSITIVE FULL-SCALE TRANSITION 1111 1111 1111 (4095) 1111 1111 1110 (4094) POSITIVE FULL-SCALE ERROR 1111 1111 1101 (4093) MID-SCALE TRANSITION 1000 0000 0000 (2048) 0111 1111 1111 (2047) OFFSET ERROR IDEAL NEGATIVE FULL-SCALE TRANSITION ACTUAL NEGATIVE FULL-SCALE TRANSITION NEGATIVE FULL-SCALE ERROR 0000 0000 0010 (2) 0000 0000 0001 (1) 0000 0000 0000 (0) -VIN/2 (VIN+) < (VIN-) (VIN+) > (VIN-) 0.0V +VIN/2 Differential Analog Input Voltage (+VIN/2) - (-VIN/2) Figure 10. Input / Output Transfer Characteristic Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP 31 ADC12D1620QML-SP SNAS717 – APRIL 2017 www.ti.com 6.19 Typical Characteristics 4 4 2 2 INL (LSB) INL (LSB) VA = VDR = VTC = VE = 1.9 V, fCLK = 1600 MHz in non-LSPSM and 800 MHz in LSPSM, fIN = 248 MHz, TA= 25°C, 1:2 demux non-DES mode, and calibration performed after temperature, supply voltage or sample rate change, unless otherwise stated. 0 ±2 -2 ±4 0 -4 -65 4095 Output Code 0.4 2 DNL (LSB) DNL (LSB) 4 0.0 ±0.4 85 Output Code 9 9 ENOB (bits) 10 8 Non-LSPSM 1600 MSPS DES 3200 MSPS LSPSM 800 MSPS 6 800 1200 1600 2000 2400 2800 3200 3600 Sample Rate (MSPS) Figure 15. ENOB vs Sample Rate 35 Temperature (RC) 85 135 Figure 14. Minimum and Maximum DNL vs Temperature Figure 13. DNL vs Code 400 -15 C004 10 7 +DNL -DNL -4 -65 4095 0 135 0 -2 ±0.8 ENOB (bits) 35 Temperature (RC) Figure 12. Minimum and Maximum INL vs Temperature Figure 11. INL vs Code 32 -15 C001 0.8 0 +INL -INL 0 8 7 Non-LSPSM 1600 MSPS DES 3200 MSPS LSPSM 800 MSPS 6 1.8 1.9 VA (V) 2 Figure 16. ENOB vs Supply Voltage Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP ADC12D1620QML-SP www.ti.com SNAS717 – APRIL 2017 Typical Characteristics (continued) 10 10 9 9 ENOB (bits) ENOB (bits) VA = VDR = VTC = VE = 1.9 V, fCLK = 1600 MHz in non-LSPSM and 800 MHz in LSPSM, fIN = 248 MHz, TA= 25°C, 1:2 demux non-DES mode, and calibration performed after temperature, supply voltage or sample rate change, unless otherwise stated. 8 Non-LSPSM 1600 MSPS DES 3200 MSPS LSPSM 800 MSPS 7 6 -55 8 Non-LSPSM 1600 MSPS DES 3200 MSPS LSPSM 800 MSPS 7 6 -25 5 35 65 Temperature (RC) 95 125 0 70 65 65 60 60 55 50 45 400 800 Non-LSPSM 1600 MSPS DES 3200 MSPS LSPSM 800 MSPS 1.9 VA (V) 65 65 60 60 55 50 35 -55 2 Figure 20. SNR vs Supply Voltage 70 SNR (dBFS) SNR (dBFS) Figure 19. SNR vs Sample Rate 70 55 50 45 Non-LSPSM 1600 MSPS DES 3200 MSPS LSPSM 800 MSPS 40 3200 50 35 1.8 1200 1600 2000 2400 2800 3200 3600 Sample Rate (MSPS) 45 2800 55 40 35 0 1200 1600 2000 2400 Input Frequency (MHz) 45 Non-LSPSM 1600 MSPS DES 3200 MSPS LSPSM 800 MSPS 40 800 Figure 18. ENOB vs Input Frequency 70 SNR (dBFS) SNR (dBFS) Figure 17. ENOB vs Temperature 400 Non-LSPSM 1600 MSPS DES 3200 MSPS LSPSM 800 MSPS 40 35 -25 5 35 65 Temperature (RC) 95 Figure 21. SNR vs Temperature 125 0 400 800 1200 1600 2000 2400 Input Frequency (MHz) 2800 3200 Figure 22. SNR vs Input Frequency Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP 33 ADC12D1620QML-SP SNAS717 – APRIL 2017 www.ti.com Typical Characteristics (continued) VA = VDR = VTC = VE = 1.9 V, fCLK = 1600 MHz in non-LSPSM and 800 MHz in LSPSM, fIN = 248 MHz, TA= 25°C, 1:2 demux non-DES mode, and calibration performed after temperature, supply voltage or sample rate change, unless otherwise stated. -40 -40 Non-LSPSM 1600 MSPS DES 3200 MSPS LSPSM 800 MSPS -50 THD (dBFS) THD (dBFS) -50 -60 -60 -70 -70 -80 1.8 -80 0 400 800 Non-LSPSM 1600 MSPS DES 3200 MSPS LSPSM 800 MSPS 1200 1600 2000 2400 2800 3200 3600 Sample Rate (MSPS) 1.9 VA (V) Figure 23. THD vs Sample Rate Figure 24. THD vs Supply Voltage -40 -40 Non-LSPSM 1600 MSPS DES 3200 MSPS LSPSM 800 MSPS Non-LSPSM 1600 MSPS DES 3200 MSPS LSPSM 800 MSPS -50 THD (dBFS) THD (dBFS) -50 -60 -70 -60 -70 -80 -55 -80 -25 5 35 65 Temperature (RC) 95 125 0 70 70 60 Non-LSPSM 1600 MSPS DES 3200 MSPS LSPSM 800 MSPS 50 400 800 1200 1600 2000 2400 2800 3200 3600 Sample Rate (MSPS) Figure 27. SFDR vs Sample Rate 34 800 1200 1600 2000 2400 Input Frequency (MHz) 2800 3200 60 50 40 400 Figure 26. THD vs Input Frequency 80 SFDR (dBFS) SFDR (dBFS) Figure 25. THD vs Temperature 80 0 2 Non-LSPSM 1600 MSPS DES 3200 MSPS LSPSM 800 MSPS 40 1.8 1.9 VA (V) 2 Figure 28. SFDR vs Supply Voltage Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP ADC12D1620QML-SP www.ti.com SNAS717 – APRIL 2017 Typical Characteristics (continued) 80 80 70 70 SFDR (dBFS) SFDR (dBFS) VA = VDR = VTC = VE = 1.9 V, fCLK = 1600 MHz in non-LSPSM and 800 MHz in LSPSM, fIN = 248 MHz, TA= 25°C, 1:2 demux non-DES mode, and calibration performed after temperature, supply voltage or sample rate change, unless otherwise stated. 60 Non-LSPSM 1600 MSPS DES 3200 MSPS LSPSM 800 MSPS 50 40 -55 60 50 Non-LSPSM 1600 MSPS DES 3200 MSPS LSPSM 800 MSPS 40 -25 5 35 65 Temperature (RC) 95 125 0 Figure 29. SFDR vs Temperature 400 800 1200 1600 2000 2400 Input Frequency (MHz) 2800 3200 Figure 30. SFDR vs Input Frequency 70 10 65 60 8 SNR (dBFS) ENOB (bits) 9 R Calibrated at 87.5 C No recalibration at other temps 55 50 Calibrated at 87.5RC No recalibration at other temps 45 7 40 6 -55 -25 5 fCLK = 1.6 GHz 35 65 Temperature (RC) 95 35 -55 125 fIN = 248 MHz -50 70 SFDR (dBFS) THD (dBFS) 80 -60 -25 fCLK = 1.6 GHz 5 35 65 Temperature (RC) 95 125 fIN = 248 MHz 125 60 Calibrated at 87.5RC No recalibration at other temps 40 -55 -25 fCLK = 1.6 GHz Figure 33. THD vs Temperature Calibration at 87.5°C Only 95 fIN = 248 MHz 50 Calibrated at 87.5RC No recalibration at other temps 35 65 Temperature (RC) Figure 32. SNR vs Temperature Calibration at 87.5°C Only -40 -80 -55 5 fCLK = 1.6 GHz Figure 31. ENOB vs Temperature Calibration at 87.5°C Only -70 -25 5 35 65 Temperature (RC) 95 125 fIN = 248 MHz Figure 34. SFDR vs Temperature Calibration at 87.5°C Only Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP 35 ADC12D1620QML-SP SNAS717 – APRIL 2017 www.ti.com Typical Characteristics (continued) VA = VDR = VTC = VE = 1.9 V, fCLK = 1600 MHz in non-LSPSM and 800 MHz in LSPSM, fIN = 248 MHz, TA= 25°C, 1:2 demux non-DES mode, and calibration performed after temperature, supply voltage or sample rate change, unless otherwise stated. -50 -50 -60 IMD3 (dBFS) IMD3 (dBFS) -60 -70 -80 -70 -80 Non-LSPSM 1600 MSPS DES 3200 MSPS -90 -90 0 1000 2000 Input Frequency (MHz) 3000 0 Figure 35. 3rd Order Intermodulation Distortion vs Input Frequency -30 0 -40 -3 -50 -60 -70 -80 1000 2000 Input Frequency (MHz) 3000 Figure 36. 3rd Order Intermodulation Distortion vs Input Frequency (DES Mode 3200 MSPS) Signal Gain (dB) Crosstalk (dBFS) -7 dBFS -13 dBFS -16 dBFS -6 -9 -12 Non-LSPSM 1600 MSPS DES 3200 MSPS DESIQ 3200 MSPS -15 I Channel Q Channel -90 -18 0 400 800 1200 1600 2000 2400 Input Frequency (MHz) 2800 3200 0 Figure 37. Cross Talk vs Input Frequency 400 800 1200 1600 2000 2400 2800 3200 3600 4000 Input Frequnecy (MHz) Figure 38. Insertion Loss vs Input Frequency 4 Power (W) 3.5 3 2.5 LSPSM Non-LSPSM 2 0 400 800 1200 1600 Sample Rate (MSPS) C024 Figure 39. Power Consumption vs Sample Rate 36 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP ADC12D1620QML-SP www.ti.com SNAS717 – APRIL 2017 7 Detailed Description 7.1 Overview The ADC12D1620 device is a versatile analog-to-digital converter (ADC) with an innovative architecture, which permits very high-speed operation. The controls available ease the application of the device to circuit solutions. Optimum performance requires adherence to the provisions discussed here and in the Application Information. This section covers an overview, a description of control modes (extended control mode and non-extended control mode), and features. The ADC12D1620 device uses a calibrated folding and interpolating architecture that achieves a high effective number of bits (ENOB). The use of folding amplifiers greatly reduces the number of comparators and power consumption. Interpolation reduces the number of front-end amplifiers required, minimizing the load on the input signal and further reducing power requirements. In addition to correcting other non-idealities, on-chip calibration reduces the INL bow often seen with folding architectures. The result is an extremely fast, high-performance, low-power converter. 7.1.1 Operation Summary A differential analog input is digitized into 12 bits. Differential input signals below the negative full-scale range cause the output word to be all zeroes. Differential inputs above the positive full-scale range results in the output word being all ones. If either case happens, the out-of-range output for the respective channel has a logic-high signal. There are 4 major sampling modes: 1. Dual-channel ADC with a sampling range of 200 to 1600 MSPS. 2. Single channel, interleaved ADC in dual-edge sampling with a sampling range of 500 to 3200 MSPS. 3. Dual-channel ADC in LSPSM with a sampling range of 200 to 800 MSPS. 4. Single channel, interleaved ADC in LSPSM and dual-edge sampling with a sampling range of 500 to 1600 MSPS. The device has many operating options. Some of these options can be controlled through pin configurations in non-extended control mode (non-ECM or sometimes known as pin-control mode). An expanded feature set is available in extended control mode (ECM) through the serial interface. Each channel has a selectable output demultiplexer that feeds two LVDS buses. Depending upon the sampling mode and the demux option chosen, the output data rate can be the same, one half, or one quarter the sample rate. 7.2 Functional Block Diagram Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP 37 ADC12D1620QML-SP SNAS717 – APRIL 2017 www.ti.com 7.3 Feature Description The ADC12D1620 offers many features to make the device convenient to use in a wide variety of applications. Table 1 is a summary of the features available, as well as details for the control mode chosen. N/A means Not Applicable. Table 1. Features and Modes NON-ECM CONTROL PIN ACTIVE IN ECM ECM DEFAULT ECM STATE AC- and DC-coupled mode selection Selected through VCMO (Pin C2) Yes Not available N/A Input full-scale range adjust Selected through FSR (Pin Y3) No Selected through the Configuration Register (Addr: 3h and Bh) Mid FSR value Not available N/A Selected through the Configuration Register (Addr: 2h and Ah) Offset = 0 mV Selected through LSPSM (Pin V4) Yes Not available N/A Selected through DES (Pin V5) No Selected through the DES bit (Addr: 0h; Bit: 7) Non-DES mode DES mode input selection Not available N/A Selected through the DEQ, DIQ bits (Addr: 0h; Bits: 6:5) N/A DESCLKIQ mode Not available N/A Selected through the DCK bit (Addr: Eh; Bit: 6) N/A DES timing adjust Not available N/A Selected through the DES Timing Adjust Reg (Addr: 7h) Mid skew offset Sampling clock phase adjust Not available N/A Selected through the Configuration Register (Addr: Ch and Dh) tAD adjust disabled DDR clock phase selection Selected through DDRPh (Pin W4) No Selected through the DPS bit (Addr: 0h; Bit: 14) 0° mode DDR / SDR DCLK selection Not available N/A Selected through the SDR bit (Addr: 0h; Bit: 2) DDR mode SDR rising / falling DCLK Selection Not available N/A Selected through the DPS bit (Addr: 0h; Bit: 14) N/A LVDS differential voltage amplitude selection Higher amplitude only N/A Selected through the OVS bit (Addr: 0h; Bit: 13) Higher amplitude LVDS common-mode voltage amplitude selection Selected through VBG (Pin B1) Yes Not available N/A Output formatting selection Offset binary only N/A Selected through the 2SC bit (Addr: 0h; Bit: 4) Offset binary Test pattern mode at output Selected through TPM (Pin A4) No Selected through the TPM bit (Addr: 0h; Bit: 12) TPM disabled Demux/Non-demux mode selection Selected through NDM (Pin A5) Yes Not available N/A AutoSync Not available N/A Selected through the Configuration Register (Addr: Eh) Master mode, RCOut1, RCOut2 disabled DCLK reset Not available N/A Selected through the Configuration Register (Addr: Eh; Bit: 0) DCLK reset disabled Time stamp Not available N/A Selected through the TSE bit (Addr: 0h; Bit: 3) Time stamp disabled FEATURE INPUT CONTROL AND ADJUST Input offset adjust setting Low-sampling power-saving mode DES / Non-DES mode selection OUTPUT CONTROL AND ADJUST 38 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP ADC12D1620QML-SP www.ti.com SNAS717 – APRIL 2017 Feature Description (continued) Table 1. Features and Modes (continued) NON-ECM CONTROL PIN ACTIVE IN ECM ECM DEFAULT ECM STATE Selected through CAL (Pin D6) Yes Selected through the CAL bit (Addr: 0h; Bit: 15) N/A (CAL = 0) Calibration Adjust Not available N/A Selected through the Configuration Register (Addr: 4h) tCAL Read/Write calibration settings Not available N/A Selected through the SSC bit (Addr: 4h; Bit: 7) R/W calibration values disabled Power down I channel Selected through PDI (Pin U3) Yes Selected through the PDI bit (Addr: 0h; Bit: 11) I-channel operational Power down Q channel Selected through PDQ (Pin V3) Yes Selected through the PDQ bit (Addr: 0h; Bit: 10) Q-channel operational FEATURE CALIBRATION On-command calibration POWER-DOWN 7.3.1 Input Control and Adjust There are several features and configurations for the input of the ADC12D1620 device that enable it to be used in many different applications. AC- and DC-coupled modes, input full-scale range adjust, input offset adjust, LSPSM, DES/non-DES modes, and sampling clock phase adjust are discussed in the following sections. 7.3.1.1 AC- and DC-Coupled Modes The analog inputs may be AC- or DC-coupled. See AC- or DC-Coupled Mode Pin (VCMO) for information on how to select the desired mode. For applications information, see DC-Coupled Input Signals and AC-Coupled Input Signals. 7.3.1.2 Input Full-Scale Range Adjust The input full-scale range for the ADC12D1620 may be adjusted through non-ECM or ECM. In non-ECM, a control pin selects a higher or lower value; see Full-Scale Input-Range Pin (FSR). In ECM, the full-scale input range of the I- and Q-channel inputs may be independently set with 15 bits precision through the I- and Qchannel Full-Scale Range Adjust Registers (Addr: 3h and Addr: Bh, respectively). See VIN_FSR in Converter Electrical Characteristics: Analog Input/Output and Reference Characteristics for electrical specification details. Note that the higher and lower full-scale input range settings in non-ECM correspond to the middle and minimum full-scale input range settings in ECM. An on-command calibration must be executed following a change of the input full-scale range. See Table 16 and Table 24 for information about the registers. 7.3.1.3 Input Offset Adjust The input offset adjust for the ADC12D1620 may be adjusted in ECM with 12 bits precision plus sign through the I- and Q-channel Offset Adjust Registers (Addr: 2h and Addr: Ah, respectively). See Table 15 and Table 23 for information about the registers. 7.3.1.4 Low-Sampling Power-Saving Mode (LSPSM) For applications with input clock speeds 200 to 800 MHz, the ADC12D1620 device can be switched to the LSPSM for a reduction in power consumption of approximately 20%. See Low-Sampling Power-Saving Mode Pin (LSPSM) for information on how to select the desired mode and details on operation in this mode. 7.3.1.5 DES Timing Adjust The performance of the ADC12D1620 in DES mode depends on how well the two channels are interleaved (that is, that the clock samples either channel with precisely a 50% duty-cycle); each channel has the same offset (nominally code 2047/2048), and each channel has the same full-scale range. The ADC12D1620 device includes an automatic clock phase background adjustment in DES mode to automatically and continuously adjust the clock phase of the I and Q channels. In addition to this, the residual fixed timing skew offset may be further Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP 39 ADC12D1620QML-SP SNAS717 – APRIL 2017 www.ti.com manually adjusted, and further reduce timing spurs for specific applications. See DES Timing Adjust (Addr: 7h). As the DES timing adjust is programmed from 0d to 127d, the magnitude of the Fs/2-Fin timing interleaving spur decreases to a local minimum and then increases again. The default, nominal setting of 64d may or may not coincide with this local minimum. The user may manually skew the global timing to achieve the lowest possible timing interleaving spur. 7.3.1.6 Sampling Clock Phase Adjust The sampling clock (CLK) phase may be delayed internally to the ADC up to 825 ps in ECM. This feature helps the system designer remove small imbalances in clock distribution traces at the board level when multiple ADCs are used, or to simplify complex system functions such as beam steering for phase-array antennas. Additional delay in the clock path also creates additional jitter when using the sampling clock phase adjust. Because the sampling clock phase adjust delays all clocks, including the DCLKs and output data, the user is strongly advised to use the minimal amount of adjustment and verify the net benefit of this feature in their system before relying on it. 7.3.2 Output Control and Adjust There are several features and configurations for the ADC12D1620 output that make the device ideal for many different applications. This section covers DDR clock phase, LVDS output differential and common-mode voltage, output formatting, test pattern mode, and time stamp. 7.3.2.1 SDR / DDR Clock The ADC12D1620 output data can be delivered in double data rate (DDR) or single data rate (SDR). For DDR, the DCLK frequency is half the data rate, and data is sent to the outputs on both edges of DCLK; see Figure 40. The DCLK-to-data phase relationship may be either 0° or 90°. For 0° mode, the data transitions on each edge of the DCLK. Any offset from this timing is tOSK; (see Converter Electrical Characteristics: AC Electrical Characteristics for details). For 90° mode, the DCLK transitions in the middle of each data cell. Setup and hold times for this transition, tSU and tH, may also be found in Converter Electrical Characteristics: AC Electrical Characteristics. The DCLK-to-data phase relationship may be selected through the DDRPh pin in non-ECM (see Dual Data-Rate Phase Pin (DDRPh)) or the DPS bit in the Configuration Register (Addr: 0h; Bit: 14) in ECM. Note that for DDR mode, the 1:2 demux mode is not available in LSPSM. Data DCLK 0° Mode DCLK 90° Mode Figure 40. DDR DCLK-to-Data Phase Relationship For SDR, the DCLK frequency is the same as the data rate, and data is sent to the outputs on a single edge of DCLK; see Figure 41. The data may transition on either the rising or falling edge of DCLK. Any offset from this timing is tOSK; see Converter Electrical Characteristics: AC Electrical Characteristics for details. The DCLK rising or falling edge may be selected through the SDR bit in the Configuration Register (Addr: 0h; Bit: 2) in ECM only. 40 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP ADC12D1620QML-SP www.ti.com SNAS717 – APRIL 2017 Data DCLK SDR Rising DCLK SDR Falling Figure 41. SDR DCLK-to-Data Phase Relationship 7.3.2.2 LVDS Output Differential Voltage The ADC12D1620 device is available with a selectable higher or lower LVDS output differential voltage. This parameter is VOD, found in Converter Electrical Characteristics: Digital Control and Output Pin Characteristics. The desired voltage may be selected through the OVS bit in the Configuration Register (Addr: 0h, Bit: 13). For many applications, such as when the LVDS outputs are very close to an FPGA on the same board, the lower setting is sufficient for good performance; this also reduces the possibility for EMI from the LVDS outputs to other signals on the board. See Configuration Register 1 for more information. 7.3.2.3 LVDS Output Common-Mode Voltage The ADC12D1620 is available with a selectable higher or lower LVDS output common-mode voltage. This parameter is VOS, found in Converter Electrical Characteristics: Digital Control and Output Pin Characteristics. See LVDS Output Common-Mode Pin (VBG) for information on how to select the desired voltage. 7.3.2.4 Output Formatting The formatting at the digital data outputs may be either offset binary or two's complement. The default formatting is offset binary, but two's complement may be selected through the 2SC bit of the Configuration Register (Addr: 0h; Bit: 4); see Configuration Register 1 for more information. 7.3.2.5 Test-Pattern Mode The ADC12D1620 can provide a test pattern at the four output buses, independent of the input signal, that aids in system debug. In test-pattern mode, the ADC is disengaged, and a test pattern generator is connected to the outputs, including ORI and ORQ. The test pattern output is the same in DES mode or non-DES mode. Each port is given a unique 12-bit word, alternating between 1's and 0's. When the device is programmed into the demux mode, the order of the test pattern is described in Table 2. If the I or Q channel is powered down, the test pattern is not output for that channel. Table 2. Test Pattern by Output Port in Non-LSPSM Demux Mode TIME Qd Id Q I ORQ ORI T0 000h 004h 008h 010h 0b 0b T1 FFFh FFBh FF7h FEFh 1b 1b T2 000h 004h 008h 010h 0b 0b T3 FFFh FFBh FF7h FEFh 1b 1b T4 000h 004h 008h 010h 0b 0b T5 000h 004h 008h 010h 0b 0b T6 FFFh FFBh FF7h FEFh 1b 1b T7 000h 004h 008h 010h 0b 0b T8 FFFh FFBh FF7h FEFh 1b 1b T9 000h 004h 008h 010h 0b 0b COMMENTS Pattern Sequence n Pattern Sequence n+1 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP 41 ADC12D1620QML-SP SNAS717 – APRIL 2017 www.ti.com Table 2. Test Pattern by Output Port in Non-LSPSM Demux Mode (continued) TIME Qd Id Q I ORQ ORI T10 000h 004h 008h 010h 0b 0b T11 FFFh FFBh FF7h FEFh 1b 1b T12 000h 004h 008h 010h 0b 0b T13 ... ... ... ... ... ... COMMENTS Pattern Sequence n+2 When the device is programmed into the non-demux mode, the test pattern’s order is described in Table 3. Table 3. Test Pattern by Output Port in Non-LSPSM Non-Demux Mode TIME Q I ORQ ORI T0 000h 004h 0b 0b T1 000h 004h 0b 0b T2 FFFh FFBh 1b 1b T3 FFFh FFBh 1b 1b T4 000h 004h 0b 0b T5 FFFh FFBh 1b 1b T6 000h 004h 0b 0b T7 FFFh FFBh 1b 1b T8 FFFh FFBh 1b 1b T9 FFFh FFBh 1b 1b T10 000h 004h 0b 0b T11 000h 004h 0b 0b T12 FFFh FFBh 1b 1b T13 FFFh FFBh 1b 1b T14 ... ... ... ... COMMENTS Pattern Sequence n Pattern Sequence n+1 Table 4. Test Pattern by Output Port in LSPSM Demux Mode 42 TIME Qd Id Q I ORQ ORI T0 FF7h FEFh 008h 010h 1b 1b T1 FF7h FEFh 008h 010h 1b 1b T2 008h 010h FF7h FEFh 1b 1b T3 008h 010h FF7h FEFh 1b 1b T4 008h 010h 008h 010h 0b 0b T5 FF7h FEFh 008h 010h 1b 1b T6 FF7h FEFh 008h 010h 1b 1b T7 008h 010h FF7h FEFh 1b 1b T8 008h 010h FF7h FEFh 1b 1b T9 008h 010h 008h 010h 0b 0b T10 FF7h FEFh 008h 010h 1b 1b T11 FF7h FEFh 008h 010h 1b 1b T12 008h 010h FF7h FEFh 1b 1b T13 ... ... ... ... ... ... Submit Documentation Feedback COMMENTS Pattern sequence n Pattern sequence n+1 Pattern sequence n+2 Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP ADC12D1620QML-SP www.ti.com SNAS717 – APRIL 2017 Table 5. Test Pattern by Output Port in LSPSM Non-Demux Mode TIME Q I ORQ ORI T0 008h 010h 0b 0b T1 FF7h FEFh 1b 1b T2 008h 010h 0b 0b T3 FF7h FEFh 1b 1b T4 008h 010h 0b 0b T5 008h 010h 0b 0b T6 FF7h FEFh 1b 1b T7 008h 010h 0b 0b T8 FF7h FEFh 1b 1b T9 008h 010h 0b 0b T10 008h 010h 0b 0b T11 FF7h FEFh 1b 1b T12 008h 010h 0b 0b T13 FF7h FEFh 1b 1b T14 ... ... ... ... COMMENTS Pattern sequence n Pattern sequence n+1 Pattern sequence n+2 7.3.2.6 Time Stamp The time-stamp feature enables the user to capture the timing of an external trigger event, relative to the sampled signal. When enabled through the TSE bit of the Configuration Register (Addr: 0h; Bit: 3), the LSB of the digital outputs (DQd, DQ, DId, DI) captures the trigger information. In effect, the 12-bit converter becomes an 11-bit converter, and the LSB acts as a 1-bit converter with the same latency as the 11-bit converter. Apply the trigger to the DCLK_RST input. It may be asynchronous to the ADC sampling clock. 7.3.3 Calibration Feature The ADC12D1620 calibration must be run to achieve specified performance. The calibration procedure is exactly the same regardless of how it was initiated or when it is run. Calibration trims the analog input differential termination resistors, the CLK input resistor, and sets internal bias currents that affect the linearity of the converter. This minimizes full-scale error, offset error, DNL and INL, which results in the maximum dynamic performance, as measured by the SNR, THD, SINAD (SNDR), and ENOB pins. 7.3.3.1 Calibration Control Pins and Bits Table 6 is a summary of the pins and bits used for calibration. See Pin Configuration and Functions for complete pin information and Figure 8 for the timing diagram. Table 6. Calibration Pins PIN (Bit) NAME FUNCTION D6 (Addr: 0h; Bit: 15) CAL (Calibration) Initiate calibration; see Calibration Pin (CAL) (Addr: 4h) Calibration Adjust Adjust calibration sequence B5 CalRun (Calibration Running) Indicates while calibration is running C1/D2 Rtrim+, Rtrim– (Input termination trim resistor) External resistor used to calibrate analog and CLK inputs C3/D3 Rext+, Rext– (External Reference resistor) External resistor used to calibrate internal linearity Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP 43 ADC12D1620QML-SP SNAS717 – APRIL 2017 www.ti.com 7.3.3.2 How to Execute a Calibration Calibration may be initiated by holding the CAL pin low for at least tCAL_L clock cycles, then holding it high for at least tCAL_H clock cycles, as defined in Timing Requirements: Calibration. The minimum tCAL_L and tCAL_H input clock cycle sequences are required to ensure that random noise does not cause a calibration to begin when it is not desired. The time taken by the calibration procedure is specified as tCAL. The CAL pin is active in both ECM and non-ECM. However, in ECM, the CAL pin is logically OR'd with the CAL bit, so both the pin and bit must be set low before executing another calibration with either pin or bit. TI recommends holding the CAL pin high during normal usage of the ADC12D1620 device to reduce the chance that an SEU causes a calibration cycle. 7.3.3.3 On-Command Calibration In addition to executing a calibration after power-on and device stabilization, in order to obtain optimal parametric performance TI recommends execution of an on-command calibration whenever the settings or conditions to the device are significantly altered. Some examples include: changing the FSR through either ECM or Non-ECM, power-cycling either channel, and switching into or out of DES mode. For best performance, it is also recommended that an on-command calibration be run 20 seconds or more after application of power and whenever the operating temperature changes significantly relative to the specific system performance requirements. See Figure 31 for the impact temperature change can have on the performance of the device without re-calibration. Due to the nature of the calibration feature, TI recommends avoiding unnecessary activities on the device while the calibration is taking place. For example, do not read or write to the serial interface or use the DCLK reset feature while calibrating the ADC; doing so impairs the performance of the device until it is re-calibrated correctly. Also, TI recommends not to apply a strong narrow-band signal to the analog inputs during calibration because this may impair the accuracy of the calibration; broad spectrum noise is acceptable. 7.3.3.4 Calibration Adjust The sequence of the calibration event itself may be adjusted. This feature can be used if a shorter calibration time than the default is required; see tCAL in Converter Electrical Characteristics: AC Electrical Characteristics. However, the performance of the device may be compromised when using this feature. The calibration sequence may be adjusted through the CSS bit of the Calibration Adjust register (Addr: 4h; Bit: 14). The default setting of CSS = 1b executes both RIN and RIN_CLK calibration (using Rtrim) and internal linearity calibration (using Rext). Executing a calibration with CSS = 0b executes only the internal linearity calibration. The first time that calibration is executed, it must be with CSS = 1b to trim RIN and RIN_CLK. However, once the device is at its operating temperature, and RIN has been trimmed at least one time, it does not drift significantly. 44 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP ADC12D1620QML-SP www.ti.com SNAS717 – APRIL 2017 7.3.3.4.1 Read/Write Calibration Settings When the ADC performs a calibration, the calibration constants are stored in an array which is accessible through the Calibration Values register (Addr: 5h). To save the time it takes to execute a calibration, tCAL, or to allow re-use of a previous calibration result, these values can be read from and written to the register at a later time. For example, if an application requires the same input impedance, RIN, this feature can be used to load a previously determined set of values. For the calibration values to be valid, the ADC must be operating under the same conditions, including temperature, at which the calibration values were originally determined by the ADC. To 1. 2. 3. read calibration values from the SPI, do the following: Set ADC to desired operating conditions. Set the SSC bit (Addr: 4h; Bit: 7) to 1. Read exactly 240 times the Calibration Values register (Addr: 5h). The register values are R0, R1, R2... R239 where R0 is a dummy value. The contents of R<239:1> should be stored. 4. Set the SSC bit (Addr: 4h; Bit: 7) to 0. 5. Continue with normal operation. To 1. 2. 3. write calibration values to the SPI, do the following: Set ADC to operating conditions at which Calibration Values were previously read. Set the SSC bit (Addr: 4h; Bit: 7) to 1. Write exactly 239 times the Calibration Values register (Addr: 5h). The registers should be written with stored register values R1, R2... R239. 4. Make two additional dummy writes of 0000h. 5. Set the SSC bit (Addr: 4h; Bit: 7) to 0. 6. Continue with normal operation. 7.3.3.5 Calibration and Power-Down If PDI and PDQ are simultaneously asserted during a calibration cycle, the ADC12D1620 device immediately powers down. The calibration cycle continues when either or both channels are powered back up, but the calibration is compromised due to the incomplete settling of bias currents directly after power up. Therefore, a new calibration must be executed upon powering the ADC12D1620 back up. In general, the ADC12D1620 must be re-calibrated when either or both channels are powered back up, or after one channel is powered down. For best results, this must be done after the device has stabilized to its operating temperature. 7.3.3.6 Calibration and the Digital Outputs During calibration, the digital outputs (including DI, DId, DQ, DQd and OR) are set logic-low, to reduce noise. The DCLK runs continuously during calibration. After the calibration is completed and the CalRun signal is logiclow, it takes an additional 60 sampling clock cycles before the output of the ADC12D1620 is valid converted data from the analog inputs. This is the time it takes for the pipeline to flush, as well as for other internal processes. 7.3.4 Power Down On the ADC12D1620, the I and Q channels may be powered down individually. This may be accomplished through the control pins, PDI and PDQ, or through ECM. In ECM, the PDI and PDQ pins are logically OR'd with the PDI and PDQ bits of the Control Register (Addr: 0h; Bits: 11:10). See Power-Down I-Channel Pin (PDI) and Power-Down Q-Channel Pin (PDQ) for more information. 7.3.5 Low-Sampling Power-Saving Mode (LSPSM) For applications with input clock speeds of 200 to 800 MHz (sample rates of 200 to 800 MSPS in non-DES mode), the ADC may be put in LSPSM using the LSPSM (V4) pin (see Low-Sampling Power-Saving Mode Pin (LSPSM)). LSPSM powers down certain areas of the device, reduces the power consumption by approximately 20%, and may improve the spectral purity of the output. In 1:2 demux mode, the output is in SDR, and the DLCK frequency will be Fs/2 . In non-demux mode, the output is switchable between DDR and SDR; see Table 8 for the DCLK frequencies for each mode and output combination. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP 45 ADC12D1620QML-SP SNAS717 – APRIL 2017 www.ti.com 7.4 Device Functional Modes 7.4.1 DES/Non-DES Mode The ADC12D1620 device can operate in dual-edge sampling (DES) or non-DES mode. In non-DES mode, inputs are sampled at the sampling clock frequency. Depending on whether channels are powered down, one or two inputs may be sampled. The DES mode enables a single analog input to be sampled by both I and Q channels. One channel samples the input on the rising edge of the sampling clock and the other samples the input signal on the falling edge of the sampling clock. A single input is thus sampled twice per clock cycle, resulting in an overall sample rate of twice the sampling clock frequency. Because DES mode uses both I and Q channels to process the input signal, both channels must be powered up for the DES mode to function properly. See Dual-Edge Sampling Pin (DES) for information on how to select the DES mode. In non-ECM only the I input may be used for the DES mode input. In ECM, either the I or Q input may be selected by first using the DES bit (Addr: 0h; Bit: 7) to select the DES mode. Setting the DEQ bit (Addr: 0h; Bit: 6) selects the Q input, while leaving the default value of DEQ=0 selects the I input. Two other DES modes are available. These provide improved input bandwidth compared to DESI and DESQ modes, but require driving the I and Q inputs with identical in-phase signals. The DESIQ mode is selected by setting the DIQ bit (Addr: 0h; Bit: 5). In this mode the I and Q input signals are connected to the I and Q converter channels and also connected to each other internally to enable better I to Q signal matching compared with the DESCLKIQ mode discussed next. DESCLKIQ mode is similar to the DESIQ mode, except that the I and Q channels remain electrically separate internal to the ADC12D1620. For this reason, the I to Q signal matching is slightly worse, and spurious performance is degraded compared to DESIQ mode. DESCLKIQ input bandwidth is slightly better than the DESIQ bandwidth. The DCK bit (Addr: Eh; Bit: 6) is used to select the 180° sampling-clock mode. Table 7 summarizes the relative bandwidth and SFDR performance of the DES sampling modes: Table 7. DES Mode Comparison DES MODE INPUTS DRIVEN INPUT BANDWIDTH SFDR PERFORMANCE DESI, DESQ I or Q Lowest Highest DESIQ I and Q Mid Mid DESCLKIQ I and Q Highest Lowest In the DES mode, the output data must be carefully interleaved in order to reconstruct the sampled signal. If the device is programmed into the 1:4 demux DES mode, the data is effectively demultiplexed by 1:4. If the sampling clock is 1600 MHz, the effective sampling rate is doubled to 3.2 GSPS, and each of the 4 output buses has an output rate of 800 MSPS. All data is available in parallel. To properly reconstruct the sampled waveform, the four words of parallel data that are output with each DCLK must be correctly interleaved. The sampling order is as follows, from the earliest to the latest: DQd, DId, DQ, DI (see Figure 3). If the device is programmed into the nondemux DES mode, two words of parallel data are output with each edge of the DCLK in the following sampling order, from the earliest to the latest: DQ, DI (see Figure 4). 7.4.2 Demux/Non-Demux Mode The ADC12D1620 device may be in one of two demultiplex modes: demux mode or non-demux mode (also sometimes referred to as 1:1 demux mode). In non-demux mode, the data from the input is simply output at the sampling rate on one 12-bit bus. In demux mode, the data from the input is output at half the sampling rate, on twice the number of buses. Demux/non-demux mode may only be selected by the NDM pin. In non-DES mode, the output data from each channel may be demultiplexed by a factor of 1:2 (1:2 demux Non-DES mode) or not demultiplexed (non-demux non-DES mode). In DES mode, the output data from both channels interleaved may be demultiplexed (1:4 demux DES mode) or not demultiplexed (non-demux DES mode). See Table 8 for a selection of available modes. 46 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP ADC12D1620QML-SP www.ti.com SNAS717 – APRIL 2017 Table 8. Supported Demux, Data Rate Modes OUTPUT MODE DCLK RCOUT DDR 0° mode / 90° mode FCLK/4 FCLK/4 SDR Rising / Falling mode FCLK/2 DDR 0° mode only FCLK/2 SDR Not available N/A NON-LSPSM, NON-DES MODE 1:2 demux 1:1 demux N/A LSPSM, NON-DES MODE 1:2 demux 1:1 demux DDR Not available N/A N/A SDR Rising / Falling mode FCLK/2 FCLK/2 DDR 0° mode only FCLK/2 SDR Rising mode only FCLK DDR 0° mode / 90° mode FCLK/4 SDR Rising / Falling mode FCLK/2 DDR 0° mode only FCLK/2 SDR Not Available N/A NON-LSPSM, DES MODE 1:4 demux 1:1 demux FCLK/4 N/A LSPSM, DES MODE 1:4 demux 1:1 demux DDR Not Available N/A N/A SDR Rising mode only FCLK/2 FCLK/2 DDR 0° mode / 90° mode FCLK/2 SDR Rising mode only FCLK 7.5 Programming 7.5.1 Control Modes The ADC12D1620 may be operated in one of two control modes: non-extended-control mode (non-ECM) or extended-control mode (ECM). In the simpler non-ECM (also sometimes referred to as pin-control mode), the user affects available configuration and control of the device through the control pins. The ECM provides additional configuration and control options through a serial interface and a set of 16 registers, most of which are available to the user. 7.5.1.1 Non-ECM In non-ECM, the serial interface is not active, and all available functions are controlled through various pin settings. Non-ECM is selected by setting the ECE pin to logic-high. Note that for the control pins, logic-high and logic-low refer to VA and GND, respectively. Nine dedicated control pins provide a wide range of control for the ADC12D1620 and facilitate its operation. These control pins provide DES mode selection, demux-mode selection, DDR-phase selection, execute calibration, power down I channel, power down Q channel, test-patternmode selection, and full-scale input-range selection. In addition to this, two dual-purpose control pins provide for AC- or DC-coupled mode selection and LVDS output common-mode voltage selection. See Table 9 for a summary. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP 47 ADC12D1620QML-SP SNAS717 – APRIL 2017 www.ti.com Programming (continued) Table 9. Non-ECM Pin Summary PIN NAME LOGIC LOW LOGIC HIGH FLOATING Non-DES mode DES mode Not valid Not valid DEDICATED CONTROL PINS DES NDM DDRPh Demux mode Non-demux mode DDR 0° mode 90° mode SDR Rising edge Falling edge CAL See Calibration Pin (CAL) Not valid Not valid LPSSM Non-LSPSM LSPSM Not valid PDI I-channel active Power down I-channel Power down I-channel PDQ Q-channel active Power down Q-channel Power down Q-channel TPM Non-test pattern mode Test pattern mode Not valid FSR Lower FS input range Higher FS input range Not valid DUAL-PURPOSE CONTROL PINS VCMO VBG AC-coupled operation Not allowed DC-coupled operation Not allowed Higher LVDS common-mode voltage Lower LVDS common-mode voltage 7.5.1.1.1 Dual-Edge Sampling Pin (DES) The dual-edge sampling (DES) pin selects whether the ADC12D1620 is in DES mode (logic-high) or non-DES mode (logic-low). DES mode means that a single analog input is sampled by both I and Q channels in a timeinterleaved manner. One of the ADCs samples the input signal on the rising sampling clock edge (duty cycle corrected); the other ADC samples the input signal on the falling sampling clock edge (duty cycle corrected). In non-ECM, only the I input may be used for DES mode, also known as DESI mode. In ECM, the Q input may be selected through the DEQ bit of the Configuration Register (Addr: 0h; Bit: 6), also known as DESQ mode. In ECM, both the I and Q inputs may be selected, also known as DESIQ or DESCLKIQ mode. To use this feature in ECM, use the DES bit in the Configuration Register (Addr: 0h; Bit: 7). See DES/Non-DES Mode for more information. 7.5.1.1.2 Non-Demultiplexed Mode Pin (NDM) The non-demultiplexed mode (NDM) pin selects whether the ADC12D1620 is in demux mode (logic-low) or nondemux mode (logic-high). In non-demux mode, the data from the input is produced at the sampled rate at a single 12-bit output bus. In demux mode, the data from the input is produced at half the sampled rate and at twice the number of output buses. For non-DES mode, each I or Q channel produces its data on one or two buses for non-demux or demux mode, respectively. For DES mode, the selected channel produces its data on two or four buses for non-demux or demux mode, respectively. This feature is pin-controlled only and remains active during both non-ECM and ECM. See Demux/Non-Demux Mode for more information. 7.5.1.1.3 Dual Data-Rate Phase Pin (DDRPh) The dual data-rate phase (DDRPh) pin selects whether the ADC12D1620 is in 0° mode (logic-low) or 90° mode (logic-high) for DDR mode. For DDR mode, the data may transition either with the DCLK transition (0° mode) or halfway between DCLK transitions (90° mode). If the device is in SDR mode, the DDRPh pin selects whether the data transitions on the rising edge of DCLK (logic-low) or the falling edge of DCLK (logic-high). The DDRPh pin selects the mode for both the I channel: DI- and DId-to-DCLKI phase relationship and for the Q channel: DQ- and DQd-to-DCLKQ phase relationship. To use this feature in ECM, use the DPS bit in the Configuration Register (Addr: 0h; Bit: 14). See SDR / DDR Clock for more information. 48 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP ADC12D1620QML-SP www.ti.com SNAS717 – APRIL 2017 7.5.1.1.4 Calibration Pin (CAL) The calibration (CAL) pin may be used to execute an on-command calibration. The effect of calibration is to maximize the dynamic performance. To initiate an on-command calibration through the CAL pin, bring the CAL pin high for a minimum of tCAL_H input clock cycles after it has been low for a minimum of tCAL_L input clock cycles (seeConverter Electrical Characteristics: AC Electrical Characteristics clock cycle specification). TI recommends holding the CAL pin high during normal usage of the ADC12D1620 device to reduce the chance that an SEU causes a calibration cycle. In ECM, this pin remains active and is logically OR'd with the CAL bit. To use this feature in ECM, use the CAL bit in the Configuration Register (Addr: 0h; Bit: 15). See Calibration Feature for more information. 7.5.1.1.5 Low-Sampling Power-Saving Mode Pin (LSPSM) The LSPSM pin selects whether the device is in non-LSPSM (logic-low) or LSPSM (logic-high). In LSPSM, the input clock is limited to 800 MHz, and the sample rate in non-DES mode is limited to 800 MSPS. The LSPSM pin remains active in ECM. See Low-Sampling Power-Saving Mode (LSPSM) for more details. 7.5.1.1.6 Power-Down I-Channel Pin (PDI) The power-down I-channel (PDI) pin selects whether the I channel is powered down (logic-high) or active (logiclow). The digital data output pins, DI and DId, (both positive and negative) are put into a high impedance state when the I channel is powered down. Upon return to the active state, the pipeline contains meaningless information and must be flushed. The supply currents (typicals and limits) are available for the I channel powered down or active and may be found in Converter Electrical Characteristics: Power Supply Characteristics . Recalibrate the device following a power-cycle of PDI (or PDQ). The PDI pin remains active in ECM, and either the PDI pin or the PDI bit of the Configuration Register (Addr: 0h; Bit: 11) may be used to power-down the I channel. See Power Down for more information. 7.5.1.1.7 Power-Down Q-Channel Pin (PDQ) The power-down Q-channel (PDQ) pin selects whether the Q channel is powered down (logic-high) or active (logic-low). This pin functions similarly to the PDI pin, except that it applies to the Q channel; review the information in Power-Down I-Channel Pin (PDI) and apply to the PDQ pin as well. The PDI and PDQ pins function independently of each other to control whether each I or Q channel is powered down or active. The PDQ pin remains active in ECM, and either the PDQ pin or the PDQ bit of the Configuration Register (Addr: 0h; Bit: 10) may be used to power-down the Q channel. See Power Down for more information. 7.5.1.1.8 Test-Pattern Mode Pin (TPM) The test-pattern-mode (TPM) pin selects whether the output of the ADC12D1620 is a test pattern (logic-high) or the converted analog input (logic-low). The ADC12D1620 can provide a test pattern at the four output buses, independentl of the input signal, to aid in system debug. In TPM, the ADC is disengaged, and a test pattern generator is connected to the outputs, including ORI and ORQ. See Test-Pattern Mode for more information. 7.5.1.1.9 Full-Scale Input-Range Pin (FSR) The full-scale input-range (FSR) pin selects whether the full-scale input range for both the I channel and Q channel is higher (logic-high) or lower (logic-low). The input full-scale range is specified as VIN_FSR in Converter Electrical Characteristics: Digital Control and Output Pin Characteristics. In non-ECM, the full-scale input range for each I and Q channel may not be set independently, but it is possible to do so in ECM. The device must be calibrated following a change in FSR to obtain optimal performance. To use this feature in ECM, use the I- and Q-channel Full Scale Range Adjust registers (Addr: 3h and Bh, respectively). See Input Control and Adjust for more information. 7.5.1.1.10 AC- or DC-Coupled Mode Pin (VCMO) The VCMO pin serves a dual purpose. When functioning as an output, it provides the optimal common-mode voltage for the DC-coupled analog inputs. When functioning as an input, it selects whether the device is ACcoupled (logic-low) or DC-coupled (floating). The VCMO pin is always active, in both ECM and non-ECM. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP 49 ADC12D1620QML-SP SNAS717 – APRIL 2017 www.ti.com 7.5.1.1.11 LVDS Output Common-Mode Pin (VBG) The VBG pin serves a dual purpose. When functioning as an output, it provides a buffered copy of the bandgap reference voltage. When functioning as an input, it selects whether the LVDS output common-mode voltage is higher (logic-high) or lower (floating). The LVDS output common-mode voltage is specified as VOS and may be found in Converter Electrical Characteristics: Digital Control and Output Pin Characteristics. The VBG pin is always active, in both ECM and non-ECM. 7.5.1.2 Extended Control Mode In extended control mode (ECM), most functions are controlled through the serial interface. In addition to this, several of the control pins remain active. See Table 1 for details. ECM is selected by setting the ECE pin to logiclow. Each time the ADC is powered up the configuration register values are in an unknown state. Therefore all registers must be user configured to the default and/or desired values before device use. If the ECE pin is set to logic-high (non-ECM), then the registers are reset to their default values. Therefore, a simple way to reset the registers is by toggling the ECE pin. Four pins on the ADC12D1620 device control the serial interface: SCS, SCLK, SDI, and SDO. This section covers the serial interface. (See also Register Definitions.) 7.5.1.2.1 Serial Interface The ADC12D1620 offers a serial interface that allows access to the sixteen control registers within the device. The serial interface is a generic 4-wire (optionally 3-wire) synchronous interface that is compatible with SPI type interfaces that are used on many micro-controllers and DSP controllers. Each serial interface access cycle is exactly 24 bits long. A register-read or register-write can be accomplished in one cycle. The signals are defined in such a way that the user can opt to simply join SDI and SDO signals in their system to accomplish a single, bidirectional SDI/O signal. A summary of the pins for this interface may be found in Table 10. See Figure 9 for the timing diagram and Timing Requirements: Serial Port Interface for timing specification details. Control register contents are retained when the device is put into power-down mode. If this feature is unused, the SCLK, SDI, and, SCS pins may be left floating because they each have an internal pullup. Table 10. Serial Interface Pins PIN NAME C4 SCS (serial chip select bar) C5 SCLK (serial clock) B4 SDI (serial data in) A3 SDO (serial data out) SCS: Each assertion (logic-low) of this signal starts a new register access, that is, the SDI command field must be ready on the following SCLK rising edge. The user is required to de-assert this signal after the 24th clock. If the SCS is de-asserted before the 24th clock, no data read/write occurs. For a read operation, if the SCS is asserted longer than 24 clocks, the SDO output holds the D0 bit until SCS is de-asserted. For a write operation, if the SCS is asserted longer than 24 clocks, data write occurs normally through the SDI input upon the 24th clock. Setup and hold times, tSCS and tHCS, with respect to the SCLK must be observed. SCS must be toggled in between register access cycles. SCLK: This signal is used to register the input data (SDI) on the rising edge and to source the output data (SDO) on the falling edge. The user may disable the clock and hold it at logic-low. There is no minimum frequency requirement for SCLK; see fSCLK in Timing Requirements: Serial Port Interface for more details. SDI: Each register access requires a specific 24-bit pattern at this input, consisting of a command field and a data field. If the SDI and SDO wires are shared (3-wire mode), during read operations it is necessary to tri-state the master must be tristate while the data field is output by the ADC on SDO. The master must be tri-state before the falling edge of the 8th clock. If SDI and SDO are not shared (4-wire mode), then this is not necessary. Setup and hold times, tSH and tSSU, with respect to the SCLK must be observed. SDO: This output is normally tri-state and is driven only when SCS is asserted, the first 8 bits of command data have been received and it is a READ operation. The data is shifted out, MSB first, starting with the falling edge of the 8th clock. At the end of the access, when SCS is de-asserted, this output is tri-state once again. If an invalid address is accessed, the data sourced will consist of all zeroes. If it is a read operation, there is a bus turnaround time, tBSU, from when the last bit of the command field was read in until the first bit of the data field is written out. Table 11 shows the serial interface bit definitions. 50 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP ADC12D1620QML-SP www.ti.com SNAS717 – APRIL 2017 Table 11. Command and Data Field Definitions BIT NO. NAME COMMENTS 1 Read/Write (R/W) 1b indicates a read operation. 0b indicates a write operation. 2-3 Reserved Bits must be set to 10b. 4-7 A<3:0> 16 registers may be addressed. The order is MSB first. 8 X This is a "don't care" bit. 9-24 D<15:0> Data written to or read from addressed register. The serial data protocol is shown for a read and write operation in Figure 42 and Figure 43, respectively. 1 2 3 4 5 6 7 8 R/W 1 0 A3 A2 A1 A0 X 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 D5 D4 D3 D2 D1 D0 SCSb SCLK SDI SDO *Only required to be tri-stated in 3-wire mode. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 Figure 42. Serial Data Protocol - Read Operation 1 2 3 4 5 6 7 8 R/W 1 0 A3 A2 A1 A0 X 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 25 SCSb SCLK SDI SDO Figure 43. Serial Data Protocol - Write Operation Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP 51 ADC12D1620QML-SP SNAS717 – APRIL 2017 www.ti.com 7.6 Register Maps 7.6.1 Register Definitions Eleven read/write registers provide several control and configuration options in the extended control mode. When the device is in non-extended control mode (non-ECM), the registers have the settings shown in the "DV" rows and cannot be changed. See Table 12 for a summary. Table 12. Register Addresses 52 A3 A2 A1 A0 HEX REGISTER ADDRESSED 0 0 0 0 0h Configuration Register 1 0 0 0 1 1h Reserved 0 0 1 0 2h I-channel Offset Adjust 0 0 1 1 3h I-channel Full-Scale Range Adjust 0 1 0 0 4h Calibration Adjust 0 1 0 1 5h Calibration Values 0 1 1 0 6h Reserved 0 1 1 1 7h DES Timing Adjust 1 0 0 0 8h Reserved 1 0 0 1 9h Reserved 1 0 1 0 Ah Q-channel Offset Adjust 1 0 1 1 Bh Q-channel Full-Scale Range Adjust 1 1 0 0 Ch Aperture Delay Coarse Adjust 1 1 0 1 Dh Aperture Delay Fine Adjust 1 1 1 0 Eh AutoSync 1 1 1 1 Fh Reserved Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP ADC12D1620QML-SP www.ti.com SNAS717 – APRIL 2017 Table 13. Configuration Register 1 Addr: 0h (0000b) Default Values: 2000h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Name CAL DPS OVS TPM PDI PDQ Res LFS DES DEQ DIQ 2SC TSE SDR DV (1) 0 0 1 0 0 0 0 0/1 0 0 0 0 0 0 (1) 1 0 Reserved 0 0 DV means Default Value. Refer to Extended Control Mode for more information on setting ECM default values. Bit 15 CAL: Calibration enable. When this bit is set to 1b, an on-command calibration is initiated. This bit is not reset automatically upon completion of the calibration. Therefore, the user must reset this bit to 0b and then set it to 1b again to execute calibration. This bit is logically OR'd with the CAL Pin; both bit and pin must be set to 0b before either is used to execute a calibration. TI recommends holding the CAL pin high during normal usage of the ADC12D1620 device to reduce the chance that an SEU causes a calibration cycle. Bit 14 DPS: DCLK phase select. In DDR, set this bit to 0b to select the 0° mode DDR data-to-DCLK phase relationship and to 1b to select the 90° mode. In SDR, set this bit to 0b to transition the data on the rising edge of DCLK; set this bit to 1b to transition the data on the falling edge of DCLK. Bit 13 OVS: Output voltage select. This bit sets the differential voltage level for the LVDS outputs including Data, OR, and DCLK. 0b selects the lower level and 1b selects the higher level. See VOD in Converter Electrical Characteristics: Digital Control and Output Pin Characteristics for details. Bit 12 TPM: Test pattern mode. When this bit is set to 1b, the device continually outputs a fixed digital pattern at the digital data and OR outputs. When set to 0b, the device continually outputs the converted signal, which was present at the analog inputs. See Test-Pattern Mode for details about the TPM pattern. Bit 11 PDI: Power-down I channel. When this bit is set to 0b, the I channel is fully operational; when it is set to 1b, the I channel is powered-down. The I channel may be powered-down through this bit or the PDI pin, which is active, even in ECM. Bit 10 PDQ: Power-down Q channel. When this bit is set to 0b, the Q channel is fully operational; when it is set to 1b, the Q channel is powered-down. The Q channel may be powered-down through this bit or the PDQ pin, which is active, even in ECM. Bit 9 Reserved. Must be set as shown. Bit 8 LFS: Low-frequency select. If the sampling clock (CLK) is at or below 300 MHz in non-LSPSM, set this bit to 1b for improved performance. In LSPSM, the device is automatically in LFS, and this bit is inactive. Bit 7 DES: Dual-edge sampling mode select. When this bit is set to 0b, the device operates in the non-DES mode; when it is set to 1b, the device operates in the DES mode. See DES/Non-DES Mode for more information. Bit 6 DEQ: DES Q input select, also known as DESQ mode. When the device is in DES mode, this bit selects the input that the device operates on. The default setting of 0b selects the I input and 1b selects the Q input. Bit 5 DIQ: DES I and Q input, also known as DESIQ mode. When in DES mode, setting this bit to 1b shorts the I and Q inputs internally to the device. In this mode, both the I and Q inputs must be externally driven; see DES/Non-DES Mode for more information. If the bit is left at its default 0b, the I and Q inputs remain electrically separate. The allowed DES modes settings are shown below. For DESCLKIQ mode, see the Table 27 register (Addr Eh). MODE ADDR 0h, BIT<7:5> ADDR Eh, BIT<6> Non-DES mode 000b 0b DESI mode 100b 0b DESQ mode 110b 0b DESIQ mode 101b 0b DESCLKIQ mode 000b 1b Bit 4 2SC: Two's complement output. For the default setting of 0b, the data is output in offset binary format; when set to 1b, the data is output in two's complement format. Bit 3 TSE: Time stamp enable. For the default setting of 0b, the time stamp feature is not enabled; when set to 1b, the feature is enabled. See Output Control and Adjust for more information about this feature. Bit 2 SDR: Single data rate. For the default setting of 0b, the data is clocked in dual data rate; when set to 1b, the data is clocked in single data rate. See Output Control and Adjust for more information about this feature. Note that for DDR mode, the 1:2 demux mode is not available in LSPSM. See Table 8 for a selection of available modes. Bits 1:0 Reserved. Must be set as shown. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP 53 ADC12D1620QML-SP SNAS717 – APRIL 2017 www.ti.com Table 14. Reserved Addr: 1h (0001b) Bit Default Values: 2907h 15 14 13 12 11 10 9 0 0 1 0 1 0 0 Name 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 Reserved DV (1) (1) 8 1 0 DV means Default Value. Refer to Extended Control Mode for more information on setting ECM default values. Bits 15:0 Reserved. Must be set as shown. Table 15. I-Channel Offset Adjust Addr: 2h (0010b) Bit 15 Name 13 Reserved DV (1) (1) Default Values: 0000h 14 0 0 12 11 10 9 8 7 OS 0 6 5 4 3 2 1 0 0 0 0 0 0 OM(11:0) 0 0 0 0 0 0 0 0 DV means Default Value. Refer to Extended Control Mode for more information on setting ECM default values. Bits 15:13 Reserved. Must be set to 0b. Bit 12 OS: Offset sign. The default setting of 0b incurs a positive offset of a magnitude set by Bits 11:0 to the ADC output. Setting this bit to 1b incurs a negative offset of the set magnitude. Bits 11:0 OM(11:0): Offset magnitude. These bits determine the magnitude of the offset set at the ADC output (straight binary coding). The range is from 0 mV for OM(11:0) = 0d to 45 mV for OM(11:0) = 4095d in steps of ~11 µV. Monotonicity is specified by design only for the 9 MSBs. CODE OFFSET [mV] 0000 0000 0000 (default) 0 1000 0000 0000 22.5 1111 1111 1111 45 Table 16. I-Channel Full Scale Range Adjust Addr: 3h (0011b) Bit 15 Name Res DV (1) 0 (1) Default Values: 4000h 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 FM(14:0) 1 0 0 0 0 0 0 0 DV means Default Value. Refer to Extended Control Mode for more information on setting ECM default values. Bit 15 Reserved. Must be set to 0b. Bits 14:0 FM(14:0): FSR magnitude. These bits increase the ADC full-scale range magnitude (straight binary coding.) The range is from 600 mV (0d) to 1000 mV (32767d) with the default setting at 800 mV (16384d). Monotonicity is specified by design only for the 9 MSBs. The mid-range (low) setting in ECM corresponds to the nominal (low) setting in non-ECM. A greater range of FSR values is available in ECM, that is, FSR values above 800 mV. See VIN_FSR in Converter Electrical Characteristics: Analog Input/Output and Reference Characteristics for characterization details. 54 CODE FSR [mV] 000 0000 0000 0000 600 100 0000 0000 0000 (default) 800 111 1111 1111 1111 1000 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP ADC12D1620QML-SP www.ti.com SNAS717 – APRIL 2017 Table 17. Calibration Adjust Addr: 4h (0100b) Default Values: DB4Bh Bit 15 14 Name Res CSS DV (1) 1 1 (1) 13 12 0 1 11 10 9 8 1 1 Reserved 1 0 7 6 5 4 1 0 0 SSC 0 3 2 1 0 0 1 1 Reserved 1 DV means Default Value. Refer to Extended Control Mode for more information on setting ECM default values. Bit 15 Reserved. Must be set as shown. Bit 14 CSS: Calibration sequence select. The default 1b selects the following calibration sequence: reset all previously calibrated elements to nominal values, do RIN calibration, do internal linearity calibration. Setting CSS = 0b selects the following calibration sequence: do not reset RIN to its nominal value, skip RIN calibration, do internal linearity calibration. The calibration must be completed at least one time with CSS = 1b to calibrate RIN. Subsequent calibrations may be run with CSS = 0b (skip RIN calibration) or 1b (full RIN and internal linearity calibration). Bits 13:8 Reserved. Must be set as shown. Bit 7 SSC: SPI scan control. Setting this control bit to 1b allows the calibration values, stored in Addr: 5h, to be read/written. When not reading/writing the calibration values, this control bit should left at its default 0b setting. See Calibration Feature for more information. Bits 6:0 Reserved. Must be set as shown. Table 18. Calibration Values Addr: 5h (0101b) Bit 15 Default Values: XXXXh 14 13 12 11 10 9 Name DV (1) (1) 8 7 6 5 4 3 2 1 0 X X X X X X X SS(15:0) X X X X X X X X X DV means Default Value. Refer to Extended Control Mode for more information on setting ECM default values. Bits 15:0 SS(15:0): SPI scan. When the ADC performs a self-calibration, the values for the calibration are stored in this register and may be read from/written to it. Set the SSC of the Calibration Adjust register (Addr: 4h, Bit: 7) to read/write. See Calibration Feature for more information. Table 19. Reserved Addr: 6h (0110b) Bit 15 Default Values: 1C2Eh 14 13 12 11 10 9 Name DV (1) (1) 8 7 6 5 4 3 2 1 0 0 1 0 1 1 1 0 Reserved 0 0 0 1 1 1 0 0 0 DV means Default Value. Refer to Extended Control Mode for more information on setting ECM default values. Bits 15:0 Reserved. Must be set as shown. Table 20. DES Timing Adjust Addr: 7h (0111b) Bit 15 Default Values: 8142h 14 13 Name DV (1) (1) 12 11 10 9 8 7 6 5 DTA(6:0) 1 0 0 0 4 3 2 1 0 0 0 1 0 Reserved 0 0 0 1 0 1 0 0 DV means Default Value. Refer to Extended Control Mode for more information on setting ECM default values. Bits 15:9 DTA(6:0): DES mode timing adjust. In the DES mode, the time at which the falling edge sampling clock samples relative to the rising edge of the sampling clock may be adjusted; the automatic duty cycle correction continues to function. See Input Control and Adjust for more information. The nominal step size is 30 fs. Bits 8:0 Reserved. Must be set as shown. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP 55 ADC12D1620QML-SP SNAS717 – APRIL 2017 www.ti.com Table 21. Reserved Addr: 8h (1000b) Bit Default Values: 0F0Fh 15 14 13 12 11 10 9 0 0 0 0 1 1 1 Name 7 6 5 4 3 2 1 0 0 0 0 1 1 1 1 Reserved DV (1) (1) 8 1 0 DV means Default Value. Refer to Extended Control Mode for more information on setting ECM default values. Bits 15:0 Reserved. Must be set as shown. Table 22. Reserved Addr: 9h (1001b) Bit 15 Default Values: 0000h 14 13 12 11 10 9 Name 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 Reserved DV (1) (1) 8 0 0 0 0 0 0 0 0 0 DV means Default Value. Refer to Extended Control Mode for more information on setting ECM default values. Bits 15:0 Reserved. Must be set as shown. Table 23. Q-Channel Offset Adjust Addr: Ah (1010b) Bit 15 Name 14 13 Reserved DV (1) (1) Default Values: 0000h 0 0 12 11 10 9 8 7 OS 0 0 6 5 4 3 2 1 0 0 0 0 0 0 OM(11:0) 0 0 0 0 0 0 0 DV means Default Value. Refer to Extended Control Mode for more information on setting ECM default values. Bits 15:13 Reserved. Must be set to 0b. Bit 12 OS: Offset sign. The default setting of 0b incurs a positive offset of a magnitude set by Bits 11:0 to the ADC output. Setting this bit to 1b incurs a negative offset of the set magnitude. Bits 11:0 OM(11:0): Offset magnitude. These bits determine the magnitude of the offset set at the ADC output (straight binary coding). The range is from 0 mV for OM(11:0) = 0d to 45 mV for OM(11:0) = 4095d in steps of ~11 µV. Monotonicity is specified by design only for the 9 MSBs. 56 CODE OFFSET [mV] 0000 0000 0000 (default) 0 1000 0000 0000 22.5 1111 1111 1111 45 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP ADC12D1620QML-SP www.ti.com SNAS717 – APRIL 2017 Table 24. Q-Channel Full-Scale Range Adjust Addr: Bh (1011b) Bit 15 Name Res DV (1) 0 (1) Default Values: 4000h 14 13 12 11 10 9 8 1 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 FM(14:0) 0 DV means Default Value. Refer to Extended Control Mode for more information on setting ECM default values. Bit 15 Reserved. Must be set to 0b. Bits 14:0 FM(14:0): FSR magnitude. These bits increase the ADC full-scale range magnitude (straight binary coding.) The range is from 600 mV (0d) to 1000 mV (32767d) with the default setting at 800 mV (16384d). Monotonicity is specified by design only for the 9 MSBs. The mid-range (low) setting in ECM corresponds to the nominal (low) setting in Non-ECM. A greater range of FSR values is available in ECM, that is, FSR values above 800 mV. See VIN_FSR in Converter Electrical Characteristics: Analog Input/Output and Reference Characteristics for characterization details. CODE FSR [mV] 000 0000 0000 0000 600 100 0000 0000 0000 (default) 800 111 1111 1111 1111 1000 Table 25. Aperture Delay Coarse Adjust Addr: Ch (1100b) Bit Default Values: 0004h 15 14 13 12 11 0 0 0 0 0 Name DV (1) (1) 10 9 8 7 6 5 4 0 0 0 0 0 CAM(11:0) 0 0 3 2 STA DCC 0 1 1 0 Res 0 0 DV means Default Value. Refer to Extended Control Mode for more information on setting ECM default values. Bits 15:4 CAM(11:0): Coarse adjust magnitude. This 12-bit value determines the amount of delay that is applied to the input CLK signal. The range is 0-ps delay for CAM(11:0) = 0d to a maximum delay of 825 ps for CAM(11:0) = 2431d (±95 ps due to PVT variation) in steps of ~340 fs. For code CAM(11:0) = 2432d and above, the delay saturates and the maximum delay applies. Additional, finer delay steps are available in register Dh. The STA (Bit 3) must be selected to enable this function. Bit 3 STA: Select tAD Adjust. Set this bit to 1b to enable the tAD adjust feature, which makes both coarse and fine adjustment settings, that is, CAM(11:0) and FAM(5:0), available. Bit 2 DCC: Duty cycle correct. This bit can be set to 0b to disable the automatic duty-cycle stabilizer feature of the chip. This feature is enabled by default. Bits 1:0 Reserved. Must be set to 0b. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP 57 ADC12D1620QML-SP SNAS717 – APRIL 2017 www.ti.com Table 26. Aperture Delay Fine Adjust Addr: Dh (1101b) Bit Default Values: 0000h 15 14 13 0 0 0 Name 11 10 9 8 7 6 0 0 0 0 0 0 FAM(5:0) DV (1) (1) 12 5 4 3 2 1 0 0 0 0 0 Reserved 0 0 0 DV means Default Value. Refer to Extended Control Mode for more information on setting ECM default values. Bits 15:10 FAM(5:0): Fine aperture adjust magnitude. This 6-bit value determines the amount of additional delay that is applied to the input CLK when the clock phase adjust feature is enabled through STA (Addr: Ch; Bit: 3). The range is straight binary from 0 ps delay for FAM(5:0) = 0d to 2.3 ps delay for FAM(5:0) = 63d (±300 fs due to PVT variation) in steps of ~36 fs. Bits 9:0 Reserved. Must be set as shown. Table 27. AutoSync Addr: Eh (1110b) Bit 15 Default Values: 0003h 14 13 12 Name DV (1) (1) 11 10 9 8 7 DRC(8:0) 0 0 0 0 0 0 0 0 0 6 5 DCK Res 4 0 0 3 SP(1:0) 0 0 2 1 0 ES DOC DR 0 1 1 DV means Default Value. Refer to Extended Control Mode for more information on setting ECM default values. Bits 15:7 DRC(8:0): Delay reference clock. These bits may be used to increase the delay on the input reference clock when synchronizing multiple ADCs. The delay may be set from a minimum of 0s (0d) to a maximum of 1200 ps (319d). The delay remains the maximum of 1200 ps for any codes above or equal to 319d. See Synchronizing Multiple ADC12D1620 Devices in a System for more information. Bit 6 DCK: DESCLKIQ mode. Set this bit to 1b to enable Dual-Edge Sampling, in which the Sampling Clock samples the I and Q inputs 180º out of phase with respect to one , that is, the DESCLKIQ mode. To select the DESCLKIQ mode, Addr: 0h, Bits <7:5> must also be set to 000b. See Input Control and Adjust for more information. Bit 5 Reserved. Must be set as shown. Bits 4:3 SP(1:0): Select phase. These bits select the phase of the reference clock that is latched. The codes correspond to the following phase shift: 00 = 0° 01 = 90° 10 = 180° 11 = 270° Bit 2 ES: Enable slave. Set this bit to 1b to enable the slave mode of operation. In this mode, the internal divided clocks are synchronized with the reference clock coming from the master ADC. The master clock is applied on the input pins RCLK. If this bit is set to 0b, then the device is in master mode. Bit 1 DOC: Disable output reference clocks. In non-LSPSM, setting this bit to 0b sends a CLK/4 signal on RCOut1 and RCOut2; in LSPSM, setting this bit to 0b sends a CLK/2 signal on RCOut1 and RCOut2. The default setting of 1b disables these output drivers. This bit functions as described, regardless of whether the device is operating in Master or Slave mode, as determined by ES (Bit 2). Bit 0 DR: Disable reset. The default setting of 1b leaves the DCLK_RST functionality disabled. Set this bit to 0b to enable DCLK_RST functionality. Table 28. Reserved Addr: Fh (1111b) Bit Default Values: 001Dh 15 14 13 12 11 10 9 0 0 0 0 0 0 0 Name 6 5 4 3 2 1 0 0 0 0 0 1 1 1 0 1 DV means Default Value. Refer to Extended Control Mode for more information on setting ECM default values. Bits 15:0 58 7 Reserved DV (1) (1) 8 Reserved. This address is read only. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP ADC12D1620QML-SP www.ti.com SNAS717 – APRIL 2017 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information 8.1.1 Analog Inputs The ADC12D1620 device continuously converts any signal that is present at the analog inputs, as long as a CLK signal is also provided to the device. This section covers important aspects related to the analog inputs including: acquiring the input, driving the ADC in DES mode, the reference voltage and FSR, out-of-range indication, ACDC-coupled signals, and single-ended input signals. 8.1.1.1 Acquiring the Input The aperture delay, tAD, is the amount of delay, measured from the sampling edge of the clock input, after which signal present at the input pin is sampled inside the device. Data is acquired at the rising edge of CLK+ in nonDES mode and both the falling and rising edges of CLK+ in DES mode. In Non-DES mode, the I and Q channels always sample data on the rising edge of CLK+. In DES mode, that is, DESI, DESQ, DESIQ, and DESCLKIQ, the I-channel samples data on the rising edge of CLK+, and the Q-channel samples data on the falling edge of CLK+. The digital equivalent of that data is available at the digital outputs a constant number of sampling clock cycles later for the DI, DQ, DId and DQd output buses, also known as latency, depending on the demultiplex mode which is selected. In addition to the latency, there is a constant output delay, tOD, before the data is available at the outputs. See tOD in the Converter Electrical Characteristics: AC Electrical Characteristics, and also see tLAT, tAD, and tOD in Converter Electrical Characteristics: AC Electrical Characteristics. 8.1.1.2 Driving the ADC in DES Mode The ADC12D1620 can be configured as either a 2-channel, 1.6 GSPS device (Non-DES mode) or a 1-channel 3.2-GSPS device (DES mode). When the device is configured in DES mode, there is a choice for with which input to drive the single-channel ADC. These are the 3 options: DES – externally driving the I-channel input only. This is the default selection when the ADC is configured in DES mode. It may also be referred to as DESI for added clarity. DESQ – externally driving the Q-channel input only. DESIQ, DESCLKIQ – externally driving both the I- and Q-channel inputs. VinI+ and VinQ+ must be driven with the exact same signal. VinI- and VinQ- must be driven with the exact same signal, which is the differential complement to the one driving VinI+ and VinQ+. The input impedance for each I and Q input is 100-Ω differential (or 50-Ω single-ended), so the trace to each VinI+, VinI-, VinQ+, and VinQ- must always be 50-Ω single-ended. If a single I or Q input is being driven, then that input presents a 100-Ω differential load. For example, if a 50-Ω single-ended source is driving the ADC, a 1:2 balun transforms the impedance to 100-Ω differential. However, if the ADC is being driven in DESIQ mode, then the 100-Ω differential impedance from the I input appears in parallel with the Q input for a composite load of 50-Ω differential, and a 1:1 balun would be appropriate. See Figure 44 for an example circuit driving the ADC in DESIQ mode. A recommended part selection uses the mini-circuits TC1-1-13MA+ balun with Ccouple = 0.22 µF. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP 59 ADC12D1620QML-SP SNAS717 – APRIL 2017 www.ti.com Application Information (continued) Ccouple 50 Ÿ Source VINI+ 100 Ÿ 1:1 Balun Ccouple VINI- Ccouple VINQ+ 100 Ÿ Ccouple VINQADC12D1600/1000RF Copyright © 2017, Texas Instruments Incorporated Figure 44. Driving DESIQ Mode when only one channel is used in non-DES mode or the ADC is driven in DESI or DESQ mode, terminate the unused analog input to reduce any noise coupling into the ADC. See Table 29 for details. Table 29. Unused Analog Input Recommended Termination MODE POWER DOWN COUPLING RECOMMENDED TERMINATION Non-DES Yes AC-DC Tie Unused+ and Unused– to VBG DES/Non-DES No DC Tie Unused+ and Unused– to VBG DES/Non-DES No AC Tie Unused+ to Unused– 8.1.1.3 FSR and the Reference Voltage The full-scale analog-differential input range (VIN_FSR) of the ADC12D1620 is derived from an internal bandgap reference. In Non-ECM, this full-scale range has two settings controlled by the FSR pin; see Full-Scale InputRange Pin (FSR). The FSR Pin operates on both I and Q channels. In ECM, the full-scale range may be independently set with 15 bits of precision for each channel through the I- and Q-channel Full-Scale Range Adjust Registers (Addr: 3h and Addr: Bh, respectively); see Table 16 and Table 24 for information about the registers. The best SNR is obtained with a higher full-scale input range, but better distortion and SFDR are obtained with a lower full-scale input range. It is not possible to use an external analog reference voltage to modify the full-scale range, and this adjustment should only be done digitally, as described. A buffered version of the internal bandgap reference voltage is made available at the VBG pin for the user. The VBG pin can drive a load of up to 80-pF and source or sink up to 100 μA. It must be buffered if current higher than 100 μA is required. This pin remains as a constant reference voltage regardless of what full-scale range is selected and may be used for a system reference. VBG is a dual-purpose pin and it may also be used to select a higher LVDS output common-mode voltage; see LVDS Output Common-Mode Pin (VBG). 8.1.1.4 Out-Of-Range Indication Differential input signals are digitized to 12 bits, based on the full-scale range. Signal excursions beyond the fullscale range, that is, greater than +VIN_FSR/2 or less than – VIN_FSR/2, are clipped at the output. An input signal above the FSR results in all 1's at the output; an an input signal that is below the FSR results in all 0's at the output. When the conversion result is clipped for the I-channel input, the out-of-range I-channel (ORI) output is activated so that ORI+ goes high and ORI– goes low while the signal is out of range. This output is active as long as accurate data on either or both of the buses is outside the range of 000h to FFFh. The Q channel has a separate ORQ, which functions similarly. 8.1.1.5 AC-Coupled Input Signals The ADC12D1620 analog inputs require a precise common-mode voltage. This voltage is generated on-chip when AC-coupling mode is selected. See AC- and DC-Coupled Modes for more information about how to select AC-coupled mode. 60 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP ADC12D1620QML-SP www.ti.com SNAS717 – APRIL 2017 In AC-coupled mode, the analog inputs must of course be AC-coupled. For an ADC12D1620 used in a typical application, this may be accomplished by on-board capacitors, as shown in Figure 45. When the AC-coupled mode is selected, terminate unused channels as shown in Table 29. Do not connect an unused analog input directly to ground. Ccouple VIN+ Ccouple VIN- VCMO ADC12D1600/1000RF Copyright © 2017, Texas Instruments Incorporated Figure 45. AC-Coupled Differential Input The analog inputs for the ADC12D1620 are internally buffered; this simplifies the task of driving these inputs and the RC pole, which is generally used at sampling ADC inputs, is not required. If the user desires to place an amplifier circuit before the ADC, take care to choose an amplifier with adequate noise and distortion performance, and adequate gain at the frequencies used for the application. 8.1.1.6 DC-Coupled Input Signals In DC-coupled mode, the ADC12D1620 differential inputs must have the correct common-mode voltage. This voltage is provided by the device itself at the VCMO output pin. TI recommends using this voltage because the VCMO output potential changes with temperature, and the common-mode voltage of the driving device should track this change. Full-scale distortion performance falls off as the input common-mode voltage deviates from VCMO. Therefore, TI recommends keeping the input common-mode voltage within 100 mV of VCMO (typical), although this range may be extended to ±150 mV (maximum). See VCMI in Converter Electrical Characteristics: Analog Input/Output and Reference Characteristics and ENOB vs VCMI in Typical Characteristics. Performance in AC- and DC-coupled modes are similar, provided that the input common mode voltage at both analog inputs remains within 100 mV of VCMO. 8.1.1.7 Single-Ended Input Signals The analog inputs of the ADC12D1620 are not designed to accept single-ended signals. The best way to handle single-ended signals is to first convert them to differential signals before presenting them to the ADC. The easiest way to accomplish single-ended to differential signal conversion is with an appropriate balun transformer, as shown in Figure 46. Ccouple 50 Ÿ Source VIN+ 100 Ÿ 1:2 Balun Ccouple VINADC12D1600/1000RF Copyright © 2017, Texas Instruments Incorporated Figure 46. Single-Ended to Differential Conversion Using a Balun When selecting a balun, it is important to understand the input architecture of the ADC. Match the impedance of the analog source to the on-chip 100-Ω differential input termination resistor of the device. The range of this termination resistor is specified as RIN in Converter Electrical Characteristics: Analog Input/Output and Reference Characteristics. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP 61 ADC12D1620QML-SP SNAS717 – APRIL 2017 www.ti.com 8.1.2 Clock Inputs The ADC12D1620 has a differential clock input, CLK+ and CLK–, which must be driven with an AC-coupled, differential clock signal. This provides the level shifting necessary so that the clock can be driven with LVDS, PECL, LVPECL, or CML levels. The clock inputs are internally terminated to 100-Ω differential and self-biased. This section covers coupling, frequency range, level, duty-cycle, jitter, and layout considerations. 8.1.2.1 CLK Coupling The clock inputs of the ADC12D1620 must be capacitively coupled to the clock pins as indicated in Figure 47. Ccouple CLK+ Ccouple CLK- ADC12D1600/1000RF Copyright © 2017, Texas Instruments Incorporated Figure 47. Differential Input Clock Connection Selection of capacitor value depends on the clock frequency, capacitor component characteristics, and other system economic factors. 8.1.2.2 CLK Frequency Although the ADC12D1620 device is tested and its performance is specified with a differential 1.6-GHz sampling clock, it typically functions well over the input clock-frequency range; see fCLK (min) and fCLK (max) in Converter Electrical Characteristics: AC Electrical Characteristics. Operation up to fCLK (max) is possible if the maximum ambient temperatures indicated are not exceeded. Operating at sample rates above fCLK (max) for the maximum ambient temperature may result in reduced device reliability and product lifetime. This is due to the fact that higher sample rates results in higher power consumption and die temperatures. If in non-LSPSM and fCLK < 300 MHz, enable LFS in the Control Register (Addr: 0h; Bit: 8). In LSPSM, the LFS bit is already enabled. 8.1.2.3 CLK Level The input clock amplitude is specified as VIN_CLK in Converter Electrical Characteristics: AC Electrical Characteristics. Input clock amplitudes above the maximum VIN_CLK may result in increased input offset voltage. This causes the converter to produce an output code other than the expected 2047/2048 when both input pins are at the same potential. Insufficient input clock levels result in poor dynamic performance. Both of these results may be avoided by keeping the clock input amplitude within the specified limits of VIN_CLK. 8.1.2.4 CLK Duty Cycle The duty cycle of the input clock signal can affect the performance of any ADC. The ADC12D1620 device features a duty-cycle-clock correction circuit, which can maintain performance over the 20%-to-80% specified clock duty-cycle range. This feature is enabled by default and provides improved ADC clocking, especially in the dual-edge sampling (DES) mode. 62 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP ADC12D1620QML-SP www.ti.com SNAS717 – APRIL 2017 8.1.2.5 CLK Jitter High-speed, high-performance ADCs such as the ADC12D1620 require a very stable input clock signal with minimum phase noise or jitter. ADC jitter requirements are defined by the ADC resolution (number of bits), maximum ADC input frequency, and the input signal amplitude relative to the ADC input full-scale range. The maximum jitter (the sum of the jitter from all sources) allowed to prevent a jitter-induced reduction in SNR is found to be: tJ(MAX) = (VIN(P-P)/ VFSR) x (1/(2(N+1) x π x fIN)) where • • • • • tJ(MAX) is the rms total of all jitter sources in seconds VIN(P-P) is the peak-to-peak analog input signal VFSR is the full-scale range of the ADC N is the ADC resolution in bits fIN is the maximum input frequency, in Hertz, at the ADC analog input (1) tJ(MAX) is the square root of the sum of the squares (RSS) of the jitter from all sources, including: ADC input clock, system, input signals, and the ADC itself. Because the effective jitter added by the ADC is beyond user control, TI recommends keeping the sum of all other externally added jitter to a minimum. 8.1.2.6 CLK Layout The ADC12D1620 clock input is internally terminated with a trimmed 100-Ω resistor. The differential input clock line pair must have a characteristic impedance of 100 Ω and (when using a balun), be terminated at the clock source in that (100-Ω) characteristic impedance. It is good practice to keep the ADC input clock line as short as possible, tightly coupled, keep it well away from any other signals, and treat it as a transmission line. Otherwise, other signals can introduce jitter into the input clock signal. Also, the clock signal can introduce noise into the analog path if it is not properly isolated. 8.1.3 LVDS Outputs The data, ORI, ORQ, DCLKI and DCLKQ outputs are LVDS. The electrical specifications of the LVDS outputs are compatible with typical LVDS receivers available on ASIC and FPGA chips; however, they are not IEEE or ANSI communications standards compliant due to the low 1.9-V supply used on this device. Terminate these outputs with a 100-Ω differential resistor placed as closely as possible to the receiver. If the 100-Ω differential resistance is built into the receiver, an externally placed resistor is not necessary. This section covers commonmode and differential voltage, and data rate. 8.1.3.1 Common-Mode and Differential Voltage The LVDS outputs have selectable common-mode and differential voltage, VOS and VOD; see Converter Electrical Characteristics: Digital Control and Output Pin Characteristics and also see Output Control and Adjust for more information. Selecting the higher VOS also increases VOD slightly. The differential voltage, VOD, may be selected for the higher or lower value. For short LVDS lines and low noise systems, satisfactory performance may be achieved with the lower VOD. This also results in lower power consumption. If the LVDS lines are long and/or the system in which the ADC12D1620 is used is noisy, it may be necessary to select the higher VOD. 8.1.3.2 Output Data Rate The data is produced at the output at the same rate it is sampled at the input. The minimum recommended input clock rate for this device is fCLK(MIN); see Converter Electrical Characteristics: AC Electrical Characteristics. However, it is possible to operate the device in 1:2 demux mode and capture data from just one 12-bit bus; for example, just DI (or DId) although both DI and DId are fully operational. This decimates the data by two and effectively halves the data rate. 8.1.3.3 Terminating Unused LVDS Output Pins If the ADC is used in non-demux mode, only the DI and DQ data outputs will have valid data present on them. The DId and DQd data outputs may be left not connected; if unused, they are internally tri-state. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP 63 ADC12D1620QML-SP SNAS717 – APRIL 2017 www.ti.com Similarly, if the Q channel is powered-down (that is, PDQ is logic-high), the DQ data output pins, DCLKQ and ORQ, may be left not connected. 8.1.4 Synchronizing Multiple ADC12D1620 Devices in a System The ADC12D1620 has two features to assist the user with synchronizing multiple ADCs in a system: AutoSync and DCLK reset. The AutoSync feature is new and designates one ADC12D1620 as the master ADC and other ADC12D1620 devices in the system as slave ADCs. The DCLK reset feature performs the same function as the AutoSync feature, but is the first-generation solution to synchronizing multiple ADCs in a system; it is disabled by default. For applications in which there are multiple master and slave ADC12D1620 devices in a system, AutoSync may be used to synchronize the slave ADC12D1620 devices to each respective master ADC12D1620, and the DCLK reset may be used to synchronize the master ADC12D1620 devices to each other. If the AutoSync or DCLK reset feature is not used, see Table 30 for recommendations about terminating unused pins. Table 30. Unused AutoSync and DCLK Reset Pin Recommendation PIN(s) UNUSED TERMINATION RCLK+, RCLK– Do not connect. RCOUT1+, RCOUT1– Do not connect. RCOUT2+, RCOUT2– Do not connect. DCLK_RST+ Connect to GND with a 1-kΩ resistor. DCLK_RST- Connect to VA with a 1-kΩ resistor. 8.1.4.1 AutoSync Feature AutoSync is a new feature which continuously synchronizes the outputs of multiple ADC12D1620 devices in a system. It may be used to synchronize the DCLK and data outputs of one or more slave ADC12D1620 devices to one master ADC12D1620. Several advantages of this feature include: no special synchronization pulse required, any upset in synchronization is recovered upon the next DCLK cycle, and the master/slave ADC12D1620 devices may be arranged as a binary tree so that any upset quickly propagates out of the system. An example system is shown in Figure 48, which consists of one master ADC and two slave ADCs. For simplicity, only one DCLK is shown; in reality, there is DCLKI and DCLKQ, but they are always in phase with one another. DCLK RCLK Slave 2 RCOut1 ADC12D1600/1000RF RCOut2 CLK RCLK CLK Slave 1 RCOut1 ADC12D1600/1000RF RCOut2 DCLK CLK RCLK Master RCOut1 ADC12D1600/1000RF RCOut2 DCLK CLK Copyright © 2017, Texas Instruments Incorporated Figure 48. AutoSync Example 64 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP ADC12D1620QML-SP www.ti.com SNAS717 – APRIL 2017 In order to synchronize the DCLK (and data) outputs of multiple ADCs, the DCLKs must transition at the same time, as well as be in phase with one another. The DCLK at each ADC is generated from the CLK after some latency, plus tOD minus tAD. Therefore, in order for the DCLKs to transition at the same time, the CLK signal must reach each ADC at the same time. To tune out any differences in the CLK path to each ADC, the tAD adjust feature may be used. However, using the tAD adjust feature also affects when the DCLK is produced at the output. If the device is in demux mode, there are four possible phases that each DCLK may be generated on because the typical CLK = 1GHz and DCLK = 250 MHz for this case. The RCLK signal controls the phase of the DCLK, so that each slave DCLK is on the same phase as the master DCLK. The AutoSync feature may only be used through the Control Registers. For more information, see AN-2132 Synchronizing Multiple GSPS ADCs in a System: The AutoSync Feature. 8.1.4.2 DCLK Reset Feature The DCLK reset feature is available through ECM, but it is disabled by default. DCLKI and DCLKQ are always synchronized, by design, and do not require a pulse from DCLK_RST to become synchronized. The DCLK_RST signal must observe certain timing requirements, which are shown in Figure 7 of Timing Requirements: Calibration. The DCLK_RST pulse must be of a minimum width, and its deassertion edge must observe setup and hold times with respect to the CLK input rising edge. These timing specifications are listed as tPWR, tSR and tHR and may be found in Converter Electrical Characteristics: AC Electrical Characteristics. The DCLK_RST signal can be asserted asynchronously to the input clock. If DCLK_RST is asserted, the DCLK output is held in a designated state (logic-high) in demux mode; in non-demux mode, the DCLK continues to function normally. Depending upon when the DCLK_RST signal is asserted, there may be a narrow pulse on the DCLK line during this reset event. When the DCLK_RST signal is de-asserted, there are tSYNC_DLY CLK cycles of systematic delay and the next CLK rising edge synchronizes the DCLK output with those of other ADC12D1620 devices in the system. For 90° mode (DDRPh = logic-high), the synchronizing edge occurs on the rising edge of CLK, 4 cycles after the first rising edge of CLK after DCLK_RST is released. For 0° mode (DDRPh = logic-low), this is 5 cycles instead. The DCLK output is enabled again after a constant delay of tOD. For both demux and non-demux modes, there is some uncertainty about how DCLK comes out of the reset state for the first DCLK_RST pulse. For the second (and subsequent) DCLK_RST pulses, the DCLK comes out of the reset state in a known way. Therefore, if using the DCLK reset feature, TI recommends applying one dummy DCLK_RST pulse before using the second DCLK_RST pulse to synchronize the outputs. This recommendation applies each time the device or channel is powered-on. When using DCLK_RST to synchronize multiple ADC12D1620 devices, the select-phase bits in the Control Register (Addr: Eh, Bits: 4:3) must be the same for each master ADC12D1620. 8.1.5 Temperature Sensor The ADC12D1620 has an on-die temperature diode connected to the Tdiode+ and Tdiode– pins that may be used to monitor the die temperature. In Figure 49, the LM95213 is used to monitor the temperature of an ADC12D1620 as well as an FPGA, see Figure 49. Typical temperature diode voltage to temperature characteristic is: (V - 0.84161) TJ = diode -0.0015 for • 1-mA diode forward current (2) If this feature is unused, the Tdiode+ and Tdiode– pins may be left floating. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP 65 ADC12D1620QML-SP SNAS717 – APRIL 2017 www.ti.com 7 ADC12D1600/1000RF IE = IF D1+ 100 pF IR 5 FPGA IE = IF D- 100 pF 6 D2+ IR LM95213 Copyright © 2017, Texas Instruments Incorporated Figure 49. Typical Temperature Sensor Application 8.2 Radiation Environments Careful consideration must be given to environmental conditions when using a product in a radiation environment. 8.2.1 Total Ionizing Dose Radiation hardness assured (RHA) products are those part numbers with a total ionizing dose (TID) level specified in the POA. Testing and qualification of these products is done on a wafer level according to MIL-STD883, Test Method 1019. Wafer level TID data are available with lot shipments. 8.2.2 Single Event Latch-Up and Functional Interrupt One time single event latch-up (SEL) and single event functional interrupt (SEFI) testing was performed according to EIA/JEDEC Standard, EIA/JEDEC57. The linear energy transfer threshold (LETth) shown in the Features section is the maximum LET tested. A test report is available upon request. 8.2.3 Single Event Upset A report on single event upset (SEU) is available upon request. 8.3 Cold Sparing The ADC12D1620QML-SP has been designed for cold sparing with no reduction in operational lifetime or increase in FIT rate as long as certain conditions are met. Cold sparing is defined as a device in which all power supplies are either floating (high-impedance) or grounded. When cold sparing, all output pins must be either floating or clamped to ground through ESD diodes of the receiving device and not pulled up to an active power supply voltage. Input pins may be driven low (or grounded) or driven to other voltages as long as they are within the Recommended Operating Conditions. Input pins (digital and analog) must maintain a maximum input level of 2.15 V and maximum input current of 50 mA per pin when cold sparing. The input current at each pin is a function of the voltage applied to the pin, the ESD diode IV curve, the power down pin settings, and conditions of the V_A supply. See Figure 50 to Figure 52 for typical IV curves. 66 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP ADC12D1620QML-SP www.ti.com SNAS717 – APRIL 2017 100 100 80 80 Input Current (mA) Input Current (mA) Cold Sparing (continued) 60 40 20 60 40 20 0 0 TJ = 30qC TJ = 100qC TJ = 30qC TJ = 100qC -20 -20 0 0.5 1 Applied Input Voltage (V) 0 1.5 0.5 1 1.5 2 Applied Input Voltage (V) D090 VA = GND VA = HiZ Figure 50. ESD Diode Current 2.5 3 D091 PDI = PDQ = Low Figure 51. ESD Diode Current 100 Input Current (mA) 80 60 40 20 0 TJ = 30qC TJ = 100qC -20 0 0.5 VA = HiZ 1 1.5 2 Applied Input Voltage (V) 2.5 3 D092 PDI = PDQ = High Figure 52. ESD Diode Current Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP 67 ADC12D1620QML-SP SNAS717 – APRIL 2017 www.ti.com 9 Power Supply Recommendations 9.1 System Power-On Considerations 9.1.1 Control Pins Upon power-on, the control pins must be set to the proper configuration per Table 9, ensuring the absolute maximum values in Absolute Maximum Ratings are not violated. This can be done through either pullup and pulldown resistors to VA and VGND or through an FPGA or ASIC. If using an FPGA or ASIC, TI does not recommended writing to the control pins or SPI before power is applied to the ADC12D1620 device. 9.1.2 Power On in Non-ECM If the device is in non-ECM at power on, the control registers are configured in the default mode shown in Table 1 and Register Definitions. The device may be run in non-ECM or switched to ECM and have the registers changed through the SPI per Extended Control Mode. After the device has been configured and has stabilized, run a calibration per Calibration Feature. 9.1.3 Power On in ECM If the device is in ECM at power on, the control registers come up in an unknown, random state. The registers must be configured through the SPI per Extended Control Mode, or the registers can be set to the default settings in Table 1 by toggling the ECE pin logic-high and then logic-low. After the device has been configured and has stabilized, run a calibration per Calibration Feature. 9.1.4 Power-on and Data Clock (DCLK) mV Many applications use the DCLK output for a system clock. For the ADC12D1620 device, each I channel and Q channel has its own DCLKI and DCLKQ, respectively. The DCLK output is always active, unless that channel is powered down or the DCLK reset feature is used while the device is in demux mode. As the supply to the device ramps, the DCLK also comes up. While the supply is too low, there is no output at DCLK. As the supply continues to ramp, DCLK functions intermittently with irregular frequency, but the amplitude continues to track with the supply. Much below the low end of operating supply range of the ADC12D1620, the DCLK is already fully operational. Slope = 1.22V/ms 1900 1710 VA 1490 1210 660 635 520 DCLK 300 time Figure 53. Supply and DCLK Ramping 68 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP ADC12D1620QML-SP www.ti.com SNAS717 – APRIL 2017 10 Layout 10.1 Layout Guidelines 10.1.1 Power Planes Source all supply buses for the ADC from a common linear voltage regulator. This ensures that all power buses to the ADC are turned on and off simultaneously. This single source is split into individual sections of the power plane, with individual decoupling and connections to the different power supply buses of the ADC. Due to the low voltage but relatively high supply-current requirement, the optimal solution may be to use a switching regulator to provide an intermediate low voltage, which is then regulated down to the final ADC supply voltage by a linear regulator. Power for the ADC must be provided through a broad plane, which is located on one layer adjacent to the ground plane(s). Placing the power and ground planes on adjacent layers provides low-impedance decoupling of the ADC supplies, especially at higher frequencies. The output of a linear regulator must feed into the power plane through a low-impedance, multi-via connection. The power plane must be split into individual power peninsulas near the ADC. Each peninsula must feed a particular power bus on the ADC, with decoupling for that power bus connecting the peninsula to the ground plane near each power/ground pin pair. Using this technique can be difficult on many printed circuit CAD tools. To work around this, 0-Ω resistors can be used to connect the power source net to the individual nets for the different ADC power buses. As a final step, the 0-Ω resistors can be removed, and the plane and peninsulas can be connected manually after all other error checking is completed. 10.1.2 Bypass Capacitors TI's general recommendation is to have one 100-nF capacitor for each power/ground pin pair. The capacitors must be surface-mount multi-layer ceramic-chip capacitors similar to Panasonic part number ECJ-0EB1A104K. 10.1.3 Ground Planes Grounding must done using continuous full ground planes to minimize the impedance for all ground return paths and provide the shortest possible image/return path for all signal traces. 10.1.4 Power System Example See Figure 54 for an example with continuous ground planes (except where clear areas are needed to provide appropriate impedance management for specific signals). Power is provided on one plane, with the 1.9-V ADC supply being split into multiple zones or peninsulas for the specific power buses of the ADC. Decoupling capacitors are connected between these power bus peninsulas and the adjacent ground planes using vias. The capacitors are located as close as possible to the individual power/ground pin pairs of the ADC. In most cases, this means the capacitors are located on the opposite side of the PCB to the ADC. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP 69 ADC12D1620QML-SP SNAS717 – APRIL 2017 www.ti.com Layout Guidelines (continued) Linear Regulator Cross Section Line Switching Regulator HV or Unreg Voltage Intermediate Voltage 1.9V ADC Main VTC VA VE VDR ADC Top Layer ± Signal 1 Dielectric 1 Ground 1 Dielectric 2 Signal 2 Dielectric 3 Ground 2 Dielectric 4 Signal 3 Dielectric 5 Power 1 Dielectric 6 Ground 3 Dielectric 7 Bottom Layer ± Signal X Figure 54. Power and Grounding Example 70 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP ADC12D1620QML-SP www.ti.com SNAS717 – APRIL 2017 10.2 Layout Example Balun transformer to convert the SE CLK signal to differential signal CLK path with minimal adjacent circuit To provide best grounding and thermal performance all the ground pins on internal pad should be connected to all the ground layers with vias. Analog input path with minimal adjacent circuit High speed data paths and DCLK signals should be of same length Figure 55. ADC12D1620 Layout Example: Top Side and Inner Layers Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP 71 ADC12D1620QML-SP SNAS717 – APRIL 2017 www.ti.com Layout Example (continued) All high speed signal routing should use impedance controlled traces, either 50-Ω single ended or 100-Ω differential Decoupling capacitors near the device Decoupling Capacitors near VIN The four holes highlighted with black squares were for the socket version of the board and are not required for end application. Figure 56. ADC12D1620 Layout Example: Bottom Side and Inner Layers 72 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP ADC12D1620QML-SP www.ti.com SNAS717 – APRIL 2017 10.3 Thermal Considerations The CCGA package is a modified ceramic-land-grid array with an added heat sink. The signal pins on the outer edge are 1.27-mm pitch, while the pins in the center attached to the heat sink are 1 mm. The smaller pitch for the center pins is to improve the thermal resistance. The center pins of the package are attached to the back of the die through a heat sink. Connecting these pins to the PCB ground planes with a low thermal resistance path is the best way to remove heat from the ADC. These pins must also be connected to the ground planes through low impedance path for electrical purposes. IC Die Cross Section Line Heat Sink Not to Scale Figure 57. CPGA Conceptual Drawing 10.4 Board Mounting Recommendation Proper thermal profile is required to establish re-flow under the package and ensure all joints meet profile specifications. Table 31. Solder Profile Specification RANGE UP PEAK TEMPERATURE (TPK) MAXIMUM PEAK TEMPERATURE RAMP DOWN ≤ 4°C/sec 210°C ≤ tPK ≤ 215°C ≤ 220°C ≤ 5°C/sec The 220°C peak temperature is driven by the requirement to limit the dissolution of lead from the high-melt pin to the eutectic solder. Too much lead increases the effective melting point of the board-side joint and makes it much more difficult to remove the device if module rework is required. Cool-down rates and methods affect CCGA assemble yield and reliability. Picking up boards or opening the oven while solder joints are in molten state can disturb the solder joint. Do not pick up boards until the solder joints have fully solidified. Board warping may potentially cause CCGA lifting off pads during cooling and this condition can also cause pin cracking when severe. This warping is a result of a high differential cooling rate between the top and bottom of the board. Both conditions can be prevented by using even top and bottom cooling. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP 73 ADC12D1620QML-SP SNAS717 – APRIL 2017 www.ti.com Figure 58. Landing Pattern Recommendation 74 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP ADC12D1620QML-SP www.ti.com SNAS717 – APRIL 2017 11 Device and Documentation Support 11.1 Device Support 11.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 11.1.2 Device Nomenclature APERTURE (SAMPLING) DELAY is the amount of delay, measured from the sampling edge of the CLK input, after which the signal present at the input pin is sampled inside the device. APERTURE JITTER (tAJ) is the variation in aperture delay from sample-to-sample. Aperture jitter can be effectively considered as noise at the input. CODE ERROR RATE (CER) is the probability of error and is defined as the probable number of word errors on the ADC output per unit of time divided by the number of words seen in that amount of time. A CER of 10–18 corresponds to a statistical error in one word about every 31.7 years for the adc12d1620QML-SP . CLOCK DUTY CYCLE is the ratio of the time that the clock waveform is at a logic high to the total time of one clock period. DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. It is measured at the relevant sample rate, fCLK, with fIN = 1 MHz sine wave. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is method of specifying signal-to-noise and distortion ratio, or SINAD. ENOB is defined as (SINAD − 1.76) / 6.02 and states that the converter is equivalent to a perfect ADC of this many (ENOB) number of bits. GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated from offset and full-scale errors. the positive gain error is the offset error minus the positive full-scale error. The negative gain error is the negative full-scale error minus the offset error. The gain error is the negative full-scale error minus the positive full-scale error; it is also equal to the positive gain error plus the negative gain error. GAIN FLATNESS is the measure of the variation in gain over the specified bandwidth. For example, for the adc12d1620QML-SP, from D.C. to Fs/2 is to 800 MHz for the non-DES mode and from D.C. to Fs/2 is 1600 MHz for the DES mode. INTEGRAL NON-LINEARITY (INL) is a measure of worst-case deviation of the ADC transfer function from an ideal straight line drawn through the ADC transfer function. The deviation of any given code from this straight line is measured from the center of that code value step. The best fit method is used. INSERTION LOSS is the loss in power of a signal due to the insertion of a device, for example the adc12d1620, expressed in dB. INTERMODULATION DISTORTION (IMD) is a measure of the near-in 3rd order distortion products (2f2 – f1, 2f1 – f2), which occur when two tones that are close in frequency (f1, f2) are applied to the ADC input. It is measured from the input tone's level to the higher of the two distortion products (dBc) or simply the level of the higher of the two distortion products (dBFS). LSB (LEAST SIGNIFICANT BIT) is the bit that has the smallest value or weight of all bits. This value is VFS / 2N where • • VFS is the differential full-scale amplitude VIN_FSR as set by the FSR input N is the ADC resolution in bits, which is 12 for the adc12d1620 (3) LOW VOLTAGE DIFFERENTIAL SIGNALING (LVDS) DIFFERENTIAL OUTPUT VOLTAGE (V ID and VOD) is two times the absolute value of the difference between the VD+ and VD- signals; each signal measured with respect to ground. VOD peak is VOD,P= (VD+ – VD–) and VOD peak-to-peak is VOD,P-P= 2 × (VD+ – VD–); for this product, the VOD is measured peak-to-peak. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP 75 ADC12D1620QML-SP SNAS717 – APRIL 2017 www.ti.com Device Support (continued) VD+ VD VOS ½×VOD VD+ VD - GND ½×VOD = | VD+ - VD- | Figure 59. LVDS Output Signal Levels LVDS OUTPUT OFFSET VOLTAGE (VOS) is the midpoint between the D+ and D– pins output voltage with respect to ground; that is , [(VD+) +( VD-)]/2. See Figure 59. MISSING CODES are those output codes that are skipped and will never appear at the ADC outputs. These codes cannot be reached with any input value. MSB (MOST SIGNIFICANT BIT) is the bit that has the largest value or weight. Its value is one half of full scale. NEGATIVE FULL-SCALE ERROR (NFSE) is a measure of how far the first code transition is from the ideal 1/2 LSB above a differential −VIN / 2 with the FSR pin low. For the adc12d1620 the reference voltage is assumed to be ideal, so this error is a combination of full-scale error and reference voltage error. NOISE FLOOR DENSITY is a measure of the power density of the noise floor, expressed in dBFS/Hz and dBm/Hz. '0 dBFS' is defined as the power of a sinusoid that precisely uses the full-scale range of the ADC. NOISE POWER RATIO (NPR) is the ratio of the sum of the power inside the notched bins to the sum of the power in an equal number of bins outside the notch, expressed in dB. OFFSET ERROR (VOFF) is a measure of how far the mid-scale point is from the ideal zero voltage differential input. Offset Error = Actual Input causing average of 8 k samples to result in an average code of 2047.5. OUTPUT DELAY (tOD) is the time delay (in addition to latency) after the rising edge of CLK+ before the data update is present at the output pins. OVER-RANGE RECOVERY TIME is the time required after the differential input voltages goes from ±1.2 V to 0 V for the converter to recover and make a conversion with its rated accuracy. PIPELINE DELAY (LATENCY) is the number of input clock cycles between initiation of conversion and when that data is presented to the output driver stage. The data lags the conversion by the latency plus the tOD. POSITIVE FULL-SCALE ERROR (PFSE) is a measure of how far the last code transition is from the ideal 1-1/2 LSB below a differential +VIN / 2. For the ADC12D1620 the reference voltage is assumed to be ideal, so this error is a combination of full-scale error and reference voltage error. SIGNAL-TO-NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the fundamental for a singletone to the rms value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or DC. SIGNAL-TO-NOISE PLUS DISTORTION (S/(N+D) or SINAD) is the ratio, expressed in dB, of the rms value of the fundamental for a single tone to the rms value of all of the other spectral components below half the input clock frequency, including harmonics but excluding DC. SPURIOUS-FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input signal at the output and the peak spurious signal, where a spurious signal is any signal present in the output spectrum that is not present at the input, excluding DC. RθJA is the thermal resistance between the junction to ambient. RθJB is the thermal resistance between the junction and the circuit board close to the outer pins. RθJT is the thermal resistance between the junction and the case, measured at the lid of the package. 76 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP ADC12D1620QML-SP www.ti.com SNAS717 – APRIL 2017 Device Support (continued) TOTAL HARMONIC DISTORTION (THD) is the ratio expressed in dB, of the rms total of the first nine harmonic levels at the output to the level of the fundamental at the output. THD is calculated as THD = 20 x log A 2 +... +A 2 f2 f10 A f12 where • • Af1 is the RMS power of the fundamental (output) frequency Af2 through Af10 are the RMS power of the first 9 harmonic frequencies in the output spectrum (4) – Second Harmonic Distortion (2nd Harm) is the difference, expressed in dB, between the RMS power in the input frequency seen at the output and the power in its 2nd harmonic level at the output. – Third Harmonic Distortion (3rd Harm) is the difference expressed in dB between the RMS power in the input frequency seen at the output and the power in its 3rd harmonic level at the output. 11.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP 77 ADC12D1620QML-SP SNAS717 – APRIL 2017 www.ti.com 12.1 Engineering Samples Engineering samples are available for order and are identified by the "MPR" in the orderable device name (see Packaging Information in the Addendum). Engineering (MPR) samples meet the performance specifications of the datasheet at room temperature only and have not received the full space production flow or testing. Engineering samples may be QCI rejects that failed tests that would not impact the performance at room temperature, such as radiation or reliability testing. 78 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: ADC12D1620QML-SP PACKAGE OPTION ADDENDUM www.ti.com 15-Apr-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) ADC12D1620CCMLS PREVIEW CCGA NAA 376 1 TBD Call TI Call TI -55 to 125 ADC12D1620CC MLS ADC12D1620CCMPR PREVIEW CCGA NAA 376 1 TBD Call TI Call TI 25 to 25 ADC12D1620CC MPR E.S. ADC12D1620LGMLS PREVIEW CLGA FVA 256 1 TBD Call TI Call TI -55 to 125 ADC12D1620LG MLS ADC12D1620LGMPR PREVIEW CLGA FVA 256 1 TBD Call TI Call TI 25 to 25 ADC12D1620LG MPR E.S. (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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