DRV3211-Q1
www.ti.com
SLVSBS4 – DECEMBER 2012
3-Phase Brushless Motor Driver
FEATURES
DESCRIPTION
•
The DRV3211-Q1 device is a field effect transistor
(FET) pre-driver designed for 3-phase motor control
and its application such as an oil pump or a water
pump. It is equipped with three high-side pre-FET
drivers and three low-side drivers which are
controlled by an external microcontroller (MCU). The
power for the high side is supplied by a charge pump
and no bootstrap cap is needed. For commutation,
this integrated circuit (IC) sends a conditional motor
drive signal and output to the MCU. Diagnostics
provide undervoltage, overvoltage, overcurrent,
overtemperature and power bridge faults. The motor
current can be measured using an integrated current
sense amplifier and comparator in a battery commonmode range, which allows the motor current to be
used in a high-side current sense application. Gain is
attained by external resistors. If the MCU does not
have enough bandwidth, the phase monitoring
sample and hold amplifiers can hold phase
information until the MCU is ready to process it. The
pre-driver and other internal settings can be
configured through the SPI interface.
1
•
•
•
•
•
•
•
•
•
•
3-Phase Pre-drivers for N-channel MOS Field
Effect Transistors (MOSFETs)
Pulse Width Modulation (PWM) Frequency up
to 20 kHz
Fault Diagnostics
Charge Pump
Phase Comparators
Phase Monitoring Sample and Hold Op-Amps
Central Processing Unit (CPU) Reset
Generator
Serial Port I/F (SPI)
Motor Current Sense
80-pin HTQFP
5-V Regulator
APPLICATIONS
•
Automotive
VCFB
VBPD
UL
VL
WL
N/C
TEST1
GFB
TEST3
VCCB
FAULT
WDEN
PRN
RES
CTLUH
CTLUL
CTLVH
CTLVL
CTLWH
TEST2
WH
VDD
CTLWL
PDCPV
SCK
UH
CPDR4
DOUT
CTLEN
CPDR3
CS
VH
CPDR2
PSS3
DGND
CPDR1
PSS2
DIN
VBCP
PSS1
PINOUT
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
Copyright © 2012, Texas Instruments Incorporated
PRODUCT PREVIEW
Check for Samples: DRV3211-Q1
DRV3211-Q1
SLVSBS4 – DECEMBER 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PIN FUNCTIONS
PIN
FUNCTION
NAME
TYPE
1
AOUT
O
–0.3–6 V
Test mode output
2
PHTM
I
–1–40 V
Phase comparator reference input
3
PH1M
I
–1–40 V
Phase comparator input
4
PH2M
I
–1–40 V
Phase comparator input
5
PH3M
I
–1–40 V
Phase comparator input
6
PMV1
O
–0.3–6 V
Phase comparator output
7
PMV2
O
–0.3–6 V
Phase comparator output
Phase comparator output
PRODUCT PREVIEW
8
PMV3
O
–0.3–6 V
9, 20, 42, 49,
50
GND
I
–0.3–0.3 V
10
PH1T
I
–2–40 V
Phase amplifier input
11
PSC1
O
–0.3–6 V
Sample and hold filter output
12
AMPG
I
–0.3–0.3 V
13
PH2T
I
–2–40 V
Phase amplifier input
14
PSC2
O
–0.3–6 V
Sample and hold filter output
15
PH3T
I
–2–40 V
Phase amplifier input
16
PSC3
O
–0.3–6 V
Sample and hold filter output
17
PTV1
O
–0.3–6 V
Phase amplifier output
18
PTV2
O
–0.3–6 V
Phase amplifier output
19
PTV3
O
–0.3–6 V
Phase amplifier output
21
PSS1
I
–0.3–6 V
Sample and hold control signal input
22
PSS2
I
–0.3–6 V
Sample and hold control signal input
23
PSS3
I
–0.3–6 V
Sample and hold control signal input
24
CS
I
–0.3–6 V
SPI chip select
25
DOUT
O
–0.3–6 V
SPI data output
26
SCK
I
–0.3–6 V
SPI clock
27
VDD
O
–0.3–3.6 V
28
DIN
I
–0.3–6 V
29
DGND
I
–0.3–0.3 V
30
CTLEN
I
–0.3–6 V
Pre-driver parallel enable input
31
CTLWL
I
–0.3–6 V
Pre-driver parallel input
32
CTLWH
I
–0.3–6 V
Pre-driver parallel input
33
CTLVL
I
–0.3–6 V
Pre-driver parallel input
34
CTLVH
I
–0.3–6 V
Pre-driver parallel input
35
CTLUL
I
–0.3–6 V
Pre-driver parallel input
36
CTLUH
I
–0.3–6 V
Pre-driver parallel input
37
RES
O
–0.3–6 V
Reset output
38
PRN
I
–0.3–6 V
Pulse input
39
WDEN
I
–0.3–6 V
Reset generator enable input
40
FAULT
O
–0.3–6 V
Diagnosis output
41
OVCR
I
–0.3–6 V
Over current reset input
43-48, 58, 67
51
2
MAX RATING
NO.
N/C
ADTH
—
—
I
–0.3–6 V
GND
Quiet GND
Digital supply output
SPI data input
Digital GND
Not connected
Motor overcurrent threshold input
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: DRV3211-Q1
DRV3211-Q1
www.ti.com
SLVSBS4 – DECEMBER 2012
PIN FUNCTIONS (continued)
PIN
FUNCTION
NAME
52
AMPG
I
–0.3–0.3 V
53
ALV
O
–0.3–6 V
Motor current sense amp output
54
AREF
O
–0.3–40 V
Motor current sense reference output
55
ALFB
O
–0.3–40 V
Motor current sense amp feedback
56
ALM
I
–0.3–40 V
Motor current sense amp negative input
57
ALP
I
–0.3–40 V
Motor current sense amp positive input
59
VLVD
I
–0.3–6 V
VCC undervoltage threshold input
60
VCCT
I
–0.3–6 V
VCC supply input
61
VCCB
O
–0.3–40 V
VCC regulator base drive for PNP external transistor
62
VCFB
I
–0.3–40 V
VCC regulator current sense input
63
VBPD
I
–0.3–40 V
VB input
64
UL
O
-0.3–20 V
Pre-driver output
65
VL
O
-0.3–20 V
Pre-driver output
66
WL
O
-0.3–20 V
Pre-driver output
68
TEST1
I
–0.3–6 V
Test input
69
GFB
I
–0.3–0.3 V
Power GND
70
TEST3
I
-0.3–20 V
Test input
71
TEST2
I
–0.3–6 V
Test input
72
UH
O
–0.3–40 V
Pre-driver output
73
VH
O
–0.3–40 V
Pre-driver output
74
WH
O
–0.3–40 V
Pre-driver output
75
PDCPV
O
–0.3–40 V
Charge pump output
76
CPDR4
O
–0.3–40 V
Charge pump output
77
CPDR3
O
–0.3–40 V
Charge pump output
78
CPDR2
O
–0.3–40 V
Charge pump output
79
CPDR1
O
–0.3–40 V
Charge pump output
80
VBCP
I
–0.3–4 0V
VB input
Quiet GND
PRODUCT PREVIEW
TYPE
MAX RATING
NO.
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: DRV3211-Q1
3
DRV3211-Q1
SLVSBS4 – DECEMBER 2012
www.ti.com
VBPD
VCFB
VCCB
PRN
FAULT
VL
CTLUH
WDEN
WL
CTLUL
UL
NC
CTLVH
GFB
TEST1
TEST3
TEST2
UH
VH
PDCPV
WH
CPDR4
COMP
CPDR3
COMP
RES
CTLVL
CTLWH
CTLWL
DGND
CTLEN
DIN
VDD
SCK
DOUT
CS
PSS3
PSS3
PSS1
PSS2
PSS2
PRODUCT PREVIEW
PSS1
COMP
ADTH
COMP
VBCP
CPDR1
CPDR2
VB
BLOCK DIAGRAM
Figure 1. Top Block Diagram
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
MIN
ESD
MAX
UNITS
(1)
ESD all
pins
ESD performance of all pins to any other pin
HBM model
–2
2
kV
CDM model
–500
500
V
TEMPERATURE
TA
Operating temperature range
-40
125
degree
TJ
Junction temperature
-40
150
degree
Ts
Storage temperature
–55
150
degree
(1)
4
ESD testing is performed according to the ACE-Q100 standard.
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: DRV3211-Q1
DRV3211-Q1
www.ti.com
SLVSBS4 – DECEMBER 2012
THERMAL INFORMATION
THERMAL METRIC (1)
DRV3202-Q1
HTQP (80-PIN)
θJA
Junction-to-ambient thermal resistance
23.0
θJCtop
Junction-to-case (top) thermal resistance
7.5
θJB
Junction-to-board thermal resistance
7.6
ψJT
Junction-to-top characterization parameter
0.2
ψJB
Junction-to-board characterization parameter
7.4
θJCbot
Junction-to-case (bottom) thermal resistance
0.3
UNIT
°C/W
spacer
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
PRODUCT PREVIEW
(1)
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: DRV3211-Q1
5
DRV3211-Q1
SLVSBS4 – DECEMBER 2012
www.ti.com
SUPPLY VOLTAGE AND CURRENT
VB = 12 V, TA = –40°C to 125°C (unless otherwise specified)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
5.3
12
18
V
20
35
mA
SUPPLY INPUT
VB
VB Supply voltage
IVB
VB Operating current
VB = 5.3 ~18 V, No PWM
WATCHDOG
Description
The watchdog monitors the PRN signal and VCC supply level and generates a reset to the MCU through the RES
pin if the status of the PRN is not normal or the VCC is lower than the specified threshold level. The watchdog
can be disabled if WDEN is set high.
Vbgr = 2.325 V
(+0.75 V / ± 0.25 V)
Band Gap VHS = 0.1 V
Regulator (+0.75 V / ± 0.05 V)
VCC
PRODUCT PREVIEW
R1
VDD Undervoltage
Detection
VCC
VCC Low
Voltage Detection
(NMI)
R_RES
Reset Logic
3k
VLVD
RES
R2
100 pF
Option
Clock
Monitor
Watch Dog Timer
WDEN
WDEN
Open: Enable
High: Disable
PRN
From CPU
Disable During
Power On Reset
Power On Reset
VNMI: Lower Threshold Voltage
VHS: Hysteresis Voltage
Figure 2. Watchdog Block Diagram
6
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: DRV3211-Q1
DRV3211-Q1
www.ti.com
SLVSBS4 – DECEMBER 2012
VB
Do not switch to RES LOW
when the VCC LOW time
is less than tRES.
VNMI+VHS
VCC
VNMI
tRES
VSTN
tRES
Ignore transient voltage falling
NMI
(Internal signal)
Switch to NMI-LOW after tRES delay
when VCC is lower than VNMIL
tRES
RES is HIGH after tON from NMI-HIGH
if internal clock is not generated
(In case of malfunction).
RES signal should remain in low voltage
(< -0.4 V) and in this case, controlled CPU
should be in
RES is HIGH after tON from of NMI-HIGH.
tRH
RES
RES is LOW at NMI-LOW.
tON
Pwth
RES is LOW at NMI-LOW.
PRODUCT PREVIEW
tRL
tON
tOFF
PRN
Detecting only rising edge of PRN signal
Switch to RES LOW if PRN stays at a High or LOW
level.
If WDEN is LOW (or OPEN),
and there is abnormal PRN:
RES is active.
If WDEN is HIGH,
and there is abnormal PRN:
no operation.
WDEN
NOTE: WDEN = High, VCC undervoltage condition sets RES = Low
Figure 3. Watchdog Timing Chart
WATCHDOG ELECTRICAL CHARACTERISTICS (1)
VB = 12 V,TA = –40°C to 125°C (unless otherwise specified)
PARAMETER (2)
CONDITIONS
MIN
TYP
MAX
UNITS
WATCHDOG
VSTN
Function start VCC voltage RES
tON
Power-on time RES
tOFF
Clock off reset time RES
tRL
Reset pulse low time RES
tRH
Reset pulse high time RES
tRES
Reset delay time RES
Pwth
Pulse width PRN
(1)
(2)
Refer to Figure 3
–
0.8
1.3
V
32
40
48
ms
64
80
96
ms
16
20
24
ms
64
80
96
ms
30
71.5
90
µs
200
–
–
ns
The watchdog function is disabled and the timing parameters are invalid when the WDEN is at a high level.
Specified by design
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: DRV3211-Q1
7
DRV3211-Q1
SLVSBS4 – DECEMBER 2012
www.ti.com
SERIAL PORT I/F
Description
The SPI is used to receive an input byte from CPU and to transmit an output byte to CPU. Four signals are
utilized according to the timing chart of Figure 4.
LSB
CS
CK
MSB
Register
Parallel Output
Parallel Input
/16
DIN
MSB First
Parallel Output
Serial input
Shift Register
(16 bits)
PRODUCT PREVIEW
SCK
Serial Output
CK
DOUT
MSB First
Parallel Input
/16
Parallel Output
EN
LSB
Parallel Input
Output Latch
(Transparent if EN = High)
Internal
Diagnosis Register
MSB
Figure 4. Block Diagram of SPI
•
•
CS – Chip Select
– This input signal is utilized to select this IC by CPU.
– This input signal is normally high and the communication is possible only when it is forced low.
– When this input signal falls, the communication between this IC and the CPU starts.
– Transmitted data is latched and the DOUT pin comes out of high impedance.
– When this input signal rises, the communication stops.
– The DOUT pin goes into high impedance. Then, the internal input register updates with the received bits
(only if the clock pulse numbers are right and the key bit of the DIN signals is correct).
– The next falling edge starts another communication.
– There is a minimum waiting time between two communications (Twait).
– The pin has an internal pullup.
SCK – Synchronization Serial Clock
– This input signal is utilized to synchronize the communication by CPU.
– It is normally high and the correct clock pulse number is 16.
– At each falling edge, the CPU writes a new bit on the DIN input and this IC writes a new bit on the DOUT
pin. At each rising edge, this IC reads the new bit on the DIN pin and the CPU reads the new bit on the
DOUT pin.
– The maximum clock frequency is 4 MHz.
– The pin has an internal pullup.
space
8
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: DRV3211-Q1
DRV3211-Q1
www.ti.com
•
•
SLVSBS4 – DECEMBER 2012
DIN – Serial Input Data
– This input signal is used to receive 16-bit data.
– The bits are received in order from the MSB (first) to the LSB (last).
– The pin has an internal pullup.
DOUT – Serial Output Data
– This output signal is used to transmit 16-bit data.
– It is a 3-state output and it is in high impedance mode when CS is high.
– The serial data bits are transmitted in order from the MSB (first) to the LSB (last).
SPI ELECTRICAL CHARACTERISTICS
VB = 12 V, TA = –40°C to 125°C (unless otherwise specified)
PARAMETER (1)
CONDITIONS
MIN
TYP
MAX
UNITS
Fop
Operating frequency
DC
–
4
MHz
Tlead
Enable lead time
100
–
–
ns
Twait
Wait time between two successive
communications
5
–
–
µs
Tlag
Enable lag time
100
–
–
ns
Tpw
SCLK pulse width
100
–
–
ns
Tsu
Data setup time
80
–
–
ns
Th
Data hold time
80
–
–
ns
Tdis
Disable time
–
–
80
ns
Tdel
Data delay time (SCK to DOUT)
–
–
80
ns
(1)
Refer to Figure 6
CL = 50 pF, Refer to Figure 6
PRODUCT PREVIEW
SPI
Specified by design
Waiting Time From b9 Through b8
CS
DIN
b15~b10
b9~b8
Select Diagnosis or Command Register
From b15 Through b10
b7~b0
Command Input or Diagnosis Result Output From b7 Through b0
DOUT
b7~b0
Echo Back of b14~b9
Figure 5. SPI Bit Sequence
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: DRV3211-Q1
9
DRV3211-Q1
SLVSBS4 – DECEMBER 2012
Tlead
www.ti.com
Tpw
Tlag
Tpw
Twait
CS
SCK
MSB
DIN
D14
D13
D11
D12
D10
D9
D7
D8
D6
D5
D3
D4
D2
D1
LSB
Th
Tsu
MSB
DOUT Hi-Z
D14
D13
D11
D12
D9
D10
D6
D7
D8
D5
D4
D2
D3
D1
LSB
Hi-Z
Tdel
Ten
Tdis
Figure 6. SPI AC Timing Definition
Table 1. SPI Bit Map (DIN)
PRODUCT PREVIEW
ITEM
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
COMMAND1
0
0
0
0
0
1
–
–
SHM
SRT
–
–
–
–
–
–
COMMAND2
0
0
0
0
1
0
–
–
AG1
AG0
–
–
–
–
–
–
COMMAND3
0
0
0
0
1
1
–
–
–
–
–
–
–
–
–
–
DIAG_READ1
0
0
1
0
0
0
–
–
–
–
–
–
–
–
–
–
DIAG_READ2
0
1
0
0
0
0
–
–
–
–
–
–
–
–
–
–
DIAG_READ3
0
1
1
0
0
0
–
–
–
–
–
–
–
–
–
–
In Table 1, the B15–B10 are the control bits, so the each command depends on them (listed below).
1.
B15-B10 = 0 0 0 0 0 1
These are the commands:
1) Phase AMP Sampling Hold Mode (B7 bit)
MM0: OFF (through) (INITIAL VALUE)
MM1: ON (use sample hold mode)
2) Phase AMP Short Mode [Short_Mode] (B6 bit)
MM0: OFF (no calibration) (INITIAL VALUE)
MM1: ON (use calibration mode)
2.
B15-B10 = 0 0 0 0 1 0
These are the commands:
1) Phase AMP Gain (B7 bit and B6 bit)
MMB7:0 B6:0; Gain x1 (INITIAL VALUE)
MMB7:0 B6:1; Gain x2
MMB7:1 B6:0; Gain x3
MMB7:1 B6:1; Gain x4
3.
B15-B10 = 0 0 0 0 1 1
4.
B15-B10 = 0 0 1 0 0 0
Not used
This command is to read the diagnosis of the current regulator,
SPI communication, overvoltage detection, and input diagnosis.
5.
B15-B10 = 0 1 0 0 0 0
6.
B15-B10 = 0 1 1 0 0 0
This command is to read the diagnosis of SPI communication.
Not used
10
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: DRV3211-Q1
DRV3211-Q1
www.ti.com
7.
SLVSBS4 – DECEMBER 2012
B15-B10 = Other command
This command sets the SPI-NG (DOUT, B7) bit.
Table 2. SPI Bit Map (DOUT)
ITEM
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
–
–
–
–
–
–
–
–
0
0
0
0
0
1
1
0
–
–
–
–
–
–
–
–
DIAG_READ1
0
0
0
1
0
0
0
0
VCC
Rsvd
CCD
VCO
VDO
CPLV
TD
EEP
DIAG_READ2
0
0
1
0
0
0
0
0
SPI
–
–
–
–
–
–
–
DIAG_READ3
0
0
1
1
0
0
0
0
–
–
–
–
–
–
–
–
ON/OFF COMMAND
ECHO BACK
1.
B14-B9 = 0 0 1 0 0 0
This flag is cleared after the register is read by the CPU.
1) VCC Current Detection (B7)
MM0: NORMAL
MM1: Fail (Short to GND or open)
2) Overcurrent Detection (B6)
MM0: NORMAL
MM1: Fail (Overcurrent)
PRODUCT PREVIEW
4) VCC Overvoltage Detection (B4)
MM0: NORMAL
MM1: Fail (VCC overvoltage)
5) VDD Overvoltage Detection (B3)
MM0: NORMAL
MM1: Fail (VDD overvoltage)
6) CPV Low Voltage Detection (B2)
MM0: NORMAL
MM1: Fail (CPV low voltage)
7) Thermal Detection (B1)
MM0: NORMAL
MM1: Fail (Overtemperature)
8) EEPROM* Data Consistency Check (B0)
MM0: NORMAL
MM1: Fail (EEPROM DATA CRC error)
*ASIC calibration EEPROM
NOTE
Just after power-on of the IC, some of the bits listed above may be set depending on the
apply sequence of VB. It is recommended to issue a DIAG_READ1 to clear these bits
prior to all S/W sequences.
2.
B14-B9 = 0 1 0 0 0 0
This flag is cleared after the register is read by the CPU.
1) SPI-NG (B7)
MM0: NORMAL
MM1: Fail (SPI read and write command is wrong)
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: DRV3211-Q1
11
DRV3211-Q1
SLVSBS4 – DECEMBER 2012
www.ti.com
Diag happen!
Twait > 5 µs
CS
CLK
MSB
~
bit10 bit9 bit8 bit7
~
bit0
MSB
~
bit10 bit9 bit8
bit7
~
bit0
DOUT Command Data for Diagnosis
DOUT Command Data for Diagnosis
DIN
New Diagnosis Data
During bit7 ~ bit0
Internal Diagnosis
Shadow Register
PRODUCT PREVIEW
Internal Diagnosis
Status Register
DOUT
Diagnosis Data Against DIN Command
DIN ECHO
Diagnosis
New Diagnosis Data
Hi-Z
DIN ECHO
Hi-Z
New
'RQ¶W FDUH
'RQ¶W FDUH
Figure 7. DIAG_READ
Internal Diagnosis Register (Status Register and Shadow Register)
If the diagnosis happens during the SPI communication, the function follows this protocol:
The diagnosis information is stored in the shadow register when the diagnosis happens.
After the output of the previous information a new diagnosis is sent from the shadow to the status register,
and both registers are output through the DOUT pin.
In this case, a FAULT signal continues to be output until a new diagnosis is read by the CPU.
All diagnosis bits read by the DIAG_READ1 command happen before the CS falling edge. So, all the diagnosis
events that happen right after the CS falling edge are not read by the current DIAG_READ1 command, instead
they are read by the next DIAG_READ1 command.
12
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: DRV3211-Q1
DRV3211-Q1
www.ti.com
SLVSBS4 – DECEMBER 2012
CHARGE PUMP
Description
The charge pump block generates the supply for high-side and low-side pre-drivers to maintain the gate voltage
on the external FETs. External storage cap (CCP) and bucket caps (C1, C2) are used to support pre-driver slope
and switching frequency requirements. R1 and R2 can reduce switching current if required. The charge pump
has a voltage supervisor for over and undervoltage, and a selectable stop condition for pre-drivers.
VB
PDCPV
CP
Supervisor
CP Logic
CP14
CPCLK
MAX
S2
VF
UV
CPDR2
C2
CPDR1
GFB
PDCPV
S4
VF
PRODUCT PREVIEW
S1
CCP
VF
CPDR4
C1
CPDR3
S3
GFB
Figure 8. Charge Pump Block Diagram
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: DRV3211-Q1
13
DRV3211-Q1
SLVSBS4 – DECEMBER 2012
www.ti.com
CHARGE PUMP ELECTRICAL CHARACTERISTICS (1)
VB = 12 V, TA = –40°C to 125°C (unless otherwise specified)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
CHARGE PUMP
Vchv1_0
VB = 5.3 V, Iload = 0 mA, C1 = C2 = 47 nF,
CCP = 2.2 µF
VB + 7
VB + 8
VB + 9
V
Vchv1_1
VB = 5.3 V, Iload = 5 mA, C1 = C2 = 47 nF,
CCP = 2.2 µF
VB + 6
VB + 7
VB + 8
V
Vchv1_2
VB = 5.3 V, Iload = 8 mA, C1 = C2 = 47 nF,
CCP = 2.2 µF
VB + 5
VB + 6
VB + 7
V
Vchv2_0
VB = 12 V, Iload = 0 mA, C1 = C2 = 47 nF,
CCP = 2.2 µF
VB + 13
VB + 14
VB + 15
V
VB = 12 V, Iload = 11 mA, C1 = C2 = 47 nF,
CCP = 2.2 µF
VB + 13
VB + 14
VB + 15
V
Vchv2_2
VB = 12 V, Iload = 18 mA, C1 = C2 = 47 nF,
CCP = 2.2 µF
VB +
12.5
VB + 13.5
VB + 15
V
Vchv3_0
VB = 18 V, Iload = 0 mA, C1 = C2 = 47 nF,
CCP = 2.2 µF
VB + 13
VB + 14
VB + 15
V
Vchv3_1
VB = 18 V, Iload = 13 mA, C1 = C2 = 47 nF,
CCP = 2.2 µF
VB + 13
VB + 14
VB + 15
V
Vchv3_2
VB = 18 V, Iload = 22 mA, C1 = C2 = 47 nF,
CCP = 2.2 µF
VB + 13
VB + 14
VB + 15
V
35
37.5
40
V
VB + 4
VB + 4.5
VB + 5
V
1
2
Vchv2_1
Output voltage
PRODUCT PREVIEW
Vchvmax
Maximum voltage
VchvUV
Undervoltage detection
threshold
Tchv (2)
Rise time
Ron
On resistance S1~S4
(1)
(2)
No variation of the external components
Specified by design
14
Submit Documentation Feedback
VB = 5.3 V, C1 = C2 = 47 nF, CCP = 2.2 µF,
VchvUV released
8
ms
Ω
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: DRV3211-Q1
DRV3211-Q1
www.ti.com
SLVSBS4 – DECEMBER 2012
PRE-DRIVER
Description
PRODUCT PREVIEW
The pre-driver block provides three high-side pre-drivers and three low-side pre-drivers to drive external Nchannel MOSFETs. The turn on side of the high-side pre-drivers supply the large N-channel transistor current to
quickly charge and PMOS support output voltage up to PDCPV. The turn off side supplies the large N-channel
transistor current to quickly discharge, while the low-side pre-drivers supply the large N-channel transistor current
for charge and discharge. The output voltage of the low-side pre-driver is controlled by VB and it has VGS
protection to make less than 18 V. The pre-driver has a stop condition in some fault conditions ($16 Error
Detection).
Figure 9. Pre-driver Block Diagram
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: DRV3211-Q1
15
DRV3211-Q1
SLVSBS4 – DECEMBER 2012
www.ti.com
PRE-DRIVER ELECTRICAL CHARACTERISTICS
VB = 12 V, TA = –40°C to 125°C (unless otherwise specified)
PARAMETER
CONDITIONS
MIN
TYP
Vchv – 2.7
Vchv –
1.35
MAX
UNITS
HIGH SIDE PRE-DRIVER
VOH_H
Output voltage high
Isink = 10 mA, U(V/W)H – GFB
VOL_H
Output voltage low
Isource = 10 mA, U(V/W)H – GFB
RONH_HP
ON resistance pull up (Pch)
U(V/W)H = PDCPV - 1 V
RONH_HN
ON resistance pull up (Nch)
U(V/W)H = PDCPV - 2.5 V
RONL_H
ON resistance pull down
Ton_h (1)
Turn-on time
VB = 5.3 ~ 18 V, CL = 11 nF, RL = 0 Ω
from 20% to 80%
Toff_h (1)
Turn-off time
Th-ondly (1)
Th-offdly (1)
V
PRODUCT PREVIEW
60
120
mV
135
270
Ω
8
16
Ω
6
12
Ω
100
300
500
ns
VB = 5.3 ~ 18 V, CL = 11 nF, RL = 0 Ω
from 80% to 20%
100
300
500
ns
Output delay time
VB = 5.3 ~ 18 V, CL = 11 nF, RL = 0 Ω to
20%,
see Figure 10
100
200
400
ns
Output delay time
VB = 5.3 ~ 18 V, CL = 11 nF, RL = 0 Ω to
80%,
see Figure 10
100
200
400
ns
VB – 0.14
VB-0.07
70
140
mV
LOW SIDE PRE-DRIVER
VOH_L
Output voltage high
Isink = 10 mA, U(V/W)L – GFB
VOL_L
Output voltage low
Isource = 10 mA, U(V/W)L – GFB
V
RONH_L
ON resistance pull up
7
14
Ω
RONL_L
ON resistance pull down
7
14
Ω
Turn-on time
VB = 5.3 ~ 18 V, CL = 22 nF, RL = 0 Ω
from 20% to 80%
100
300
800
ns
Toff_I (1)
Turn-off time
VB = 5.3 ~ 18 V, CL = 22 nF, RL = 0 Ω
from 80% to 20%
100
300
800
ns
Tl-ondly (1)
Output delay time
VB = 5.3 ~ 18 V, CL = 22 nF, RL = 0 Ω to
20%,
see Figure 10
100
200
400
ns
Tl-offdly (1)
Output delay time
VB = 5.3 ~ 18 V, CL = 22 nF, RL = 0 Ω to
80%,
see Figure 10
100
200
400
ns
VCLAMP
VGS protection voltage
16
18
20
V
Ton_l
(1)
(1)
Tdiff2 (1)
Tdiff1
(1)
16
Differential time 1
VB = 5.3 ~ 18 V (Th-on)–(Tl-off), see
Figure 10
–300
300
ns
Differential time 2
VB = 5.3 ~ 18 V (Tl-on)–(Th-off), see
Figure 10
–300
300
ns
Specified by design
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: DRV3211-Q1
DRV3211-Q1
www.ti.com
SLVSBS4 – DECEMBER 2012
CTLUH
CTLVH
CTLWH
CTLUL
CTLVL
CTLWL
Th-ondly
Th-offdly
80%
20%
20%
Th-on(Th-ondly + Ton)
80%
UL
VL
WL
GFB
Th-off(Th-offdly + Toff)
PRODUCT PREVIEW
80%
UH
VH
WH
80%
20%
GFB
20%
TI-ondly
TI-offdly
TI-off(TI-offdly + Toff)
TI-on(TI-ondly + Ton)
Figure 10. Delay Time from Input to Output
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: DRV3211-Q1
17
DRV3211-Q1
SLVSBS4 – DECEMBER 2012
www.ti.com
PHASE COMPARATOR
Description
A 3-channel comparator module monitors the external FET by detecting voltage across the drain-source for highside and low-side FETs. PHTM is the threshold level of comparators usable for sensorless communication.
Figure 11 shows an example of the threshold level. There is no detection when CTLEN = Low.
UHS,
VHS,
WHS
CTLEN
VCOM
VCC
PHxM
+
Clamp
PMVx
PHTM
-
Clamp
Figure 11. Phase Comparator Block Diagram
PRODUCT PREVIEW
PHASE COMPARATORS ELECTRICAL CHARACTERISTICS
VB = 12 V, TA = –40°C to 125°C (unless otherwise specified)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
–15
–
15
mV
1.325
–
4.5
V
PHASE COMPARATOR
Viofs
Input offset voltage
Vinp
Input voltage range (PHTM)
Vinm
Input voltage range (PHxM)
Vihys
Input hysteresis voltage
VOH
Output high voltage
Isink = 2.5 mA
VOL
Output low voltage
Isource = 2.5 mA
(1)
Response time (rising)
Tres_tf (1)
Response time (falling)
Tres_tr
(1)
18
VB = 5.3 ~18 V
–1
–
VB
V
100
200
400
mV
0.9 × VCC
–
–
V
–
–
0.1 × VCC
V
CL = 100 pF
–
0.2
0.5
µs
CL = 100 pF
–
0.4
1
µs
Specified by design
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: DRV3211-Q1
DRV3211-Q1
www.ti.com
SLVSBS4 – DECEMBER 2012
MOTOR CURRENT SENSE
Description
The operational amplifier is operating with an external resistor network for higher flexibility to adjust the current
measurement to application requirements. The first stage amplifier is operating with the external resistor and the
output voltage up to VB at ALFB. The gain of the amplifier is adjustable by external resistors from x10 to x30.
The second stage amplifier is a buffer to MCU at ALV. Current sense has a comparator for motor overcurrent
(OVAD). ADTH is the overcurrent threshold level and sets the value by the external resistor as well. Figure 13
shows the curve of the detection level. ALFB is divided by 2, compare this value with ADTH. In the
recommended application, zero-point adjustment is required as a large error offset in the initial condition.
OVAD
+
VCC
-
R3
ADTH
½ ALFB
CLAMP
R4
VCC
CLAMP
+
ALV
PRODUCT PREVIEW
-
VB
-
ALFB
+
R22
C1
Battery
R11
ALP
ALM
*R11, R12, R21, R22 # 0.1%
*VGain
X10: R11 = R12 = 3 k , R21 = R22 = 30 k
1V
X20: R11 = R12 = 1.5 k , R21 = R22 = 30 k
X30: R11 = R12 = 1 k , R21 = R22 = 30 k
C2 = 10 n ~ 20 nF
C1 = 0 ~ 10 pF
*ALV = VGain x (Rshunt x lmotor) + AREF
*ADTH = {R4 / (R3 + R4)} x VCC
*OVAD = (2 x ADTH ± AREF) / (Rshunt x VGain)
+
R12
R21
VCC
Imotor
Rshunt
M
AREF
-
C2
CLAMP
Figure 12. Motor Current Sense Block Diagram
MOTOR CURRENT SENSE ELECTRICAL CHARACTERISTICS (1)
VB = 12 V, TA = –40°C to 125°C (unless otherwise specified)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
MOTOR CURRENT (2) SENSE
VOfs
Input offset voltage
VO_0
(1)
(2)
Output voltage (ALV)
–5
VB = 5.3 ~ 18 V,
Imotor = 0 A
5
1
mV
V
No variation of the external components
Motor current is converted to voltage in test
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: DRV3211-Q1
19
DRV3211-Q1
SLVSBS4 – DECEMBER 2012
www.ti.com
MOTOR CURRENT SENSE ELECTRICAL CHARACTERISTICS(1) (continued)
VB = 12 V, TA = –40°C to 125°C (unless otherwise specified)
PARAMETER
VLine
Linearity (ALV)
VGain
Gain
CONDITIONS
VB = 5.3 ~ 18 V,
Rshunt = 1 mΩ,
R11 = R12 = 1 kΩ, R21 = R22 = 30 kΩ
MIN
TYP
MAX
UNITS
–2%
30
2%
mV/A
10
30
Settling time (Rise) ALV ±1%
VB = 5.3 ~ 18 V,
Rshunt = 1 mΩ, C1 = 4.7 pF, CL = 100 pF,
R11 = R12 = 1 kΩ, R21 = R22 = 30 kΩ,
Imotor = 0 → 30 A, (ALV : 1→1.9 V)
–
1
2.5
µs
Settling time (Rise) ALV ±1%
VB = 5.3 ~ 18 V,
Rshunt = 1 mΩ, C1 = 4.7 pF, CL = 100 pF,
R11 = R12 = 1 kΩ, R21 = R22 = 30 kΩ,
Imotor = 0 → 100 A, (ALV : 1 → 4 V)
–
1
2.5
µs
Settling time (Fall) ALV ±1%
VB = 5.3 ~ 18 V,
Rshunt = 1 mΩ, C1 = 4.7 pF, CL = 100 pF,
R11 = R12 = 1 kΩ, R21 = R22 = 30 kΩ,
Imotor = 30 → 0 A, (ALV : 1.9 → 1 V)
–
1
2.5
µs
Settling time (Fall) ALV ±1%
VB = 5.3 ~ 18 V,
Rshunt = 1 mΩ, C1 = 4.7 pF, CL = 100 pF,
R11 = R12 = 1 kΩ, R21 = R22 = 30 kΩ,
Imotor = 100 → 0 A, (ALV : 4 → 1 V)
–
1
2.5
µs
OVAD
Overcurrent threshold
150-A detection,
Rshunt = 1 mΩ,
R11 = R12 = 1 kΩ, R21 = R22 = 30 kΩ,
R3 = 8.2 kΩ, R4 = 10 kΩ
–10%
150
10%
A
TDEL_OVAD (3)
Propagation delay (Rise or fall)
–
–
1.5
µs
Tset_TR1
Tset_TR2
Tset_TF1
PRODUCT PREVIEW
Tset_TF2
(3)
Specified by design
ALV
ALFB / 2
VCC
ADTH
VLine
= ûY / ûX
ûY
ûX
VO_0
0A
Imotor
OVAD
0A
Imotor
*ALFB up to VB
Figure 13. Motor Current Sense and Overcurrent
20
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: DRV3211-Q1
DRV3211-Q1
www.ti.com
SLVSBS4 – DECEMBER 2012
Motor
Overcurrent
OVAD
OVCR
Enable
PreDRV
Disable
Enable
Figure 14. Motor Overcurrent Event
RES
OVCR
MOTOR OVERCURRENT
OVAD
PRE-DRIVER ENABLE OR DISABLE
0
–
–
0 (Clear)
Disable (1)
1
(1)
(2)
(3)
(2) (3)
0
–
0 (Clear)
1
0
Keep
Enable
1
1 (Set)
Disable
PRODUCT PREVIEW
Table 3. Motor Overcurrent Truth Table
Enable
The CTLEN goes to Hi-Z because the external CPU will not drive it when RES = 0, then all the pre-drivers are turned off because
CTLEN is internally pulled down.
The OVAD is not set, even if a motor overcurrent error is generated during OVCR = 0.
The OVAD is cleared if OVCR = 0 even when the motor overcurrent error is generated.
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: DRV3211-Q1
21
DRV3211-Q1
SLVSBS4 – DECEMBER 2012
www.ti.com
PHASE AMPLIFIER (Sample and Hold Mode and Through Mode)
Description
The 3-channel amplifier module monitors the drain-source for high-side and low-side FETs. Two modes (selected
by the SPI) are provided: sample and hold mode, and through mode. Sample and hold is controlled by PSSx at
the external pins and PSCx connects the charging capacitor. Through mode is real-time detection and the
amplifier has x1–x4 gain control.
SH_MODE
High: Sample and Hold Mode
Low: Through Mode
VB
R2
CLAMP
open
VCC
VCC
R1
-
7:1
+
+
PH1T
PH2T
PH3T
VCC
-
-
+
CAL_MODE
PTV1
PTV2 PTVx = ¼ x (R2 / R1) x (PHxT-½ x VB) + 2.5 V
PTV3
Sample
and
Hold
PSC
CLAMP
VCC
-
R1
PSC1
PSC2
PSC3
+
3:1
R2
CAL_MODE
PRODUCT PREVIEW
VCC
-
PSS1
PSS2
PSS3
+
2.5 V
Figure 15. Sample and Hold Mode Block Diagram
SHORT_MODE
High: Sample and Hold Mode
Low: Through Mode
VB
R2
CLAMP
Short
VCC
7:1
VCC
R1
PH1T
PH2T
PH3T
SHORT_MODE
CLAMP
VCC
Open
PTVx = ¼*(R2 / R1)*(PHxT ± ½*VB) + 2.5 V
Disable
PTV1
PTV2
PTV3
VCC
R1
PSC1
PSC2
PSC3
3:1
R2
SHORT_MODE
VCC
PSS1
PSS2
PSS3
2.5 V
Figure 16. Through Mode Block Diagram
22
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: DRV3211-Q1
DRV3211-Q1
www.ti.com
SLVSBS4 – DECEMBER 2012
SH_MODE
High: Sample and Hold Mode
Low: Through Mode
VB
R2
CLAMP
Open/Short
VCC
Short/Open
2.5 V
7:1
PH1T
PH2T
PH3T
VCC
VCC
R1
PTVX = 2.5 V
PTV1
PTV2
PTV3
SHORT_MODE
PSC
CLAMP
VCC
R1
2.5 V
3:1
PSC1
PSC2
PSC3
SHORT_MODE
R2
VCC
PSS1
PSS2
PSS3
2.5 V
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: DRV3211-Q1
PRODUCT PREVIEW
Figure 17. Short Mode (Optional) Block Diagram
23
DRV3211-Q1
SLVSBS4 – DECEMBER 2012
www.ti.com
PHASE AMPLIFIER ELECTRICAL CHARACTERISTICS (1)
VB = 12 V, TA = –40°C to 125°C (unless otherwise specified)
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
PHASE AMPLIFIER
Vofs_SH
Output offset voltage, sample and hold
mode
VB = 5.3–18 V, Gain = 1
–50
–
50
mV
Vofs_TH
Output offset voltage, through mode
VB = 5.3–18 V, Gain = 1
–50
–
50
mV
Vin_cm
Common mode input range
VB = 5.3–18 V, Gain = 1–4
1.5
Vout_max
Maximum output voltage
VB = 5.3–18 V, Gain = 1–4
4.5
Vout_min
Minimum output voltage
VB = 5.3–18 V, Gain = 1–4
VB –
1.5
V
–
–
V
–
–
0.5
V
–
1
2
3
4
–
PRODUCT PREVIEW
Vgain (2)
Gain
Vout_SH0
Output voltage, sample and hold mode VB = 5.3–18 V, Gain = 1–4, PHxT = VB / 2
–
2.5
–
V
Vout_TH0
Output voltage, through mode
–
2.5
–
V
Vout_SH1
Output voltage, sample and hold mode VB = 12 V, Gain = 1, PHxT = 1.5 V
–
1.375
–
V
Vout_TH1
Output voltage, through mode
–
1.375
–
V
Vout_SH2
Output voltage, sample and hold mode VB = 12 V, Gain = 1, PHxT = 10.5 V
–
3.625
–
V
Vout_TH2
Output voltage, through mode
VB = 12 V, Gain = 1, PHxT = 10.5 V
–
3.625
–
V
STL_SHTR
Settling time (rise), sample and hold
mode PTVx ±1%
VB = 12 V, Gain = 1, PSC = 470 pF,
PTVx = 100 pF, PHxT = 1.5 V ≥ 10.5 V,
(PTVx = 1.375 V → 3.625 V), see Figure 20
1.5
3
µs
STL_THTR
Settling time (rise), through mode
PTVx ±1%
VB = 12 V, Gain = 1, PTVx = 100 pF,
PHxT = 1.5 V ≥ 10.5 V,
(PTVx = 1.375 V → 3.625 V), see Figure 21
1.5
3
µs
STL_SHTF
Settling time (fall), sample and hold
mode PTVx ±1%
VB = 12 V, Gain = 1, PSC = 470 pF,
PTVx = 100 pF, PHxT = 10.5 V ≥ 1.5 V,
(PTVx = 3.625 V → 1.375 V), see Figure 20
1.5
3
µs
STL_THTF
VB = 12 V, Gain = 1, PTVx = 100 pF,
Settling time (fall), through mode PTVx
PHxT = 10.5 V ≥ 1.5V,
±1%
(PTVx = 3.625 V → 1.375 V), see Figure 21
1.5
3
µs
SH Error
Voltage
Falling voltage
5
75
mV
(1)
(2)
VB = 5.3–18 V, Gain = 1–4 PHxT = VB / 2
VB = 12 V, Gain = 1, PHxT = 1.5 V
VB = 5.3–18 V, PSC = 470 pF, TH = 1 mS, see
Figure 19
No variation of the external components.
Vgain is an SPI setting
PHxT
PSSx
Sampling Time
PTVx
Figure 18. Sampling Timing Chart
24
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: DRV3211-Q1
DRV3211-Q1
www.ti.com
SLVSBS4 – DECEMBER 2012
TH
PSSx
PTVx
SH Error Voltage
Figure 19. Holding Timing Chart
PHxT
50%
50%
PRODUCT PREVIEW
PSSx
PTVx
STL_SHTRx_XXX
STL_SHTFx_XXX
Figure 20. Settling Time Timing Chart (Sample and Hold Mode)
PHxT
PTVx
STL_THTRx_XXX
STL_THTFx_XXX
Figure 21. Settling Time Timing Chart (Through Mode)
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: DRV3211-Q1
25
DRV3211-Q1
SLVSBS4 – DECEMBER 2012
www.ti.com
REGULATORS
Description
The regulator block offers a 5-V LDO and a 3.3-V LDO. The VCC LDO regulates VB down to 5 V with an external
PNP controlled by the regulator block. The 5-V LDO is supplied to the MCU and other components. The 5-V LDO
is protected against a short to GND fault, and the external resistors R1 and R2 set the undervoltage. The VDD
regulator regulates VB down to 3.3-V with an internal FET and a controller.
The regulators detect the overvoltage and undervoltage events of both supplies.
VB
Current
Limit
OC
Rsns
VCF
B
BG
+
AMP
VCC
B
-
PNP Tr
CVCC
PRODUCT PREVIEW
Trim
VCCT(VCC)
AMPG
VLVD
Supervisor
R1
Supervisor
R2
OV
UV
* Rsns = 0.2 V / ICLVCC
* VCCUV = 2.325 x {(R1+R2) / R2}
Figure 22. VCC Block Diagram
VB
BG
+
AMP
-
VDD
CVDD
AMPG
OV
UV
Supervisor
Figure 23. VDD Block Diagram
26
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: DRV3211-Q1
DRV3211-Q1
www.ti.com
SLVSBS4 – DECEMBER 2012
VCC AND VDD ELECTRICAL CHARACTERISTICS (1)
VB = 12 V, TA = –40°C to 125°C (unless otherwise specified)
PARAMETER
CONDITIONS
MIN
TYP
MAX
4.9
5
5.1
UNITS
VCC
VCC
Output voltage
IBVCC
Base current
VB = 5.3–18 V, Iload = 5–150 mA
1.5
hfePNP
DC current gain of external VCC
100
VLRVCC
Load regulation
CVCC
Load capacitance
RVCC
ESR of external capacitance
VCCUV
Undervoltage detection threshold
VCCUVHY
S
Undervoltage detection threshold
hysteresis
VCCOV
Overvoltage detection threshold
ICLVCC
Current limit
Rsns = 0.51 Ω
TVCC1
Rise time
VCC > UVVCC, CVCC = 22 µF
TVCC2
Rise time
VCC > UVVCC, CVCC = 100 µF
VDD
Output voltage
VB = 5.3–18 V, Iload = 0–2 mA
CVDD
Load capacitance
VDDUV
Undervoltage detection threshold
2.2
2.3
2.4
V
VDDOV
Overvoltage detection threshold
4.1
4.3
4.5
V
75
150
µs
VB = 5.3–18 V, Iload = 5–150 mA
–50
–
22
R1 = 7.5 kΩ, R2 = 10 kΩ,
VCCUV > 4 V
3.97
V
mA
4.07
50
mV
100
µF
300
mΩ
4.17
V
100
mV
6
6.5
7
300
400
550
mA
V
0.3
0.5
ms
1
1.5
ms
3.3
3.6
Tvdd
(1)
(2)
(2)
3
1
Rise time
VDD > VDDUV, CVDD = 1 µF
PRODUCT PREVIEW
VDD
V
µF
No variation of the external components
Specified by design
VB Monitor
Description
The block monitors VB overvoltage.
VB
+
VB_OV
BG
-
Figure 24. VB Monitor Block Diagram
VB MONITOR ELECTRICAL CHARACTERISTICS
VB = 12 V, TA = –40°C to 125°C (unless otherwise specified)
PARAMETER
CONDITIONS
MIN
TYP MAX UNITS
26.5
27.5
VB MONITOR
Vstop
Pre-driver stop VB voltage
28.5
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: DRV3211-Q1
V
27
DRV3211-Q1
SLVSBS4 – DECEMBER 2012
www.ti.com
THERMAL SHUTDOWN
Description
The device has temperature sensors that produce a pre-driver stop condition if the chip temperature exceeds
175°.
IPTAT
TSD
PRODUCT PREVIEW
Figure 25. Thermal Shutdown Block Diagram
THERMAL SHUTDOWN ELECTRICAL CHARACTERISTICS
VB = 12 V, TA = –40°C to 125°C (unless otherwise specified)
PARAMETER
CONDITIONS
MIN
TYP MAX UNITS
155
175
THERMAL SHUT DOWN
TSD (1)
(1)
Thermal shut down threshold
195
°C
Specified by design
OSCILLATOR
Description
Oscillator block generates two 10-MHZ clock signals. OSC1 is the main clock used for internal logic
synchronization and timing control. OSC2 is the secondary clock which is used to monitor the status of OSC1.
OSC1(OSC2)
VREF
Figure 26. Oscillator Block Diagram
28
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: DRV3211-Q1
DRV3211-Q1
www.ti.com
SLVSBS4 – DECEMBER 2012
OSCILLATOR ELECTRICAL CHARACTERISTICS
VB = 12 V, TA = –40°C to 125°C (unless otherwise specified)
PARAMETER
CONDITIONS
MIN
TYP MAX UNITS
OSCILLATOR
OSC
OSC frequency
9
10
11
MHz
I/O
PRODUCT PREVIEW
Figure 27. Input Buffer 1 Block Diagram
Figure 28. Output Buffer 1 Block Diagram
VDD
VCC
VCC
Level Shift
DOUT
EN
Figure 29. Output Buffer 2 Block Diagram
VCC
VDD
VCC
VCC
R_RES
RES
Level Shift
Figure 30. Output Buffer 3 Block Diagram
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: DRV3211-Q1
29
DRV3211-Q1
SLVSBS4 – DECEMBER 2012
www.ti.com
ELECTRICAL CHARACTERISTICS
VB = 12 V, TA = –40°C to 125°C (unless otherwise specified)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
INPUT BUFFER 1
VIH
Input threshold logic high
VIL
Input threshold logic low
0.7 × VCC
Ru
Input pullup resistance
50
Rd
Input pulldown resistance
50
V
0.3 × VCC
V
100
150
kΩ
100
150
kΩ
OUTPUT BUFFER 1 AND 2
VOH
Output level logic high
Isink = 2.5 mA
VOL
Output level logic low
Isource = 2.5 mA
0.9 × VCC
V
0.1 × VCC
V
4.5
kΩ
0.1 × VCC
V
OUTPUT BUFFER 3
R_RES
Pullup resistor
VOL
Output level logic low
1.5
3
Isource = 2 mA
ERROR DETECTION
Table 4. Error Detection
PRODUCT PREVIEW
ITEMS
SPI
PRE-DRIVER
FAULT SIGNAL
RES
VB – Overvoltage
–
STOP
L
H
CP – Overvoltage
–
STOP
L
H
CP – Undervoltage
Error Bit (CPLV)
–
L
H
VCC – Overvoltage
Error Bit (VCO)
–
L
H
VCC – Undervoltage
–
STOP
L
L
Error Bit (VCC)
–
H
H
VCC – Overcurrent
Motor – Overcurrent
Error Bit (OVAD)
STOP
H
H
VDD – Overvoltage
Error Bit (VDO)
–
L
H
VDD – Undervoltage
–
STOP
L
L
Thermal Shut Down
Error Bit (TD)
STOP
H
H
Watchdog
EEPROM Data Check
Clock Monitor
SPI
30
–
–
L
L
Error Bit (EEP)
–
L
H
–
–
L
L
Error Bit (SPI)
–
L
H
Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: DRV3211-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
21-Mar-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
DRV3211QPFPQ1
ACTIVE
Package Type Package Pins Package Qty
Drawing
HTQFP
PFP
80
96
Eco Plan
Lead/Ball Finish
(2)
Green (RoHS
& no Sb/Br)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
CU NIPDAU
Level-3-260C-168 HR
(4)
-40 to 125
DRV3211
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Only one of markings shown within the brackets will appear on the physical device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation
www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom
www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2013, Texas Instruments Incorporated