H CAT28C17A EE GEN FR ALO 16K-Bit CMOS PARALLEL EEPROM LE A D F R E ETM FEATURES ■ Fast Read Access Times: 200 ns ■ End of Write Detection: –DATA DATA Polling BSY Pin –RDY/BSY ■ Low Power CMOS Dissipation: –Active: 25 mA Max. –Standby: 100 µA Max. ■ Hardware Write Protection ■ Simple Write Operation: ■ CMOS and TTL Compatible I/O –On-Chip Address and Data Latches –Self-Timed Write Cycle with Auto-Clear ■ 10,000 Program/Erase Cycles ■ 10 Year Data Retention ■ Fast Write Cycle Time: 10ms Max ■ Commercial,Industrial and Automotive Temperature Ranges DESCRIPTION The CAT28C17A is a fast, low power, 5V-only CMOS parallel EEPROM organized as 2K x 8-bits. It requires a simple interface for in-system programming. On-chip address and data latches, self-timed write cycle with auto-clear and VCC power up/down write protection eliminate additional timing and protection hardware. DATA Polling and a RDY/BSY pin signal the start and end of the self-timed write cycle. Additionally, the CAT28C17A features hardware write protection. The CAT28C17A is manufactured using Catalyst’s advanced CMOS floating gate technology. It is designed to endure 10,000 program/erase cycles and has a data retention of 10 years. The device is available in JEDEC approved 28-pin DIP and SOIC or 32-pin PLCC packages. BLOCK DIAGRAM A4–A10 ADDR. BUFFER & LATCHES ROW DECODER VCC INADVERTENT WRITE PROTECTION HIGH VOLTAGE GENERATOR CE OE WE CONTROL LOGIC 2,048 x 8 EEPROM ARRAY I/O BUFFERS DATA POLLING & RDY/BUSY TIMER I/O0–I/O7 A0–A3 ADDR. BUFFER & LATCHES COLUMN DECODER RDY/BUSY © 2004 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. 1075, Rev. B CAT28C17A PIN CONFIGURATION A7 A6 RDY/BUSY NC 1 28 2 27 WE NC A8 A9 A7 3 4 26 NC A8 A4 1 28 2 3 27 VCC WE A5 4 5 26 25 24 A4 A3 6 7 23 22 NC OE A2 A1 A0 I/O0 8 9 10 11 21 20 19 A10 CE I/O7 I/O6 I/O1 I/O2 12 13 17 VSS 14 5 25 24 6 7 23 22 A1 A0 I/O0 8 9 10 11 21 20 19 18 I/O1 12 17 16 I/O5 I/O4 I/O2 13 15 I/O3 VSS 14 18 A6 A5 A3 A2 PLCC Package (N, G) VCC A9 NC OE A10 CE I/O7 NC VCC WE NC RDY/BUSY NC SOIC Package (J,W) (K, X) A7 NC RDY/BUSY DIP Package (P, L) 4 3 2 1 32 31 30 A6 5 29 A8 A5 6 7 28 27 A9 A3 A2 8 26 NC OE A1 10 11 A4 16 I/O6 I/O5 I/O4 A0 NC 15 I/O3 I/O0 9 TOP VIEW NC 25 24 23 A10 12 22 13 21 14 15 16 17 18 19 20 I/O7 I/O6 CE Pin Name I/O1 I/O2 VSS NC I/O3 I/O4 I/O5 PIN FUNCTIONS Function A0–A10 Address Inputs I/O0–I/O7 Data Inputs/Outputs RDY/BUSY Ready/BUSY Status CE Chip Enable OE Output Enable WE Write Enable VCC 5V Supply VSS Ground NC No Connect MODE SELECTION Mode CE WE OE Read L H Byte Write (WE Controlled) L Byte Write (CE Controlled) I/O Power L DOUT ACTIVE H DIN ACTIVE L H DIN ACTIVE Standby, and Write Inhibit H X X High-Z STANDBY Read and Write Inhibit X H H High-Z ACTIVE Test Max. Units Conditions Input/Output Capacitance 10 pF VI/O = 0V Input Capacitance 6 pF VIN = 0V CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V Symbol CI/O (1) CIN(1) Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. Doc. No. 1075, Rev. B 2 CAT28C17A ABSOLUTE MAXIMUM RATINGS* *COMMENT Temperature Under Bias ................. –55°C to +125°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Storage Temperature ....................... –65°C to +150°C Voltage on Any Pin with Respect to Ground(2) ........... –2.0V to +VCC + 2.0V VCC with Respect to Ground ............... –2.0V to +7.0V Package Power Dissipation Capability (Ta = 25°C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300°C Output Short Circuit Current(3) ........................ 100 mA RELIABILITY CHARACTERISTICS Symbol Parameter Min. Max. Units Test Method 10,000 Cycles/Byte MIL-STD-883, Test Method 1033 10 Years MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 NEND(1) Endurance TDR(1) Data Retention VZAP(1) ESD Susceptibility 2000 Volts ILTH(1)(4) Latch-Up 100 mA JEDEC Standard 17 D.C. OPERATING CHARACTERISTICS VCC = 5V ±10%, unless otherwise specified. Limits Symbol Parameter Min. Typ. Max. Units Test Conditions ICC VCC Current (Operating, TTL) 35 mA CE = OE = VIL, f = 1/tRC min, All I/O’s Open ICCC(5) VCC Current (Operating, CMOS) 25 mA CE = OE = VILC, f = 1/tRC min, All I/O’s Open ISB VCC Current (Standby, TTL) 1 mA CE = VIH, All I/O’s Open ISBC(6) VCC Current (Standby, CMOS) 100 µA CE = VIHC, All I/O’s Open ILI Input Leakage Current –10 10 µA VIN = GND to VCC ILO Output Leakage Current –10 10 µA VOUT = GND to VCC, CE = VIH VIH(6) High Level Input Voltage 2 VCC +0.3 V VIL(5) Low Level Input Voltage –0.3 0.8 V VOH High Level Output Voltage 2.4 VOL Low Level Output Voltage VWI Write Inhibit Voltage 0.4 3.0 V IOH = –400µA V IOL = 2.1mA V Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (3) Output shorted for no more than one second. No more than one output shorted at a time. (4) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC +1V. (5) VILC = –0.3V to +0.3V. (6) VIHC = VCC –0.3V to VCC +0.3V. 3 Doc. No. 1075, Rev. B CAT28C17A A.C. CHARACTERISTICS, Read Cycle VCC = 5V ±10%, unless otherwise specified. 28C17A-20 Symbol Parameter Min. Max. 200 Units tRC Read Cycle Time tCE CE Access Time 200 ns tAA Address Access Time 200 ns tOE OE Access Time 80 ns tLZ(1) CE Low to Active Output 0 ns tOLZ(1) OE Low to Active Output 0 ns tHZ(1)(2) CE High to High-Z Output 55 ns tOHZ(1)(2) OE High to High-Z Output 55 ns tOH(1) Output Hold from Address Change 0 Figure 1. A.C. Testing Input/Output Waveform(3) 2.4 V 2.0 V INPUT PULSE LEVELS REFERENCE POINTS 0.8 V 0.45 V Figure 2. A.C. Testing Load Circuit (example) 1.3V 1N914 3.3K DEVICE UNDER TEST OUT CL = 100 pF CL INCLUDES JIG CAPACITANCE Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer. (3) Input rise and fall times (10% and 90%) < 10 ns. Doc. No. 1075, Rev. B 4 ns ns CAT28C17A A.C. CHARACTERISTICS, Write Cycle VCC = 5V ±10%, unless otherwise specified. 28C17A-20 Symbol Parameter Min. Max. Units 10 ms tWC Write Cycle Time tAS Address Setup Time 10 ns tAH Address Hold Time 100 ns tCS CE Setup Time 0 ns tCH CE Hold Time 0 ns tCW(2) CE Pulse Time 150 ns tOES OE Setup Time 15 ns tOEH OE Hold Time 15 ns tWP(2) WE Pulse Width 150 ns tDS Data Setup Time 50 ns tDH Data Hold Time 10 ns tDL Data Latch Time 50 ns tINIT(1) Write Inhibit Period After Power-up 5 tDB Time to Device Busy 20 ms 80 ns Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) A write pulse of less than 20ns duration will not initiate a write cycle. 5 Doc. No. 1075, Rev. B CAT28C17A DEVICE OPERATION Read Ready/BUSY (RDY/BUSY) Data stored in the CAT28C17A is transferred to the data bus when WE is held high, and both OE and CE are held low. The data bus is set to a high impedance state when either CE or OE goes high. This 2-line control architecture can be used to eliminate bus contention in a system environment. The RDY/BUSY pin is an open drain output which indicates device status during programming. It is pulled low during the write cycle and released at the end of programming. Several devices may be OR-tied to the same RDY/BUSY line. Figure 3. Read Cycle tRC ADDRESS tCE CE tOE OE VIH tLZ WE tOHZ tOLZ HIGH-Z DATA OUT tHZ tOH DATA VALID DATA VALID tAA Figure 4. Byte Write Cycle [WE Controlled] tWC ADDRESS tAS tAH tCH tCS CE OE tOES tWP tOEH WE tDL RDY/BUSY tDB DATA OUT DATA IN HIGH-Z DATA VALID tDS Doc. No. 1075, Rev. B tDH 6 CAT28C17A Byte Write DATA Polling A write cycle is executed when both CE and WE are low, and OE is high. Write cycles can be initiated using either WE or CE, with the address input being latched on the falling edge of WE or CE, whichever occurs last. Data, conversely, is latched on the rising edge of WE or CE, whichever occurs first. Once initiated, a byte write cycle automatically erases the addressed byte and the new data is written within 10 ms. DATA polling is provided to indicate the completion of a byte write cycle. Once a byte write cycle is initiated, attempting to read the last byte written will output the complement of that data on I/O7 (I/O0–I/O6 are indeterminate) until the programming cycle is complete. Upon completion of the self-timed byte write cycle, all I/O’s will output true data during a read cycle. Figure 5. Byte Write Cycle [CE Controlled] tWC ADDRESS tAS tAH tDL tCW CE tOEH OE tCS tOES tCH WE RDY/BUSY tDB HIGH-Z DATA OUT DATA IN DATA VALID tDS tDH Figure 6. DATA Polling ADDRESS CE WE tOEH tOES tOE OE tWC I/O7 DIN = X DOUT = X 7 DOUT = X Doc. No. 1075, Rev. B CAT28C17A HARDWARE DATA PROTECTION teristics), provides a 5 to 20 ms delay before a write sequence, after VCC has reached 3.0V min. The following is a list of hardware data protection features that are incorporated into the CAT28C17A. (3) Write inhibit is activated by holding any one of OE low, CE high or WE high. (1) VCC sense provides for write protection when VCC falls below 3.0V min. (4) Noise pulses of less than 20 ns on the WE or CE inputs will not result in a write cycle. (2) A power on delay mechanism, tINIT (see AC charac- Doc. No. 1075, Rev. B 8 CAT28C17A ORDERING INFORMATION Prefix Device # CAT 28C17A Optional Company ID Product Number Suffix N Temperature Range Blank = Commercial (0˚C to +70˚C) I = Industrial (-40˚C to +85˚C) A = Automotive (-40˚ to +105˚C)* Package P: PDIP N: PLCC J: SOIC (JEDEC) K: SOIC (EIAJ) L: PDIP (Lead free, Halogen free) G: PLCC (Lead free, Halogen free) W: SOIC (JEDEC) (Lead free, Halogen free) X: SOIC (EIAJ) (Lead free, Halogen free) T -20 I Tape & Reel Speed 20: 200ns * -40˚C to +125˚C is available upon request Notes: (1) The device used in the above example is a CAT28C17ANI-20T (PLCC, Industrial temperature, 200 ns Access Time, Tape & Reel). 9 Doc. No. 1075, Rev. B REVISION HISTORY Date Revision Comments 3/29/2004 A Added Green packages in all areas 04/19/04 B Delete data sheet designation Update Block Diagram Update Ordering Information Update Revision History Update Rev Number Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP ™ AE2 ™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000. 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Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catsemi.com Publication #: Revison: Issue date: 1075 B 04/19/04