CC256x www.ti.com SWRS121D – JULY 2012 – REVISED JANUARY 2014 Bluetooth® and Dual-Mode Controller 1 Bluetooth and Dual-Mode Controller 1.1 Features 1234567 • Single-Chip Bluetooth Solution Integrating Bluetooth Basic Rate (BR)/Enhanced Data Rate (EDR)/Low Energy (LE) Features Fully Compliant With the Bluetooth 4.0 Specification Up to the HCI Layer • BR/EDR Features Include: – Up to 7 Active Devices – Scatternet: Up to 3 Piconets Simultaneously, 1 as Master and 2 as Slaves – Up to 2 SCO Links on the Same Piconet – Support for All Voice Air-Coding – Continuously Variable Slope Delta (CVSD), A-Law, μ-Law, and Transparent (Uncoded) • CC2560B/CC2564B Devices Provide an Assisted Mode for HFP 1.6 Wideband Speech (WBS) Profile or A2DP Profile to Reduce Host Processing and Power • LE Features Include: – Support of Up to 10 (CC2564 and CC2564B) Simultaneous Connections – Multiple Sniff Instances Tightly Coupled to Achieve Minimum Power Consumption – Independent Buffering for LE Allows Large Numbers of Multiple Connections Without Affecting BR/EDR Performance. – Built-In Coexistence and Prioritization Handling for BR/EDR and LE • Flexibility for Easy Stack Integration and Validation Into Various Microcontrollers, Such as MSP430™ and ARM® Cortex™-M3 and Cortex™-M4 MCUs • Highly Optimized for Low-Cost Designs: – Single-Ended 50-Ω RF Interface • • • • • – Package Footprint: 76 Pins, 0.6-mm Pitch, 8.10-mm x 8.10-mm mrQFN Best-in-Class Bluetooth (RF) Performance (TX Power, RX Sensitivity, Blocking) – Class 1.5 TX Power Up to +12 dBm – Internal Temperature Detection and Compensation to Ensure Minimal Variation in RF Performance Over Temperature, No External Calibration Required – Improved Adaptive Frequency Hopping (AFH) Algorithm With Minimum Adaptation Time – Provides Longer Range, Including 2x Range Over Other BLE-Only Solutions – ROM Spin to Enable Offload Host and Save Current With Assisted Audio (SBC Encode and Decode On Chip) Advanced Power Management for Extended Battery Life and Ease of Design: – On-Chip Power Management, Including Direct Connection to Battery – Low Power Consumption for Active, Standby, and Scan Bluetooth Modes – Shutdown and Sleep Modes to Minimize Power Consumption Physical Interface: – Fully Programmable Digital PCM-I2S Codec Interface CC256x Bluetooth Hardware Evaluation Tool: PC-Based Application to Evaluate RF Performance of the Device and Configure Service Pack Device Pin-to-Pin Compatible With Previous Devices or Modules 1 2 3 4 5 6 7 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. MSP430, DRP are trademarks of Texas Instruments. Cortex is a trademark of ARM Limited. ARM7TDMIE is a registered trademark of ARM Limited. ARM is a registered trademark of ARM Physical IP, Inc. iPod is a registered trademark of Apple, Inc. Bluetooth is a registered trademark of Bluetooth SIG, Inc. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012–2014, Texas Instruments Incorporated CC256x SWRS121D – JULY 2012 – REVISED JANUARY 2014 1.2 • • • www.ti.com Applications Mobile phone accessories Sports and fitness applications Wireless audio solutions 1.3 • • Remote controls Toys Description The TI CC256x device is a complete Bluetooth BR/EDR/LE HCI solution that reduces design effort and enables fast time to market. Based on TI’s seventh-generation Bluetooth core, the CC256x device provides a product-proven solution that supports Bluetooth 4.0 dual-mode (BR/EDR/LE) protocols. When coupled with a microcontroller unit (MCU), the HCI device provides best-in-class RF performance. TI’s power-management hardware and software algorithms provide significant power savings in all commonly used Bluetooth BR/EDR/LE modes of operation. With transmit power and receive sensitivity, this solution provides a best-in-class range of about 2x, compared to other BLE-only solutions. A royalty-free software Bluetooth stack available from TI is preintegrated with TI's MSP430 and ARM Cortex-M3 and Cortex-M4 MCUs. The stack is also available for made for iPod® (MFi) solutions and on other MCUs through TI's partner Stonestreet One (www.stonestreetone.com). Some of the profiles supported today include: serial port profile (SPP), advanced audio distribution profile (A2DP), human interface device (HID), and several BLE profiles (these profiles vary based on the supported MCU). In addition to software, this solution consists of multiple reference designs with a low BOM cost, including a new Bluetooth audio sink reference design for customers to create a variety of applications for low-end, low-power audio solutions. For more information on TI’s wireless platform solutions for Bluetooth, see TI's Wireless Connectivity Wiki (processors.wiki.ti.com/index.php/CC256x). Table 1-1 lists the CC256x family members. Table 1-1. CC256x Family Members Module Description Technology Supported BR/EDR CC2560A CC2564 (2) CC2560B CC2564B (1) (2) 2 (2) Bluetooth 4.0 (with EDR) √ Bluetooth 4.0 + BLE √ Bluetooth 4.0 + ANT √ Bluetooth 4.0 (with EDR) √ Bluetooth 4.0 + BLE √ Bluetooth 4.0 + ANT √ LE Assisted Modes Supported (1) ANT HFP 1.6 (WBS) A2DP √ √ √ √ √ √ √ √ √ √ The assisted modes (HFP 1.6 and A2DP) are not supported simultaneously. Furthermore, the assisted modes are not supported simultaneously with BLE or ANT. The device does not support simultaneous operation of LE and ANT. Bluetooth and Dual-Mode Controller Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback CC256x www.ti.com 1.4 SWRS121D – JULY 2012 – REVISED JANUARY 2014 Functional Block Diagram Figure 1-1 shows the device block diagram. CC256x 2.4-GHz band pass filter Coprocessor PCM/I2S (See Note) Modem arbitrator I/O interface DRP RF BR/EDR main processor UART HCI Power management Clock management Power Shutdown Fast clock Slow clock Note: The following technologies and assisted modes cannot be used simultaneously with the coprocessor: LE, ANT, assisted HFP 1.6 (WBS), and assisted A2DP. One and only one technology or assisted mode can be used at a time. SWRS121-001 Figure 1-1. Functional Block Diagram ............... 1.1 Features ............................................. 1.2 Applications .......................................... 1.3 Description ........................................... 1.4 Functional Block Diagram ........................... Revision History .............................................. 2 Bluetooth ................................................. 2.1 BR/EDR Features .................................... 2.2 LE Features .......................................... 1 Bluetooth and Dual-Mode Controller 4 ................................. General Device Requirements and Operation ..... Bluetooth BR/EDR RF Performance ............... Bluetooth LE RF Performance ..................... Interface Specifications ............................. Device Specifications 27 1 4.1 27 2 4.2 2 4.3 3 4.4 4 5 5 5 6 7 5 ................. ................................ Device Quantity and Direction ...................... Insertion of Device ................................. Tape Specification .................................. Reel Specification .................................. Packing Method .................................... Packing Specification ............................... 7.1 Package and Ordering Information 7.2 Empty Tape Portion ..................................... 6 Detailed Description .................................... 7 3.1 Pin Designation ...................................... 7 3.2 Terminal Functions .................................. 8 3.3 Device Power Supply ............................... 10 3.4 Clock Inputs ........................................ 12 3.5 Functional Blocks ................................... 15 7.3 2.4 Transport Layers 31 33 34 Reference Design and BOM for Power and Radio Connections ............................................ 37 mrQFN Mechanical Data ............................. 38 Chip Packaging and Ordering ...................... 40 Changes from CC2560A and CC2564 to CC2560B and CC2564B Devices .............................. 6 2.3 3 1 7.4 7.5 7.6 7.7 7.8 Contents Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback 40 41 41 41 42 42 42 43 3 CC256x SWRS121D – JULY 2012 – REVISED JANUARY 2014 www.ti.com Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (August 2013) to Revision D: (1) 4 Version Literature Number Date D SWRS121 January 2014 Notes See (1) . Sections impacted by changes between version C and version D: • Features: Changed support of simultaneous connections for CC2564 variant from 6 to 10. • Features: Added reference to ROM spin. • Features: Added reference to H5 protocol (2-wire) support. • Features: Added reference to pin-to-pin compatibility with previous devices and modules. • Features: Removed references to the following physical interfaces: HCI over H4 UART and HCI over H5 UART. • Description: Added reference to multiple reference designs capability, including Bluetooth audio sink. Contents Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback CC256x www.ti.com SWRS121D – JULY 2012 – REVISED JANUARY 2014 2 Bluetooth 2.1 BR/EDR Features The CC256x device fully complies with the Bluetooth 4.0 specification up to the HCI level (for the family members and technology supported, see Table 1-1): • Up to seven active devices • Scatternet: Up to 3 piconets simultaneously, 1 as master and 2 as slaves • Up to two synchronous connection oriented (SCO) links on the same piconet • Very fast AFH algorithm for asynchronous connection-oriented link (ACL) and extended SCO (eSCO) link • Supports typically 12-dBm TX power without an external power amplifier (PA), thus improving Bluetooth link robustness • Digital radio processor (DRP™) single-ended 50-Ω I/O for easy RF interfacing • Internal temperature detection and compensation to ensure minimal variation in RF performance over temperature • Flexible pulse-code modulation (PCM) and inter-IC sound (I2S) digital codec interface: – Full flexibility of data format (linear, A-Law, μ-Law) – Data width – Data order – Sampling – Slot positioning – Master and slave modes – High clock rates up to 15 MHz for slave mode (or 4.096 MHz for master mode) • Support for all voice air-coding – CVSD – A-Law – μ-Law – Transparent (uncoded) • The CC2560B and CC2564B devices provide an assisted mode for the HFP 1.6 (wide-band speech [WBS]) profile or A2DP profile to reduce host processing and power. 2.2 LE Features The device fully complies with the Bluetooth 4.0 specification up to the HCI level (for the family members and technology supported, see Table 1-1): • Supports all roles defined by the Bluetooth v4.0 specifications • Solution optimized for proximity and sports use cases • Supports up to 10 (CC2564 or CC2564B) simultaneous connections • Multiple sniff instances that are tightly coupled to achieve minimum power consumption • Independent buffering for LE, allowing large numbers of multiple connections without affecting BR/EDR performance. • Includes built-in coexistence and prioritization handling for BR/EDR and LE NOTE ANT and the assisted modes (HFP 1.6 and A2DP) are not available when BLE is enabled. Bluetooth Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback 5 CC256x SWRS121D – JULY 2012 – REVISED JANUARY 2014 2.3 www.ti.com Changes from CC2560A and CC2564 to CC2560B and CC2564B Devices The CC2560B and CC2564B devices include the following changes from the CC2560A and CC2564 devices: • From a hardware perspective, both devices are pin compatible. From a software perspective, each device requires a different service pack. When operating with the two devices using the supported Bluetooth stack, the devices are integrated seamlessly and use remains identical for each device. • Assisted mode for the HFP 1.6 (WBS) profile or the A2DP profile to enable more advanced features without using host processing or power • Support for the H5 protocol in the UART transport layer using 2-wire UART • Enable 10 Bluetooth LE connections 2.4 Transport Layers Figure 2-1 shows the Bluetooth transport layers. UART transport layer Host controller interface Data Control HCI data handler General modules: Event HCI command handler Data HCI vendorspecific Trace Link manager Timers Data Sleep Link controller RF SWRS121-016 Figure 2-1. Bluetooth Transport Layers 6 Bluetooth Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback CC256x www.ti.com SWRS121D – JULY 2012 – REVISED JANUARY 2014 3 Detailed Description 3.1 Pin Designation NC DIG_LDO_OUT A40 DIG_LDO_OUT B36 AUD_IN NC A39 B35 B33 B34 A38 VDD_IO AUD_OUT A37 NC AUD_CLK NC AUD_FSYNC A35 B32 A36 VDD_IO NC B30 B31 NC A34 NC HCI_TX A33 A32 B22 B6 DIG_LDO_OUT MLDO_OUT VSS_FREF B19 B9 A22 B10 MLDO_OUT NC NC A11 A10 NC NC A12 VSS_DCO DCO_LDO_OUT A13 NC NC NC B11 B12 A14 A15 NC NC B13 B14 A16 NC DIG_LDO_OUT NC A17 VDD_IO B15 B16 A18 NC NC A19 A20 NC VDD_IO ADC_PPA_LDO_OUT BT_RF A9 A21 CL1.5_LDO_OUT MLDO_OUT A8 B8 nSHUTD CL1.5_LDO_IN B7 B20 MLDO_OUT MLDO_IN A7 A23 XTALM/FREFM XTALP/FREFP A6 B21 VDD_IO NC B5 B17 NC B23 A24 NC A3 A5 NC NC DIG_LDO_OUT B4 A25 VDD_IO A2 A4 A26 NC SRAM_LDO_OUT B3 B24 VDD_IO VSS B29 B25 NC SLOW_CLK B2 A27 TX_DBG HCI_RX B26 A28 VDD_IO NC B1 A29 DIG_LDO_OUT VSS A1 B27 NC HCI_CTS B28 A30 B18 NC DIG_LDO_OUT HCI_RTS NC A31 NC Figure 3-1 shows the bottom view of the pin designations. SWRS121-002 Figure 3-1. Pin Designation (Bottom View) Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback 7 CC256x SWRS121D – JULY 2012 – REVISED JANUARY 2014 3.2 www.ti.com Terminal Functions Table 3-1 describes the terminal functions. Table 3-1. Device Pad Descriptions No. Pull at Reset Def. Dir. (1) I/O Type (2) HCI_RX A26 PU I 8 mA HCI universal asynchronous receiver/transmitter (UART) data receive HCI_TX A33 PU O 8 mA HCI UART data transmit HCI_RTS A32 PU O 8 mA HCI UART request-to-send The host is allowed to send data when HCI_RTS is low. HCI_CTS A29 PU I 8 mA HCI UART clear-to-send The CC256x device is allowed to send data when HCI_CTS is low. AUD_FSYNC A35 PD I/O 4 mA pulse-code modulation (PCM) frame-sync signal Fail-safe AUD_CLK B32 PD I/O HY, 4 mA PCM clock Fail-safe AUD_IN B34 PD I 4 mA PCM data input Fail-safe AUD_OUT B33 PD O 4 mA PCM data output Fail-safe 2 mA TI internal debug messages. TI recommends leaving an internal test point. Name Description I/O Signals TX_DBG B24 PU O Clock Signals SLOW_CLK A25 I 32.768-kHz clock in Fail-safe Fail-safe Fail-safe XTALP/FREFP B4 I Fast clock in analog (sine wave) Output terminal of fast-clock crystal XTALM/FREFM A4 I Fast clock in digital (square wave) Input terminal of fast-clock crystal Analog Signals BT_RF B8 nSHUTD A6 I/O PD Bluetooth RF I/O I Shutdown input (active low) A17, A34, A38, B18, B19, B21, B22, B25 I I/O power supply (1.8-V nominal) B5 I Main LDO input Connect directly to battery A5, A9, B2, B7 I/O CL1.5_LDO_IN B6 I Power amplifier (PA) LDO input Connect directly to battery CL1.5_LDO_OUT A7 O PA LDO output A2, A3, B15, B26, B27, B35, B36 O Digital LDO output QFN pin B26 or B27 must be shorted to other DIG_LDO_OUT pins on the PCB. SRAM_LDO_OUT B1 O SRAM LDO output DCO_LDO_OUT A12 O DCO LDO output Power and Ground Signals VDD_IO MLDO_IN MLDO_OUT DIG_LDO_OUT (1) (2) 8 Main LDO output (1.8-V nominal) I = input; O = output; I/O = bidirectional I/O Type: Digital I/O cells. HY = input hysteresis, current = typical output current Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback CC256x www.ti.com SWRS121D – JULY 2012 – REVISED JANUARY 2014 Table 3-1. Device Pad Descriptions (continued) Name ADC_PPA_LDO_OUT No. Pull at Reset Def. Dir. (1) I/O Type (2) Description A8 O ADC/PPA LDO output VSS A24, A28 I Ground VSS_DCO B11 I DCO ground VSS_FREF B3 I Fast clock ground No Connect NC A1 Not connected NC A10 Not connected NC A11 Not connected NC A14 Not connected NC A18 Not connected NC A19 Not connected NC A20 Not connected NC A21 Not connected NC A22 Not connected NC A23 Not connected NC A27 Not connected NC A30 Not connected NC A31 Not connected NC A40 Not connected NC B9 Not connected NC B10 Not connected NC B16 Not connected NC B17 Not connected NC B20 Not connected NC B23 Not connected NC A13 O TI internal use NC A15 O TI internal use NC A16 I/O TI internal use NC A36 I/O TI internal use NC A37 I/O TI internal use NC A39 I/O TI internal use NC B12 I TI internal use NC B13 I TI internal use NC B14 O TI internal use NC B29 O TI internal use NC B30 I/O TI internal use NC B31 I TI internal use NC B28 I TI internal use Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback 9 CC256x SWRS121D – JULY 2012 – REVISED JANUARY 2014 3.3 www.ti.com Device Power Supply The CC256x power-management hardware and software algorithms provide significant power savings, which is a critical parameter in an MCU-based system. The power-management module is optimized for drawing extremely low currents. 3.3.1 Power Sources The CC256x device requires two power sources: • VDD_IN: main power supply for the module • VDD_IO: power source for the 1.8-V I/O ring The HCI module includes several on-chip voltage regulators for increased noise immunity and can be connected directly to the battery. 3.3.2 Device Power-Up and Power-Down Sequencing The device includes the following power-up requirements (see Figure 3-2): • nSHUTD must be low. VDD_IN and VDD_IO are don't-care when nSHUTD is low. However, signals are not allowed on the I/O pins if I/O power is not supplied, because the I/Os are not fail-safe. Exceptions are SLOW_CLK_IN and AUD_xxx, which are fail-safe and can tolerate external voltages with no VDD_IO and VDD_IN. • VDD_IO and VDD_IN must be stable before releasing nSHUTD. • The fast clock must be stable within 20 ms of nSHUTD going high. • The slow clock must be stable within 2 ms of nSHUTD going high. The device indicates that the power-up sequence is complete by asserting RTS low, which occurs up to 100 ms after nSHUTD goes high. If RTS does not go low, the device is not powered up. In this case, ensure that the sequence and requirements are met. Shut down before VDD_IO removed 20 µs max nSHUTD VDD_IO VDD_IN 2 ms max SLOW CLOCK 20 ms max FAST CLOCK ± 100 ms HCI_RTS CC256x ready SWRS098-008 Figure 3-2. Power-Up and Power-Down Sequence 10 Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback CC256x www.ti.com 3.3.3 SWRS121D – JULY 2012 – REVISED JANUARY 2014 Power Supplies and Shutdown—Static States The nSHUTD signal puts the device in ultra-low power mode and performs an internal reset to the device. The rise time for nSHUTD must not exceed 20 μs; nSHUTD must be low for a minimum of 5 ms. To prevent conflicts with external signals, all I/O pins are set to the high-impedance (Hi-Z) state during shutdown and power up of the device. The internal pull resistors are enabled on each I/O pin, as described in Table 3-1. Table 3-2 describes the static operation states. Table 3-2. Power Modes VDD_IN (1) (1) VDD_IO (1) nSHUTD (1) PM_MODE Comments 1 None None Asserted Shut down I/O state is undefined. No I/O voltages are allowed on nonfailsafe pins. 2 None None Deasserted Not allowed I/O state is undefined. No I/O voltages are allowed on nonfailsafe pins. 3 None Present Asserted Shut down I/Os are defined as 3-state with internal pullup or pulldown enabled. 4 None Present Deasserted Not allowed I/O state is undefined. No I/O voltages are allowed on nonfailsafe pins. 5 Present None Asserted Shut down I/O state is undefined. No I/O voltages are allowed on nonfailsafe pins. 6 Present None Deasserted Not allowed I/O state is undefined. No I/O voltages are allowed on nonfailsafe pins. 7 Present Present Asserted Shut down I/Os are defined as 3-state with internal pullup or pulldown enabled. 8 Present Present Deasserted Active See Section 3.3.4, I/O States In Various Power Modes. The terms None or Asserted can imply any of the following conditions: directly pulled to ground or driven low, pulled to ground through a pulldown resistor, or left NC or floating (high-impedance output stage). 3.3.4 I/O States In Various Power Modes CAUTION Some device I/Os are not fail-safe (see Table 3-1). Fail-safe means that the pins do not draw current from an external voltage applied to the pin when I/O power is not supplied to the device. External voltages are not allowed on these I/O pins when the I/O supply voltage is not supplied because of possible damage to the device. Table 3-3 lists the I/O states in various power modes. Table 3-3. I/O States in Various Power Modes I/O Name Shut Down (1) Default Active (1) Deep Sleep (1) I/O State Pull I/O State Pull I/O State Pull HCI_RX Z PU I PU I PU HCI_TX Z PU O-H — O — HCI_RTS Z PU O-H — O — HCI_CTS Z PU I PU I PU AUD_CLK Z PD I PD I PD AUD_FSYNC Z PD I PD I PD AUD_IN Z PD I PD I PD AUD_OUT Z PD Z PD Z PD TX_DBG Z PU O — (1) I = input, O = output, Z = Hi-Z, — = no pull, PU = pullup, PD = pulldown, H = high, L = low Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback 11 CC256x SWRS121D – JULY 2012 – REVISED JANUARY 2014 3.4 www.ti.com Clock Inputs 3.4.1 Slow Clock An external source must supply the slow clock and connect to the SLOW_CLK_IN pin (for example, the host or external crystal oscillator). The source must be a digital signal in the range of 0 to 1.8 V. The accuracy of the slow clock frequency must be 32.768 kHz ±250 ppm for Bluetooth use (as specified in the Bluetooth specification). The external slow clock must be stable within 64 slow-clock cycles (2 ms) following the release of nSHUTD. 3.4.2 Fast Clock Using External Clock Source An external clock source is fed to an internal pulse-shaping cell to provide the fast-clock signal for the device. The device incorporates an internal, automatic clock-scheme detection mechanism that automatically detects the fast-clock scheme used and configures the FREF cell accordingly. This mechanism ensures that the electrical characteristics (loading) of the fast-clock input remain static regardless of the scheme used and eliminates any power-consumption penalty-versus-scheme used. This section describes the requirements for fast clock use. The frequency variation of the fast-clock source must not exceed ±20 ppm (as defined by the Bluetooth specification). The external clock can be AC- or DC-coupled, sine or square wave. 3.4.2.1 External FREF DC-Coupled Figure 3-3 and Figure 3-4 show the clock configuration when using a square wave, DC-coupled external source for the fast clock input. NOTE A shunt capacitor with a range of 10 nF must be added on the oscillator output to reject high harmonics and shape the signal to be close to a sinusoidal waveform. TI recommends using only a dedicated LDO to feed the oscillator. Do not use the same VIO for the oscillator and the CC256x device. FREFP CC256x FREFM SWRS121-009 Figure 3-3. Clock Configuration (Square Wave, DC-Coupled) 12 Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback CC256x www.ti.com SWRS121D – JULY 2012 – REVISED JANUARY 2014 VFref [V] 2.1 1.0 0.37 Vhigh_min Vlow_max –0.2 t clksqtd_wrs064 Figure 3-4. External Fast Clock (Square Wave, DC-Coupled) Figure 3-5 and Figure 3-6 show the clock configuration when using a sine wave, DC-coupled external source for the fast clock input. FREFP CC256x FREFM VDD_IO SWRS121-007 Figure 3-5. Clock Configuration (Sine Wave, DC-Coupled) VIN 1.6 V VPP = 0.4 – 1.6 Vp-p Vdc = 0.2 – 1.4 V 0 t SWRS097-023 Figure 3-6. External Fast Clock (Sine Wave, DC-Coupled) 3.4.2.2 External FREF Sine Wave, AC-Coupled Figure 3-7 and Figure 3-8 show the configuration when using a sine wave, AC-coupled external source for the fast-clock input. FREFP 68 pF CC256x FREFM VDD_IO SWRS121-008 Figure 3-7. Clock Configuration (Sine Wave, AC-Coupled) Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback 13 CC256x SWRS121D – JULY 2012 – REVISED JANUARY 2014 www.ti.com VIN [V] 1V VPP = 0.4 – 1.6 Vp-p 0.8 0.2 0 t –0.2 –0.8 SWRS097-022 Figure 3-8. External Fast Clock (Sine Wave, AC-Coupled) In cases where the input amplitude is greater than 1.6 Vp-p, the amplitude can be reduced to within limits. Using a small series capacitor forms a voltage divider with the internal input capacitance of approximately 2 pF to provide the required amplitude at the device input. 3.4.2.3 Fast Clock Using External Crystal The CC256x device incorporates an internal crystal oscillator buffer to support a crystal-based fast-clock scheme. The supported crystal frequency is 26 MHz. The frequency accuracy of the fast clock source must not exceed ±20 ppm (including the accuracy of the capacitors, as specified in the Bluetooth specification). Figure 3-9 shows the recommended fast-clock circuitry. CC256x C1 XTALM Oscillator buffer XTAL XTALP C2 SWRS098-003 Figure 3-9. Fast-Clock Crystal Circuit Table 3-4 lists component values for the fast-clock crystal circuit. Table 3-4. Fast-Clock Crystal Circuit Component Values (1) 14 FREQ (MHz) C1 (pF) (1) C2 (pF) (1) 26 12 12 To achieve the required accuracy, values for C1 and C2 must be taken from the crystal manufacturer's data sheet and layout considerations. Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback CC256x www.ti.com 3.5 SWRS121D – JULY 2012 – REVISED JANUARY 2014 Functional Blocks The CC256x architecture comprises a DRP™ and a point-to-multipoint baseband core. The architecture is based on a single-processor ARM7TDMIE® core. The device includes several on-chip peripherals to enable easy communication with a host system and the Bluetooth BR/EDR/LE core. 3.5.1 RF The device is the third generation of TI Bluetooth single-chip devices using DRP architecture. Modifications and new features added to the DRP further improve radio performance. Figure 3-10 shows the DRP block diagram. Transmitter path Amplitude TX digital data Digital ADPLL Phase DPA Receiver path RX digital data Demodulation ADC IFA Filter LNA SWRS092-005 Figure 3-10. DRP Block Diagram 3.5.1.1 Receiver The receiver uses near-zero-IF architecture to convert the RF signal to baseband data. The signal received from the external antenna is input to a single-ended low-noise amplifier (LNA) and passed to a mixer that downconverts the signal to IF, followed by a filter and amplifier. The signal is then quantized by a sigma-delta analog-to-digital converter (ADC) and further processed to reduce the interference level. The demodulator digitally downconverts the signal to zero-IF and recovers the data stream using an adaptive-decision mechanism. The demodulator includes EDR processing with: • State-of-the-art performance • A maximum-likelihood sequence estimator (MLSE) to improve the performance of basic-rate GFSK sensitivity • Adaptive equalization to enhance EDR modulation New features include: • LNA input range narrowed to increase blocking performance • Active spur cancellation to increase robustness to spurs Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback 15 CC256x SWRS121D – JULY 2012 – REVISED JANUARY 2014 3.5.1.2 www.ti.com Transmitter The transmitter is an all-digital, sigma-delta phase-locked loop (ADPLL) based with a digitally controlled oscillator (DCO) at 2.4 GHz as the RF frequency clock. The transmitter directly modulates the digital PLL. The power amplifier is also digitally controlled. The transmitter uses the polar-modulation technique. While the phase-modulated control word is fed to the ADPLL, the amplitude-modulated controlled word is fed to the class-E amplifier to generate a Bluetooth standard-compliant RF signal. New features include: • Improved TX output power • LMS algorithm to improve the differential error vector magnitude (DEVM) 3.5.2 Host Controller Interface The CC256x device incorporates one UART module dedicated to the HCI transport layer. The HCI interface transports commands, events, and ACL between the device and the host using HCI data packets. All members of the CC256x family support the H4 protocol (4-wire UART) with hardware flow control. The CC2560B and CC2564B devices also support the H5 protocol (3-wire UART) with software flow control. The CC256x device automatically detects the protocol when it receives the first command. The maximum baud rate of the UART module is 4 Mbps; however, the default baud rate after power up is set to 115.2 kbps. The baud rate can thereafter be changed with a VS command. The device responds with a command complete event (still at 115.2 kbps), after which the baud rate change occurs. The UART module includes the following features: • Receiver detection of break, idle, framing, FIFO overflow, and parity error conditions • Transmitter underflow detection • CTS and RTS hardware flow control (H4 protocol) • XON and XOFF software flow control (H5 protocol) Table 3-5 lists the UART module default settings. Table 3-5. UART Module Default Settings 3.5.2.1 Parameter Value Bit rate 115.2 kbps Data length 8 bits Stop bit 1 Parity None H4 Protocol—4-Wire UART Interface The H4 UART interface includes four signals: • TX • RX • CTS • RTS Flow control between the host and the CC256x device is bytewise by hardware. Figure 3-11 shows the H4 UART interface. 16 Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback CC256x www.ti.com SWRS121D – JULY 2012 – REVISED JANUARY 2014 Host_RX HCI_RX Host_TX HCI_TX Host_CTS HCI_CTS Host_RTS HCI_RTS Host CC256x SWRS121-003 Figure 3-11. H4 UART Interface When the UART RX buffer of the CC256x device passes the flow control threshold, it sets the HCI_RTS signal high to stop transmission from the host. When the HCI_CTS signal is set high, the CC256x device stops transmission on the interface. If HCI_CTS is set high while transmitting a byte, the device finishes transmitting the byte and stops the transmission. The H4 protocol device includes a mechanism that handles the transition between active mode and sleep mode. The protocol occurs through the CTS and RTS UART lines and is known as the enhanced HCI low level (eHCILL) power-management protocol. For more information on the H4 UART protocol, see Volume 4 Host Controller Interface, Part A UART Transport Layer of the Bluetooth Core Specifications (www.bluetooth.org/enus/specification/adoptedspecifications). 3.5.2.2 H5 Protocol—3-Wire UART Interface (CC2560B and CC2564B Devices) The H5 UART interface consists of three signals (see Figure 3-12): • TX • RX • GND Host_RX HCI_RX Host_TX HCI_TX Host CC256x GND GND SWRS121-015 Figure 3-12. H5 UART Interface The H5 protocol supports the following features: • Software flow control (XON/XOFF) • Power management using the software messages: – WAKEUP – WOKEN – SLEEP • CRC data integrity check For more information on the H5 UART protocol, see Volume 4 Host Controller Interface, Part D ThreeWire UART Transport Layer of the Bluetooth Core Specifications (www.bluetooth.org/enus/specification/adoptedspecifications). 3.5.3 Digital Codec Interface The codec interface is a fully programmable port to support seamless interfacing with different PCM and I2S codec devices. The interface includes the following features: • Two voice channels • Master and slave modes Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback 17 CC256x SWRS121D – JULY 2012 – REVISED JANUARY 2014 • • • • • 3.5.3.1 www.ti.com All voice coding schemes defined by the Bluetooth specification: linear, A-Law, and μ-Law Long and short frames Different data sizes, order, and positions High flexibility to support a variety of codecs Bus sharing: Data_Out is in Hi-Z state when the interface is not transmitting voice data. Hardware Interface The interface includes four signals: • Clock: configurable direction (input or output) • Frame_Sync and Word_Sync: configurable direction (input or output) • Data_In: input • Data_Out: output or 3-state The CC256x device can be the master of the interface when generating the Clock and Frame_Sync signals or the slave when receiving these two signals. For slave mode, clock input frequencies of up to 15 MHz are supported. At clock rates above 12 MHz, the maximum data burst size is 32 bits. For master mode, the device can generate any clock frequency between 64 kHz and 4.096 MHz. 3.5.3.2 I2S When the codec interface is configured to support the I2S protocol, these settings are recommended: • Bidirectional, full-duplex interface • Two time slots per frame: time slot-0 for the left channel audio data; and time slot-1 for the right channel audio data • Each time slot is configurable up to 40 serial clock cycles long, and the frame is configurable up to 80 serial clock cycles long. 3.5.3.3 Data Format The data format is fully configurable: • The data length can be from 8 to 320 bits in 1-bit increments when working with 2 channels, or up to 640 bits when working with 1 channel. The data length can be set independently for each channel. • The data position within a frame is also configurable within 1 clock (bit) resolution and can be set independently (relative to the edge of the Frame_Sync signal) for each channel. • The Data_In and Data_Out bit order can be configured independently. For example; Data_In can start with the most significant bit (MSB); Data_Out can start with the least significant bit (LSB). Each channel is separately configurable. The inverse bit order (that is, LSB first) is supported only for sample sizes up to 24 bits. • Data_In and Data_Out are not required to be the same length. • The Data_Out line is configured to Hi-Z output between data words. Data_Out can also be set for permanent Hi-Z, regardless of the data output. This configuration allows the device to be a bus slave in a multislave PCM environment. At power up, Data_Out is configured as Hi-Z. 3.5.3.4 Frame Idle Period The codec interface handles frame idle periods, in which the clock pauses and becomes 0 at the end of the frame, after all data are transferred. The device supports frame idle periods both as master and slave of the codec bus. When the device is the master of the interface, the frame idle period is configurable. There are two configurable parameters: 18 Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback CC256x www.ti.com • • SWRS121D – JULY 2012 – REVISED JANUARY 2014 Clk_Idle_Start: indicates the number of clock cycles from the beginning of the frame to the beginning of the idle period. After Clk_Idle_Start clock cycles, the clock becomes 0. Clk_Idle_End: indicates the time from the beginning of the frame to the end of the idle period. The time is given in multiples of clock periods. The delta between Clk_Idle_Start and Clk_Idle_End is the clock idle period. For example, for clock rate = 1 MHz, frame sync period = 10 kHz, Clk_Idle_Start = 60, Clk_Idle_End = 90. Between both Frame_Sync signals there are 70 clock cycles (instead of 100). The clock idle period starts 60 clock cycles after the beginning of the frame and lasts 90 – 60 = 30 clock cycles. Thus, the idle period ends 100 – 90 = 10 clock cycles before the end of the frame. The data transmission must end before the beginning of the idle period. Figure 3-13 shows the frame idle timing. Frame period Frame_Sync Data_In Data_Out Frame idle Clock Clk_Idle_Start Clk_Idle_End frmidle_swrs064 Figure 3-13. Frame Idle Period 3.5.3.5 Clock-Edge Operation The codec interface of the device can work on the rising or the falling edge of the clock and can sample the Frame_Sync signal and the data at inversed polarity. Figure 3-14 shows the operation of a falling-edge-clock type of codec. The codec is the master of the bus. The Frame_Sync signal is updated (by the codec) on the falling edge of the clock and is therefore sampled (by the device) on the next rising clock. The data from the codec is sampled (by the device) on the falling edge of the clock. PCM FSYNC PCM CLK D7 PCM DATA IN D6 D5 D4 D3 D2 D1 D0 CC256x SAMPLE TIME SWRS121-004 Figure 3-14. Negative Clock Edge Operation Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback 19 CC256x SWRS121D – JULY 2012 – REVISED JANUARY 2014 3.5.3.6 www.ti.com Two-Channel Bus Example Figure 3-15 shows a 2-channel bus in which the two channels have different word sizes and arbitrary positions in the bus frame. (FT stands for frame timer.) ... Clock FT 127 0 1 2 3 4 5 6 7 ... 42 43 44 8 9 127 0 Fsync MSB MSB LSB LSB Data_Out bit bit bit bit bit bit bit bit bit bit bit 0 1 2 3 4 5 6 7 8 9 10 bit bit bit bit bit bit bit bit 0 1 2 3 4 5 6 7 ... Data_In bit bit bit bit bit bit bit bit bit bit bit 0 1 2 3 4 5 6 7 8 9 10 bit bit bit bit bit bit bit bit 0 1 2 3 4 5 6 7 ... PCM_data_window CH1 data start FT = 0 CH1 data length = 11 CH2 data start FT = 43 CH2 data length = 8 Fsync period = 128 Fsync length = 1 twochpcm_swrs064 Figure 3-15. 2-Channel Bus Timing 3.5.3.7 Improved Algorithm For Lost Packets The device features an improved algorithm to improve voice quality when received voice data packets are lost. There are two options: • Repeat the last sample: possible only for sample sizes up to 24 bits. For sample sizes larger than 24 bits, the last byte is repeated. • Repeat a configurable sample of 8 to 24 bits (depending on the real sample size) to simulate silence (or anything else) in the bus. The configured sample is written in a specific register for each channel. The choice between those two options is configurable separately for each channel. 3.5.3.8 Bluetooth and Codec Clock Mismatch Handling In Bluetooth RX, the device receives RF voice packets and writes them to the codec interface. If the device receives data faster than the codec interface output allows, an overflow occurs. In this case, the Bluetooth has two possible modes of behavior: • Allow overflow: if overflow is allowed, the Bluetooth continues receiving data and overwrites any data not yet sent to the codec. • Do not allow overflow: if overflow is not allowed, RF voice packets received when the buffer is full are discarded. 3.5.4 Assisted Modes (CC2560B and CC2564B Devices) The CC256x devices contain an embedded coprocessor (see Figure 1-1) that can be used for multiple purposes. The CC2564 and CC2564B devices use the coprocessor to perform the LE or ANT functionality. The CC2560B and CC2564B devices use the coprocessor to execute the assisted HFP 1.6 (WBS) or assisted A2DP functions. Only one of these functions can be executed at a time because they all use the same resources (that is, the coprocessor; see Table 1-1 for the modes of operation supported by each device). 20 Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback CC256x www.ti.com SWRS121D – JULY 2012 – REVISED JANUARY 2014 This section describes the assisted HFP 1.6 (WBS) and assisted A2DP modes of operation in the CC2560B and CC2564B devices. These modes of operation minimize host processing and power by taking advantage of the device coprocessor to perform the voice and audio SBC processing required in HFP 1.6 (WBS) and A2DP profiles. This section also compares the architecture of the assisted modes with the common implementation of the HFP 1.6 and A2DP profiles. The assisted HFP 1.6 (WBS) and assisted A2DP modes of operation comply fully with the HFP 1.6 and A2DP Bluetooth specifications. For more information on these profiles, see the corresponding Bluetooth Profile Specification (www.bluetooth.org/en-us/specification/adopted-specifications). 3.5.4.1 Assisted HFP 1.6 (WBS) The HFP 1.6 Profile Specification adds the requirement for WBS support. The WBS feature allows twice the voice quality versus legacy voice coding schemes at the same air bandwidth (64 kbps). This feature is achieved using a voice sampling rate of 16 kHz, a modified subband coding (mSBC) scheme, and a packet loss concealment (PLC) algorithm. The mSBC scheme is a modified version of the mandatory audio coding scheme used in the A2DP profile with the parameters listed in Table 3-6. Table 3-6. mSBC Parameters Parameter Value Channel mode Mono Sampling rate 16 kHz Allocation method Loudness Subbands 8 Block length 15 Bitpool 26 The assisted HFP 1.6 mode of operation implements this WBS feature on the embedded coprocessor. That is, the mSBC voice coding scheme and the PLC algorithm are executed in the coprocessor rather than in the host, thus minimizing host processing and power. One WBS connection at a time is supported and WBS and NBS connections cannot be used simultaneously in this mode of operation. Figure 3-16 shows the architecture comparison between the common implementation of the HFP 1.6 profile and the assisted HFP 1.6 solution. Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback 21 CC256x SWRS121D – JULY 2012 – REVISED JANUARY 2014 www.ti.com Figure 3-16. HFP 1.6 Architecture Versus Assisted HFP 1.6 Architecture For detailed information on the HFP 1.6 profile, see the Hands-Free Profile 1.6 Specification (www.bluetooth.org/en-us/specification/adopted-specifications). 3.5.4.2 Assisted A2DP The A2DP enables wireless transmission of high-quality mono or stereo audio between two devices. A2DP defines two roles: • A2DP source is the transmitter of the audio stream. • A2DP sink is the receiver of the audio stream. A typical use case streams music from a tablet, phone, or PC (the A2DP source) to headphones or speakers (the A2DP sink). This section describes the architecture of these roles and compares them with the corresponding assisted-A2DP architecture. To use the air bandwidth efficiently, the audio data must be compressed in a proper format. The A2DP mandates support of the SBC scheme. Other audio coding algorithms can be used; however, both Bluetooth devices must support the same coding scheme. SBC is the only coding scheme spread out in all A2DP Bluetooth devices, and thus the only coding scheme supported in the assisted A2DP modes. Table 3-7 lists the recommended parameters for the SBC scheme in the assisted A2DP modes. 22 Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback CC256x www.ti.com SWRS121D – JULY 2012 – REVISED JANUARY 2014 Table 3-7. Recommended Parameters for the SBC Scheme in Assisted A2DP Modes SBC Encoder Settings (1) Mid Quality High Quality Mono Joint Stereo Mono Joint Stereo Sampling frequency (kHz) 44.1 48 44.1 48 44.1 48 44.1 48 Bitpool value 19 18 35 33 31 29 53 51 Resulting frame length (bytes) 46 44 83 79 70 66 119 115 Resulting bit rate (Kbps) 127 132 229 237 193 198 328 345 (1) Other settings: Block length = 16; allocation method = loudness; subbands = 8. The SBC scheme supports a wide variety of configurations to adjust the audio quality. Table 3-8 through Table 3-15 list the supported SBC capabilities in the assisted A2DP modes. Table 3-8. Channel Modes Channel Mode Status Mono Supported Stereo Supported Joint stereo Supported Table 3-9. Sampling Frequency Sampling Frequency (kHz) Status 16 Supported 44.1 Supported 48 Supported Table 3-10. Block Length Block Length Status 16 Supported Table 3-11. Subbands Subbands Status 8 Supported Table 3-12. Allocation Method Allocation Method Status Loudness Supported Table 3-13. Bitpool Values Bitpool Range Status Assisted A2DP sink: TBD Supported Assisted A2DP source: 2–57 Supported Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback 23 CC256x SWRS121D – JULY 2012 – REVISED JANUARY 2014 www.ti.com Table 3-14. L2CAP MTU Size L2CAP MTU Size (Bytes) Status Assisted A2DP sink: 260–800 Supported Assisted A2DP source: 260–1021 Supported Table 3-15. Miscellaneous Parameters Item Value Status A2DP content protection Protected Not supported AVDTP service Basic type Supported L2CAP mode Basic mode Supported L2CAP flush Nonflushable Supported For detailed information on the A2DP profile, see the A2DP Profile Specification (www.bluetooth.org/enus/ specification/adopted-specifications). 3.5.4.2.1 Assisted A2DP Sink The A2DP sink role is the receiver of the audio stream in an A2DP Bluetooth connection. In this role, the A2DP layer and its underlying layers are responsible for link management and data decoding. To handle these tasks, two logic transports are defined: • Control and signaling logic transport • Data packet logic transport The assisted A2DP takes advantage of this modularity to handle the data packet logic transport in the CC256x device by implementing a light L2CAP layer (L-L2CAP) and light AVDTP layer (L-AVDTP) to defragment the packets. Then the assisted A2DP performs the SBC decoding on-chip to deliver raw audio data through the CC256x PCM–I2S interface. Figure 3-17 shows the comparison between a common A2DP sink architecture and the assisted A2DP sink architecture. 24 Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback CC256x www.ti.com SWRS121D – JULY 2012 – REVISED JANUARY 2014 A2DP Sink Architecture Assisted A2DP Sink Architecture Host Processor Host Processor Bluetooth Stack PCM / I2S A2DP Profile Bluetooth Stack 44.1 KHz 48 KHz Audio CODEC 16 bits A2DP Profile SBC AVDTP AVDTP Data Control Control L2CAP L2CAP HCI HCI Control Data Control HCI Data HCI CC256x Bluetooth Controller CC256x Bluetooth Controller PCM / I2S 44.1 KHz 48 KHz 16 bits Audio CODEC SBC L-AVDTP L-L2CAP Figure 3-17. A2DP Sink Architecture Versus Assisted A2DP Sink Architecture For more information on the A2DP sink role, see the A2DP Profile Specification (www.bluetooth.org/enus/ specification/adopted-specifications). 3.5.4.2.2 Assisted A2DP Source The role of the A2DP source is to transmit the audio stream in an A2DP Bluetooth connection. In this role, the A2DP layer and its underlying layers are responsible for link management and data encoding. To handle these tasks, two logic transports are defined: • Control and signaling logic transport • Data packet logic transport The assisted A2DP takes advantage of this modularity to handle the data packet logic transport in the CC256x device. First, the assisted A2DP encodes the raw data from the CC256x PCM–I2S interface using an on-chip SBC encoder. The assisted A2DP then implements an L-L2CAP layer and an L-AVDTP layer to fragment and packetize the encoded audio data. Figure 3-18 shows the comparison between a common A2DP source architecture and the assisted A2DP source architecture. Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback 25 CC256x SWRS121D – JULY 2012 – REVISED JANUARY 2014 www.ti.com A2DP Source Architecture Assisted A2DP Source Architecture Host Processor Host Processor Bluetooth Stack PCM / I2S A2DP Profile Bluetooth Stack 44.1 KHz 48 KHz Audio CODEC 16 bits A2DP Profile SBC AVDTP AVDTP Data Control Control L2CAP L2CAP HCI HCI Control Data Control HCI Data HCI CC256x Bluetooth Controller CC256x Bluetooth Controller PCM / I2S 44.1 KHz 48 KHz 16 bits Audio CODEC SBC L-AVDTP L-L2CAP Figure 3-18. A2DP Source Architecture Versus Assisted A2DP Source Architecture For more information on the A2DP source role, see (www.bluetooth.org/enus/ specification/adopted-specifications). 26 Detailed Description the A2DP Profile Specification Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback CC256x www.ti.com SWRS121D – JULY 2012 – REVISED JANUARY 2014 4 Device Specifications Unless otherwise indicated, all measurements are taken at the device pins of the TI test evaluation board (EVB). All specifications are over process, voltage, and temperature, unless otherwise indicated. 4.1 General Device Requirements and Operation 4.1.1 Absolute Maximum Ratings Over operating free-air temperature range (unless otherwise indicated) NOTE Unless otherwise indicated, all parameters are measured as follows: VDD_IN = 3.6 V, VDD_IO = 1.8 V See (1) Value Unit –0.5 to 4.8 V (2) Ratings over operating free-air temperature range VDD_IN Supply voltage range VDD_IO –0.5 to 2.145 V Input voltage to analog pins (3) –0.5 to 2.1 V Input voltage to all other pins –0.5 to (VDD_IO + 0.5) V –40 to 85 °C Operating ambient temperature range (4) Storage temperature range –55 to 125 °C 10 dBm Bluetooth RF inputs ESD stress voltage (5) (1) (2) (3) (4) (5) (6) (7) Human body model (HBM) (6) Charged device model (CDM) (7) Device 500 Device 250 V Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Maximum allowed depends on accumulated time at that voltage: VDD_IN is defined in Section 5, Reference Design for Power and Radio Connections. Analog pins: BT_RF, XTALP, and XTALM The reference design supports a temperature range of –20°C to 70°C because of the operating conditions of the crystal. ESD measures device sensitivity and immunity to damage caused by electrostatic discharges into the device. The level listed is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process, and manufacturing with less than 500-V HBM is possible, if necessary precautions are taken. Pins listed as 1000 V can actually have higher performance. The level listed is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process, and manufacturing with less than 250-V CDM is possible, if necessary precautions are taken. Pins listed as 250 V can actually have higher performance. 4.1.2 Recommended Operating Conditions Sym Min Max Unit Power supply voltage Rating Condition VDD_IN 2.2 4.8 V I/O power supply voltage VDD_IO 1.62 1.92 V V High-level input voltage Default VIH 0.65 x VDD_IO VDD_IO Low-level input voltage Default VIL 0 0.35 x VDD_IO V tr and tf 1 10 ns 1 2.5 ns 400 mV 85 °C I/O input rise and all times,10% to 90% — asynchronous mode I/O input rise and fall times, 10% to 90% — synchronous mode (PCM) Voltage dips on VDD_IN (VBAT) duration = 577 μs to 2.31 ms, period = 4.6 ms Maximum ambient operating temperature (1) (1) (2) (2) –40 The device can be reliably operated for 7 years at Tambient of 85°C, assuming 25% active mode and 75% sleep mode (15,400 cumulative active power-on hours). A crystal-based solution is limited by the temperature range required of the crystal to meet 20 ppm. Device Specifications Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback 27 CC256x SWRS121D – JULY 2012 – REVISED JANUARY 2014 4.1.3 www.ti.com Current Consumption 4.1.3.1 Static Current Consumption Typ Max Unit Shutdown mode (1) Operational Mode Min 1 7 µA Deep sleep mode (2) 40 105 µA Idle mode 4 mA Total I/O current consumption in active mode 1 mA Continuous transmission—GFSK (3) 77 mA Continuous transmission—EDR (4) (5) 82.5 mA (1) (2) (3) (4) (5) VBAT + VIO + VSHUTDOWN VBAT + VIO At maximum output power (10 dBm) At maximum output power (8 dBm) Both π/4 DQPSK and 8DPSK 4.1.3.2 Dynamic Current Consumption 4.1.3.2.1 Current Consumption for Different Bluetooth BR/EDR Scenarios Conditions: VDD_IN = 3.6 V, 25°C, 26-MHz XTAL, nominal unit, 4-dBm output power Operational Mode Master and Slave Average Current Unit Synchronous connection oriented (SCO) link HV3 Master and slave 13.7 mA Extended SCO (eSCO) link EV3 64 kbps, no retransmission Master and slave 13.2 mA eSCO link 2-EV3 64 kbps, no retransmission Master and slave 10 mA GFSK full throughput: TX = DH1, RX = DH5 Master and slave 40.5 mA EDR full throughput: TX = 2-DH1, RX = 2-DH5 Master and slave 41.2 mA EDR full throughput: TX = 3-DH1, RX = 3-DH5 Master and slave 41.2 mA Sniff, one attempt, 1.28 seconds Master and slave 250 μA Page or inquiry scan 1.28 seconds, 11.25 ms Master and slave 400 μA Page (1.28 seconds) and inquiry (2.56 seconds) scans, 11.25 ms Master and slave 500 μA Conditions: VDD_IN = 3.6 V, 25°C, 26-MHz fast clock, nominal unit, 4-dBm output power Master and Slave Average Current Unit Synchronous connection oriented (SCO) link HV3 Operational Mode Master and slave 12 mA Extended SCO (eSCO) link EV3 64 kbps, no retransmission Master and slave 11.5 mA eSCO link 2-EV3 64 kbps, no retransmission Master and slave 8.3 mA GFSK full throughput: TX = DH1, RX = DH5 Master and slave 38.5 mA EDR full throughput: TX = 2-DH1, RX = 2-DH5 Master and slave 39.2 mA EDR full throughput: TX = 3-DH1, RX = 3-DH5 Master and slave 39.2 mA Sniff, one attempt, 1.28 seconds Master and slave 76 and 100 μA Page or inquiry scan 1.28 seconds, 11.25 ms Master and slave 300 μA Page (1.28 seconds) and inquiry (2.56 seconds) scans, 11.25 ms Master and slave 430 μA 28 Device Specifications Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback CC256x www.ti.com SWRS121D – JULY 2012 – REVISED JANUARY 2014 4.1.3.2.2 Current Consumption for Different LE Scenarios Conditions: VDD_IN = 3.6 V, 25°C, 26-MHz fast clock, nominal unit, 10-dBm output power 4.1.4 Mode Description Average Current Unit Advertising, nonconnectable Advertising in all three channels 1.28-seconds advertising interval 15 bytes advertise data 104 µA Advertising, discoverable Advertising in all three channels 1.28-seconds advertising interval 15 bytes advertise data 121 µA Scanning Listening to a single frequency per window 1.28-seconds scan interval 11.25-ms scan window 302 µA Connected (master role) 500-ms connection interval 0-ms slave connection latency Empty TX and RX LL packets 169 µA General Electrical Characteristics Rating Condition High-level output voltage, VOH Low-level output voltage, VOL I/O input impedance Output rise and fall times, 10% to 90% (digital pins) I/O pull currents PCM-I2S bus, TX_DBG All others 4.1.5 Min Max At 2, 4, 8 mA 0.8 x VDD_IO VDD_IO At 0.1 mA VDD_IO – 0.2 VDD_IO At 2, 4, 8 mA 0 0.2 x VDD_IO At 0.1 mA 0 0.2 Resistance 1 Unit V V MΩ Capacitance 5 pF CL = 20 pF 10 ns PU typ = 6.5 3.5 9.7 PD typ = 27 9.5 55 PU typ = 100 50 300 PD typ = 100 50 360 μA μA nSHUTD Requirements Sym Min Max Unit Operation mode level (1) Parameter VIH 1.42 1.98 V Shutdown mode level (1) VIL 0 0.4 Minimum time for nSHUT_DOWN low to reset the device Rise and fall times (1) 5 tr and tf V ms 20 μs An internal pulldown retains shut-down mode when no external signal is applied to this pin. Device Specifications Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback 29 CC256x SWRS121D – JULY 2012 – REVISED JANUARY 2014 4.1.6 www.ti.com Slow Clock Requirements Characteristics Condition Sym Min Typ Input slow clock frequency Input slow clock accuracy (Initial + temp + aging) ±250 ANT ±50 tr and tf 200 Frequency input duty cycle 15% Square wave, DC-coupled 50% 85% VDD_IO V peak VIL 0 0.35 × VDD_IO V peak 1 MΩ 5 pF External Fast Clock Crystal Requirements and Operation Characteristics Condition Sym Supported crystal frequencies Min fin Typ Iosc = 0.5 mA 650 940 490 710 Unit MHz ±20 26 MHz, external capacitance = 8 pF Crystal oscillator negative resistance Max 26 Frequency accuracy (Initial + temperature + aging) ppm Ω 26 MHz, external capacitance = 20 pF Iosc = 2.2 mA Fast Clock Source Requirements (–40°C to +85°C) Characteristics Condition Sym Supported frequencies Initial + temp + aging Fast clock input voltage limits Square wave, DC-coupled Max 26 Unit MHz ±20 ppm –0.2 0.37 V VIH 1.0 2.1 V Sine wave, AC-coupled 0.4 1.6 Vp-p Sine wave, DC-coupled 0.4 1.6 Vp-p 0 1.6 V Square wave, DC-coupled Duty cycle Phase noise for 26 MHz Typ VIL Sine wave input limits, DC-coupled Fast clock input rise time (as % of clock period) Min FREF Reference frequency accuracy 30 ns 0.65 × VDD_IO Input capacitance 4.1.8 ppm VIH Input impedance 4.1.7 Unit Hz Bluetooth Input transition time tr and tf (10% to 90%) Slow clock input voltage limits Max 32768 10% 35% 50% 65% @ offset = 1 kHz –123.4 @ offset = 10 kHz –133.4 @ offset = 100 kHz –138.4 Device Specifications dBc/Hz Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback CC256x www.ti.com 4.2 SWRS121D – JULY 2012 – REVISED JANUARY 2014 Bluetooth BR/EDR RF Performance All parameters in this section that are fast-clock dependent are verified using a 26-MHz XTAL under a temperature range from –20°C to 70°C and an RF load of 50 Ω at the BT_RF port. 4.2.1 Bluetooth Receiver—In-Band Signals Characteristics Condition Min Operation frequency range Typ 2402 Bluetooth Specification 1 Input impedance 50 MHz MHz Ω GFSK, BER = 0.1% –91.5 –95 –70 Pi/4-DQPSK, BER = 0.01% –90.5 –94.5 –70 –81 –87.5 –70 1E–7 1E–5 8DPSK, BER = 0.01% BER error floor at sensitivity + 10 dB, dirty TX off Pi/4-DQPSK 1E–6 8DPSK 1E–6 1E–5 Maximum usable input power GFSK, BER = 0.1% –5 –20 Pi/4-DQPSK, BER = 0.1% –10 8DPSK, BER = 0.1% –10 Intermodulation characteristics Level of interferers (for n = 3, 4, and 5) –36 C/I performance (2) GFSK, co-channel EDR, co-channel Image = –1 MHz EDR, adjacent ±1 MHz, (image) EDR, adjacent, +2 MHz Pi/4-DQPSK 9.5 11 13 8DPSK 16.5 20 21 –10 –5 0 Pi/4-DQPSK –10 –5 0 8DPSK –5 –1 5 –38 –35 –30 Pi/4-DQPSK –38 –35 –30 8DPSK –38 –30 –25 –28 –20 –20 Pi/4-DQPSK –28 –20 –20 8DPSK –22 –13 –13 –45 –43 –40 Pi/4-DQPSK –45 –43 –40 8DPSK –44 –36 –33 GFSK, adjacent ≥ |±3| MHz EDR, adjacent ≥ |±3| MHz RF return loss (2) dB Frf = (received RF – 0.6 MHz) –63 dB –58 dBm Sensitivity degradation up to 3 dB may occur for minimum and typical values where the Bluetooth frequency is a harmonic of the fast clock. Numbers show ratio of desired signal to interfering signal. Smaller numbers indicate better C/I performance. 4.2.2 Bluetooth Receiver—General Blocking Characteristics Condition Blocking performance over full range, according to Bluetooth specification (1) (1) dBm –10 RX mode LO leakage (1) –39 11 GFSK, adjacent –2 MHz EDR, adjacent –2 MHz –30 10 GFSK, adjacent +2 MHz dBm dBm 8 GFSK, adjacent ±1 MHz Unit 2480 Channel spacing Sensitivity, dirty TX on (1) Max Min Typ 30 to 2000 MHz –6 2000 to 2399 MHz –6 2484 to 3000 MHz –6 3 to 12.75 GHz –6 Unit dBm Exceptions are taken out of the total 24 allowed in the Bluetooth specification. Device Specifications Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback 31 CC256x SWRS121D – JULY 2012 – REVISED JANUARY 2014 4.2.3 www.ti.com Bluetooth Transmitter—GFSK Characteristics Min Typ Maximum RF output power (1) 10 12 Power variation over Bluetooth band –1 Gain control range Max Bluetooth Specification dBm 1 dB 30 Power control step 5 8 2 to 8 Adjacent channel power |M–N| = 2 –45 –39 ≤ –20 Adjacent channel power |M–N| > 2 –50 –42 ≤ –40 (1) 2 Unit dB dBm To modify maximum output power, use an HCI VS command. 4.2.4 Bluetooth Transmitter—EDR Characteristics Maximum RF output power (1) Min Typ Pi/4-DQPSK 6 8 8DPSK 6 8 Max –2 1 Power variation over Bluetooth band –1 1 –4 to +1 dB 30 Power control step 2 Unit dBm Relative power Gain control range Bluetooth Specification 5 8 2 to 8 –36 –30 ≤ –26 dBc Adjacent channel power |M–N| = 2 (2) –30 –23 ≤ –20 dBm Adjacent channel power |M–N| > 2 (2) –42 –40 ≤ –40 dBm Adjacent channel power |M–N| = 1 (1) (2) To modify maximum output power, use an HCI VS command. Assumes 3-dB insertion loss from Bluetooth RF ball to antenna 4.2.5 Bluetooth Modulation—GFSK Characteristics Condition –20 dB bandwidth GFSK Modulation characteristics Δf1avg Δf2max ≥ limit for at least 99.9% of all Δf2max Absolute carrier frequency drift Sym Min Mod data = 4 1s, 4 0s: 111100001111... F1 avg 150 Mod data = 1010101... F2 max 32 Max Bluetooth Specification Unit 925 165 995 ≤ 1000 kHz 170 140 to 175 kHz 115 Δf2avg, Δf1avg 85 DH1 –25 DH3 and DH5 –35 f0 – fTX –75 Device Specifications 130 > 115 kHz Drift rate Initial carrier frequency tolerance Typ 88 > 80 % 25 < ±25 kHz 35 < ±40 15 < 20 kHz/ 50 μs 75 < ±75 kHz Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback CC256x www.ti.com 4.2.6 SWRS121D – JULY 2012 – REVISED JANUARY 2014 Bluetooth Modulation—EDR Characteristics Max Bluetooth Specification Unit Carrier frequency stability ±5 ≤ 10 kHz Initial carrier frequency tolerance ±75 ±75 kHz Rms DEVM (1) 99% DEVM (1) Peak DEVM (1) (1) Condition Min Typ Pi/4-DQPSK 6 15 20 8DPSK 6 13 13 Pi/4-DQPSK 30 30 8DPSK 20 20 Pi/4-DQPSK 14 30 35 8DPSK 16 25 25 Max performance refers to maximum TX power. 4.2.7 Bluetooth Transmitter—Out-of-Band and Spurious Emissions Characteristics Condition Second harmonic (1) Third harmonic (1) Measured at maximum output power Fourth harmonics (1) (1) % Typ Max Unit –14 –2 dBm –10 –6 dBm –19 –11 dBm Meets FCC and ETSI requirements with external filter shown in Figure 5-1 4.3 Bluetooth LE RF Performance All parameters in this section that are fast-clock dependent are verified using a 26-MHz XTAL under a temperature range from –20°C to 70°C and an RF load of 50 Ω at the BT_RF port. 4.3.1 BLE Receiver—In-Band Signals Characteristic Condition Operation frequency range Min 2402 Channel spacing –93 Maximum usable input power GMSK, PER = 30.8% –5 Intermodulation characteristics Level of interferers (for n = 3, 4, 5) –36 RX mode LO leakage (1) (2) BLE Specification 2480 Unit MHz MHz Ω 50 PER = 30.8%; dirty TX on C/I performance (2) Image = –1 MHz Max 2 Input impedance Sensitivity, dirty TX on (1) Typ –96 –30 ≤ –70 dBm ≥ –10 dBm ≥ –50 dBm GMSK, co-channel 8 12 ≤ 21 GMSK, adjacent ±1 MHz –5 0 ≤ 15 GMSK, adjacent +2 MHz –45 –38 ≤ –17 GMSK, adjacent –2 MHz –22 –15 ≤ –15 GMSK, adjacent ≥ |±3| MHz –47 –40 ≤ –27 Frf = (received RF – 0.6 MHz) –63 –58 dB dBm Sensitivity degradation up to 3 dB may occur where the BLE frequency is a harmonic of the fast clock. Numbers show wanted signal-to-interfering signal ratio. Smaller numbers indicate better C/I performance. Device Specifications Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback 33 CC256x SWRS121D – JULY 2012 – REVISED JANUARY 2014 4.3.2 www.ti.com BLE Receiver—General Blocking Characteristics Condition Typ BLE Specification Blocking performance over full range, according to BLE specification (1) 30 to 2000 MHz –15 ≥ –30 2000 to 2399 MHz –15 ≥ –35 2484 to 3000 MHz –15 ≥ –35 3 to 12.75 GHz –15 ≥ –30 (1) Min Unit dBm Exceptions are taken out of the total 10 allowed in the BLE specification. 4.3.3 BLE Transmitter Characteristics Min Typ Maximum RF output power (1) 10 12 (2) Power variation over BLE band –1 Max BLE Specification Unit ≤10 dBm dBm 1 dB Adjacent channel power |M-N| = 2 –45 –39 ≤ –20 Adjacent channel power |M-N| > 2 –50 –42 ≤ –30 (1) (2) To modify maximum output power, use an HCI VS command. To achieve the BLE specification of 10-dBm maximum, an insertion loss of > 2 dB is assumed between the RF ball and the antenna. Otherwise, use an HCI VS command to modify the output power. 4.3.4 BLE Modulation Characteristics Modulation characteristics Condition Δf1avg Δf2max ≥ limit for at least 99.9% of all Δf2max Δf2avg, Δf1avg Absolute carrier frequency drift Sym Min Typ Max BLE Specification Mod data = 4 1s, 4 0s: 111100001111000 0... Δf1 avg 240 250 260 225 to 275 Mod data = 1010101... Δf2 max 185 kHz 4.3.5 ≥ 185 210 kHz 0.85 ≥ 0.8 0.9 –25 Drift rate Initial carrier frequency tolerance Unit –75 25 ≤ ±50 kHz 15 ≤ 20 kHz/50 ms 75 ≤ ±100 kHz BLE Transceiver, Out-Of-Band and Spurious Emissions See Section 4.2.7, Bluetooth Transmitter, Out-of-Band and Spurious Emissions. 4.4 4.4.1 Interface Specifications UART Figure 4-1 shows the UART timing diagram. Table 4-1 lists the UART timing characteristics. 34 Device Specifications Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback CC256x www.ti.com SWRS121D – JULY 2012 – REVISED JANUARY 2014 HCI_RTS t2 t1 HCI_RX t6 HCI_CTS t3 t4 HCI_TX Start bit Stop bit 10 bits td_uart_swrs064 Figure 4-1. UART Timing Table 4-1. UART Timing Characteristics Symbol Characteristics Condition Min Baud rate Max Unit 37.5 4000 kbps 1.5 % Baud rate accuracy per byte Receive and transmit –2.5 Baud rate accuracy per bit Receive and transmit –12.5 t3 CTS low to TX_DATA on 0 t4 CTS high to TX_DATA off t6 CTS-high pulse width 1 t1 RTS low to RX_DATA on 0 t2 RTS high to RX_DATA off Typ 12.5 % μs 2 Hardware flow control 1 byte bit μs 2 Interrupt set to 1/4 FIFO 16 byte Figure 4-2 shows the UART data frame. Table 4-2 describes the symbols used in Figure 4-2. tb TX D0 STR D1 Dn D2 PAR STP td_uart_swrs064 Figure 4-2. Data Frame Table 4-2. Data Frame Key Symbol Description STR Start bit D0...Dn Data bits (LSB first) PAR Parity bit (optional) STP Stop bit Device Specifications Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback 35 CC256x SWRS121D – JULY 2012 – REVISED JANUARY 2014 4.4.2 www.ti.com PCM Figure 4-3 shows the interface timing for the PCM. Table 4-3 and Table 4-4 list the associated master and slave parameters, respectively. Tclk Tw Tw AUD_CLK tis tih AUD_IN / FSYNC_IN top AUD_OUT / FSYNC_OUT td_aud_swrs064 Figure 4-3. PCM Interface Timing Table 4-3. PCM Master Symbol Parameter Condition Min Max 244.14 (4.096 MHz) 15625 (64 kHz) Tclk Cycle time Tw High or low pulse width tis AUD_IN setup time 25 tih AUD_IN hold time 0 top AUD_OUT propagation time 40-pF load 0 10 top FSYNC_OUT propagation time 40-pF load 0 10 Min Max Unit 50% of Tclk min ns Table 4-4. PCM Slave Symbol 36 Parameter Condition Tclk Cycle time Tw High or low pulse width Tis AUD_IN setup time 8 Tih AUD_IN hold time 0 Unit 66.67 (15 MHz) 40% of Tclk tis AUD_FSYNC setup time 8 tih AUD_FSYNC hold time 0 top AUD_OUT propagation time 40-pF load Device Specifications 0 ns 21 Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback CC256x www.ti.com SWRS121D – JULY 2012 – REVISED JANUARY 2014 5 Reference Design and BOM for Power and Radio Connections Figure 5-1 shows the reference schematics for the CC256x device. Figure 5-1. Reference Schematics Table 5-1 lists the BOM for the CC256x device. Table 5-1. Bill of Materials Qty Reference Des. Value Description Manufacturer Manufacturer Part Number Alternate Part 1 ANT1 NA ANT_IIFA_CC2420_32mil_MI R NA IIFA_CC2420 Chip antenna 6 Capacitor 0.1 μF CAP CER 1.0-µF 6.3-V X5R 10% 0402 Kemet C0402C104K9RACTU 2 Capacitor 1.0 μF CAP CER 10-pF 50-V 5% NP0 0402 Taiyo Yuden JMK105BJ105KV-F 2 Capacitor 12 pF CAP CER 12 pF 6.3-V X5R 10% 0402 Murata Electronics GRM1555C1H120JZ01D 2 Capacitor 0.47 μF CAP CER .47-µF 6.3-V X5R ±10% 0402 Taiyo Yuden JMK105BJ474KV-F 1 FL1 2.45 GHz FILTER CER BAND PASS 2.45-GHZ SMD Murata Electronics LFB212G45SG8C341 Place brown marking up 1 OSC1 32,768 kHz 15 pF OSC 32.768-kHZ 15-pF 1.5-V 3.3-V SMD Abracon Corporation ASH7K-32.768KHZ-T Optional 1 U5 CC2560ARVM, CC2564RVM, CC2560BRVM, CC2564BRVM Bluetooth BR/EDR/LE or ANT Single-Chip Solution Texas Instruments CC256xRVM 1 Y1 26 MHz Crystal, 26 MHz NDK NX2016SA 1 C31 22 pF CAP CER 22-PF 25-V 5% NP0 0201 Murata Electronics North America GRM0335C1E220JD01D Copyright © 2012–2014, Texas Instruments Incorporated Note Copper antenna on PCB TZ1325D (Tai-Saw TST) Reference Design and BOM for Power and Radio Connections Submit Documentation Feedback 37 CC256x SWRS121D – JULY 2012 – REVISED JANUARY 2014 www.ti.com 6 mrQFN Mechanical Data RVM (S-PVQFN-N76) PLASTIC QUAD FLATPACK NO-LEAD B18 A20 A31 B28 B19 B27 8,10 SQ 7,90 A40 B10 A11 B36 7,83 SQ 7,63 B9 A10 A1 B1 Pin 1 Indentifier 0,90 0,80 0,65 0,55 Seating Plane 0,08 C 0,05 0,00 4X 5,40 A11 B10 B9 B1 B36 A40 A1 A10 4X 4,80 0,30 TYP 4X 0,70 THERMAL PAD CL – PKG. 0,17 SIZE AND SHAPE SHOWN ON SEPARATE SHEET CL – PAD 76X 0,60 4X 0,24 0,25 0,15 A20 B19 B18 A21 B28 B27 A30 A31 0,60 4X 0,24 0,60 0,50 76X 0,30 0,10 0,10 4211965/B 12/11 Bottom View NOTES: A. B. C. D. E. C A B C A B All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5-1994. This drawing is subject to change without notice. QFN (Quad Flatpack No-Lead) Package configuration. The package thermal pad must be soldered to the board for thermal and mechanical performance. See the additional figure in the Product Data Sheet for details regarding the exposed thermal pad features and dimensions. SWRS115-001 38 mrQFN Mechanical Data Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback CC256x www.ti.com SWRS121D – JULY 2012 – REVISED JANUARY 2014 RVM (S-PVQFN-N76) PLASTIC QUAD FLATPACK NO-LEAD THERMAL INFORMATION This package incorporates an exposed thermal pad that is designed to be attached directly to an external heatsink. The thermal pad must be soldered directly to the printed circuit board (PCB). After soldering, the PCB can be used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly to the appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a special heatsink structure designed into the PCB. This design optimizes the heat transfer from the integrated circuit (IC). For information on the Quad Flatpack No-Lead (QFN) package and its advantages, refer to Application Report, QFN/SON PCB Attachment, Texas Instruments Literature No. SLUA271. This document is available at www.ti.com. B36 A11 B10 B9 B1 A40 A1 A10 The exposed thermal pad dimensions for this package are shown in the following illustration. CLPKG. 0,17 3,30±0,10 A20 B18 B19 A21 B28 A30 A31 B27 CLPAD 3,00±0,10 Bottom View Exposed Thermal Pad Dimensions 4212066/B 12/11 NOTE: All linear dimensions are in millimeters SWRS115-018 mrQFN Mechanical Data Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback 39 CC256x SWRS121D – JULY 2012 – REVISED JANUARY 2014 www.ti.com 7 Chip Packaging and Ordering 7.1 Package and Ordering Information The mrQFN packaging is 76 pins and a 0.6-mm pitch. For detailed information, see Section 6, mrQFN Mechanical Data. Table 7-1 lists the package and order information for the device family members. Table 7-1. Package and Order Information Device Package Suffix Pieces/Reel CC2560ARVMT RVM 250 CC2560ARVMR RVM 2500 CC2564RVMT RVM 250 CC2564RVMR RVM 2500 CC2560BRVMT RVM 250 CC2560BRVMR RVM 2500 CC2564BRVMT RVM 250 CC2564BRVMR RVM 2500 Figure 7-1 shows the chip markings for the CC256x family. CC2560A CC2564 CC2560B CC2564B YM7 ZLLL G3 YM7 ZLLL G3 YM7 ZLLL G3 YM7 ZLLL G3 Y = Last digit of the year M = Month in hex number, 1-C for Jan-Dec 7 = Primary site code for ANM Z = Secondary site code for ANM LLL = Assembly lot code = Pin 1 indicator SWRS121-010 Figure 7-1. Chip Markings 7.1.1 Device Support Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers. These prefixes represent evolutionary stages of product development from engineering prototypes through fully qualified production devices. X null 40 Experimental, preproduction, sample or prototype device. Device may not meet all product qualification conditions and may not fully comply with TI specifications. Experimental/Prototype devices are shipped against the following disclaimer: “This product is still in development and is intended for internal evaluation purposes.” Notwithstanding any provision to the contrary, TI makes no warranty expressed, implied, or statutory, including any implied warranty of merchantability of fitness for a specific purpose, of this device. Device is qualified and released to production. TI’s standard warranty applies to production devices. Chip Packaging and Ordering Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback CC256x www.ti.com 7.2 SWRS121D – JULY 2012 – REVISED JANUARY 2014 Empty Tape Portion Figure 7-2 shows the empty portion of the carrier tape. Empty portion Empty portion Device on tape portion End Start 270-mm MIN User direction of feed The length is to extend so that no unit is visible on the outer layer of tape. swrs064-001 Figure 7-2. Carrier Tape and Pockets 7.3 Device Quantity and Direction When pulling out the tape, the A1 corner is on the left side (see Figure 7-3). A1 corner Carrier tape Sprocket hole Embossment Cover tape User direction of feed SWRS064-002 Figure 7-3. Direction of Device 7.4 Insertion of Device Figure 7-4 shows the insertion of the device. insert_swrs064 Figure 7-4. Insertion of Device Chip Packaging and Ordering Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback 41 CC256x SWRS121D – JULY 2012 – REVISED JANUARY 2014 7.5 www.ti.com Tape Specification The dimensions of the tape are: • Tape width: 16 mm • Cover tape: The cover tape does not cover the index hole and does not shift to outside from the carrier tape. • Tape structure: The carrier tape is made of plastic. The device is put in the embossed area of the carrier tape and covered by the cover tape, which is made of plastic. • ESD countermeasure: The plastic material used in the carrier tape and the cover tape is static dissipative. 7.6 Reel Specification 16.4 20.8 330.0 REF 100.0 REF Figure 7-5 shows the reel specifications: • 330-mm reel, 16-mm width tape • Reel material: Polystyrene (static dissipative/antistatic) +2.0 –0.0 2.0 +–0.5 Ø 13.0 +0.5/–0.2 SWRS121-006 Figure 7-5. Reel Dimensions (mm) 7.7 Packing Method The end of the leader tape is secured by drafting tape. The reel is packed in a moisture barrier bag fastened by heat-sealing (see Figure 7-6). 42 Chip Packaging and Ordering Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback CC256x www.ti.com SWRS121D – JULY 2012 – REVISED JANUARY 2014 Moisture-barrier bag reelpk_swrs064 Figure 7-6. Reel Packing Method CAUTION This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause devices not to meet their published specifications. 7.8 7.8.1 Packing Specification Reel Box Each moisture-barrier bag is packed into a reel box, as shown in Figure 7-7. rlbx_swrs064 Figure 7-7. Reel Box (Carton) 7.8.2 Reel Box Material The reel box is made from corrugated fiberboard. 7.8.3 Shipping Box If the shipping box has excess space, filler (such as cushion) is added. Figure 7-8 shows a typical shipping box. Chip Packaging and Ordering Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback 43 CC256x SWRS121D – JULY 2012 – REVISED JANUARY 2014 www.ti.com NOTE The size of the shipping box may vary depending on the number of reel boxes packed. box_swrs064 Figure 7-8. Shipping Box (Carton) 7.8.4 Shipping Box Material The shipping box is made from corrugated fiberboard. 44 Chip Packaging and Ordering Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 1-Sep-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) CC2560ARVMR NRND VQFNP-MR RVM 76 2500 Green (RoHS & no Sb/Br) CU SN | Call TI Level-3-260C-168 HR -40 to 85 CC256 0A CC2560ARVMT NRND VQFNP-MR RVM 76 250 Green (RoHS & no Sb/Br) CU SN | Call TI Level-3-260C-168 HR -40 to 85 CC256 0A CC2560BRVMR ACTIVE VQFNP-MR RVM 76 2500 Green (RoHS & no Sb/Br) CU SN | Call TI Level-3-260C-168 HR CC2560B CC2564BRVMR ACTIVE VQFNP-MR RVM 76 2500 Green (RoHS & no Sb/Br) CU SN | Call TI Level-3-260C-168 HR CC2564B CC2564BRVMT ACTIVE VQFNP-MR RVM 76 250 Green (RoHS & no Sb/Br) CU SN | Call TI Level-3-260C-168 HR CC2564B CC2564RVMR NRND VQFNP-MR RVM 76 2500 Green (RoHS & no Sb/Br) CU SN | Call TI Level-3-260C-168 HR -40 to 85 CC256 4 CC2564RVMT NRND VQFNP-MR RVM 76 250 Green (RoHS & no Sb/Br) CU SN | Call TI Level-3-260C-168 HR -40 to 85 CC256 4 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 1-Sep-2015 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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