Holt HI8454PSMF Integrated do-160g level 3 lightning protection Datasheet

HI-8450, HI-8451, HI-8454, HI-8455
Single / Quad ARINC 429 Line Receivers with
Integrated DO-160G Level 3 Lightning Protection
December 2016
GENERAL DESCRIPTION
Holt’s family of ARINC 429 line receivers include internal
lightning protection circuitry which ensures compliance
with RTCA/DO-160G, Section 22 Level 3 Pin Injection
Test Waveform Set A (3 & 4), Set B (3 & 5A) and Set Z (3
& 5B) without the use of any external components. Pin
surge levels for Level 3 are summarized below. The HI8450 and HI-8451 are single ARINC 429 line receivers
available in compact 8-pin SOIC packages. The HI-8454
and HI-8455 contain 4 independent ARINC 429 line
receivers.
Waveform
3
Waveform
4
Waveform
5A
Waveform
5B
VOC/ISC
VOC/ISC
VOC/ISC
VOC/ISC
600V/24A
300V/60A
300V/300A
300V/300A
The devices are designed to operate from either a 5V or
3.3V supply. Each receiver channel translates incoming
ARINC 429 data bus signals to a pair of TTL / CMOS
outputs.
The TESTA and TESTB inputs bypass the analog inputs
for testing purposes. They force the receiver outputs to
the specified ZERO, ONE or NULL state. The ARINC
inputs are ignored when the devices are in test mode.
The HI-8451 and HI-8454 produce low outputs when
the TESTA and TESTB inputs are held high, whereas
the HI-8450 produces high impedance outputs when
the TESTA and TESTB inputs are held high. The HI8455 does not have TEST inputs and these pins may be
considered no-connect (NC).
o
o
The parts are available in Industrial -40 C to +85 C, or
o
o
Extended, -55 C to +125 C temperature ranges. Optional
burn-in is available on the extended temperature range.
FEATURES
• Internal lightning protection circuitry ensures
compliance with RTCA/DO-160G, Section 22
Level 3 Pin Injection Test Waveform Set A (3 &
4), Set B (3 & 5A) and Set Z (3 & 5B)
• Direct connection to ARINC 429 bus with no
external components
• Test inputs bypass analog inputs and force digital
outputs to a one, zero, or null state (not available
on HI-8455)
• Industrial and Extended temperature ranges
• Burn-in available
PIN CONFIGURATION (TOP VIEW)
VDD
1
TESTA
2
INB
3
INA
4
8 TESTB
HI-8450PSx
HI-8451PSx
7 OUTB
6 OUTA
5 GND
8-PIN PLASTIC SOIC - NB
IN1A
IN1B
IN2A
IN2B
TESTA (8454 only)
TESTB (8454 only)
IN3A
IN3B
IN4A
IN4B
1
20
2
19
3
4
5
HI-8454PSx
&
HI-8455PSx
18
17
16
6
7
8
15
Quad
Receiver
14
13
9
12
10
11
OUT1A
OUT1B
OUT2A
OUT2B
VDD
GND
OUT3A
OUT3B
OUT4A
OUT4B
20-PIN PLASTIC TSSOP PACKAGE
Table 1. Function Table
ARINC
INPUTS
INA - INB
TESTA
TESTB
OUTA
OUTB
-2.5 to +2.5V
0
0
0
0
< -6.5V
0
0
0
1
> +6.5V
0
0
1
0
x
0
1
0
1
x
1
0
1
0
x
1
1
0
x
1
1
HI-Z
(1)
(2)
0 (1)
HI-Z (2)
Note (1): HI-8451 and HI-8454 only.
Note (2): HI-8450 only.
• 3.3V or 5.0V single supply operation
DS8450 Rev. A
HOLT INTEGRATED CIRCUITS
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12/16
HI-8450, HI-8451, HI-8454, HI-8455
FUNCTIONAL DESCRIPTION
The status of the ARINC receiver input is latched. A Null
input resets the latches and a One or Zero input sets the
latches.
Figure 1 shows the general architecture of an ARINC 429
receiver. The receiver operates off the VDD supply only.
The inputs RINA and RINB may be connected directly to
the ARINC 429 bus. Internal lightning protection circuitry
ensures compliance with RTCA/DO-160G, Section 22
Level 3 Pin Injection Test Waveform Set A (3 & 4), Set
B (3 & 5A) and Set Z (3 & 5B) without the use of any
external components.
The logic at the output is controlled by the test signal
which is generated by the logical OR of the TESTA and
TESTB pins (not available on HI-8455). If TESTA and
TESTB are both One, the outputs are pulled low (HI8451 and HI-8454 only). This allows the digital outputs
of a transmitter to be connected to the test inputs
through control logic for system self-test purposes. In
the case of HI-8450, if TESTA and TESTB are both One,
the outputs are high impedance (HI-Z).
After level translation, the inputs are buffered and
become inputs to a differential amplifier. The amplitude
of the differential signal is compared to levels derived
from a divider between VDD and Ground. The nominal
settings correspond to a One/Zero amplitude of 6.0V
and a Null amplitude of 3.3V.
BLOCK DIAGRAMS
TEST
ONE
S
Q
ROUTA
LATCH
TESTA
R
TESTB
RINA
RINB
NULL
LIGHTNING
PROTECTION
AND
TRANSLATION
TEST
ZERO
S
Q
ROUTB
LATCH
R
TESTA
TESTB
NULL
Figure 1. Line Receiver Block Diagram
IN1A
IN1B
OUT1A
OUT1B
IN2A
IN2B
OUT2A
OUT2B
IN3A
IN3B
OUT3A
OUT3B
IN4A
IN4B
OUT4A
OUT4B
TESTA
TESTB
Figure 2. HI-8454 Block Diagram
HOLT INTEGRATED CIRCUITS
2
HI-8450, HI-8451, HI-8454, HI-8455
PIN DESCRIPTIONS
Table 2. Pin Descriptions
Symbol
Function
Description
IN1A
ARINC INPUT
Receiver 1 positive input
IN1B
ARINC INPUT
Receiver 1 negative input
IN2A
ARINC INPUT
Receiver 2 positive input
IN2B
ARINC INPUT
Receiver 2 negative input
TESTA
LOGIC INPUT
Test input (not available on HI-8455)
TESTB
LOGIC INPUT
Test input (not available on HI-8455)
IN3A
ARINC INPUT
Receiver 3 positive input
IN3B
ARINC INPUT
Receiver 3 negative input
IN4A
ARINC INPUT
Receiver 4 positive input
IN4B
ARINC INPUT
Receiver 4 negative input
OUT4B
LOGIC OUTPUT
Receiver 4 “ZERO” output
OUT4A
LOGIC OUTPUT
Receiver 4 “ONE” output
OUT3B
LOGIC OUTPUT
Receiver 3 “ZERO” output
OUT3A
LOGIC OUTPUT
Receiver 3 “ONE” output
GND
POWER
Ground supply voltage
VDD
POWER
+3.3V or +5V supply voltage
OUT2B
LOGIC OUTPUT
Receiver 2 “ZERO” output
OUT2A
LOGIC OUTPUT
Receiver 2 “ONE” output
OUT1B
LOGIC OUTPUT
Receiver 1 “ZERO” output
OUT1A
LOGIC OUTPUT
Receiver 1 “ONE” output
HOLT INTEGRATED CIRCUITS
3
HI-8450, HI-8451, HI-8454, HI-8455
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VDD)
-0.3V to +7V
Logic input voltage range
-0.3V to +5.5V
ARINC input voltage
-120V to + 120V
o
Solder Temperature (reflow)
o
Storage Temperature
260 C
o
-65 C to +150 C
ESD-HBM (JS-001-2012)
RECOMMENDED OPERATING
CONDITIONS
Supply Voltages
VDD ................................... 3.0V to +5.5V
Temperature Range
o
o
Logic and supply pins
2,000V
ARINC 429 bus input pins
1,000V
RTCA/DO-160G, Section 22 pin injection
Waveform
Voc/Isc
3
1,000V/40A
4
500V/100A
5A
500V/500A
5B
500V/500A
o
Industrial Screening .............. -40 C to +85 C
o
Hi-Temp Screening .............. -55 C to +125 C
NOTE: Stresses above absolute maximum ratings or outside
recommended operating conditions may cause permanent damage to
the device. These are stress ratings only. Operation at the limits is not
recommended.
ELECTRICAL CHARACTERISTICS
Table 3. DC Electrical Characteristics
VDD = +5.0V ± 10% or +3.3V ± 10%, GND = 0V, TA = Operating Temperature Range (unless otherwise stated)
Parameters
Symbol
Test Conditions
Min
Typ
Max
Units
ONE or ZERO
VDIN
Differential Input voltage
6.5
10
13
V
NULL
VNIN
Differential Input voltage
2.5
V
Common mode
VCOM
With respect to GND
±5.0
V
INA to INB
RDIFF
Supplies floating
30
kΩ
Input to GND or VDD
RSUP
Supplies floating
15
kΩ
ARINC INPUTS
Input Voltage
Input Resistance
Input Hysteresis
Input Capacitance
VHYS
ARINC differential
CAD
ARINC single ended
to GND
CAS
HOLT INTEGRATED CIRCUITS
4
0.5
1.0
5
V
10
pF
10
pF
HI-8450, HI-8451, HI-8454, HI-8455
Parameters
Symbol
Test Conditions
Min
Typ
Max
Units
TEST INPUTS
Logic Input Voltage
Logic Input Current
High
VIH
80%VDD
V
Low
VIL
Sink
IIH
VIH = VDD
Source
IIL
VIL = 0V
-1.0
μA
IOH = -5.0mA, VDD = 5.0V
2.4
V
IOH = -4.0mA, VDD = 3.3V
2.4
V
20%VDD
V
200
μA
OUTPUTS
Logic Output Voltage
Logic Output Voltage
(CMOS)
High
VOH
Low
VOL
High
VOHC
IOH = -100μA
Low
VOLC
IOL = 100μA
IOH = 5.0mA, VDD = 5.0V
0.4
IOH = 4.0mA, VDD = 3.3V
0.5
VDD−0.2
V
V
GND+0.2
V
SUPPLY CURRENT
VDD Current
IDD
(HI-8454, HI-8455)
VDD Current
IDD
(HI-8450, HI-8451)
VDD = 5.0V
14
20
mA
VDD = 3.3V
9
15
mA
VDD = 5.0V
12
18
mA
VDD = 3.3V
8
14
mA
Typ
Max
Units
Table 4. AC Electrical Characteristics
VDD = +5.0V ± 10% or +3.3V ± 10%, GND = 0V, TA = Operating Temperature Range (unless otherwise stated)
Parameters
Symbol
Test Conditions
Min
tLH
CL = 50pF
150
300
ns
tHL
CL = 50pF
150
300
ns
Output Rise Time
tR
10% to 90%
15
50
ns
Output Fall Time
tF
90% to 10%
15
50
ns
SWITCHING CHARACTERISTICS
Propagation Delay
Propagation Delay
IN to OUT
TEST to OUT
tTOH
50
ns
tTOL
50
ns
HOLT INTEGRATED CIRCUITS
5
HI-8450, HI-8451, HI-8454, HI-8455
LIGHTNING INDUCED TRANSIENT VOLTAGE WAVEFORMS
Waveform 3.
V or I
Largest
Peak
25% to 75%
of Largest Peak
50%
0
t
Figure 3. DO-160G Lightning Induced Transient Voltage Waveform 3.
Voc = 600V, Isc = 24A, Frequency = 1MHz ± 20%.
Waveform 4.
V or I
Peak
T1 = 6.4µs ± 20%
T2 = 70µs ± 20%
50%
0
T1
T2
t
Figure 4. DO-160G Lightning Induced Transient Voltage Waveform 4.
Voc = 300V, Isc = 60A.
HOLT INTEGRATED CIRCUITS
6
HI-8450, HI-8451, HI-8454, HI-8455
Waveform 5.
V or I
Peak
5A: T1 = 40µs ± 20%
T2 = 120µs ± 20%
5B: T1 = 50µs ± 20%
T2 = 500µs ± 20%
50%
0
T1
T2
t
Figure 5. DO-160G Lightning Induced Transient Voltage Waveforms 5A and 5B.
Voc = 300V, Isc = 300A.
HOLT INTEGRATED CIRCUITS
7
HI-8450, HI-8451, HI-8454, HI-8455
26 - N/C
25 - N/C
28 - OUT1A
27 - OUT1B
30 - N/C
29 - VDD
32 - IN1B
31 - IN1A
ADDITIONAL PIN CONFIGURATIONS
24 - N/C
N/C - 1
IN2A - 2
23 - OUT2A
IN2B - 3
22 - OUT2B
HI-8454PCx
TESTA - 4
TESTB - 5
21 - VDD
20 - GND
IN3A - 6
19 - OUT3A
IN3B - 7
18 - OUT3B
N/C - 8
OUT4B - 15
OUT4A - 16
N/C - 13
GND - 14
N/C - 12
IN4B - 11
N/C - 9
IN4A - 10
17 - N/C
32-PIN PLASTIC QFN
ORDERING INFORMATION
HI - 845xxx x x (Plastic)
PART NUMBER
Blank
F
PART NUMBER
I
LEAD FINISH
Tin / Lead (Sn / Pb) Solder
100% Matte Tin (Pb-free, RoHS compliant)
TEMPERATURE RANGE
-40oC to +85oC
o
o
FLOW
BURN IN
I
No
T
-55 C to +125 C
T
No
M
-55oC to +125oC
M
Yes
PART NUMBER
PACKAGE DESCRIPTION
8450PS
8 PIN PLASTIC NARROW BODY SOIC (8HN)
8451PS
8 PIN PLASTIC NARROW BODY SOIC (8HN)
8454PS
20 PIN PLASTIC TSSOP (20HS)
8454PC
32 PIN PLASTIC QFN (32PCS)
8455PS
20 PIN PLASTIC TSSOP (20HS)
HOLT INTEGRATED CIRCUITS
8
HI-8450, HI-8451, HI-8454, HI-8455
REVISION HISTORY
Revision
DS8450,
Date
Description of Change
Rev. New
01/14/14
Initial Release
Rev. A
12/05/16
Remove Power Dissipation spec from “Absolute Maximum Ratings”.
HOLT INTEGRATED CIRCUITS
9
HI-8450, HI-8451, HI-8454, HI-8455
PACKAGE DIMENSIONS
8-PIN PLASTIC SMALL OUTLINE (SOIC) - NB
(Narrow Body)
millimeters (inches)
Package Type: 8HN
4.90 BSC
(0.193)
0.175 ± 0.075
(0.007 ± 0.003)
6.00
BSC
(0.236)
3.90
BSC
(0.154)
PIN 1
See Detail A
0.41 ± 0.10
(0.016 ± 0.004)
1.25
(0.049) min.
o
o
0 to 8
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
1.27
BSC
(0.050)
0.175 ± 0.075
(0.007 ± 0.003)
0.835 ± 0.435
(0.033 ± 0.017)
Detail A
20-PIN PLASTIC TSSOP
millimeters (inches)
Package Type: 20HS
6.500 ± 0.100
(0.256 ± .004)
6.400 ± 0.150
(0.252 ± 0.006)
Pin 1
0.145 ± 0.055
(0.006 ± 0.002)
4.400 ± 0.100
(0.173 ± 0.004)
See Detail A
0.220 ± 0.050
(0.0087 ± 0.002)
0.925 ± 0.125
(0.036 ± 0.005)
0.650
BSC
(0.026)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
0° to 8°
0.600 ± 0.150
(0.024 ± 0.006)
HOLT INTEGRATED CIRCUITS
10
0.100 ± 0.050
(0.004 ± 0.002)
Detail A
HI-8450, HI-8451, HI-8454, HI-8455
32-PIN PLASTIC CHIP-SCALE PACKAGE (QFN)
millimeters (inches)
Package Type: 32PCS
5.000
BSC
(0.197)
Electrically isolated heat sink
pad on bottom of package.
Connect to any ground or
power plane for optimum
thermal dissipation.
3.400 ± 0.050
(0.134 ± 0.002)
0.50 BSC
(0.0197)
5.000
BSC
(0.197)
3.400 ± 0.050
(0.134 ± 0.002)
Top View
1.00
max
(0.039)
0.200
typ
(0.008)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
HOLT INTEGRATED CIRCUITS
11
Bottom
View
0.25
(0.010) typ
0.400 ± 0.050
(0.016 ± 0.002)
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