MB39A136
2ch PFM/PWM DC/DC Converter IC with
Synchronous Rectification
MB39A136 is 2ch step-down DC/DC converter IC of the current mode N-ch/N-ch synchronous rectification method. It contains the
enhanced protection features, and supports the symmetrical-phase method and the ceramic capacitor. MB39A136 realizes rapid
response, high efficiency, and low ripple voltage, and its high-frequency operation enables the miniaturization of inductors and I/O
capacitors.
Features
■
High efficiency
■
For frequency setting by external resistor : 100 kHz to 1 MHz
■
Error Amp threshold voltage
: 0.7 V 1.0
■
Minimum output voltage value
: 0.7 V
■
Wide range of power-supply voltage
: 4.5 V to 25 V
■
PFM/PWM auto switching mode and fixed PWM mode selectable
■
Supports Symmetrical-Phase method
■
With built-in over voltage protection function
■
With built-in under voltage protection function
■
With built-in over current protection function
■
With built-in over-temperature protection function
■
With built-in soft start/stop circuit without load dependence
■
With built-in synchronous rectification type output steps for N-ch MOS FET
■
Standby current
: 0 [A] Typ
■
Small package
: TSSOP-24
Application
■
Digital TV
■
Photocopiers
■
Surveillance cameras
■
Set-top boxes (STB)
■
DVD players, DVD recorders
■
Projectors
■
IP phones
■
Vending machine
■
Consoles and other non-portable devices
Cypress Semiconductor Corporation
Document Number: 002-08376 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 22, 2016
MB39A136
Contents
Pin Assignment ................................................................ 3
Pin Description ................................................................. 4
Block Diagram .................................................................. 5
Absolute Maximum Ratings ............................................ 6
Recommended Operating Conditions ............................ 7
Electrical Characteristics ................................................. 8
Typical Characteristics .................................................. 12
Function Description ...................................................... 14
Current Mode ............................................................ 14
Protection Function Table ............................................. 18
I/O Pin Equivalent Circuit Diagram ............................... 19
Example Application Circuit .......................................... 21
Parts List ......................................................................... 22
Document Number: 002-08376 Rev. *A
Application Note ............................................................. 24
Reference Data ............................................................... 41
Usage Precaution ........................................................... 43
Ordering Information ...................................................... 44
EV Board Ordering Information ................................. 44
RoHS Compliance Information Of
Lead (Pb) Free Version .................................................. 45
Marking Format (Lead Free version) ......................... 45
Labeling Sample (Lead free version) ....................... 46
MB39A136PFT Recommended Conditions
Of Moisture Sensitivity Level ........................................ 47
Package Dimensions ...................................................... 48
Major Changes ................................................................ 49
Page 2 of 50
MB39A136
1. Pin Assignment
(TOP VIEW)
CTL1
1
24
CB1
CS1
2
23
DRVH1
FB1
3
22
LX1
COMP1
4
21
DRVL1
ILIM1
5
20
VCC
RT
6
19
VB
VREF
7
18
GND
CTL2
8
17
DRVL2
ILIM2
9
16
LX2
COMP2
10
15
DRVH2
FB2
11
14
CB2
CS2
12
13
MODE
(FPT-24P-M09)
Document Number: 002-08376 Rev. *A
Page 3 of 50
MB39A136
2. Pin Description
Pin No.
Symbol
I/O
Description
1
CTL1
I
CH1 control pin.
2
CS1
I
CH1 soft-start time setting capacitor connection pin.
3
FB1
I
CH1 Error amplifier inverted input pin.
4
COMP1
O
CH1 error amplifier output pin.
5
ILIM1
I
CH1 over current detection level setting voltage input pin.
6
RT
Oscillation frequency setting resistor connection pin.
7
VREF
O
Reference voltage output pin.
8
CTL2
I
CH2 control pin.
9
ILIM2
I
CH2 over current detection level setting voltage input pin.
10
COMP2
O
CH2 error amplifier output pin.
11
FB2
I
CH2 Error amplifier inverted input pin.
12
CS2
I
CH2 soft-start time setting capacitor connection pin.
13
MODE
I
PFM/PWM switch pin. (CH1 and CH2 commonness) It becomes fixed PWM operation with
the VREF connection, and it becomes PFM/PWM operation with the GND connection.
14
CB2
CH2 connection pin for boot strap capacitor.
15
DRVH2
O
CH2 output pin for external high-side FET gate drive.
16
LX2
CH2 inductor and external high-side FET source connection pin.
17
DRVL2
O
CH2 output pin for external low-side FET gate drive.
18
GND
Ground pin.
19
VB
O
Bias voltage output pin.
20
VCC
Power supply pin for reference voltage and control circuit.
21
DRVL1
O
CH1 output pin for external low-side FET gate drive.
22
LX1
CH1 inductor and external high-side FET source connection pin.
23
DRVH1
O
CH1 output pin for external high-side FET gate drive.
24
CB1
CH1 connection pin for boot strap capacitor.
Document Number: 002-08376 Rev. *A
Page 4 of 50
MB39A136
3. Block Diagram
MODE
VCC
RT
13
20
6
<CH1>
<Soft-Start,
Soft-Stop>
CS1
2
COMP1
FB1
VREF
ctl1
/uvp_out
/otp_out
5.5
μA
/uvlo
ovp_out
70 kΩ
<PFM Comp. >
+
pfm1
−
<I Comp.>
−
+
+
180° out of phase
RS-FF
RQ
−
+
S
intref
ILIM1
19
VB
pfm2
ch.1
ch.2
<Error Amp>
Bias
Reg.
2.0 V
4
3
Clock
generator
24
Hi-side
Drive
23
Drive
Logic
22
CB1
DRVH1
LX1
VB
CLK
5
21
Lo-side
Drive
Vs
DRVL1
Level
Converter
<Di Comp.>
<OVP Comp.>
<UVP Comp.>
+
−
−
+
intref
x 1.15 V
−
+
intref
x 0.7 V
ovp1
uvp1
<UVLO>
ovp1
ovp2
uvp1
uvp2
50 μs
delay
512/fOSC
delay
ovp_out
SQ
R
SQ
R
CS2
12
uvp_out
VB
UVLO
uvlo
VREF
UVLO
H:UVLO
release
otp_out
OTP
<CH2>
14
The configuration of a control circuit is the same as that of CH1.
COMP2
FB2
15
10
16
11
17
CB2
DRVH2
LX2
DRVL2
VB ctl1, ctl2
ILIM2
9
<REF> <CTL>
intref
(3.3 V)
7
VREF
Document Number: 002-08376 Rev. *A
ON/OFF
CTL1
1
8 CTL2
18
GND
Page 5 of 50
MB39A136
4. Absolute Maximum Ratings
Parameter
Symbol
Rating
Conditions
Power-supply voltage
VVCC
VCC pin
CB pin input voltage
VCB
CB1, CB2 pins
LX pin input voltage
VLX
LX1, LX2 pins
Voltage between CB and LX
VCBLX
Control input voltage
VI
CTL1, CTL2 pins
Input voltage
VFB
FB1, FB2 pins
VILIM
ILIM1, ILIM2 pins
VCSx
CS1, CS2 pins
VMODE
MODE pin
Output current
IOUT
DC DRVL1, DRVL2 pins,
DRVH1, DRVH2 pins
Power dissipation
PD
Ta 25°C
Storage temperature
TSTG
Min
55
Unit
Max
27
V
32
V
27
V
7
V
27
V
VVREF 0.3
V
VVREF 0.3
V
VVREF 0.3
V
VVB 0.3
V
60
mA
1644
150
mW
°C
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
Document Number: 002-08376 Rev. *A
Page 6 of 50
MB39A136
5. Recommended Operating Conditions
Parameter
Symbol
Power supply voltage
VVCC
CB pin
input voltage
VCB
Reference voltage
output current
IVREF
Bias output current
CTL pin input voltage
Input voltage
Peak output current
Value
Conditions
Min
Typ
100
IVB
1
VI
CTL1, CTL2 pins
0
VFB
FB1, FB2 pins
0
VILIM
ILIM1, ILIM2 pins
0.3
VCS
CS1, CS2 pins
0
VMODE
MODE pin
0
IOUT
DRVH1, DRVH2 pins
DRVL1, DRVL2 pins
Duty 5 (t 1/fOSC×Duty)
4.5
1200
25.0
V
30
V
A
mA
25
V
VVREF
V
1.94
V
VVREF
V
VVREF
V
Operation frequency range
fOSC
100
500
Timing resistor
RRT
RT pin
47
Soft start capacitor
CCS
CS1, CS2 pins
0.0075
CB pin capacitor
CCB
CB1, CB2 pins
Reference voltage
output capacitor
CVREF
VREF pin
Bias voltage output
capacitor
CVB
VB pin
Operating ambient temperature
Ta
30
Unit
Max
1200
mA
1000
kHz
k
0.0180
0.1
1.0
F
0.1
1.0
F
2.2
10
F
25
85
F
°C
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
Document Number: 002-08376 Rev. *A
Page 7 of 50
MB39A136
6. Electrical Characteristics
Parameter
Reference
Voltage Block
[REF]
Bias Voltage
Block
[VB Reg.]
Clock
Generator
Block
[OSC]
Symbol
Output voltage
VVREF
7
3.24
3.30
3.36
V
Input stability
VREF
LINE
7
VCC pin 4.5 V to 25 V
1
10
mV
Load stability
VREF
LOAD
7
VREF pin 0 A to
100 A
1
10
mV
Short-circuit output
current
VREF
IOS
7
VREF pin 0 V
14.5
10.0
7.5
mA
Output voltage
VVB
19
4.85
5.00
5.15
V
Input stability
VB
LINE
19
VCC pin 6 V to 25 V
10
100
mV
Load stability
VB
LOAD
19
VB pin 0 A to 1 mA
10
100
mV
Short-circuit output
current
VB
IOS
19
VB pin 0 V
200
140
100
mA
Threshold voltage
VTLH1
19
VB pin
4.0
4.2
4.4
V
VTHL1
19
VB pin
3.4
3.6
3.8
V
VH1
19
VB pin
0.6*
V
Under voltage
Lockout
Hysteresis width
Protection
Threshold
Circuit Block
voltage
[UVLO]
Soft-start /
Soft-stop
Block
[Soft-Start,
Soft-Stop]
(Ta 25°C, VCC pin 15 V, CTL pin 5 V, VREF pin 0 A, VB pin 0A)
Value
Pin
Conditions
Unit
No.
Min
Typ
Max
VTLH2
7
VREF pin
2.7
2.9
3.1
V
VTHL2
7
VREF pin
2.5
2.7
2.9
V
Hysteresis width
VH2
7
VREF pin
0.2*
V
Charge current
ICS
2, 12
CTL1, CTL2 pins 5 V,
CS1, CS2 pins 0 V
7.9
5.5
4.2
A
Soft-start
end voltage
VCS
2, 12
CTL1, CTL2 pins 5 V
2.2
2.4
2.6
V
Electrical discharge
resistance at
soft-stop
RDISCG
2, 12
CTL1, CTL2 pins 0 V,
CS1, CS2 pins 0.5 V
49
70
91
k
Soft-stop
end voltage
VDISCG
2, 12
CTL1, CTL2 pins 0 V
0.1*
V
Oscillation
frequency
fOSC
6
RT pin 47 k
450
500
550
kHz
Oscillation
frequency when
under voltage is
detected
fSHORT
6
RT pin 47 k
62.5
kHz
Frequency
Temperature
variation
df/dT
6
Ta 30°C to 85°C
3*
%
(Continued)
Document Number: 002-08376 Rev. *A
Page 8 of 50
MB39A136
Parameter
Threshold
voltage
Under-voltage
Protection
Circuit Block
[UVP Comp.]
Over-temperature
Protection
Circuit Block
[OTP]
PFM Control
Circuit Block
(MODE)
Symbol
EVTH
3, 11
0.693
0.700
0.707
V
0.689*
0.700*
0.711*
V
EVTHT
3, 11
Ta 30°C to 85°C
Input current
IFB
3, 11
FB1, FB2 pins 0 V
0.1
Output current
ISOURCE
4, 10
FB1, FB2 pins 0 V,
COMP1, COMP2 pins
1V
390
ISINK
4, 10
FB1, FB2 pins
VREF pin,
COMP1, COMP2 pins 1 V
8.4
12.0
16.8
mA
Output clamp
voltage
VILIM
4, 10
FB1, FB2 pins 0 V,
ILIM1, ILIM2 pins 1.5 V
1.35
1.50
1.65
V
ILIM pin
input current
IILIM
5, 9
FB1, FB2 pins 0 V,
ILIM1, ILIM2 pins 1.5 V
1
Over-voltage
detecting
voltage
VOVP
3, 11
FB1, FB2 pins
0.776
0.805
0.835
V
Over-voltage
detection time
tOVP
3, 11
49
70
91
s
Under-voltage
detecting
voltage
VUVP
3, 11
FB1, FB2 pins
0.450
0.490
0.531
V
Under-voltage
detection time
tUVP
3, 11
s
Detection
temperature
TOTPH
TOTPL
Synchronous rectification stop voltage
VTHLX
PFM/PWM mode
condition
Error Amp Block
[Error Amp1,
Error Amp2]
Over-voltage
Protection
Circuit Block
[OVP Comp.]
(Ta 25°C, VCC pin 15 V, CTL pin 5 V, VREF pin 0 A, VB pin 0 A)
Value
Pin
Conditions
Unit
No.
Min
Typ
Max
0
300
0
512/
fOSC
0.1
A
210
A
1
Junction temperature
22, 16
LX1, LX2 pins
0*
mV
VPFM
13
MODE pin
0
1.4
V
Fixed PWM mode
condition
VPWM
13
MODE pin
2.2
VVREF
V
MODE pin input
current
IMODE
13
MODE pin 0 V
Junction temperature
1
160*
135*
0
A
1
°C
°C
A
(Continued)
Document Number: 002-08376 Rev. *A
Page 9 of 50
MB39A136
Parameter
High-side
output
on-resistance
Low-side
output
on-resistance
Output source
current
Symbol
(Ta 25°C, VCC pin 15 V, CTL pin 5 V, VREF pin 0 A, VB pin 0 A)
Value
Pin No.
Conditions
Unit
Min
Typ
Max
4
7
DRVH1, DRVH2 pins
100 mA
1.0
3.5
21, 17
DRVL1, DRVL2 pins
100 mA
4
7
RON_SL
21, 17
DRVL1, DRVL2 pins
100 mA
0.75
1.70
ISOURCE
23, 15,
21, 17
LX1, LX2 pins = 0 V,
CB1, CB2 pins 5 V
DRVH1, DRVH2 pins,
DRVL1, DRVL2 pins 2.5 V
Duty 5%
A
23, 15
LX1, LX2 pins = 0 V,
CB1, CB2 pins 5 V
DRVH1, DRVH2 pins 2.5 V
Duty 5%
21, 17
LX1, LX2 pins 0 V,
CB1, CB2 pins 5 V
DRVL1, DRVL2 pins 2.5 V
Duty 5
RON_MH
23, 15
DRVH1, DRVH2 pins
100 mA
RON_ML
23, 15
RON_SH
Output Block
[DRV]
Output sink current ISINK
Level
Converter Block
[LVCNV]
0.5*
0.9*
A
1.2*
A
Minimum on time
tON
23, 15
COMP1, COMP2 pins 1 V
250*
Maximum
on-duty
DMAX
23, 15
FB1, FB2 pins 0 V
75
80
Dead time
tD
23, 21,
15, 17
LX1, LX2 pins 0 V,
CB1, CB2 pins 5 V
60
ns
Maximum
current sense
voltage
VRANGE
22, 16
VCC pin LX1, LX2 pins
220*
mV
Voltage
conversion gain
ALV
22, 16
5.4
6.8
8.2
V/V
Offset voltage at
voltage
conversion
VIO
22, 16
300
mV
Slope
compensation
inclination
SLOPE
22, 16
2*
V/V
LX pin
input current
ILX
22, 16
LX1, LX2 pins VCC pin
320
420
600
A
ns
(Continued)
Document Number: 002-08376 Rev. *A
Page 10 of 50
MB39A136
(Continued)
Parameter
Control Block
[CTL1, CTL2]
General
Symbol
(Ta 25°C, VCC pin 15 V, CTL pin 5 V, VREF pin 0 A, VB pin 0 A)
Value
Pin No.
Conditions
Unit
Min
Typ
Max
ON condition
VON
1, 8
CTL1, CTL2 pins
2
OFF condition
VOFF
1, 8
CTL1, CTL2 pins
0
Hysteresis width
VH
1, 8
CTL1, CTL2 pins
Input current
ICTLH
1, 8
CTL1, CTL2 pins 5 V
ICTLL
1, 8
CTL1, CTL2 pins 0 V
Standby
current
ICCS
20
CTL1, CTL2 pins 0 V
Power-supply
current
ICC
20
LX1, LX2 pins 0 V,
FB1, FB2 pins 1.0 V,
MODE pin VREF pin
25
V
0.8
V
0.4*
V
25
40
A
0
1
A
0
10
A
3.3
4.7
mA
* : This value is not be specified. This should be used as a reference to support designing the circuits.
Document Number: 002-08376 Rev. *A
Page 11 of 50
MB39A136
7. Typical Characteristics
■
Typical data
Power dissipation
Power dissipation vs. Operating ambient temperature
2000
Power dissipation PD (mW)
1800
1644
1600
1400
1200
1000
800
600
400
200
0
−50
−25
0
+25
+50
+75
+100
+125
Operating ambient temperature Ta (°C)
Error Amp threshold voltage vs.
Operating ambient temperature
VREF bias voltage VVREF (V)
3.36
3.34
3.32
3.3
3.28
VCC = 15 V
fosc = 500 kHz
3.26
3.24
-40
-20
0
+20
+40
+60
+80
+100
Operating ambient temperature Ta (°C)
Error Amp threshold voltage EVTH (V)
VREF bias voltage vs.
Operating ambient temperature
0.71
0.705
CH1
0.7
CH2
VCC = 15 V
fosc = 500 kHz
0.695
0.69
-40
-20
0
+20
+40
+60
+80
+100
Operating ambient temperature Ta (°C)
(Continued)
Document Number: 002-08376 Rev. *A
Page 12 of 50
MB39A136
(Continued)
Dead time vs.
Operating ambient temperature
90
505
VCC = 15 V
500
495
490
485
480
-20
0
+20
+40
+60
+80
tD1
50
-20
0
+20
+40
+60
+80
+100
Operating ambient temperature Ta(°C)
tD1 : period from DRVL off to DRVH on
tD2 : period from DRVH off to DRVL on
VB bias voltage vs. VB bias output current
Oscillation frequency vs. Timing resistor value
1000
6
5.5
VB bias voltage VVB (V)
VCC = 15 V
Ta = + 25°C
10
100
4.5
VCC = 5 V
4
3.5
3
VCC = 4.5 V
fosc = 500 kHz
Ta = + 25°C
2.5
2
-0.025
1000
-0.02
-0.015
-0.01
-0.005
Timing resistor value RRT (k)
VB bias output current IVB (A)
Maximum duty cycle vs.
Power supply voltage
Maximum duty cycle vs.
Operating ambient temperature
80
fosc = 500 kHz
Ta = + 25°C
79
78
CH2
77
CH1
76
0
VCC = 6 V
5
100
10
20
Power supply voltage VVCC (V)
Document Number: 002-08376 Rev. *A
30
Maximum duty cycle DMAX ()
Oscillation frequency fOSC (kHz)
60
30
-40
+100
Operating ambient temperature Ta (°C)
Maximum duty cycle DMAX ()
tD2
70
40
475
-40
75
VCC = 15 V
fosc = 500 kHz
80
Dead time tD (ns)
Oscillation frequency fOSC (kHz)
Oscillation frequency vs.
Operating ambient temperature
0
80
VCC = 15 V
fosc = 500 kHz
79
CH2
78
CH1
77
76
75
-40
-20
0
+20
+40
+60
+80
+100
Operating ambient temperature Ta (°C)
Page 13 of 50
MB39A136
8. Function Description
8.1 Current Mode
It uses the current waveform from the switching (Q1) as a control waveform to control the output voltage, as described below:
1. The clock (CK) from the internal clock generator (OSC) sets RS-FF and turns on the high-side FET.
2. Turning on the high-side FET causes the inductor current (IL) rise. Generate Vs that converts this current into the voltage.
3. The current comparator (I Comp.) compares this Vs with the output (COMP) from the error amplifier (Error Amp) that is
negative-feedback from the output voltage (Vo).
4. When I Comp. detects that Vs exceeds COMP, it resets RS-FF and turns off high-side FET.
5. The clock (CK) from the clock generator (OSC) turns on the high-side FET again.
Thus, switching is repeated.
Operate so that the FB electrical potential may become INTREF electrical potential, and stabilize the output voltage as a feedback
control.
VIN
<Error Amp>
FB
<I Comp.>
−
+
−
COMP
+
INTREF
DRVH
RS-FF
R
Q
S
Drive
Logic
CK
Q1
Current
Sense
DRVL
OSC
IL
VO
Q2
Vs
Rs
4
1
5
OSC(CK)
IL
3
COMP
Vs
2
toff
DRVH
ton
8.1.1 Reference Voltage Block (REF)
The reference voltage circuit (REF) generates a temperature-compensated reference voltage (3.3 [V] Typ) using the voltage supplied
from the VCC pin. The voltage is used as the reference voltage for the IC's internal circuit. The reference voltage can be used to
supply a load current of up to 100 A to an external device through the VREF pin.
Document Number: 002-08376 Rev. *A
Page 14 of 50
MB39A136
8.1.2 Bias Voltage Block (VB Reg.)
Bias Voltage Block (VB Reg.) generates the reference voltage used for IC’s internal circuit, using the voltage supplied from the VCC
pin. The reference voltage is a temperature-compensated stable voltage (5 [V] Typ) to supply a current of up to 100 mA through the
VB pin.
8.1.3 Under Voltage Lockout Protection Circuit Block (UVLO)
The circuit protects against IC malfunction and system destruction/deterioration in a transitional state or a momentary drop when a
bias voltage (VB) or an internal reference voltage (VREF) starts. It detects a voltage drop at the VB pin or the VREF pin and stops IC
operation. When voltages at the VB pin and the VREF pin exceed the threshold voltage of the under voltage lockout protection circuit,
the system is restored.
8.1.4 Soft-start/Soft-stop Block (Soft-Start, Soft-Stop)
Soft-start
It protects a rush current or an output voltage (VOx) from overshooting at the output start. Since the lamp voltage generated by charging
the capacitor connecting to the CSx pin is used for the reference voltage of the error amplifier (Error Amp), it can set the soft-start
time independent of a load of the output (VOx). When the IC starts with “H” level of the CTLx pin, the capacitor at the CSx pin (CS)
starts to be charged at 5.5 A. The output voltage (VOx) during the soft-start period rises in proportion to the voltage at the CSx pin
generated by charging the capacitor at the CSx pin.
During the soft-start with 0.8 V > voltage at CS1 and CS2 pins, operations are as follows:
■
Fixed PWM operation only (fixed PWM even if MODE pin is set to “L”)
■
Over-voltage protection function and under-voltage protection function are invalid.
Soft-stop
It discharges electrical charges stored in a smoothing capacitor at output stop. Setting the CTLx pin to “L” level starts the soft-stop
function independent of a load of output (Vox). Since the capacitor connecting to the CSx pin starts to discharge through the IC-built-in
soft-stop discharging resistance (70 [k] Typ) when the CTLx pin sets at “L” level enters its lamp voltage into the error amplifier (Error
Amp), the soft-stop time can be set independent of a load of output (VOx). When discharging causes the voltage at the CSx pin to
drop below 100 mV (Typ), the IC shuts down and changes to the stand-by state. In addition, the soft-stop function operates after the
under-voltage protection circuit block (UVP Comp.) is latched or after the over-temperature protection circuit block (OTP) detects
over-temperature.
During the soft-stop with, 0.8 V > voltage at CS1 and CS2 pins, operations are as follows:
■
Fixed PWM operation only (fixed PWM even if MODE pin is set to “L”)
■
Over-voltage protection function and under-voltage protection function are invalid.
8.1.5 Clock Generator Block (OSC)
The clock generator has the built-in oscillation frequency setting capacitor and generates a clock that 180phase shifted from each
channel by connecting the oscillation frequency setting resistor to the RT pin (Symmetrical-Phase method).
8.1.6 Error Amp Block (Error Amp1, Error Amp2)
The error amplifiers (Error Amp1 and Error Amp2) detect the output voltage from the DC/DC converter and output to the current
comparators (I Comp.1 and I Comp.2). The output voltage setting resistor externally connected to FB1 and FB2 pins allows an arbitrary
output voltage to be set.
In addition, since an external resistor and an external capacitor serially connected between COMP1 and FB1 pins and between
COMP2 and FB2 pins allow an arbitrary loop gain to be set, it is possible for the system to compensate a phase stably.
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8.1.7 Over Current Detection (Protection) Block (ILIM)
It is the current detection circuit to restrict an output current (IOX). The over current detection block (ILIM) compares an output waveform
of the level converter of each channel (see “8.1.13” Level Converter Block (LVCNV)) with the ILIMx pin voltage in every cycle. As a
load resistance (ROX) drops, a load current (IOX) increases. Therefore, the output waveform of the level converter exceeds the ILIM
pin voltage of each channel. At this time, the output current can be restricted by turning off FET on the high-side and suppressing a
peak value of the inductor current.
As a result, the output voltage (VOX) should drop.
Furthermore, if the output voltage drops and the electrical potential at the FBx pin drops below 0.3 V, the oscillation frequency (fOSC)
drops to 1/8.
8.1.8 Over-voltage Protection Circuit Block (OVP Comp.)
The circuit protects a device connecting to the output when the output voltage (VOx) rises.
It compares 1.15 times (Typ) of the internal reference voltage (INTREF) (0.7 V) that is non-inverting-entered into the error amplifier
with the feedback voltage that is inverting-entered into the error amplifier and if it detects the state where the latter is higher than the
former by 50 s (Typ). It stops the voltage output by setting the RS latch, setting the DRVHx pin to “L” level, setting the DRVLx pin to
“H” level, turning off the high-side FETs, and turning on the low-side FETs.
The conditions below cancel the protection function:
■
Setting CTL1 and CTL2 to “L”.
■
Setting the power supply voltage below the UVLO threshold voltage (VTHL1 and VTHL2).
8.1.9 Under-voltage Protection Circuit Block (UVP Comp.)
It protects a device connecting to the output by stopping the output when the output voltage (VOX) drops.
It compares 0.7 times (Typ) of the internal reference voltage (INTREF) (0.7 V) that is non-inverting-entered into the error amplifier with
the feedback voltage that is inverting-entered into the error amplifier and if it detects the state where the latter is lower than the former
by 512/fosc [s](Typ), it stops the voltage output for both channels by setting the RS latch.
The conditions below cancel the protection function:
■
Setting CTL1 and CTL2 to “L”.
■
Setting the power supply voltage below the UVLO threshold voltage (VTHL1 and VTHL2).
8.1.10 Over temperature Protection Circuit Block (OTP)
The circuit protects an IC from heat-destruction. If the temperature at the joint part reaches +160°C, the circuit stops the voltage output
for both channels by discharging the capacitor connecting to the CSx pin through the soft-stop discharging resistance (70 [k] Typ)
in the IC.
In addition, if the temperature at the joint part drops to 135°C, the output restarts again through the soft-start function.
Make sure to design the DC/DC power supply system so that the over temperature protection does not start frequently.
8.1.11 PFM Control Circuit Block (MODE)
It sets the control mode of the IC and makes control at automatic PFM/PWM switching.
MODE pin connection
Control mode
Features
“L” (GND)
Automatic PFM/PWM
switching
Highly-efficient at light load
“H” (VREF)
Fixed PWM
Stable oscillation frequency
Stable switching ripple voltage
Excellent in rapid load change characteristic at heavy load to light load
Automatic PFM/PWM switching mode operation
It compares the LX1 pin and the LX2 pin voltages with GND electrical potential at Di Comp. In the comparison, the negative voltage
at the LX pin causes the low-side FET to set on, positive voltage causes it to set off (Di Comp. method) . As a result, the method
restricts the back flow of the inductor current at a light load and makes the switching of the inductor current discontinuous (DCM) .
Such an operation allows the oscillation frequency to drop, resulting in high efficiency at a light load.
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8.1.12 Output Block (DRV)
The output circuit is configured in CMOS type for both of the high-side and the low-side, allowing the external N-ch MOS FET to drive.
8.1.13 Level Converter Block (LVCNV)
The circuit detects and converts the current when the high-side FET turns on. It converts the voltage waveform between drain side
(VCC pin voltage) and the source side (LX1 and LX2 pin voltage) on the high-side FET into the voltage waveform for GND reference.
Note: x : Each channel number
8.1.14 Control Block (CTL1, CTL2)
The circuit controls on/off of the output from the IC.
Control function table
CTL1
CTL2
DC/DC converter
(VO1)
DC/DC converter
(VO2)
L
L
OFF
OFF
H
L
ON
OFF
L
H
OFF
ON
H
H
ON
ON
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Remarks
Standby
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9. Protection Function Table
The following table shows the state of each pin when each protection function operates.
Output of each pin after detection
Detection
Protection Function
condition
VREF
VB
DRVHx
DRVLx
DC/DC output
dropping operation
Under Voltage Lock Out
Protection
(UVLO)
VB < 3.6 V
VREF < 2.7 V
< 2.7 V
< 3.6 V
L
L
Self-discharge by load
Under Voltage Protection
(UVP)
FBx < 0.49 V
3.3 V
5V
L
L
Electrical discharge by soft-stop
function
Over Voltage Protection
(OVP)
FBx > 0.805 V
3.3 V
5V
L
H
0 V clamping
Over Current Protection
(ILIM)
COMPx > ILIMx
3.3 V
5V
switching
switching
The output voltage is dropping to
keep constant output current.
Over Temperature
Protection
(OTP)
Tj > 160°C
3.3 V
5V
L
L
Electrical discharge by soft-stop
function
CONTROL
(CTL)
CTLx : H→L
(CSx > 0.1 V)
3.3 V
5V
L
L
Note: x is the each channel number
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10. I/O Pin Equivalent Circuit Diagram
VREF pin
CTL1, CTL2 pins
VCC
VB
CTL1,CTL2
VREF
ESD protection element
GND
GND
VB pin
CS1, CS2 pins
VCC
VREF
VB
CS1,CS2
GND
FB1, FB2 pins
VREF
GND
COMP1, COMP2 pins
VREF
FB1,FB2
COMP1,
COMP2
GND
GND
(Continued)
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(Continued)
ILM1, ILM2 pins
RT pin
VREF
VREF
VB
ILIM1,ILIM2
ILIM1,ILIM2
RT
GND
GND
GND
MODE pin
CB1, CB2, DRVH1, DRVH2, LX1, LX2 pins
CB1,CB2
CB1,CB2
VREF
VREF
VREF
DRVH1,
DRVH1,
DRVH2
DRVH2
MODE
LX1,LX2
LX1,LX2
GND
DRVL1, DRVL2 pins
GND
GND
VB
DRVL1,DRVL2
GND
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11. Example Application Circuit
R21
VREF
VIN
(4.5 V to 25 V)
RT
MODE
13
C13
VCC
6
20
MB39A136
19
CS1
2
A
VB
<CH1>
C7
A
D2
COMP1
4
R8-1
R8-2
24
CB1
FB1
23
3
22
R9
R11
ILIM1
5
21
VO1
L1
C5
R23
C9
Q1
DRVH1
LX1
Q1
DRVL1
C2-1
C2-2
C2-3
C1
R12
C14
CS2
B
12
<CH2>
14
C8
15
COMP2
R14-1
R14-2
C11
10
16
R25
FB2
11
17
R15
R17
B
D2
CB2
Q2
VO2
C6
DRVH2
LX2
DRVL2
Q2
C3-1
C3-2
ILIM2
L2
C4-1
C4-2
C4-3
9
1 CTL1
8 CTL2
R18
7
VREF
18
GND
C15
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12. Parts List
Component
Item
Specification
Vendor
Package
Parts Name
Remark
Q1
N-ch FET
VDS 30 V,
ID 8 A,
Ron 21 m
RENESAS
SO-8
PA2755
Dual type
(2 elements)
Q2
N-ch FET
VDS 30 V,
ID 8 A,
Ron 21 m
RENESAS
SO-8
PA2755
Dual type
(2 elements)
D2
Diode
VF 0.35 V
at IF 0.2 A
ON Semi
SOT-323
BAT54AWT1
Dual type
L1
Inductor
1.5 H
(6.2 m, 8.9 A)
TDK
VLF10040T-1R5N
L2
Inductor
3.3 H
(9.7 m, 6.9 A)
TDK
VLF10045T-3R3N
C1
Ceramic capacitor
22 F (25 V)
TDK
3225
C3225JC1E226M
C2-1
C2-2
C2-3
Ceramic capacitor
Ceramic capacitor
Ceramic capacitor
22 F (10 V)
22 F (10 V)
22 F (10 V)
TDK
TDK
TDK
3216
3216
3216
C3216JB1A226M
C3216JB1A226M
C3216JB1A226M
C3-1
C3-2
Ceramic capacitor
Ceramic capacitor
22 F (25 V)
22 F (25 V)
TDK
TDK
3225
3225
C3225JC1E226M
C3225JC1E226M
C4-1
C4-2
C4-3
Ceramic capacitor
Ceramic capacitor
Ceramic capacitor
22 F (10 V)
22 F (10 V)
22 F (10 V)
TDK
TDK
TDK
3216
3216
3216
C3216JB1A226M
C3216JB1A226M
C3216JB1A226M
C5
Ceramic capacitor
0.1 F (50 V)
TDK
1608
C1608JB1H104K
C6
Ceramic capacitor
0.1 F (50 V)
TDK
1608
C1608JB1H104K
C7
Ceramic capacitor
0.022 F (50 V)
TDK
1608
C1608JB1H223K
C8
Ceramic capacitor
0.022 F (50 V)
TDK
1608
C1608JB1H223K
C9
Ceramic capacitor
820 pF (50 V)
TDK
1608
C1608CH1H821J
C11
Ceramic capacitor
1000 pF (50 V)
TDK
1608
C1608CH1H102J
C13
Ceramic capacitor
0.01 F (50 V)
TDK
1608
C1608JB1H103K
C14
Ceramic capacitor
2.2 F (16 V)
TDK
1608
C1608JB1C225K
C15
Ceramic capacitor
0.1 F (50 V)
TDK
1608
C1608JB1H104K
R8-1
R8-2
Resistor
1.6 k
9.1 k
SSM
SSM
1608
1608
RR0816P162D
RR0816P912D
R9
Resistor
15 k
SSM
1608
RR0816P153D
R11
Resistor
56 k
SSM
1608
RR0816P563D
R12
Resistor
47 k
SSM
1608
RR0816P473D
R14-1
R14-2
Resistor
1.8 k
39 k
SSM
SSM
1608
1608
RR0816P182D
RR0816P393D
R15
Resistor
11 k
SSM
1608
RR0816P113D
3 capacitors in parallel
2 capacitors in parallel
3 capacitors in parallel
2 capacitors in series
2 capacitors in series
(Continued)
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(Continued)
Component
Item
Specification
Vendor
Package
Parts Name
R17
Resistor
56 k
SSM
1608
RR0816P563D
R18
Resistor
56 k
SSM
1608
RR0816P563D
R21
Resistor
82 k
SSM
1608
RR0816P823D
R23
Resistor
22 k
SSM
1608
RR0816P223D
R25
Resistor
56 k
SSM
1608
RR0816P563D
RENESAS
ON Semi
TDK
SSM
Remark
: Renesas Electronics Corporation
: ON Semiconductor
: TDK Corporation
: SUSUMU Co.,Ltd.
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13. Application Note
Setting method for PFM/PWM and fixed PWM modes
For the setting method for each mode, see“Function Description 8.1.11 PFM Control Circuit Block (MODE)”.
Cautions at PFM/PWM mode
If a load current drops rapidly because of rapid load change and others, it tends to take a lot of time to restore overshooting of an
output voltage.
As a result, the over-voltage protection may operate.
In this case, solution are possible by the addition of the load resistance of value to be able to restore the output voltage in the
over-voltage detection time.
Setting method of output voltage
Set it by adjusting the output voltage setting zero-power resistance ratio.
VO
R1 R2
R2
VO
R1, R2
× 0.7
: Output setting voltage [V]
: Output setting resistor value []
VO
R1
FB1
FB2
R2
Make sure that the setting does not exceed the maximum on-duty.
Calculate the on-duty by the following formula:
DMAX_Min
DMAX_Min
VIN
VO
RON_Main
RON_Sync
IOMAX
VO RON_Sync × IOMAX
VIN RON_Main × IOMAX RON_Sync × IOMAX
: Minimum value of the maximum on-duty cycle
: Power supply voltage of switching system [V]
: Output setting voltage [V]
: High-side FET ON resistance []
: Low-side FET ON resistance []
: Maximum load current [A]
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Oscillation frequency setting method
Set it by adjusting the RT pin resistor value.
fOSC
RRT
fOSC
RRT
1.09
× 40 × 10 -12 300 × 10 -9
: RT resistor value []
: Oscillation frequency [Hz]
The oscillation frequency must set for on-time (tON) to become 300ns or more.
Calculate the on-time by the following formula.
VO
VIN × fOSC
tON
tON
VIN
VO
fOSC
: On-time [s]
: Power supply voltage of switching system [V]
: Output setting voltage [V]
: Oscillation frequency [Hz]
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Setting method of soft-start time
Calculate the soft-start time by the following formula.
tS 1.4 ×105 ×CCS
ts
CCS
: Soft-start time [s] (Time to becoming output 100)
: CS pin capacitor value [F]
Calculate delay time until the soft-start beginning by the following formula.
td1 30 × CVB 290 × CVREF 1.455 × 104 × CCS
td1
CCS
CVB
CVREF
: Delay time including VB voltage and VREF voltage starts [s]
: CS pin capacitor value [F]
: VB pin capacitor value [F]
: VREF pin capacitor value [F] (0.1 [F] Typ)
Calculate delay time for starting while one channel has already started (UVLO released : VB, VREF output before) by the following
formula.
td2 1.455 × 104 × CCS
: Delay time for starting while one channel has already started [s]
td2
CCS
: CS pin capacitor value [F]
Calculate the discharge time at the soft-stop by the following formula.
tdis 1.44 × 105 × CCS
tdis
: Discharge time [s]
CCS
: CS pin capacitor value [F]
In addition, calculate the delay time to the discharge starting by the following formula.
td3 7.87 × 104 × CCS
: Delay time until discharge start [s]
td3
: CS pin capacitor value [F]
CCS
ts
tdis
CTL1
CTL2
VO1
VO2
td1
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td2
td3
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■
Simultaneous operation of plural channels
Soft-start/soft-stop operation according to the same timing as two channels can be achieved by even connecting it as shown in the
figure below at the power supply on/off.
<Connection example 1> When you adjust the soft-start time
Make the CS capacitor common. Connect CTL1 and CTL2.
Note: In this case, the soft-start time (ts), the discharge time (tdis), and the delay time (td1, td2, td3) decrease in the
half value of compared with when CS capacitor is connected to each channel.
DC/DC 1 : Vo = 1.2 V setting
CS1
V
< DC/DC 2 >
1.8 V
MB39A136
< DC/DC 1 >
Vo
1.2 V
CTL
CTL1
CTL2
CS2
CS
capacitor
CTL
t
DC/DC 2 : Vo = 1.8 V setting
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Setting method of over current detection value
It is possible to set over-current detection value (ILIM) by adjusting the over-current detection setting resistor value ratio.
Calculate the over current detection setting resistor value by the following formula.
ILIM
3.3×R2
0.3
R1 × R2
6.8 × RON
VIN VO
L
× (200 × 10 -9
VO
)
2 × fOSC × VIN
200 ×103 ≥ R1 R2 ≥ 30 × 103
ILIM
R1, R2
L
VIN
VO
fOSC
RON
*
: Over current detection value [A]
: ILIM setting resistor value []*
: Inductor value [H]
: Power supply voltage of switching system [V]
: Output setting voltage [V]
: Oscillation frequency [Hz]
: High-side FET ON resistance []
Since the over current detection value depends on the on-resistance of FET, the over current detection setting resistor value ratio
should be adjusted in consideration of the temperature characteristics of the on-resistance. When the temperature at the FET joint
part rises by 100 °C, the on-resistance of FET increases to about 1.5 times.
Inductor current
VREF
Over-current
detection value
ILIM
R1
IO
ILIM*
R2
0
*
Time
If the over current detection function is not used, connect the ILIM pin (ILIM1 and ILIM2) to the VREF pin.
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Selection of smoothing inductor
The inductor value selects the value that the ripple current peak-to-peak value becomes 50% or less of the maximum load current as
a rough standard. Calculate the inductor value in this case by the following formula.
L≥
VIN VO
×
LOR × IOMAX
L
IOMAX
LOR
VIN
VO
fOSC
VO
VIN × fOSC
: Inductor value [H]
: Maximum load current [A]
: Ripple current peak-to-peak value of Maximum load current ratio (=0.5)
: Power supply voltage of switching system [V]
: Output setting voltage [V]
: Oscillation frequency [Hz]
An inductor ripple current value limited on the principle of operation is necessary for this device. However, when it uses the high-side
FET of the low Ron resistance, the switching ripple voltage become small, and the inductor ripple current value may become
insufficient. This should be solved by the oscillation frequency or reducing the inductor value.
Select the one of the inductor value that meets a requirement listed below.
L
VIN VO
VRON
L
VIN
VO
fOSC
VRON
RON
VO
×RON
VIN × fOSC
×
: Inductor value [H]
: Power supply voltage of switching system [V]
: Output setting voltage [V]
: Oscillation frequency [Hz]
: Ripple voltage [V] (20 mV or more is recommended)
: High-side FET ON resistance []
It is necessary to calculate the maximum current value that flows to the inductor to judge whether the electric current that flows to the
inductor is a rated value or less. Calculate the maximum current value of the inductor by the following formula.
ILMAX ≥ IoMAX
ILMAX
IoMAX
IL
L
VIN
VO
fOSC
IL
2
, IL
VIN VO
L
×
VO
VIN×fOSC
: Maximum current value of inductor [A]
: Maximum load current [A]
: Ripple current peak-to-peak value of inductor [A]
: Inductor value [H]
: Power supply voltage of switching system [V]
: Output setting voltage [V]
: Oscillation frequency [Hz]
Inductor current
ILMAX
IoMAX
ΔIL
t
0
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Selection of SWFET
The switching ripple voltage generated between drain and sources on high-side FET is necessary for this device operation. Select
the one of the SWFET of on-resistance that satisfies the following formula.
RON_Main ≥
VRON_Main
IL
RON_Main
IL
VRON_Main
ILIM
VRONMAX
, RON_Main
VRONMAX
IL
ILIM
2
: High-side FET ON resistance []
: Ripple current peak-to-peak value of inductor [A]
: High-side FET ripple voltage [V] (20mV or more is recommended)
: Over current detection value [A]
: Maximum current sense voltage [V] (240mV or less is recommended)
Select FET ratings with a margin enough for the input voltage and the load current. Ratings with the over-current detection setting
value or more are recommended.
Calculate a necessary rated value of high-side FET and low-side FET by the following formula.
IL
2
ID IoMAX
ID
IoMAX
IL
: Rated drain current [A]
: Maximum load current [A]
: Ripple current peak-to-peak value of inductor [A]
VDS VIN
VDS
VIN
: Rated voltage between drain and source [V]
: Power supply voltage of switching system [V]
VGS VB
VGS
VB
: Rated voltage between gate and source [V]
: VB voltage [V]
Moreover, it is necessary to calculate the loss of SWFET to judge whether a permissible loss of SWFET is a rated value or less.
Calculate the loss on high-side FET by the following formula.
PMainFET PRON_Main PSW_Main
PMainFET
PRON_Main
PSW_Main
: High-side FET loss [W]
: High-side FET conduction loss [W]
: High-side FET SW loss [W]
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High-side FET conduction loss
PRON_Main IoMAX2 ×
PRON_Main
IOMAX
VIN
VO
RON_Main
VO
VIN
× RON_Main
: High-side FET conduction loss [W]
: Maximum load current [A]
: Power supply voltage of switching system [V]
: Output voltage [V]
: High-side FET ON resistance []
High-side FET SW loss
PSW_Main
VIN × fOSC × (Ibtm × tr Itop × tf)
2
: High-side FET SW loss [W]
: Power supply voltage of switching system [V]
: Oscillation frequency [Hz]
: Ripple current bottom value of inductor [A]
: Ripple current top value of inductor [A]
: Turn-on time on high-side FET [s]
: Turn-off time on high-side FET[s]
PSW_Main
VIN
fOSC
Ibtm
Itop
tr
tf
Calculate the Ibtm, the Itop, the tr and the tf simply by the following formula.
IOMAX
IL
2
Itop IOMAX
IL
2
Ibtm
tr
Qgd×4
5 Vgs (on)
IOMAX
IL
Qgd
Vgs (on)
tf
Qgd×1
Vgs (on)
: Maximum load current [A]
: Ripple current peak-to-peak value of inductor [A]
: Quantity of charge between gate and drain on high-side FET [C]
: Voltage between gate and source in Qgd on high-side FET [V]
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MB39A136
Calculate the loss on low-side FET by the following formula.
PSyncFET PRon_Sync* IoMAX2× (1
PSyncFET
PRon_Sync
IOMAX
VIN
VO
Ron_Sync
VO
)×Ron_Sync
VIN
: Low-side FET loss [W]
: Low-side FET conduction loss [W]
: Maximum load current [A]
: Power supply voltage of switching system [V]
: Output voltage [V]
: Low-side FET on-resistance []
* : The transition voltage of the voltage between drain and source on low-side FET is generally small, and the switching
loss is omitted here for the small one as it is possible to disregard it.
The gate drive power of SWFET is supplied by LDO in IC, therefore all SWFET allowable maximum total charge
(QgTotalMax) of 2ch is determined by the following formula.
0.095
fOSC
QgTotalMax
QgTotalMax
fOSC
: SWFET allowable maximum total charge [C]
: Oscillation frequency [Hz]
Selection of fly-back diode
When the conversion efficiency is valued, the improved property of the conversion efficiency is possible by the addition of
the fly-back diode. Thought it is usually unnecessary. The effect is achieved in the condition where the oscillation frequency
is high or output voltage is lower. Select schottky barrier diode (SBD) that the forward current is as small as possible. In this
DC/DC control IC, the period for the electric current flows to fly back diode is limited to synchronous rectification period (60
ns 2) because of using the synchronous rectification method. Therefore, select the one that the electric current of fly back
diode doesn't exceed ratings of forward current surge peak (IFSM).Calculate the forward current surge peak ratings of fly
back diode by the following formula.
IL
2
IFSM ≥ IoMAX
IFSM
IoMAX
IL
: Forward current surge peak ratings of fly back diode [A]
: Maximum load current [A]
: Ripple current peak-to-peak value of inductor [A]
Calculate ratings of the fly-back diode by the following formula:
VR_Fly VIN
VR_Fly : Reverse voltage of fly-back diode direct current [V]
VIN
: Power supply voltage of switching system [V]
Document Number: 002-08376 Rev. *A
Page 32 of 50
MB39A136
Selection of output capacitor
This device supports a small ceramic capacitor of the ESR. The ceramic capacitor that is low ESR is an ideal to reduce the ripple
voltage compared with other capacitor. Use the tantalum capacitor and the polymer capacitor of the low ESR when a mass capacitor
is needed as the ceramic capacitor can not support. To the output voltage, the ripple voltage by the switching operation of DC/DC is
generated. Discuss the lower bound of output capacitor value according to an allowable ripple voltage. Calculate the output ripple
voltage from the following formula.
1
VO (
2×fOSC×CO
VO
ESR
IL
CO
fOSC
ESR) ×IL
: Switching ripple voltage [V]
: Series resistance component of output capacitor []
: Ripple current peak-to-peak value of inductor [A]
: Output capacitor value [F]
: Oscillation frequency [Hz]
Notes:
• The ripple voltage can be reduced by raising the oscillation frequency and the inductor value besides capacitor.
• Capacitor has frequency characteristic, the temperature characteristic, and the electrode bias characteristic, etc. The effective
capacitor value might become extremely small depending on the condition. Note the effective capacitor value in the condition.
Calculate ratings of the output capacitor by the following formula:
VCO VO
: Withstand voltage of the output capacitor [V]
: Output voltage [V]
VCO
VO
Note: Select the capacitor rating with withstand voltage allowing a margin enough for the output voltage.
In addition, use the allowable ripple current with an enough margin, if it has a rating.
Calculate an allowable ripple current of the output capacitor by the following formula:
Irms ≥
IL
23
Irms
IL
: Allowable ripple current (effective value) [A]
: Ripple current peak-to-peak value of inductor [A]
Document Number: 002-08376 Rev. *A
Page 33 of 50
MB39A136
Selection of input capacitor
Select the input capacitor whose ESR is as small as possible. The ceramic capacitor is an ideal. Use the tantalum capacitor and the
polymer capacitor of the low ESR when a mass capacitor is needed as the ceramic capacitor can not support. To the power supply
voltage, the ripple voltage by the switching operation of DC/DC is generated. Discuss the lower bound of input capacitor according to
an allowable ripple voltage. Calculate the ripple voltage of the power supply from the following formula.
VIN
IOMAX
CIN
×
VO
VIN × fOSC
ESR × (IOMAX
IL
2
)
VIN
: Switching system power supply ripple voltage peak-to-peak value [V]
IOMAX : Maximum load current value [A]
CIN
: Input capacitor value [F]
VIN
: Power supply voltage of switching system [V]
VO
: Output setting voltage [V]
fOSC
: Oscillation frequency [Hz]
ESR
: Series resistance component of input capacitor []
IL
: Ripple current peak-to-peak value of inductor [A]
Notes:
• The ripple voltage of the power supply can be reduced by raising the oscillation frequency besides capacitor.
• Capacitor has frequency characteristic, the temperature characteristic, and the electrode bias characteristic, etc. The effective
capacitor value might become extremely small depending on the condition. Note the effective capacitor value in the condition.
Calculate ratings of the input capacitor by the following formula:
VCIN VIN
VCIN
VIN
: Withstand voltage of the input capacitor [V]
: Power supply voltage of switching system [V]
Note: Select the capacitor rating with withstand voltage with margin enough for the input voltage.
In addition, use the allowable ripple current with an enough margin, if it has a rating.
Calculate an allowable ripple current by the following formula:
Irms ≥ IOMAX×
Irms
IOMAX
VIN
VO
VO × (VIN VO)
VIN
: Allowable ripple current (effective value) [A]
: Maximum load current value [A]
: Power supply voltage of switching system [V]
: Output voltage [V]
Document Number: 002-08376 Rev. *A
Page 34 of 50
MB39A136
Selection of boot strap diode
Select Schottky barrier diode (SBD), that forward current is as small as possible. The electric current that drives the gate of high-side
FET flows to SBD of the bootstrap circuit. Calculate the mean current by the following formula. Select it so as not to exceed the electric
current ratings.
ID ≥ Qg × fOSC
ID
Qg
fOSC
: Forward current [A]
: Total quantity of charge of gate on high-side FET [C]
: Oscillation frequency [Hz]
Calculate ratings of the boot strap diode by the following formula:
VR_BOOT VIN
VR_BOOT : Reverse voltage of boot strap diode direct current [V]
VIN
: Power supply voltage of switching system [V]
Selection of boot strap capacitor
To drive the gate of high-side FET, the bootstrap capacitor must have enough stored charge. Therefore, a minimum value as a target
is assumed the capacitor which can store electric charge 10 times that of the Qg on high-side FET. And select the boot strap capacitor.
CBOOT ≥ 10×
Qg
VB
CBOOT : Boot strap capacitor [F]
Qg
: Amount of gate charge on high-side FET [C]
VB
: VB voltage [V]
Calculate ratings of the boot strap capacitor by the following formula:
VCBOOT VB
VCBOOT : Withstand voltage of the boot strap capacitor [V]
VB
: VB voltage [V]
Document Number: 002-08376 Rev. *A
Page 35 of 50
MB39A136
Design of phase compensation circuit
Assume the phase compensation circuit of 1pole-1zero to be a standard in this device.
1pole-1zero phase compensation circuit
VO
Rc
R1
FB
Cc
+
To I Comp.
COMP
R2
INTREF
Error
Amp
As for crossover frequency (fCO) that shows the band width of the control loop of DC/DC. The higher it is, the more excellent the rapid
response becomes, however, the possibility of causing the oscillation due to phase margin shortage increases. Though this crossover
frequency (fCO) can be arbitrarily set, make 1/10 of the oscillation frequencies (fosc) a standard, and set it to the upper limit. Moreover,
set the phase margin at least to 30°C, and 45°C or more if possible as a reference.
Set the constants of Rc and Cc of the phase compensation circuit using the following formula as a target.
RC
(VIN VO) ALVCNV × RON_Main × fCO × 2 × CO × VO
VIN × fOSC × L × IOMAX
CC
CO × V O
RC × IOMAX
×R1
RC
CC
VIN
VO
fOSC
IOMAX
L
CO
RON_Main
R1
ALVCNV
: Phase compensation resistor value []
: Phase compensation capacitor value [F]
: Power supply voltage of switching system [V]
: Output setting voltage [V]
: Oscillation frequency [Hz]
: Maximum load current value [A]
: Inductor value [H]
: Output capacitor value [F]
: High-side FET ON resistance[]
: Output setting resistor value []
fCO
: Cross-over frequency (arbitrary setting) [Hz]
: Level converter voltage gain [V/V]
On-duty 50 : ALVCNV = 6.8
On-duty > 50 : ALVCNV = 13.6
Document Number: 002-08376 Rev. *A
Page 36 of 50
MB39A136
VB pin capacitor
2.2 F is assumed to be a standard, and when Qg of SWFET used is large, it is necessary to adjust it. To drive the gate of high-side
FET, the bootstrap capacitor must have enough stored charge. Therefore, a minimum value as a target is assumed the capacitor,
which can store electric charge 100 times that of the Qg of the SWFET. And select it.
CVB ≥ 100 ×
CVB
Qg
VB
Qg
VB
: VB pin capacitor value [F]
: Total amount of gate charge of 2 ch respectively: high-side FET and low-side FET [C]
: VB voltage [V]
Calculate ratings of the VB pin capacitor by the following formula:
VCVB VB
VCVB : Withstand voltage of the VB pin capacitor [V]
VB
: VB voltage [V]
Document Number: 002-08376 Rev. *A
Page 37 of 50
MB39A136
VB regulator
In the condition for which the potential difference between VCC and VB is insufficient, the decrease in the voltage of VB happens
because of power output on-resistance and load current (mean current of all external FET gate driving current and load current of
internal IC) of the VB regulator. Stop the switching operation when the voltage of VB decreases and it reaches threshold voltage
(VTHL1) of the under voltage lockout protection circuit. Therefore, set oscillation frequency or external FET or I/O potential difference
of the VB regulator using the following formula as a target when you use this IC.
VCC ≥ VB (VTHL1)
VCC
VB (VTHL1)
Qg
fOSC
ICC
RVB
(Qg × fOSC ICC) × RVB
: Power supply voltage [V] (VIN)
: Threshold voltage of VB under-voltage lockout protection circuit [V] (3.8 [V] Max )
: Total amount of gate charge of 2 ch respectively: high-side FET and low-side FET [C]
: Oscillation frequency [Hz]
: Power supply current [A] (4.7×103[A] =: Load current of VB (LDO) )
: VB output on-resistance [] (100 (The reference value at VCC 4.5 V) )
If the I/O potential difference is small, the problem can be solved by connecting the VB pin and the VCC pin.
The conditions of the input voltage range are as follows:
VIN input voltage ranges:
4.5 V
25 V
6.0 V
(1)
(3)
(1) For 4.5 V < VIN < 6.0 V
→ Connect VB pin to VCC.
(2) When the input voltage range steps over 6.0 V
→ Normal use (VCC to VB not connected)
(3) For 6.0 V VIN
→Normal use (VCC to VB not connected)
(2)
Note that if the I/O potential difference is not enough when used, use the actual machine to check carefully the operations at the
normal operation, start operation, and stop operation. In particular, care is needed when the input voltage range over 6 V.
Document Number: 002-08376 Rev. *A
Page 38 of 50
MB39A136
Power dissipation and the thermal design
As for this IC, considerations of the power dissipation and thermal design are not necessary in most cases because of its high
efficiency. However, they are necessary for the use at the conditions of a high power supply voltage, a high oscillation frequency, high
load, and the high temperature.
Calculate IC internal loss (PIC) by the following formula.
PIC VCC × (ICC Qg × fOSC)
PIC
VCC
ICC
Qg
fOSC
: IC internal loss [W]
: Power supply voltage (VIN) [V]
: Power supply current [A] (4.7 [mA] Max)
: All SWFET total quantity of charge for ch 2 [C] (Total with Vgs 5 V)
: Oscillation frequency[Hz]
Calculate junction temperature (Tj) by the following formula.
Tj Ta ja × PIC
Tj
Ta
ja
PIC
: Junction temperature [°C] (+150 [°C] Max)
: Ambient temperature [°C]
: TSSOP-24 Package thermal resistance (76°C/W)
: IC internal loss [W]
Handling of the pins when using a single channel
Although this device is a 2-channel DC/DC converter control IC, it is also able to be used as a 1-channel DC/DC converter by handling
the pins of the unused channel as shown in the following diagram.
CBx
COMPx
“Open”
FBx
DRVHx
“Open”
DRVLx
“Open”
CSx
CTLx
LXx
ILIMx
Note: x is the unused channel number.
Document Number: 002-08376 Rev. *A
Page 39 of 50
MB39A136
Board layout
Consider the points listed below and do the layout design.
■
Provide the ground plane as much as possible on the IC mounted face. Connect bypass capacitor connected with the VCC and VB
pins, and GND pin of the switching system parts with switching system GND (PGND). Connect other GND connection pins with
control system GND (AGND), and separate each GND, and try not to pass the heavy current path through the control system GND
(AGND) as much as possible. In that case, connect control system GND (AGND) and switching system GND (PGND) right under IC.
■
Connect the switching system parts as much as possible on the surface. Avoid the connection through the through-hole as much
as possible.
■
As for GND pins of the switching system parts, provide the through hole at the proximal place, and connect it with GND of internal layer.
■
Pay the most attention to the loop composed of input capacitor (CIN), SWFET, and fly-back diode (SBD). Consider making the current
loop as small as possible.
■
Place the boot strap capacitor (CBOOT1, CBOOT2) proximal to CBx and LXx pins of IC as much as possible.
■
This device monitors the voltage between drain and source on high-side FET as voltage between VCC and LX pins. Place the input
capacitor (CIN) and the high-side FET of each CH proximally as much as possible. Draw out the wiring to VCC pin from the proximal
place to the input capacitor of CH1 and CH2. As for the net of the LXx pin, draw it out from the proximal place to the source pin on
high-side FET. Moreover, a large electric current flows momentary in the net of the LXx pin. Wire the linewidth of about 0.8mm to
be a standard, as short as possible.
■
Large electric current flows momentary in the net of DRVHx and DRVLx pins connected with the gate of SWFET. Wire the linewidth
of about 0.8mm to be a standard, as short as possible.
■
By-pass capacitor (CVCC, CVREF, CVB) connected with VREF, VCC, and VB, and the resistor (RRT) connected with the RT pin should
be placed close to the pin as much as possible. Also connect the GND pin of the by-pass capacitor with GND of internal layer in the
proximal through-hole.
■
Consider the net connected with RT, FBx, and the COMPx pins to keep away from a Switching system parts as much as possible
because it is sensitive to the noise. Moreover, place the output voltage setting resistor and the phase compensation circuit element
connected with this net close to the IC as much as possible, and try to make the net as short as possible. In addition, for the internal
layer right under the installing part, provide the control system GND (AGND) of few ripple and few spike noises, or provide the ground
plane of the power supply voltage as much as possible.
Switching system parts : Input capacitor (CIN), SWFET, Fly-back diode (SBD), Inductor (L), Output capacitor (CO)
Note: x : Each channel number
Layout example of switching components
Layout example of IC
To the VCC pin
High-side FET
CBOOT1
1pin
Through-hole
High-side FET
CVCC
AGND
VIN
Through-hole
RRT
CIN
To the LX1 pin
PGND
Low-side
FET
Low-side FET
PGND
CVB
CVREF
To the LX2
pin
CIN
SBD (option)
SBD (option)
CO
CBOOT2
PGND
AGND
CO
L
L
Vo1
Vo2
AGND and PGND are connected right under IC.
Surface
Internal
layer
Document Number: 002-08376 Rev. *A
Output voltage
Vo1 feedback
Output voltage
Vo2 feedback
Page 40 of 50
MB39A136
14. Reference Data
CH1 Conversion Efficiency
CH2 Conversion Efficiency
Conversion Efficiency vs. Load Current
Conversion Efficiency vs. Load Current
100
CH1
VIN = 12 V
VO1 = 1.2 V
fosc = 300 kHz
Ta = + 25°C
95
90
85
Conversion Efficiency ()
Conversion Efficiency ()
100
80
PFM/PWM
75
70
Fixed PWM
65
60
0.01
0.1
1
CH2
VIN = 12 V
VO2 = 3.3 V
fosc = 300 kHz
Ta = + 25°C
95
90
85
PFM/PWM
80
75
Fixed PWM
70
65
60
0.01
10
Load Current IO1(A)
1
10
Load Current IO2 (A)
CH1 Load Regulation
Output Voltage vs. Load Current
CH2 Load Regulation
Output Voltage vs. Load Current
1.30
3.60
VIN = 12 V
VO1 = 1.2 V
MODE = VREF
fosc = 300 kHz
Ta = + 25°C
1.26
1.24
VIN = 12 V
VO2 = 3.3 V
MODE = VREF
fosc = 300 kHz
Ta = + 25°C
3.50
Output Voltage VO2(V)
1.28
Output Voltage VO1 (V)
0.1
1.22
1.20
1.18
1.16
1.14
3.40
3.30
3.20
3.10
1.12
1.10
3.00
0
1
2
3
Load Current IO1(A)
4
5
0
1
2
3
4
5
Load Current IO2 (A)
(Continued)
Document Number: 002-08376 Rev. *A
Page 41 of 50
MB39A136
(Continued)
CH1
Load Sudden Change Waveform
CH2
Load Sudden Change Waveform
IO1 : 1 A/div
2A
IO2 : 1 A/div
2A
0A
0A
100 μs/div
100 μs/div
VO1 : 200 mV/div (1.2 V offset)
VIN 12 V, VO1 1.2 V
IO1 0←→2 A, fOSC 300 kHz, Ta
25°C
VO2 : 200 mV/div (3.3 V offset)
VIN 12 V, VO2 3.3 V
IO2 0←→2 A, fOSC 300 kHz, Ta
CTL Startup Waveform
CTL Stop Waveform
CTL1, 2 : 5 V/div
CTL1, 2 : 5 V/div
VO2: 1 V/div
VO2: 1 V/div
VO1: 1 V/div
VO1: 1 V/div
1 ms/div
25°C
1 ms/div
VIN 12 V, fOSC 300 kHz, Ta 25°C, Soft-start setting time 3.0 ms
VO1 1.2 V, IO1 5 A (0.24 ) , VO2 3.3 V, IO2 5 A (0.66 )
Normal operation → Over current protection → Under voltage protection operation waveform
VO1 : 0.5 V/div
1
CS1 : 2 V/div
2
VIN 12 V
VO1 1.2 V
fOSC 300 kHz
Ta 25°C
LX1 : 10 V/div
3
IO1 : 10 A/div
4
500 μs/div
Normal operation
Over current
protection operation
Document Number: 002-08376 Rev. *A
Under voltage
protection operation
Page 42 of 50
MB39A136
15. Usage Precaution
1. Do not configure the IC over the maximum ratings.
If the IC is used over the maximum ratings, the LSI may be permanently damaged.
It is preferable for the device to be normally operated within the recommended usage conditions. Usage outside of these conditions
can have an adverse effect on the reliability of the LSI.
2. Use the device within the recommended operating conditions.
The recommended values guarantee the normal LSI operation under the recommended operating conditions.
The electrical ratings are guaranteed when the device is used within the recommended operating conditions and under the
conditions stated for each item.
3. Printed circuit board ground lines should be set up with consideration for common impedance.
4. Take appropriate measures against static electricity.
• Containers for semiconductor materials should have anti-static protection or be made of conductive material.
• After mounting, printed circuit boards should be stored and shipped in conductive bags or containers.
• Work platforms, tools, and instruments should be properly grounded.
• Working personnel should be grounded with resistance of 250 k to 1 M in series between body and ground.
5. Do not apply negative voltages.
The use of negative voltages below 0.3 V may make the parasitic transistor activated, and can cause malfunctions.
Document Number: 002-08376 Rev. *A
Page 43 of 50
MB39A136
16. Ordering Information
Part number
MB39A136PFT
Package
Remarks
24-pin plastic TSSOP
(FPT-24P-M09)
16.1 EV Board Ordering Information
Part number
MB39A136EVB-01
Document Number: 002-08376 Rev. *A
EV board version No.
Remarks
MB39A136EVB-01 Rev2.0
TSSOP-24
Page 44 of 50
MB39A136
17. RoHS Compliance Information Of Lead (Pb) Free Version
The LSI products of Cypress Semiconductor with “E1” are compliant with RoHS Directive, and has observed the standard of lead,
cadmium, mercury, Hexavalent chromium, polybrominated biphenyls (PBB), and polybrominated diphenyl ethers (PBDE). A product
whose part number has trailing characters “E1” is RoHS compliant.
17.1
Marking Format (Lead Free version)
39A136
XXXX
E1 XXX
INDEX
Document Number: 002-08376 Rev. *A
Lead Free version
Page 45 of 50
MB39A136
17.2 Labeling Sample (Lead free version)
Lead-free mark
JEITA logo
MB123456P - 789 - GE1
(3N) 1MB123456P-789-GE1
1000
(3N)2 1561190005 107210
JEDEC logo
G
Pb
QC PASS
PCS
1,000
MB123456P - 789 - GE1
2006/03/01
ASSEMBLED IN JAPAN
MB123456P - 789 - GE1
1/1
0605 - Z01A
1000
1561190005
The part number of a lead-free product has
the trailing characters “E1”.
Document Number: 002-08376 Rev. *A
“ASSEMBLED IN CHINA” is printed on the label
of a product assembled in China.
Page 46 of 50
MB39A136
18. MB39A136PFT Recommended Conditions Of Moisture Sensitivity Level
[Cypress Semiconductor Recommended Mounting Conditions]
Item
Condition
Mounting Method
IR (infrared reflow) , Manual soldering (partial heating method)
Mounting times
2 times
Storage period
Before opening
Please use it within two years after
Manufacture.
From opening to the 2nd
reflow
Less than 8 days
When the storage period after
opening was exceeded
Please process within 8 days
after baking (125°C, 24h)
Storage conditions
5°C to 30°C, 70RH or less (the lowest possible humidity)
[Mounting Conditions]
1. IR (infrared reflow)
260°C
255°C
Main heating
170 °C
to
190 °C
(b)
RT
(a)
“H” level : 260°C Max
(a) Temperature increase gradient
(b) Preliminary heating
(c) Temperature increase gradient
(d) Peak temperature
(d’) Main heating
(e) Cooling
(c)
(d)
(e)
(d')
: Average 1°C/s to 4°C/s
: Temperature 170°C to 190°C, 60 s to 180 s
: Average 1°C/s to 4°C/s
: Temperature 260°C Max; 255°C or more, 10 s or less
: Temperature 230°C or more, 40 s or less
or
Temperature 225°C or more, 60 s or less
or
Temperature 220°C or more, 80 s or less
: Natural cooling or forced cooling
Note: Temperature : on the top of the package body
2. Manual soldering (partial heating method)
Temperature at the tip of an soldering iron: 400°C max
Time: Five seconds or below per pin
Document Number: 002-08376 Rev. *A
Page 47 of 50
MB39A136
19. Package Dimensions
24-pin plastic TSSOP
Lead pitch
0.50 mm
Package width ×
package length
4.40 mm × 6.50 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.20 mm MAX
Weight
0.08 g
(FPT-24P-M09)
24-pin plastic TSSOP
(FPT-24P-M09)
Note 1) Pins width and pins thickness include plating thickness.
Note 2) Pins width do not include tie bar cutting remainder.
Note 3) #: These dimensions do not include resin protrusion.
# 6.50±0.10(.256±.004)
0.145±0.045
(.0057±.0018)
24
13
BTM E-MARK
# 4.40±0.10 6.40±0.20
(.173±.004) (.252±.008)
INDEX
Details of "A" part
+0.10
1.10 –0.15
+.004
(Mounting height)
.043 –.006
1
12
"A"
+0.07
0.50(.020)
0.20 –0.02
.008
+.003
–.001
0.13(.005)
M
0~8°
0.60±0.15
(.024±.006)
0.10±0.05
(Stand off)
(.004±.002)
0.10(.004)
C
2007-2010 FUJITSU SEMICONDUCTOR LIMITED F24032S-c-2-5
Document Number: 002-08376 Rev. *A
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Page 48 of 50
MB39A136
20. Major Changes
Spansion Publication Number: DS04-27262-4E
A change on a page is indicated by a vertical line drawn on the left side of that page.
Page
Section
Change Results
10
Electrical Characteristics
Revised the minimum value of “Maximum on-duty” in “Output Block [DRV]”:
72 →75
NOTE: Please see “Document History” about later revised information.
Document History
Document Title: MB39A136 2ch PFM/PWM DC/DC Converter IC with Synchronous Rectification
Document Number: 002-08376
Rev.
ECN No.
Orig. of
Change
Submission
Date
**
TAOA
01/10/2013
Migrated to Cypress and assigned document number 002-08376.
No change to document contents or format.
*A
5138039
TAOA
02/22/2016
Updated to Cypress template.
Document Number: 002-08376 Rev. *A
Description of Change
Page 49 of 50
MB39A136
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Wireless/RF
cypress.com/psoc
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation 2008-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
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Document Number: 002-08376 Rev. *A
Revised February 22, 2016
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