STMicroelectronics M440T1MV 3.3v, 32 mbit (1024 kbit x 32) timekeeper sram Datasheet

M440T1MV
3.3V, 32 Mbit (1024 Kbit x 32) TIMEKEEPER® SRAM
FEATURES SUMMARY
■
■
■
■
■
■
■
■
■
■
3.3V ± 10%
INTEGRATED ULTRA LOW POWER SRAM,
REAL TIME CLOCK, POWER-FAIL
CONTROL CIRCUIT, BATTERY, AND
CRYSTAL
PRECISION POWER MONITORING AND
POWER SWITCHING CIRCUITRY
AUTOMATIC WRITE-PROTECTION WHEN
VCC IS OUT-OF-TOLERANCE
POWER-FAIL DESELECT VOLTAGE:
– VCC = 3.0 to 3.6V; 2.8V ≤ VPFD ≤ 2.97V
BATTERY LOW PIN (BL)
DUAL BATTERY SNAPHAT® HOUSING IS
REPLACEABLE
85ns SRAM CHIP ENABLE ACCESS (70ns
ADDRESS ACCESS)
SLEEP MODE FUNCTION
150ns CLOCK ACCESS
October 2004
Figure 1. Package
M440T1MV
168-ball PBGA
Module
1/26
M440T1MV
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2.
Table 1.
Figure 3.
Figure 4.
Figure 5.
Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PBGA Connections (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M440T1MV Hardware Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M440T1MV PBGA Module Solution (Side/Top). . . . . . . . . . . . . . . .
......
......
......
......
......
......
......
......
......
......
.....4
.....4
.....5
.....6
.....7
OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Memory READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Clock READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2. Memory Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. Clock Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. Memory READ Mode AC Waveforms, Chip Enable- or Output Enable-Controlled . . . . . . 9
Figure 7. Memory READ Mode AC Waveforms, Address-Controlled . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 8. Clock READ Mode AC Waveforms, Chip Enable- or Output Enable-Controlled . . . . . . . 10
Figure 9. Clock READ Mode AC Waveforms, Address-Controlled. . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. Memory/Clock READ Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Memory WRITE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Clock WRITE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 10.Memory WRITE Mode AC Waveforms, WRITE Enable-Controlled . . . . . . . . . . . . . . . . 11
Figure 11.Memory WRITE Mode AC Waveforms, Chip Enable-Controlled . . . . . . . . . . . . . . . . . . 12
Figure 12.Clock WRITE Mode AC Waveforms, WRITE Enable-Controlled . . . . . . . . . . . . . . . . . . 12
Figure 13.Clock WRITE Mode AC Waveforms, Chip Enable-Controlled. . . . . . . . . . . . . . . . . . . . . 13
Table 5. Memory/Clock WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Clock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Reading and Setting the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Clock Alarm Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Watchdog Alarm Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 6. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 7. Time of Day Alarm Mask Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Battery Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Sleep Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 8. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2/26
M440T1MV
Table 9. DC and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 14.AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 10. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 11. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 15.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 12. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 13. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 16.PBGA-ZA – 168-ball Plastic Ball Grid Array Package Outline . . . . . . . . . . . . . . . . . . . . 22
Table 14. PBGA-ZA – 168-ball Plastic Ball Grid Array Package Mechanical Data . . . . . . . . . . . . . 23
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 15. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 16. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3/26
M440T1MV
SUMMARY DESCRIPTION
The M440T1MV TIMEKEEPER® RAM is a 16Mbit,
non-volatile static RAM organized as 1,024K by 32
bits and real time clock organized as 64 bytes by
8 bits. The special PBGA package provides a fully
integrated battery back-up memory and real time
clock solution. In the event of power instability or
absence, a self-contained battery maintains the
timekeeping operation and provides power for a
CMOS static RAM. Control circuitry monitors VCC
and invokes write protection to prevent data corruption in the memory and RTC.
The clock keeps track of tenths/hundredths of seconds, seconds, minutes, hours, day, date, month,
and year information. The last day of the month is
automatically adjusted for months with less than
31 days, including leap year correction.
The clock operates in one of two formats:
– a 12-hour mode with an AM/PM indicator; or
– a 24-hour mode
The M440T1MV is in a 168-ball PBGA module that
integrates the RTC, the battery, and SRAM in one
package.
Figure 2. Logic Diagram
Table 1. Signal Names
A0 - A19
Address Inputs
DQ0 - DQ31
NVRAM Data Input/Output
DQC0 - DQC7
Clock Data Input/Output
E1 - E4
NVRAM Chip Enable Inputs
EC
Clock Chip Enable Input
W1 - W4
NVRAM WRITE Enable Inputs
DQC0 – DQC7
WC
Clock WRITE Enable Input
BL
G
Output Enable Input
IRQ
GC
Clock Output Enable Input
RSV1
BL
Battery Low Output (Open
Drain)
IRQ
Interrupt Output (Open Drain)
RSV1
Reserved
RSV2
Reserved
NC
No Connect
VCC
Supply Voltage
VSS
Ground
VCC
A0 – A19
DQ0 – DQ31
E1 – E4
EC
W1 – W4
M440T1MV
WC
G
RSV2
GC
VSS
AI04200
4/26
M440T1MV
67
66
A9
A0
W4
A1
60
69
68
A11
A8
A4
VCC
71
70
E4
A10
63
72
GC
62
61
74
73
A2
A3
75
W2
E2
65
64
76
G
WC
78
77
EC
BL
E1
VCC
80
79
Figure 3. PBGA Connections (Top View)
1
A15
E3
59
2
A17
58
3
A13
DQ31
DQ30
4
A18
DQ29
5
W1
A16
W3
56
55
DQ28
54
7
8
A14
DQ27
53
A12
DQ24
52
9
A7
10
A6
DQ25
DQ26
51
50
6
M440T1MV
57
11
A5
DQ16
49
12
DQ7
48
13
DQ6
DQ5
DQ17
DQ18
DQ23
A19
DQ4
DQ22
45
44
14
15
16
17
RSV1
DQ0
47
46
43
DQC2
DQ10
DQ9
DQ8
DQ15
IRQ
DQ14
30
31
32
34
35
DQ11
VSS
DQC1
29
39
40
DQC0
28
DQ13
DQC7
27
36
DQC6
26
33
RSV2
24
25
22
23
20
21
DQ12
41
38
DQ19
37
DQ2
DQC5
19
DQC4
42
DQC3
DQ21
DQ20
DQ3
DQ1
VSS
18
AI04794
Note: This diagram is TOP VIEW perspective (view through package).
5/26
M440T1MV
VOUTA
E1CON
E
8
1M x 8
SRAM
1M x 8
SRAM
A0-A5
DQ8-DQ15
A0-A19
VCC
VCC
VCC
6
8
20
M48T224W
3.3V
20
A0-A19
DQ0-DQ7
Figure 4. M440T1MV Hardware Hookup
G
W
G
W1
E
G
W
G
W2
INTB/INTB
IRQ
G
E1
E1
E2
E2
E3
E3
E4
E4
BL
BL
20
GC
VOUTB
VCC
VCC
SLEEP
PAD
SLEEP
1M x 8
SRAM
8kΩ
VOUTA
THS
VSS
E3CON
E
DQ24-DQ31
W
8
WC
A0-A19
DQC0 - DQC7
20
DQ0 - DQ7
8
E
A0-A19
EC
DQ16-DQ23
E2CON
G
1M x 8
SRAM
W
E
G
W
G
W4
E4CON
G W3
AI04795
6/26
M440T1MV
Figure 5. M440T1MV PBGA Module Solution (Side/Top)
AI04628b
7/26
M440T1MV
OPERATION MODES
Memory READ Mode
The M440T1MV is in the 32-bit READ Mode whenever W1 - W4 (WRITE Enable Byte 1 to 4) are high
and E1 - E4 - Chip Enable Bytes 1 to 4 are low
(see Table 2., page 8). The unique address specified by the 20 address inputs defines which one of
the 1,048,576 long words of data is to be accessed. Valid data will be available at the Data I/O pins
within Address Access Time (tAVQV) after the last
address input signal is stable, providing the E1-4
and G access times are also satisfied. If the E1-4
and G access times are not met, valid data will be
available after the latter of the Chip Enable Access
Times (tELQV) or Output Enable Access Time
(tGLQV).
The state of the thirty-two three-state Data I/O signals is controlled by E1-4 and G. If the outputs are
activated before tAVQV, the data lines will be driven
to an indeterminate state until tAVQV. If the Address Inputs are changed while E1-4 and G remain active, output data will remain valid for
Output Data Hold Time (tAXQX) but will go indeterminate until the next Address Access.
Clock READ Mode
The clock is in the READ Mode whenever WC
(Clock WRITE Enable) is high and EC (Clock Chip
Enable) is low. The unique address specified by
the 6 Address Inputs defines which one of the 64
bytes of clock data is to be accessed. Valid data
will be available at the Data I/O pins (DQC0-7)
within Address Access Time (tAVQV) after the last
address input signal is stable, providing the EC
and GC access times are also satisfied. If the EC
and GC access times are not met, valid data will
be available after the latter of the Chip Enable Access Times (tELQV) or Output Enable Access Time
(tGLQV).
The state of the eight three-state Data I/O signals
is controlled by EC and G. If the outputs are activated before tAVQV, the data lines will be driven to
an indeterminate state until tAVQV. If the Address
Inputs are changed while EC and G remain active,
output data will remain valid for Output Data Hold
Time (tAXQX) but will go indeterminate until the
next Address Access. See section on Reading and
Setting the Clock under CLOCK OPERATION for
more details.
Table 2. Memory Operating Modes
Mode
VCC
Byte WRITE
E4
E3
E2
E1
G
W4
W3
W2
W1
H
H
H
L
H
X
X
X
L
DQ24- DQ16- DQ8- DQ0DQ31 DQ23 DQ15 DQ7
Hi-Z
Hi-Z
Hi-Z
Power
DIN
Active
Byte WRITE
H
H
L
H
H
X
X
L
X
Hi-Z
Hi-Z
DIN
Hi-Z
Active
Byte WRITE
H
L
H
H
H
X
L
X
X
Hi-Z
DIN
Hi-Z
Hi-Z
Active
Byte WRITE
L
H
H
H
H
L
X
X
X
DIN
Hi-Z
Hi-Z
Hi-Z
Active
Byte WRITE
X
X
X
L
H
H
H
H
L
Hi-Z
Hi-Z
Hi-Z
DIN
Active
Byte WRITE
X
X
L
X
H
H
H
L
H
Hi-Z
Hi-Z
DIN
Hi-Z
Active
Byte WRITE
X
L
X
X
H
H
L
H
H
Hi-Z
DIN
Hi-Z
Hi-Z
Active
Byte WRITE
L
X
X
X
H
L
H
H
H
DIN
Hi-Z
Hi-Z
Hi-Z
Active
L
L
L
L
H
L
L
L
L
DIN
DIN
DIN
DIN
Active
H
H
H
L
L
X
X
X
H
Hi-Z
Hi-Z
Hi-Z
DOUT
Active
Long Word
WRITE
2.97 to 3.6V
Byte READ
Byte READ
H
H
L
H
L
X
X
H
X
Hi-Z
Hi-Z
DOUT
Hi-Z
Active
Byte READ
H
L
H
H
L
X
H
X
X
Hi-Z
DOUT
Hi-Z
Hi-Z
Active
Byte READ
L
H
H
H
L
H
X
X
X
DOUT
Hi-Z
Hi-Z
Hi-Z
Active
Long Word
READ
L
L
L
L
L
H
H
H
H
DOUT
DOUT
DOUT
DOUT
Active
Deselect
H
H
H
H
X
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Stdby
CMOS
Standby
VSO to
Deselect
VPFD(min)(1)
X
X
X
X
X
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Deselect
≤ VSO(1)
X
X
X
X
X
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
Battery
Hi-Z Back-up
Mode
Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
1. See Table 12., page 20 for details.
8/26
M440T1MV
Table 3. Clock Operating Modes
VCC
Mode
EC
GC
WC
DQC0 - 7
VIH
X
X
Hi-Z
VIL
X
VIL
DIN
READ
VIL
VIL
VIH
DOUT
READ
VIL
VIH
VIH
Hi-Z
Deselect
WRITE
2.97 to 3.6V
VSO to
Deselect
VPFD(min)(1)
X
X
X
Hi-Z
Deselect
≤ VSO(1)
X
X
X
Hi-Z
Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
1. See Table 12., page 20 for details.
Figure 6. Memory READ Mode AC Waveforms, Chip Enable- or Output Enable-Controlled
tAVAV
A0-A19
VALID
tAVQV
tAXQX
tELQV
tEHQZ
E1 - E4
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ31
DATA OUT
AI05606
Figure 7. Memory READ Mode AC Waveforms, Address-Controlled
tAVAV
VALID
A0-A19
tAVQV
tAXQX
DQ0-DQ31
DATA VALID
DATA VALID
AI05607
9/26
M440T1MV
Figure 8. Clock READ Mode AC Waveforms, Chip Enable- or Output Enable-Controlled
tAVAV
A0-A5
VALID
tAVQV
tAXQX
tELQV
tEHQZ
EC
tELQX
tGLQV
tGHQZ
GC
tGLQX
DQC0-DQC7
DATA OUT
AI04653
Figure 9. Clock READ Mode AC Waveforms, Address-Controlled
tAVAV
VALID
A0-A5
tAVQV
tAXQX
DQC0-DQC7
DATA VALID
DATA VALID
AI04654
Table 4. Memory/Clock READ Mode AC Characteristics
M440T1MV
Parameter(1)
Symbol
Memory
Clock
–85
–15
Min
Max
Min
Unit
Max
tRC
tAVAV
READ Cycle Time
tACC
tAVQV
Address Valid to Output Valid
70
150
ns
tCO
tELQV
Chip Enable Low to Output Valid
85
150
ns
tOE
tGLQV
Output Enable Low to Output Valid
45
70
ns
tCEL
tELQX
Chip Enable Low to Output Transition
5
10
ns
tOEL
tGLQX
Output Enable Low to Output Transition
5
5
ns
85
150
ns
tCEZ
tEHQZ(2) Chip Enable High to Output Hi-Z
40
50
ns
tOEZ
tGHQZ(2) Output Enable High to Output Hi-Z
30
50
ns
tOH
tAXQX
Address Transition to Output Transition
5
5
Note: 1. Valid for Ambient Operating Temperature: TA = –15 to 75°C; VCC = 3.0 to 3.6V (except where noted).
2. CL = 5pF.
10/26
ns
M440T1MV
Clock WRITE Mode
The clock is in the WRITE Mode whenever WC
(Clock WRITE Enable) and EC (Clock Chip Enable) are in the low state after the address inputs
are stable. The start of a WRITE is referenced
from the latter occurring falling edge of WC or EC.
A WRITE is terminated by the earlier rising edge of
WC or EC. The addresses must be held valid
throughout the cycle. EC or WC must return high
for a minimum of tEHAX from Chip Enable Clock or
tWHAX from WRITE Enable Clock prior to the initiation of another READ or WRITE cycle. Data-in
must be valid tDVWH prior to the end of WRITE and
remain valid for tWHDX afterward. GC should be
kept high during WRITE cycles to avoid bus contention; although, if the output bus has been activated by a low on EC and GC a low on WC will
disable the outputs tWLQZ after WC falls. See section on Reading and Setting the Clock under
CLOCK OPERATION for more details.
Memory WRITE Mode
The M440T1MV is in the WRITE Mode whenever
any or all of W1-4 (WRITE Enable Byte 1 to 4) and
any corresponding E1-4 (Chip Enable Byte 1 to 4)
are in a low state after the address inputs are stable. Thus a Byte WRITE (8-bit), Word WRITE (16bit) or Long Word WRITE (32-bit) may be performed. The start of a WRITE is referenced from
the latter occurring falling edge of W1-4 or E1-4. A
WRITE is terminated by the earlier rising edge of
W1-4 or E1-4. The addresses must be held valid
throughout the cycle. E1-4 or W1-4 must return
high for a minimum of tEHAX from Chip Enable or
tWHAX from WRITE Enable prior to the initiation of
another READ or WRITE cycle. Data-in must be
valid tDVWH prior to the end of WRITE and remain
valid for tWHDX afterward. G should be kept high
during WRITE cycles to avoid bus contention; although, if the output bus has been activated by a
low on E1-4 and G, a low on W1-4 will disable the
outputs tWLQZ after W1-4 falls.
Figure 10. Memory WRITE Mode AC Waveforms, WRITE Enable-Controlled
tAVAV
A0-A19
VALID
tAVWH
tWHAX
tAVEL
E1 - E4
tWLWH
tAVWL
W1 - W4
tWHQX
tWLQZ
tWHDX
DQ0-DQ31
DATA INPUT
tDVWH
AI05608
Note: Output Enable (G) = Low
11/26
M440T1MV
Figure 11. Memory WRITE Mode AC Waveforms, Chip Enable-Controlled
tAVAV
VALID
A0-A19
tAVEH
tELEH
tAVEL
tEHAX
E1 - E4
tAVWL
W1 - W4
tWHDX
DATA INPUT
DQ0-DQ31
tDVWH
AI05609
Note: Output Enable (G) = High
Figure 12. Clock WRITE Mode AC Waveforms, WRITE Enable-Controlled
tAVAV
VALID
A0-A5
tAVWH
tWHAX
tAVEL
EC
tWLWH
tAVWL
WC
tWHQX
tWLQZ
tWHDX
DQC0-DQC7
DATA INPUT
tDVWH
AI04651
Note: Clock Output Enable (GC) = Low
12/26
M440T1MV
Figure 13. Clock WRITE Mode AC Waveforms, Chip Enable-Controlled
tAVAV
VALID
A0-A5
tAVEH
tAVEL
tELEH
tEHAX
EC
tAVWL
WC
tWHDX
DQC0-DQC7
DATA INPUT
tDVWH
AI04652
Note: Clock Output Enable (GC) = High
Table 5. Memory/Clock WRITE Mode AC Characteristics
M440T1MV
Symbol
Parameter(1)
Memory
Clock
–85
–15
Unit
Min
tWC
Max
Min
Max
tAVAV
WRITE Cycle Time
85
150
ns
tAVWL
Address Valid to WRITE Enable Low
0
0
ns
tAVEL
Address Valid to Chip Enable Low
0
0
ns
tWP
tWLWH
WRITE Enable Pulse Width
60
100
ns
tCEW
tELEH
Chip Enable Low to Chip Enable High
65
150
ns
tWHAX
WRITE Enable High to Address Transition
0
10
ns
tEHAX
Chip Enable High to Address Transition
15
10
ns
tDVWH
Input Valid to WRITE Enable High
35
50
ns
tDVEH
Input Valid to Chip Enable High
35
50
ns
tWHDX
WRITE Enable High to Input Transition
0
0
ns
tEHDX
Chip Enable High to Input Transition
15
0
ns
tAW
tWR
tDS
tDH
tWEZ
tOEW
tWLQZ(2,3) WRITE Enable Low to Output Hi-Z
30
50
ns
tAVWH
Address Valid to WRITE Enable High
70
150
ns
tAVEH
Address Valid to Chip Enable High
70
150
ns
WRITE Enable High to Output Transition
5
5
ns
tWHQX(3)
Note: 1. Valid for Ambient Operating Temperature: TA = –15 to 75°C; VCC = 3.0 to 3.6V (except where noted).
2. CL = 5pF.
3. If E1 - E4 and EC goes low simultaneously with W1 - W4 and WC going low, the outputs remain in the high impedance state.
13/26
M440T1MV
CLOCK OPERATION
Clock Registers
Registers 00h, 01h, 02h, 04h, 06h, 08h, 09h, and
0Ah contain the time of day data in BCD. Eleven
bits within these eight registers are not used and
will always read '0' regardless of how they are written. Bits 6 and 7 in the Months Register (09h) are
binary bits. When set to logic '0,' EOSC (Bit 7) enables the Real Time Clock oscillator. This bit will
normally be turned on by the user during device
initialization. However, the oscillator can be turned
on and off as necessary by setting this bit to the
appropriate level. Bit 6 of the Hours Register is defined as the 12- or 24-hour select bit. When set to
logic '1,' the 12-hour format is selected. In the 12hour format, Bit 5 is the AM/PM bit with logic '1' being PM. In the 24-hour mode, Bit 5 is the second
10-hour bit (20-23 hours). The Clock Registers are
updated every 0.01 seconds from the Real Time
Clock, except when the TE Bit (Bit 7 of Register
0Bh) is set low or the clock oscillator is not running.
Reading and Setting the Clock
The preferred method of synchronizing data access to and from the TIMEKEEPER® is to access
the Command Register by doing a WRITE cycle to
address location 0Bh and setting TE Bit (Transfer
Enable Bit) to a logic '0.' This will freeze the External Clock Registers at the present recorded time,
allowing access to occur without danger of simultaneous update. When the clock registers have
been read or written, a second WRITE cycle to location 0Bh and setting the TE Bit to a logic '1' will
put the Clock Registers back to being updated every 0.01 second. No time is lost in the Real Time
Clock because the internal copy of the Clock Register buffers is continually incremented while the
external memory registers are frozen. An alternate
method of reading and writing the Clock Registers
is to ignore synchronization. However, any single
READ may give erroneous data as the Real Time
Clock may be in the process of updating the external memory registers as data is being read. The internal copies of seconds through years are
incremented, and the time of day alarm is checked
during the period that hundreds of seconds reads
“99” to “00.” A way of making sure data is valid is
to do multiple READs and compare. Writing the
registers can also produce erroneous results for
the same reasons. A way of making sure that the
WRITE cycle has caused proper update is to do a
READ to verify and re-execute the WRITE cycle if
data is not correct. While the possibility of errone-
14/26
ous results from READ and WRITE cycles has
been stated, it is worth noting that the probability
of an incorrect result is kept to a minimum due to
the redundant structure of the TIMEKEEPER.
Clock Alarm Registers
Registers 03h, 05h, and 07h contain the Clock
Alarm Registers. Bits 3, 4, 5, and 6 of Register 07h
will always read '0' regardless of how they are written. Bit 7 of Registers 03h, 05h, and 07h are mask
bits (see Table 6., page 15). When all of the mask
bits are logic '0,' a Clock Alarm will only occur
when Registers 02h, 04h, and 06h match the values stored in Registers 03h, 05h, and 07h. An
alarm will be generated every day when Bit 7 of
Register 07h is set to a logic '1.' Similarly, an alarm
is generated every hour when Bit 7 of Registers
07h and 05h is set to a logic '1.' When Bit 7 of Registers 07h, 05h, and 03h is set to a logic '1,' an
alarm will occur every minute when Register 1
(seconds) rolls from “59” to “00.”
Clock Alarm Registers are written and read in the
same format as the Clock Registers. The Clock
Alarm Flag and Interrupt are always cleared when
alarm Registers are read or written.
Watchdog Alarm Registers
Registers 0Ch and 0Dh contain the time for the
watchdog alarm. The two registers contain a time
count from 00.01 to 99.99 seconds in BCD. The
value written into the Watchdog Alarm Registers
can be written or read in any order. Any access to
Register 0Ch or 0Dh will cause the watchdog
alarm to re-initialize and clears the Watchdog Flag
Bit and the Watchdog Interrupt Output. When a
new value is entered or the Watchdog Registers
are read, the watchdog timer will start counting
down from the entered value to zero. When zero is
reached, the Watchdog Interrupt Output will go to
the active state. The watchdog timer countdown is
interrupted and re-initialized back to the entered
value every time either of the registers are accessed. In this manner, controlled periodic accesses to
the watchdog timer can prevent the watchdog
alarm from going to an active level. If access does
not occur, the countdown alarm will be repetitive.
The Watchdog Alarm Registers always read the
entered value. The actual countdown register is internal and is not readable. Writing registers 0Ch
and 0Dh to '0' will disable the watchdog alarm feature.
M440T1MV
Table 6. Register Map
ADDRESS
BIT 0
BIT 7
0
CLOCK
CALENDAR/
TIME OF DAY
ALARM
REGISTERS
0.1 SECONDS
USER
REGISTERS
00-99
0
10 SECONDS
SECONDS
00-59
2
0
10 MINUTES
MINUTES
00-59
3
M
10 MIN ALARM
MIN ALARM
00-59
4
0
12/24
5
M
12/24
6
0
0
0
0
0
DAYS
01-07
7
M
0
0
0
0
DAY ALARM
01-07
8
0
0
EOSC
ESQW
A
WATCHDOG
ALARM
REGISTERS
0.01 SECONDS
1
9
COMMAND
REGISTER
RANGE
B
10
A/P
10
A/P
10
10
HR
HOURS
01-12+A/P
00-23
HR
HOURS ALARM
01-12+A/P
00-23
10DATE
10MO
0
10YEARS
TE
IPSW
IBH
PU
LO
LVL
WAM
DATE
01-31
MONTHS
01-12
YEARS
00-99
TDM
WAF
TDF
C
0.1 SECONDS
0.01 SECONDS
00-99
D
10 SECONDS
SECONDS
00-99
E - 3F
SRAM ADDRESS SPACE
AI04208
Table 7. Time of Day Alarm Mask Bits
Register
(03h) Minutes
(05h) Hours
(07h) Days
1
1
1
Alarm once per minute
0
1
1
Alarm when minutes match
0
0
1
Alarm when hours and minutes match
0
0
0
Alarm when hours, minutes, and days match
Note: Any other bit combinations of mask bit settings produce an illegal operation.
15/26
M440T1MV
Command Register
Address location 0Bh is the Command Register
where mask bits, control bits, and flag bits reside.
The operation of each bit is as follows:
TE - Bit 7 Transfer Enable. This bit, when set to
logic '0,' will disable the transfer of data between
internal and external clock registers. The contents
in the external clock registers are now frozen and
READs or WRITEs will not be affected with updates. This bit must be set to a logic '1' to allow updates.
IPSW - Bit 6 Interrupt Switch. When set to a
logic '1,' IRQ/(IRQ) is the Watchdog Alarm. When
set to a logic '0,' IRQ/(IRQ) is the time of day alarm
output.
IBH/LO - Bit 5 IRQ Sink or Source Current.
When this bit is set to a logic '1' and VCC is applied,
IRQ/(IRQ) will source current (see Table
11., page 19, IOH). When this bit is set to a logic
'0,' IRQ will sink current (see Table 11., page 19,
IOL).
PU/LVL - Bit 4 Interrupt Pulse Mode or Level
Mode. This bit determines whether the interrupt
will output a pulse or level signal. When set to a
logic '0,' IRQ/(IRQ) will be in the level mode. When
this bit is set to a logic '1,' the pulse mode is selected. IRQ/(IRQ) will either sink or source current, depending on the condition of Bit 5, for a minimum of
3ms and then release. IRQ will only source current
when there is voltage present on VCC.
WAM - Bit 3 Watchdog Alarm Mask. When this
bit is set to a logic '0,' the watchdog interrupt output
will be activated. The activated state is determined
by bits 1, 4, 5, and 6 of the Command Register.
when this bit is set to a logic '1,' the watchdog interrupt output is deactivated.
TDM - Bit 2 Time of Day Alarm Mask. When
this bit is set to a logic '0,' the time of day alarm interrupt output will be activated. The activated state
is determined by bits 0, 4, 5, and 6 of the Command Register. When this bit is set to a logic '1,'
the time of day alarm interrupt output is deactivated.
WAF - Bit 1 Watchdog Alarm Flag. This bit is
set to a logic '1' when a watchdog alarm interrupt
occurs. This bit is “Read only.” The bit is reset
when any of the watchdog alarm registers are accessed.
When the interrupt is in the pulse mode (see PU/
LVL - Bit 4 Interrupt Pulse Mode or Level Mode),
this flag will be in the logic '1' state only during the
time the interrupt is active.
TDF - Bit 0 Time of Day Flag. This is a “Read
only” bit. This bit is set to a logic '1' when a time of
day alarm has occurred. the time the alarm occurred can be determined by reading the time of
16/26
day alarm registers. This bit is reset to a logic '0'
state when any of the time of day registers are accessed.
When the interrupt is in the pulse mode (see PU/
LVL - Bit 4 Interrupt Pulse Mode or Level Mode),
this flag will be in the logic '1' state only during the
time the interrupt is active.
Battery Low
The M440T1MV automatically performs battery
voltage monitoring upon power-up, and at factoryprogrammed time intervals of at least 24 hours.
The Battery Low (BL) signal will be asserted if the
battery voltage is found to be less than approximately 2.5V. The BL signal will remain asserted
until completion of battery replacement and subsequent battery low monitoring tests, either during
the next power-up sequence or the next scheduled
24-hour interval (see application note, “AN1540,
NVRAM PBGA Dual Battery Hat Mounting and
Removal” for more information).
If a battery low is generated during a power-up sequence, this indicates that one of the batteries is
below 2.5V and may not be able to maintain data
integrity in the SRAM. Data should be considered
suspect, and verified as correct. Fresh batteries
should be installed.
If a battery low indication is generated during the
24-hour interval check, this indicates that the battery is near end of life. However, data is not compromised due to the fact that a nominal VCC is
supplied. In order to insure data integrity during
subsequent periods of battery back-up mode, the
batteries should be replaced. The SNAPHAT® top
should be replaced with valid VCC applied to the
device.
The M440T1MV only monitors the batteries when
a nominal VCC is applied to the device. Thus applications which require extensive durations in the
battery back-up mode should be powered-up periodically (at least once every few months) in order
for this technique to be beneficial. Additionally, if a
battery low is indicated, data integrity should be
verified upon power-up via a checksum or other
technique. The BL signal is an open drain output
and an appropriate pull-up resistor should be chosen to control the rise time.
Sleep Mode
Forcing the sleep pad more positive than +7.5V
above ground will cause the batteries to be isolated from the RAM, preserving the remaining battery
life. This mode may be used when device operation is not necessary for an extended period of
time.
Note: Implementation of this Sleep Mode will result in complete loss of data.
M440T1MV
MAXIMUM RATINGS
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicated in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability.
Refer
also
to
the
STMicroelectronics SURE Program and other relevant quality documents.
Table 8. Absolute Maximum Ratings
Symbol
Value
Unit
Operating Temperature
–15 to 75
°C
TSTG
Storage Temperature (VCC, Oscillator Off)
–40 to 85
°C
TSLD
Lead Solder Temperature for 10 seconds
260
°C
VCC
Supply Voltage (on any pin relative to Ground)
–0.3 to + 4.6
V
VIO
Input or Output Voltages
–0.3 to VCC + 0.3
V
TA
Parameter
IO
Output Current
20
mA
PD
Power Dissipation
1
W
CAUTION! Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up Mode
17/26
M440T1MV
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. Designers should check that the operating conditions
in their projects match the measurement conditions when using the quoted parameters.
Table 9. DC and AC Measurement Conditions
Parameter
M440T1MV
VCC Supply Voltage
3.0 to 3.6V
Ambient Operating Temperature
–15 to 75°C
Load Capacitance (CL)
30pF
Input Rise and Fall Times
≤ 5ns
Input Pulse Voltages
0 to 3V
Input and Output Timing Ref. Voltages
1.5V
Note: Output Hi-Z is defined as the point where data is no longer driven.
Figure 14. AC Testing Load Circuit
645Ω
DEVICE
UNDER
TEST
CL = 30 pF
1.75V
AI05605
Table 10. Capacitance
CIN
COUT(3)
CIO(3)
M440T1MV
Parameter(1,2)
Symbol
Unit
Min
A0 - A5
50
pF
A6 - A19, G
40
pF
All Other Inputs
10
pF
Output Capacitance (BL)
10
pF
Input / Output Capacitance
10
pF
Input Capacitance
Note: 1. Effective capacitance measured with power supply at 3V; sampled only; not 100% tested.
2. At 25°C, f = 1MHz.
3. Outputs were deselected.
18/26
Max
M440T1MV
Table 11. DC Characteristics
Sym
Parameter
ILI
Input Leakage Current
ILO
Output Leakage Current
ICC1
Supply Current
ICC2
Supply Current (TTL Standby)
ICC3
VCC Power Supply Current
VIL(2)
Input Low Voltage
VIH(2)
Input High Voltage
VOL
VOH
M440T1MV
Unit
Min
Typ
Max
0V ≤ VIN ≤ VCC
±4
µA
0V ≤ VOUT ≤ VCC
±4
µA
210
mA
E1 - E4,
EC = VIH
5
12
mA
E1 - E4,
EC = VCCI – 0.2
2
3
mA
–0.3
0.6
V
2.2
VCC + 0.3
V
Output Low Voltage
IOL = 2.0mA
0.4
V
Output Low Voltage (Open drain)(3)
IOL = 10mA
0.4
V
Output High Voltage
VPFD(2) Power Fail Deselect
VSO(2)
Test Condition(1)
Battery Back-up Switchover
IOH = –1.0mA
2.2
V
2.80
2.97
2.5
V
V
Note: 1. Valid for Ambient Operating Temperature: TA = –15 to 75°C; VCC = 3.0 to 3.6V (except where noted).
2. All voltages are referenced to Ground.
3. For BL and IRQ (Open drain); if pulled-up to supply other than VCC, this supply must be equal to, or less than 3.0V when VCC = 0V
(during battery back-up mode).
19/26
M440T1MV
Data Retention Mode
Should the supply voltage decay, the RAM will automatically deselect, write protecting itself when
VCC falls between VPFD (max), VPFD (min) window. All outputs become high impedance and all
inputs are treated as “Don't care.”
Note: A power failure during a WRITE cycle may
corrupt data at the current addressed location, but
does not jeopardize the rest of the RAM's content.
At voltages below VPFD (min), the memory will be
in a write protected state, provided the VCC fall
time is not less than tF. The M440T1MV may respond to transient noise spikes on VCC that cross
into the deselect window during the time the device is sampling VCC.Therefore, decoupling of the
power supply lines is recommended. When VCC
drops below VSO, the control circuit switches power to the internal battery, preserving data and powering the clock. The internal energy source will
maintain data in the M440T1MV for an accumulated period of 5 years at 45°C. As system power rises above VSO, the battery is disconnected, and the
power supply is switched to external VCC. Write
protection continues until VCC reaches VPFD (min)
plus tER (min). Normal RAM operation can resume
tER after VCC exceeds VPFD (max). Refer to Application Note (AN1012) on the ST Web Site for more
information on battery life.
Figure 15. Power Down/Up Mode AC Waveforms
VCC
VPFD (max)
VPFD (min)
VSO
VSS
tF
tDR
tR
tRB
tFB
INPUTS
RECOGNIZED
tREC
DON'T CARE
RECOGNIZED
HIGH-Z
OUTPUTS
VALID
VALID
AI04792
Table 12. Power Down/Up Trip Points DC Characteristics
Symbol
Parameter(1,2)
VPFD
Power-fail Deselect Voltage
VSO
Battery Back-up Switchover Voltage
tDR(3)
Expected Data Retention Time
M440T1MV
Unit
Min
Typ
Max
2.8
2.9
2.97
2.5
5
Note: 1. Valid for Ambient Operating Temperature: TA = –15 to 75°C; VCC = 3.0 to 3.6V (except where noted).
2. All voltages referenced to VSS.
3. At 45°C, VCC = 0V.
20/26
V
V
YEARS
M440T1MV
Table 13. Power Down/Up AC Characteristics
Symbol
Parameter(1)
Min
Max
Unit
tF(2)
VPFD (max) to VPFD (min) VCC Fall Time
300
µs
tFB(3)
VPFD (min) to VSS VCC Fall Time
10
µs
tR
VPFD (min) to VPFD (max) VCC Rise Time
10
µs
tRB
VSS to VPFD (min) VCC Rise Time
1
µs
Power-up Deselect Time
40
tREC
200
ms
Note: 1. Valid for Ambient Operating Temperature: TA = –15 to 75°C; VCC = 3.0 to 3.6V (except where noted).
2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after VCC passes VPFD (min).
3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
21/26
M440T1MV
PACKAGE MECHANICAL INFORMATION
Figure 16. PBGA-ZA – 168-ball Plastic Ball Grid Array Package Outline
A3
A
B
E
A
A1
A2
HE
B
D B
45˚
GD
B3
B2
B1
TOP VIEW
GE
FD
SIDE VIEW
e
E5
ddd C
Non-plated
thru holes
1
BALL 1
CORNER
D3
eee S C A S B S
fff S C
b
b
D D1
D2
e
SOLDER BALL (Typ)
DETAIL A
Fiducial and
Soldermask
opening (3X)
e
E4
Detail A
E1
E2
FE
0.20 (4X)
E3
E
BOTTOM VIEW
Note: Drawing is not to scale.
22/26
PBGA-Z04
M440T1MV
Table 14. PBGA-ZA – 168-ball Plastic Ball Grid Array Package Mechanical Data
mm
inches
Symb
Typ
Min
Max
Typ
Min
Max
A
11.64
11.24
12.04
0.458
0.443
0.474
A1
6.60
6.30
6.90
0.260
0.248
0.272
A2
1.50
1.40
1.60
0.059
0.055
0.063
A3
9.25
9.00
9.50
0.364
0.354
0.374
B
44.40
44.30
44.50
1.748
1.744
1.752
B1
36.60
36.50
36.70
1.441
1.437
1.445
B2
28.25
28.15
28.35
1.112
1.108
1.116
B3
23.10
23.00
23.20
0.909
0.906
0.913
b
0.76
0.71
0.81
0.030
0.028
0.032
D
44.50
44.30
44.70
1.752
1.744
1.760
D1
27.94
D2
40.00
39.80
40.20
1.575
1.567
1.583
D3
20.56
20.46
20.66
0.809
0.806
0.813
e
1.27
E
44.50
1.744
1.760
E1
22.86
0.900
E2
28.40
1.118
E3
40.00
39.80
40.20
1.575
1.567
1.583
E4
15.75
15.65
15.85
0.620
0.616
0.624
E5
14.38
14.28
14.48
0.566
0.562
0.570
FD
8.28
8.08
8.48
0.326
0.318
0.334
FE
10.82
10.72
10.92
0.426
0.422
0.430
GD
0.85
0.65
1.05
0.033
0.026
0.041
GE
1.00
HE
1.32
0.044
0.060
n
1.100
0.050
44.30
44.70
1.752
0.039
1.12
1.52
0.052
168
168
Tolerance
Tolerance
ddd
0.15
0.006
eee
0.25
0.010
fff
0.10
0.004
23/26
M440T1MV
PART NUMBERING
Table 15. Ordering Information Scheme
Example:
M440T
1MV
–15
ZA
9
Device Type
M440T
Supply Voltage and Write Protect Voltage
1MV = VCC = 3.0 to 3.6V; VPFD = 2.8 to 2.97V
Speed
–15 = 150ns
Package(1)
ZA = 168-ball Ball Grid Array
Temperature Range
9 = –15 to 75 °C
Note: 1. Where “Z” is the symbol for PBGA packages and “A” denotes 1.27mm ball pitch
For other options, or for more information on any aspect of this device, please contact the ST Sales Office
nearest you.
24/26
M440T1MV
REVISION HISTORY
Table 16. Document Revision History
Date
Version
Revision Details
September 2002
1.0
First issue
16-Jan-03
1.1
Modify mechanical data (Table 14)
31-Mar-03
1.2
Update test condition (Table 12)
11-Apr-03
2.0
Updated with template v2.2
05-Oct-04
3.0
Reformatted; update mechanical dimensions (Figure 16; Table 14)
25/26
M440T1MV
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2004 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
26/26