AD ADL5246ACPZN-R7 3 ghz variable gain lna with integrated â½ w driver amplifier Datasheet

3 GHz Variable Gain LNA with Integrated
½ W Driver Amplifier
ADL5246
Data Sheet
FEATURES
GENERAL DESCRIPTION
RF output frequency range: 0.6 GHz to 3 GHz
Output IP3: 37 dBm at 2.2 GHz
Output P1dB: 28 dBm at 2.2 GHz
Noise figure of input amplifier: 1 dB at 2.2 GHz
Maximum gain: 31.5 dB at 2.2 GHz
Voltage variable attenuation range: 45 dB
0 V to 3.3 V attenuation control range
Integrated bypass switch for low noise VGA
Matched 50 Ω input stage
3.3 V to 5 V single supply
32-lead, 5 mm × 5 mm LFCSP package
The ADL5246 is a high performance, low noise variable gain
amplifier (VGA) optimized for multistandard base station receivers
and point to point receive (Rx) and transmit (Tx) applications. The
low noise figure and excellent linearity performance allow the
device to be used in a variety of applications.
The device consists of a low noise amplifier, a high linearity
VGA, and a ½ W output driver stage. The variable attenuator
networks are optimized to provide high linearity performance
over the 45 dB gain control range. Gain is set using a unipolar
control voltage from 0 V to 3.3 V. The output stage of the ADL5246
is an externally tuned ½ W driver amplifier, which allows the
device to be optimized anywhere between the 0.6 GHz to 3 GHz
range, with an average tuning bandwidth of 200 MHz wide. An
external filter can be used between the VGA and the final driver
amplifier. The ADL5246 can be biased between 3.3 V and 5 V to
trade off between performance and power consumption.
APPLICATIONS
Multistandard radio receivers
Point to point Rx and Tx
Instrumentation
Military and aerospace
The ADL5246 is fabricated on an advanced GaAs process. The
device is available in a 32-lead, RoHS compliant, 5 mm × 5 mm
LFCSP and thermally rated to operate over the −40°C to +105°C
temperature range.
RFIN2
VGAIN1
VSW1
VSW1
VGAIN2
RFOUT2
RFIN3
VPOS1
VPOS2
FUNCTIONAL BLOCK DIAGRAM
30
15
6
13
16
18
21
11
28
RFOUT1 32
AMP3
AMP1
VVA1
RFOUT3
VVA2
2
AMP2
4
5
7
8
9
12 14 17 19 22
ADL5246
1
3
10 20 23 24 25 27 29 31
EP
NIC
GND
12233-001
RFIN1
26
Figure 1.
Rev. A
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ADL5246
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Terminology .................................................................................... 22
Applications ....................................................................................... 1
Theory of Operation ...................................................................... 23
General Description ......................................................................... 1
Basic Connections ...................................................................... 23
Functional Block Diagram .............................................................. 1
Error Vector Magnitude (EVM) Performance ........................... 27
Revision History ............................................................................... 2
Thermal Information and Recommended PCB Land Pattern ...28
Specifications..................................................................................... 3
Full Chain Operation Considerations ..................................... 28
Absolute Maximum Ratings............................................................ 8
Evaluation Board ............................................................................ 29
Thermal Resistance ...................................................................... 8
Characterization Information ....................................................... 33
ESD Caution .................................................................................. 8
Outline Dimensions ....................................................................... 34
Pin Configuration and Function Descriptions ............................. 9
Ordering Guide .......................................................................... 34
Typical Performance Characteristics ........................................... 10
REVISION HISTORY
9/15—Rev. 0 to Rev. A
Changes to Table 1 ............................................................................ 5
Added Figure 21 to Figure 26; Renumbered Sequentially ........ 13
Added Figure 27 to Figure 32........................................................ 14
Added Figure 33 to Figure 38........................................................ 15
Changes to Figure 57, Figure 58, Figure 59 ................................. 19
Changes to Full Chain Operation Considerations Section ....... 28
4/14—Revision 0: Initial Version
Rev. A | Page 2 of 36
Data Sheet
ADL5246
SPECIFICATIONS
VPOS = 5 V, TA = 25°C, unless otherwise noted. Amplifier 1 = AMP1, Amplifier 2 = AMP2, and Amplifier 3 = AMP3.
Table 1.
Parameter
OVERALL FUNCTION
Frequency Range
AMP1 FREQUENCY = 0.75 GHz
Gain
vs. Frequency
vs. Temperature
vs. Supply
Input Return Loss
Output Return Loss
Output 1 dB Compression
Point
Output Third Order Intercept
Noise Figure
AMP1 FREQUENCY = 0.9 GHz
Gain
vs. Frequency
vs. Temperature
vs. Supply
Input Return Loss
Output Return Loss
Output 1 dB Compression
Point
Output Third Order Intercept
Noise Figure
AMP1 FREQUENCY = 1.5 GHz
Gain
vs. Frequency
vs. Temperature
vs. Supply
Input Return Loss
Output Return Loss
Output 1 dB Compression
Point
Output Third Order Intercept
Noise Figure
AMP1 FREQUENCY = 1.9 GHz
Gain
vs. Frequency
vs. Temperature
vs. Supply
Input Return Loss
Output Return Loss
Output 1 dB Compression
Point
Output Third Order Intercept
Noise Figure
Test Conditions/Comments
Min
3.3 V
Typ
0.6
5V
Max
Min
3
0.6
Typ
Max
Unit
3
GHz
RFIN1 and RFOUT1 pins
±50 MHz
−40°C ≤ TA ≤ +105°C
3.135 V to 3.465 V, 4.75 V to 5.25 V
S11
S22
∆f = 1 MHz, POUT = 0 dBm/tone
19.5
±0.3
±0.6
±0.1
−21
−9
18.5
20
±0.3
±0.5
±0.05
−22
−9
21.5
dB
dB
dB
dB
dB
dB
dBm
31
1.4
34.5
1.5
dBm
dB
19
±0.4
±0.5
±0.1
−21
−11
19
18.5
±0.4
±0.5
±0.05
−24
−10
22
dB
dB
dB
dB
dB
dB
dBm
32
0.9
35
1.2
dBm
dB
15
±0.7
±0.4
±0.1
−14.5
−14
19
14.5
±0.4
±0.5
±0.1
−16
−12
22.5
dB
dB
dB
dB
dB
dB
dBm
33
0.8
37
0.85
dBm
dB
12.5
±0.5
±0.5
±0.1
−13
−14
19
13
±0.5
±0.5
±0.05
−14
−12
22.5
dB
dB
dB
dB
dB
dB
dBm
34
0.9
37.5
0.9
dBm
dB
RFIN1 and RFOUT1 pins
±50 MHz
−40°C ≤ TA ≤ +105°C
3.135 V to 3.465 V, 4.75 V to 5.25 V
S11
S22
∆f = 1 MHz, POUT = 0 dBm/tone
RFIN1 and RFOUT1 pins
±100 MHz
−40°C ≤ TA ≤ +105°C
3.135 V to 3.465 V, 4.75 V to 5.25 V
S11
S22
∆f = 1 MHz, POUT = 0 dBm/tone
RFIN1 and RFOUT1 pins
±100 MHz
−40°C ≤ TA ≤ +105°C
3.135 V to 3.465 V, 4.75 V to 5.25 V
S11
S22
∆f = 1 MHz, POUT = 0 dBm/tone
Rev. A | Page 3 of 36
ADL5246
Parameter
AMP1 FREQUENCY = 2.2 GHz
Gain
vs. Frequency
vs. Temperature
vs. Supply
Input Return Loss
Output Return Loss
Output 1 dB Compression
Point
Output Third Order Intercept
Noise Figure
AMP1 FREQUENCY = 2.6 GHz
Gain
vs. Frequency
vs. Temperature
vs. Supply
Input Return Loss
Output Return Loss
Output 1 dB Compression
Point
Output Third Order Intercept
Noise Figure
AMP2 FREQUENCY = 0.75 GHz
Gain
vs. Frequency
vs. Temperature
Gain Range
Input Return Loss
Output Return Loss
Input 1 dB Compression
Point
Input Third Order Intercept
Noise Figure
AMP2 FREQUENCY = 0.9 GHz
Gain
vs. Frequency
vs. Temperature
Gain Range
Input Return Loss
Output Return Loss
Input 1 dB Compression
Point
Input Third Order Intercept
Noise Figure
Data Sheet
Test Conditions/Comments
RFIN1 and RFOUT1 pins
Min
±100 MHz
−40°C ≤ TA ≤ +105°C
3.135 V to 3.465 V, 4.75 V to 5.25 V
S11
S22
∆f = 1 MHz, POUT = 0 dBm/tone
3.3 V
Typ
5V
Max
Min
Typ
Max
Unit
11
±0.5
±0.5
±0.05
−11
−15
19
11.5
±0.5
±0.5
±0.05
−12
−12
22.3
dB
dB
dB
dB
dB
dB
dBm
34
1
37.5
1
dBm
dB
10
±0.4
±0.4
±0.05
−10
−17
19.5
10
±0.5
±0.5
±0.05
−11
−13
22.5
dB
dB
dB
dB
dB
dB
dBm
34
1.2
37.4
1.2
dBm
dB
12.5
±0.4
+3 to −4
15
−10
−29
2
16
±0.4
+0.5 to −2
60
−9
−16
4.5
dB
dB
dB
dB
dB
dB
dBm
13
4.5
15
3.5
dBm
dB
11.5
±0.5
+2.5 to −4
15
−9.5
−21
3.5
14.5
±0.5
+0.5 to −2
60
−9
−15
5.5
dB
dB
dB
dB
dB
dB
dBm
14
4.2
15.5
3.2
dBm
dB
RFIN1 and RFOUT1 pins
±100 MHz
−40°C ≤ TA ≤ +105°C
3.135 V to 3.465 V, 4.75 V to 5.25 V
S11
S22
∆f = 1 MHz, POUT = 0 dBm/tone
RFIN2 to RFOUT2 at maximum gain
±50 MHz
−40°C ≤ TA ≤ +105°C
HG mode
∆f = 1 MHz, PIN = −5 dBm/tone
RFIN2 to RFOUT2 at maximum gain
±50 MHz
−40°C ≤ TA ≤ +105°C
HG mode
∆f = 1 MHz, PIN = −5 dBm/tone
Rev. A | Page 4 of 36
Data Sheet
Parameter
AMP2 FREQUENCY = 1.5 GHz
Gain
vs. Frequency
vs. Temperature
Gain Range
Input Return Loss
Output Return Loss
Input 1 dB Compression
Point
Input Third Order Intercept
Noise Figure
AMP2 FREQUENCY = 1.9 GHz
Gain
vs. Frequency
vs. Temperature
Gain Range
Input Return Loss
Output Return Loss
Input 1 dB Compression
Point
Input Third Order Intercept
Noise Figure
AMP2 FREQUENCY = 2.2 GHz
Gain
vs. Frequency
vs. Temperature
Gain Range
Input Return Loss
Output Return Loss
Input 1 dB Compression
Point
Input Third Order Intercept
Noise Figure
AMP2 FREQUENCY = 2.6 GHz
Gain
vs. Frequency
vs. Temperature
Gain Range
Input Return Loss
Output Return Loss
Input 1 dB Compression
Point
Input Third Order Intercept
Noise Figure
AMP2 GAIN SETTLING, 0.9 GHz
Full Range Step, VGAIN1 or
VGAIN2
0 to 3.3 V
3.3 to 0 V
0.5 VGAIN Step
HG to LG Transition
LG to HG Transition
ADL5246
Test Conditions/Comments
RFIN2 to RFOUT2 at maximum gain
Min
±100 MHz
−40°C ≤ TA ≤ +105°C
HG mode
∆f = 1 MHz, PIN = −5 dBm/tone
3.3 V
Typ
5V
Max
Min
Typ
Max
Unit
7.5
±0.6
+2.5 to −4
14.5
−9
−12
7
10
±0.7
+0.5 to −2
50
−10
−10
8
dB
dB
dB
dB
dB
dB
dBm
18.5
4.2
19.5
3.2
dBm
dB
5
±0.6
+2.5 to −4
14
−9
−10
9
7.5
±0.6
+0.5 to −2
48
−10
−8
10
dB
dB
dB
dB
dB
dB
dBm
20.5
4.6
21.5
3.6
dBm
dB
3.5
±0.5
+2 to −3
13.5
−9
−8
11
5.5
±0.5
+0.5 to −2
45
−10
−7
11
dB
dB
dB
dB
dB
dB
dBm
22.5
5.1
23
4.2
dBm
dB
1.5
±0.5
+2 to −3
13
−9
−7.5
14
3.7
±0.5
+0.3 to −3
42
−10
−6.5
13.5
dB
dB
dB
dB
dB
dB
dBm
24
5.3
24.5
4.3
dBm
dB
2
4
4
1
3
3
µs
µs
µs
0.3
0.2
0.2
0.1
µs
µs
RFIN2 to RFOUT2 at maximum gain
±100 MHz
−40°C ≤ TA ≤ +105°C
HG mode
∆f = 1 MHz, PIN = −5 dBm/tone
RFIN2 to RFOUT2 at maximum gain
±100 MHz
−40°C ≤ TA ≤ +105°C
HG mode
∆f = 1 MHz, PIN = −5 dBm/tone
RFIN2 to RFOUT2 at maximum gain
±100 MHz
−40°C ≤ TA ≤ +105°C
HG mode
∆f = 1 MHz, PIN = –5 dBm/tone
RFIN2 to RFOUT2
1 dB settling, HG mode
HG mode, VGAIN1 = 2.0 to 1.5 V, 1 dB
settling
VGAIN1 = VGAIN2 = 0 V, 1 dB settling
VGAIN1 = VGAIN2 = 0 V, 1 dB settling
Rev. A | Page 5 of 36
ADL5246
Parameter
AMP3 FREQUENCY = 0.75GHz
Gain
vs. Frequency
vs. Temperature
vs. Supply
Input Return Loss
Output Return Loss
Output 1 dB Compression
Point
Output Third Order Intercept
Noise Figure
AMP3 FREQUENCY = 0.9 GHz
Gain
vs. Frequency
vs. Temperature
vs. Supply
Input Return Loss
Output Return Loss
Output 1 dB Compression
Point
Output Third Order Intercept
Noise Figure
AMP3 FREQUENCY = 1.9 GHz
Gain
vs. Frequency
vs. Temperature
vs. Supply
Input Return Loss
Output Return Loss
Output 1 dB Compression
Point
Output Third Order Intercept
Noise Figure
AMP3 FREQUENCY = 2.2 GHz
Gain
vs. Frequency
vs. Temperature
vs. Supply
Input Return Loss
Output Return Loss
Output 1 dB Compression
Point
Output Third Order Intercept
Noise Figure
Data Sheet
Test Conditions/Comments
RFIN3 to RFOUT3 pins
Min
3.3 V
Typ
5V
Max
Min
Typ
+0 to −1.25
+0.6 to −0.9
Max
Unit
dB
dB
dB
dB
dB
±50 MHz
−40°C ≤ TA ≤ +105°C
3.135 V to 3.465 V
4.75 V to 5.25 V
+0 to −1
+0.5 to −1
+0.3 to −0.3
S11
S22
−10.5
−10
26
+0.05 to
−0.1
−14
−12.4
28.8
∆f = 1 MHz, POUT = 0 dBm/tone
31.8
3.5
41
4.5
dBm
dB
16.3
+0 to −0.7
+0.6 to −0.8
+0.3 to −0.3
16.3
+0 to −1
+0.6 to −0.9
dB
dB
dB
dB
dB
dB
dB
dBm
RFIN3 to RFOUT3 pins
±50 MHz
−40°C ≤ TA ≤ +105°C
3.135 V to 3.465 V
4.75 V to 5.25 V
S11
S22
−11.5
−12.5
25.5
+0.05 to
−0.15
−13.5
−13.5
29
∆f = 1 MHz, POUT = 0 dBm/tone
33.8
3.3
41.4
4.3
dBm
dB
12.8
0 to −2
+0.7 to −1
+0.3 to −0.2
−14
−16
24.5
13.8
0 to −1.5
+0.7 to −1
0 to −0.2
−14
−18
28.5
dB
dB
dB
dB
dB
dB
dBm
30.5
5.8
37.8
6.1
dBm
dB
12
0 to −1.75
+1 to −1
+0.4 to −0.2
−14
−16
25
12.8
0 to −1.8
+1 to −1
0 to −0.3
−15.5
−18
28.8
dB
dB
dB
dB
dB
dB
dBm
28
5.4
37
5.9
dBm
dB
dB
dB
dBm
RFIN3 to RFOUT3 pins
±100 MHz
−40°C ≤ TA ≤ +105°C
3.135 V to 3.465 V, 4.75 V to 5.25 V
S11
S22
∆f = 1 MHz, POUT = 0 dBm/tone
RFIN3 to RFOUT3 pins
±100 MHz
−40°C ≤ TA ≤ +105°C
3.135 V to 3.465 V, 4.75 V to 5.25 V
S11
S22
∆f = 1 MHz, POUT = 0 dBm/tone
Rev. A | Page 6 of 36
Data Sheet
Parameter
AMP3 FREQUENCY = 2.6 GHz
Gain
vs. Frequency
vs. Temperature
vs. Supply
Input Return Loss
Output Return Loss
Output 1 dB Compression
Point
Output Third Order Intercept
Noise Figure
FULL CHAIN FREQUENCY =
2.2 GHz
Gain
vs. Frequency
Gain Range
Input Return Loss
Output Return Loss
Output 1 dB Compression
Point
Output Third Order Intercept
Noise Figure
LOGIC INPUTS
Logic Level Low
Logic Level High
Bias Current, VSW1
Bias Current, VSW1
GAIN CONTROL INTERFACE
VGAIN Minimum
VGAIN Maximum
Bias Current
Input Resistance
POWER SUPPLIES
Voltage
Total Supply Current
Individual Supply Currents
1
2
ADL5246
Test Conditions/Comments
RFIN3 to RFOUT3 pins
Min
±100 MHz
−40°C ≤ TA ≤ +105°C
3.135 V to 3.465 V, 4.75 V to 5.25 V
S11
S22
∆f = 1 MHz, POUT = 0 dBm/tone
3.3 V
Typ
5V
Max
Min
Typ
Max
Unit
10.3
0 to −1.8
+1 to −1.2
+0.4 to −0.1
−10
−17
22.5
11.1
0 to −1.4
+1 to −1.2
0 to −0.3
−10
−17
27
dB
dB
dB
dB
dB
dB
dBm
30
7.5
38
7.8
dBm
dB
27.5
0 to −1.4
13
−6
−13
24
31.5
0 to −1.6
44
−9
−16
28
dB
dB
dB
dB
dB
dBm
29
1.8
37
1.5
dBm
dB
AMP1→AMP2→AMP3, AMP2 at
maximum gain
±100 MHz
HG mode
S11
S22
∆f = 1 MHz, POUT = 5 dBm/tone
Pin VSW1 and Pin VSW1
Maximum voltage for a logic low
Minimum voltage for a logic high
VVSW1 = 0 V
0.8
<1
<1
V
V
μA
VVSW1 = 3.3 V
290
290
μA
VVSW1 = 0 V
VVSW1 = 3.3 V
Pin VGAIN1 and Pin VGAIN2
Minimum gain control voltage
Maximum gain control voltage
VGAIN1, VGAIN2 = 0 V
VGAIN1, VGAIN2 = 3.3 V
<1
<1
<1
<1
μA
μA
1.8
0.8
1.8
0
0
3.3
3.3
−120
190
10.6
3.135
All three amplifiers active,
maximum gain
LG mode, VGAIN1 = VGAIN2 = 0 V
AMP1
AMP2 (VPOS1 only, HG mode) 1
AMP2 (VPOS1 only, LG mode)1
VPOS2, VGAIN1 = VGAIN2 = 0 V1
VPOS2, VGAIN1 = VGAIN2 = 3.3 V1
AMP3 (output bias only) 2
VPOS1 and VPOS2 are both required for AMP2 functionality.
VPOS2 and AMP3 output bias are both required for AMP3 functionality.
Rev. A | Page 7 of 36
3.3
141
105
37
37
<1
6
9.5
61
−120
190
10.6
3.465
4.75
5
270
211
59
59
<1
13
17
139
5.25
V
V
μA
μA
kΩ
V
mA
mA
mA
mA
mA
mA
mA
mA
ADL5246
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 2.
Parameter
Supply Voltage, VPOS
Maximum RF Input Level (AMP1)
Internal Power Dissipation
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature Range (Soldering 30 sec)
Human Body Model (HBM) ESD Rating
(ESDA/JEDEC JS-001-2011)
Rating
5.5 V
20 dBm
3W
150°C
–40°C to +105°C
–65°C to +150°C
250°C
±1.0 kV
θJA is specified for a ADL5246 soldered to the evaluation board,
a 4-layer circuit board with a 5 × 5 thermal via array under the
exposed paddle. θJA measured at the top of the package. θJC
derived using a JEDEC test board.
Table 3. Thermal Resistance
Package Type
32-Lead LFCSP
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. A | Page 8 of 36
θJA
16.5
θJC
1.15
Unit
°C/W
Data Sheet
ADL5246
32
31
30
29
28
27
26
25
RFOUT1
GND
RFIN2
GND
VPOS2
GND
RFOUT3
GND
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
ADL5246
TOP VIEW
EXPOSED PAD
24
23
22
21
20
19
18
17
GND
GND
NIC
RFIN3
GND
NIC
RFOUT2
NIC
NOTES
1. NIC = NO INTERNAL CONNECTION.
2. THE EXPOSED PADDLE (EP) MUST BE SOLDERED
TO A LOW IMPEDANCE GROUND PLANE.
12233-002
NIC
GND
VPOS1
NIC
VSW1
NIC
VGAIN1
VGAIN2
9
10
11
12
13
14
15
16
GND
RFIN1
GND
NIC
NIC
VSW1
NIC
NIC
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1, 3, 10, 20, 23, 24,
25, 27, 29, 31, EP
2
4, 5, 7, 8, 9, 12,
14, 17, 19, 22
Mnemonic
GND
Description
Ground. The exposed paddle (EP) and ground pins must be soldered to a low impedance ground plane.
RFIN1
NIC
6
11
13
15
16
18
21
26
28
30
32
VSW1
VPOS1
VSW1
VGAIN1
VGAIN2
RFOUT2
RFIN3
RFOUT3
VPOS2
RFIN2
RFOUT1
RF Input. This pin requires a dc blocking capacitor. Use a 100 pF capacitor for normal operation.
No Internal Connection. These pins are not connected to internal circuitry. The user may optionally solder
to a low impedance ground plane for grounding, shielding, and printed circuit board (PCB) trace
impedance continuity.
Bypass Switch Control. Logic low = 0 V, and logic high = 3.3 V. Switch logic is shown in Table 5.
Bias for the AMP2 LNA. Connect this pin to the dc supply voltage through an RF choke.
Bypass Switch Control. Logic low = 0 V, and logic high = 3.3 V. Switch logic is shown in Table 5.
Gain Control for VVA1. The gain control range is 0 V to 3.3 V.
Gain Control VVA2. The gain control range is 0 V to 3.3 V.
RF Output of the Voltage Variable Attenuator (VVA) Block.
Driver Amplifier Input. This pin requires a dc blocking capacitor. Use a 100 pF capacitor for normal operation.
Driver Amplifier Output. Connect this pin to a dc supply through an RF choke.
Bias for VVA1, VVA2, and the AMP3 Bias Circuit. Connect this pin to the dc supply voltage through an RF choke.
RF Input to the VGA Block.
Low Noise Amplifier Output. Connect this pin to a dc supply through an RF choke.
Rev. A | Page 9 of 36
ADL5246
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
35
30
45
25
25
20
15
20
10
15
GAIN, 5.0V
OIP3, 5.0V
NOISE FIGURE, 5.0V
GAIN, 3.3V
OIP3, 3.3V
NOISE FIGURE, 3.3V
OP1dB, 5.0V
OP1dB, 3.3V
0
0.6
1.0
0
1.4
1.8
2.2
–5
3.0
2.6
FREQUENCY (GHz)
25
OP1dB, 5.0V
15
OP1dB, 3.3V
10
0.6
1.0
1.4
24
8
16
4
8
38
34
32
0.9GHz, 5.0V
1.9GHz, 5.0V
2.6GHz, 5.0V
0.9GHz, 3.3V
1.9GHz, 3.3V
2.6GHz, 3.3V
30
26
1.6
1.8
2.0
2.2
2.4
2.6
2.8
24
–10
12233-004
0
1.4
3.0
FREQUENCY (GHz)
0
5
POUT (dBm)
10
15
3.0
0
–5
TA = –40°C, 5.0V
TA = –40°C, 3.3V
TA = +25°C, 5.0V
TA = +25°C, 3.3V
TA = +85°C, 5.0V
TA = +85°C, 3.3V
TA = +105°C, 5.0V
TA = +105°C, 3.3V
2.5
AMP1 NOISE FIGURE (dB)
–10
–15
–20
–25
S11,
S12,
S22,
S11,
S12,
S22,
–30
–35
1.0
1.4
1.8
2.2
FREQUENCY (GHz)
5.0V
5.0V
5.0V
3.3V
3.3V
3.3V
2.6
2.0
1.5
1.0
0.5
3.0
12233-005
AMP1 MAGNITUDE (dB)
–5
Figure 7. AMP1 OIP3 vs. POUT by Frequency
Figure 4. AMP1 Gain vs. Frequency by Temperature
–40
0.6
15.0
3.0
2.6
40
28
1.2
2.2
FREQUENCY (GHz)
AMP1 OIP3 (dBm)
12
1.0
1.8
17.5
36
32
0.8
22.5
20.0
20
40
16
0
0.6
25.0
Figure 6. AMP1 OIP3 at POUT = 0 dBm/Tone and OP1dB vs.
Frequency by Temperature
AMP1 GAIN (dB), 3.3V
AMP1 GAIN (dB), 5.0V
20
TA = –40°C
TA = +25°C
TA = +85°C
TA = +105°C
OIP3, 5.0V
30
48
TA = –40°C
TA = +25°C
TA = +85°C
TA = +105°C
27.5
35
Figure 3. AMP1 Gain, OIP3 at POUT = 0 dBm/Tone, Noise Figure,
and OP1dB vs. Frequency
24
30.0
40
12233-007
5
5
32.5
OIP3, 3.3V
Figure 5. AMP1 Magnitude of Input Return Loss (S11), Output Return Loss (S22),
and Reverse Isolation (S12) vs. Frequency
Rev. A | Page 10 of 36
0
0.6
1.0
1.4
1.8
2.2
2.6
3.0
FREQUENCY (GHz)
Figure 8. AMP1 Noise Figure vs. Frequency by Temperature
12233-008
10
AMP1 OP1dB (dBm)
30
35.0
AMP1 OIP3 AND OP1dB (dBm), 3.3V
50
12233-006
35
AMP1 OIP3 AND OP1dB (dBm), 5.0V
40
12233-003
AMP1 GAIN, OIP3, AND NOISE FIGURE (dB, dBm)
All supply pins at 5 V, TA = 25°C, unless otherwise noted.
ADL5246
20
15
10
10
0
5
AMP2 GAIN (dB)
–10
–20
0.9GHz, 5.0V, HG
0.9GHz, 5.0V, LG
1.9GHz, 5.0V, HG
1.9GHz, 5.0V, LG
2.6GHz, 5.0V, HG
2.6GHz, 5.0V, LG
–30
–40
–5
–10
1.0
1.5
2.0
2.5
3.0
3.5
VGAIN1, VGAIN2 (V)
–25
Figure 9. AMP2 Gain vs. VGAIN1, VGAIN2 at Three Frequencies, 5 V Supply,
Both Gain Controls Varied, VGAIN1 = VGAIN2
10
0
5
AMP2 GAIN (dB)
10
0.9GHz, 5V, HG, VGAIN1
0.9GHz, 5V, LG, VGAIN1
0.9GHz, 5V, HG, VGAIN2
0.9GHz, 5V, LG, VGAIN2
2.6GHz, 5V, HG, VGAIN1
2.6GHz, 5V, LG, VGAIN1
2.6GHz, 5V, HG, VGAIN2
2.6GHz, 5V, LG, VGAIN2
–40
–50
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.9GHz, 3.3V, HG, VGAIN1
0.9GHz, 3.3V, HG, VGAIN2
2.6GHz, 3.3V, HG, VGAIN2
2.6GHz, 3.3V, HG, VGAIN1
0
–5
0.9GHz, 3.3V, LG, VGAIN1
0.9GHz, 3.3V, LG, VGAIN2
–10
2.6GHz, 3.3V, LG, VGAIN1
2.6GHz, 3.3V, LG, VGAIN2
–20
–60
0
1.5
–15
2.0
2.5
3.0
3.5
VGAIN1, VGAIN2 (V)
–25
12233-010
–30
1.0
Figure 12. AMP2 Gain vs. VGAIN1,VGAIN2 at Three Frequencies, 3.3 V Supply,
Both Gain Controls Varied, VGAIN1 = VGAIN2
15
–20
0.5
VGAIN1, VGAIN2 (V)
20
–10
0
Figure 10. AMP2 Gain vs. VGAIN1,VGAIN2 at Two Frequencies, 5 V Supply,
Only One Gain Control Varied
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VGAIN1, VGAIN2 (V)
12233-013
0.5
12233-009
0
12233-012
–20
–60
AMP2 GAIN (dB)
0
–15
–50
Figure 13. AMP2 Gain vs. VGAIN1, VGAIN2 at Two Frequencies, 3.3 V Supply,
Only One Gain Control Varied
200
300
AMP2 UNWRAPPED PHASE (Degrees)
250
1.9GHz, 5.0V, HG
2.6GHz, 5.0V, HG
200
150
100
50
2.6GHz, 5.0V, LG
1.9GHz, 5.0V, LG
0.9GHz, 5.0V, LG
0
–50
–100
–150
0.9GHz, 5.0V, HG
–200
0
0.5
1.0
1.5
2.0
VGAIN1, VGAIN2 (V)
2.5
3.0
3.5
Figure 11. AMP2 Unwrapped Phase vs. VGAIN1, VGAIN2 at Three Frequencies,
5 V Supply, Both Gain Controls Varied, VGAIN1 = VGAIN2
1.9GHz, 3.3V, HG
2.6GHz, 3.3V, HG
150
100
50
2.6GHz, 3.3V, LG
1.9GHz, 3.3V, LG
0.9GHz, 3.3V, LG
0
–50
–100
–150
0.9GHz, 3.3V, HG
–200
12233-011
AMP2 UNWRAPPED PHASE (Degrees)
0.9GHz, 3.3V, HG
0.9GHz, 3.3V, LG
1.9GHz, 3.3V, HG
1.9GHz, 3.3V, LG
2.6GHz, 3.3V, HG
2.6GHz, 3.3V, LG
0
0.5
1.0
1.5
2.0
VGAIN1, VGAIN2 (V)
2.5
3.0
3.5
12233-014
AMP2 GAIN (dB)
Data Sheet
Figure 14. AMP2 Unwrapped Phase vs. VGAIN1, VGAIN2 at Three Frequencies,
3.3 V Supply, Both Gain Controls Varied, VGAIN1 = VGAIN2
Rev. A | Page 11 of 36
ADL5246
Data Sheet
18
30
16
28
26
AMP2 INPUT IP3 (dBm)
5.0V
3.3V
12
10
8
6
4
20
18
16
1.4
1.8
2.2
2.6
3.0
FREQUENCY (GHz)
10
0.6
12233-015
1.0
Figure 15. AMP2 Input P1dB vs. Frequency at Maximum Gain, HG Only
–10
–10
AMP2 MAGNITUDE OF S22 (dB)
0
–30
–50
0.6
1.0
1.4
1.8
2.2
FREQUENCY (GHz)
2.6
3.0
Figure 16. AMP2 Magnitude of Input Return Loss (S11) vs. Frequency,
5 V Supply, Gain Stepped Across Full Range
2.6
3.0
–20
–30
–40
–50
0.6
12233-016
–40
1.4
1.8
2.2
FREQUENCY (GHz)
Figure 18. AMP2 Input IP3 vs. Frequency at Maximum Gain, HG Only
0
–20
1.0
12233-018
12
0
0.6
AMP2 MAGNITUDE OF S11 (dB)
5.0V
3.3V
22
14
2
1.0
1.4
1.8
2.2
2.6
3.0
FREQUENCY (GHz)
Figure 19. AMP2 Magnitude of Output Return Loss (S22) vs. Frequency,
5 V Supply, Gain Stepped Across Full Range
16
20
TA = –40°C, 5.0V
TA = +25°C, 5.0V
TA = +85°C, 5.0V
TA = +105°C, 5.0V
TA = –40°C, 3.3V
TA = +25°C, 3.3V
TA = +85°C, 3.3V
TA = +105°C, 3.3V
10
14
AMP2 NOISE FIGURE (dB)
15
AMP2 GAIN (dB)
24
12233-019
AMP2 INPUT P1dB (dBm)
14
5
12
10
5.0V, HG
3.3V, HG
5.0V, LG
3.3V, LG
8
6
4
0
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
FREQUENCY (GHz)
2.4
2.6
2.8
3.0
0
0.6
12233-017
–5
0.6
1.0
1.4
1.8
2.2
FREQUENCY (GHz)
Figure 17. AMP2 Gain vs. Frequency by Temperatures at Maximum Gain
Rev. A | Page 12 of 36
2.6
3.0
12233-020
2
Figure 20. AMP2 Noise Figure vs. Frequency at VGAIN1 = VGAIN2 = 0 V
ADL5246
80
4
80
3
60
3
60
2
40
1
20
0
–1
–20
–2
–2
–40
–3
–60
–3
–80
–4
–1
–4
–1
0
1
2
3
4
5
6
TIME (µs)
RF OUTPUT (mV)
–20
–1
20
1
–40
–60
0
1
2
3
4
5
6
–80
12233-124
0
0
40
2
VGAIN2 (V)
RF OUTPUT INTO 50Ω (mV)
4
12233-121
VGAIN1 (V)
Data Sheet
TIME (µs)
Figure 21. AMP2 Typical Output Response with 3.3 V Step on VGAIN1,
VGAIN2 = 0 V, HG Mode, 0.9 GHz
Figure 24. AMP2 Typical Output Response with 3.3 V Step on VGAIN2,
VGAIN1 = 0 V, HG Mode, 0.9 GHz
2.5
4.0
200
15
1.5
100
1.0
50
0.5
10
3.0
0
2.5
RF OUTPUT INTO 50Ω (mV)
150
5
2.0
VGAIN2 (V)
2.0
RF OUTPUT INTO 50Ω (mV)
VGAIN1 (V)
3.5
1.5
0
1.0
–5
0.5
0
–10
–0.5
TIME (µs)
–1.0
–4
300
2
250
1
200
0
150
–1
100
LG MODE
HG MODE
LG MODE
–2
50
–3
0
–4
–50
–5
–0.3 –0.2 –0.1
0
–100
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
TIME (μs)
6
8
10
12
–15
16
14
Figure 23. AMP2 Typical Output Response During Gain Mode Switching,
VGAIN1 = VGAIN2 = 0 V, 0.9 GHz
6
4
–40°C
2
0
+85°C
–2
+105°C
–4
–6
–8
0
0.5
1.0
1.5
2.0
VGAIN1, VGAIN2 (V)
2.5
3.0
12233-126
3
AMP2 GAIN SHIFT AT TEMPERATURE (dB)
350
4
8
RF OUTPUT INTO 50Ω (mV)
4
2
Figure 25. AMP2 Typical Output Response with 3.3 V Step on VGAIN2,
VGAIN1 = 3.3 V, HG Mode, 0.9 GHz
12233-123
VVSW1, VVSW1 (V)
400
0
TIME (µs)
Figure 22. AMP2 Typical Output Response with 0.5 V Step on VGAIN1,
VGAIN2 = 0 V, HG Mode, 0.9 GHz
5
–2
12233-125
12233-122
0
–50
–4 –3 –2 –1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Figure 26. AMP2 Typical Gain Shift at Temperature With Respect to 25 °C vs.
VGAIN1 = VGAIN2, Both Gain Controls Varied, 1.75 GHz
Rev. A | Page 13 of 36
ADL5246
Data Sheet
50
TA = –40°C
TA = +25°C
TA = +85°C
TA = +105°C
45
40
AMP3 OIP3 AND OP1dB (dBm)
35
30
25
20
10
5V
3.3V
40
35
OIP3, 3.3 V
30
OP1dB, 5V
25
OP1dB, 3.3 V
5
0.71
0.72
0.73
0.74
0.75
0.76
0.77
0.78
0.79
0.80
FREQUENCY (GHz)
Figure 27. AMP3 0.75 GHz Gain, OIP3 at POUT = 0 dBm/Tone, OP1dB and
Noise Figure vs. Frequency
28
50
19
26
48
18
24
17
22
16
20
15
18
14
16
TA = –40°C
TA = +25°C
14
TA = +85°C
TA = +105°C
12
0.78 0.79 0.80
12
0.70
0.71
0.72
0.73
0.74
0.75
0.76
0.77
0.74
0.75
0.76
0.77
0.78
0.79
0.80
5V
3.3V
0.70GHz
0.75GHz
0.80GHz
AMP3 OIP3 (dBm)
AMP3 GAIN AT 3.3V (dB)
44
42
40
38
36
34
32
30
–10
–5
0
5
10
20
0.80
15
POUT (dBm)
Figure 28. AMP3 0.75 GHz Gain vs. Frequency by Temperature
Figure 31. AMP3 0.75 GHz OIP3 vs. POUT by Frequency
0
7
–5
AMP3 NOISE FIGURE (dB)
6
–10
–15
–20
–25
–40°C
+25°C
+85°C
+105°C
5V
3.3V
5
4
3
–30
S11 (dB)
S12 (dB)
S22 (dB)
0.70
0.75
0.80
0.85
FREQUENCY (GHz)
Figure 29. AMP3 0.75 GHz Magnitude of Input Return Loss (S11),
Output Return Loss (S22), and Reverse Isolation (S12) vs. Frequency
2
0.70
12233-129
AMP3 MAGNITUDE (dB)
0.73
46
FREQUENCY (GHz)
–35
0.65
0.72
Figure 30. AMP3 0.75 GHz OIP3 at POUT = 0 dBm/Tone and OP1dB vs.
Frequency by Temperature
20
13
0.71
FREQUENCY (GHz)
12233-128
AMP3 GAIN AT 5V (dB)
20
0.70
12233-127
0
0.70
12233-131
GAIN
OP1dB
OIP3
NOISE FIGURE
15
OIP3, 5V
12233-132
AMP3 GAIN, OIP3, OP1dB,
AND NOISE FIGURE (dB, dBm)
45
12233-130
50
0.71
0.72
0.73
0.74
0.75
0.76
FREQUENCY (GHz)
0.77
0.78
0.79
Figure 32. AMP3 0.75 GHz Noise Figure vs. Frequency by Temperature
Rev. A | Page 14 of 36
Data Sheet
ADL5246
45
45
OIP3, 5.0V
30
25
20
GAIN
OP1dB
OIP3
NOISE FIGURE
5
0
0.85
0.86
0.87
0.88
5V
3.3V
0.89
0.90
0.91
0.92
0.93
0.94
0.95
FREQUENCY (GHz)
0.87
0.88
0.89
0.90
0.91
0.92
45
16
22
15
20
14
18
13
16
40
35
0.85GHz, 5.0V
0.90GHz, 5.0V
0.95GHz, 5.0V
0.85GHz, 3.3V
0.90GHz, 3.3V
0.95GHz, 3.3V
30
0.88
0.89
0.90
0.91
0.92
0.93
0.94
14
0.95
25
–10
12233-134
0.87
0.95
26
24
0.86
0.94
28
17
12
0.85
0.93
Figure 36. AMP3 0.9 GHz OIP3 at POUT = 0 dBm/Tone and OP1dB vs.
Frequency by Temperature
AMP3 OIP3 (dBm)
18
0.86
TA = +85°C
TA = +105°C
50
GAIN AT 3.3V (dB)
AMP3 GAIN AT 5V (dB)
19
TA = –40°C
TA = +25°C
FREQUENCY (GHz)
30
TA = –40°C
TA = +25°C
TA = +85°C
TA = +105°C
OP1dB, 3.3V
25
20
0.85
Figure 33. AMP3 0.9 GHz Gain, OIP3 at POUT = 0 dBm/Tone, OP1dB, and
Noise Figure vs. Frequency
20
OP1dB, 5.0V
30
FREQUENCY (GHz)
–5
0
5
10
15
20
12233-137
10
OIP3, 3.3V
35
0.95
12233-138
15
40
12233-136
AMP3 OPIP3 AND OP1dB (dBm)
35
12233-133
AMP3 GAIN, OIP3, OP1dB
AND NOISE FIGURE (dB, dBm)
40
POUT (dBm)
Figure 34. AMP3 0.9 GHz Gain vs. Frequency by Temperature
Figure 37. AMP3 0.9 GHz OIP3 vs. POUT by Frequency
0
6
TA = –40°C
TA = +25°C
TA = +85°C
TA = +105°C
5.05V
3.35V
AMP3 NOISE FIGURE (dB)
–10
–15
–20
–25
–30
–35
0.80
5
4
3
S11 (dB)
S12 (dB)
S22 (dB)
0.85
0.90
FREQUENCY (GHz)
0.95
1.00
2
0.85
12233-135
AMP3 MAGNITUDE (dB)
–5
Figure 35. AMP3 0.9 GHz Input Return Loss (S11), Output Return Loss (S22),
and Reverse Isolation (S12) vs. Frequency
0.86
0.87
0.88
0.89
0.90
0.91
FREQUENCY (GHz)
0.92
0.93
0.94
Figure 38. AMP3 0.9 GHz Noise Figure vs. Frequency by Temperature
Rev. A | Page 15 of 36
Data Sheet
42
40
40
35
30
25
20
GAIN, 5.0V
OP1dB, 5.0V
OIP3, 5.0V
NOISE FIGURE, 5.0V
GAIN, 3.3V
OP1dB, 3.3V
OIP3, 3.3V
NOISE FIGURE, 3.3V
15
10
36
32
28
22
1.80
1.95
2.00
24
14
22
12
20
OP1dB, 3.3V
1.85
1.90
1.95
2.00
FREQUENCY (GHz)
Figure 39. AMP3 1.9 GHz Gain, OIP3 at POUT = 0 dBm/Tone, OP1dB, and
Noise Figure vs. Frequency
16
OP1dB, 5.0V
26
24
1.90
OIP3, 3.3V
30
0
1.80
FREQUENCY (GHz)
TA = –40°C
TA = +25°C
TA = +85°C
TA = +105°C
34
5
1.85
OIP3, 5.0V
38
12233-024
AMP3 OIP3 AND OP1dB (dBm)
45
12233-021
AMP3 GAIN, OIP3, OP1dB,
AND NOISE FIGURE (dB, dBm)
ADL5246
Figure 42. AMP3 1.9 GHz OIP3 at POUT = 0 dBm/Tone and OP1dB vs.
Frequency by Temperature
45
16
6
14
4
12
2
10
35
30
1.8GHz, 5.0V
1.9GHz, 5.0V
2.0GHz, 5.0V
1.8GHz, 3.3V
1.9GHz, 3.3V
2.0GHz, 3.3V
25
1.85
1.90
1.95
8
2.00
20
–10
12233-022
FREQUENCY (GHz)
15
20
TA = –40°C, 5.0V
TA = +25°C, 5.0V
TA = +85°C, 5.0V
TA = +105°C, 5.0V
TA = –40°C, 3.3V
TA = +25°C, 3.3V
TA = +85°C, 3.3V
TA = +105°C, 3.3V
9
AMP3 NOISE FIGURE (dB)
AMP3 MAGNITUDE (dB)
10
10
–5
S11 (dB)
S12 (dB)
S22 (dB)
–20
–25
8
7
6
5
4
1.85
1.90
FREQUENCY (GHz)
1.95
2.00
3
1.80
12233-023
–30
1.80
5
Figure 43. AMP3 1.9 GHz OIP3 vs. POUT by Frequency
0
–15
0
POUT (dBm)
Figure 40. AMP3 1.9 GHz Gain vs. Frequency by Temperature
–10
–5
Figure 41. AMP3 1.9 GHz Magnitude of Input Return Loss (S11),
Output Return Loss (S22), and Reverse Isolation (S12) vs. Frequency
1.85
1.90
FREQUENCY (GHz)
1.95
2.00
12233-026
0
1.80
12233-025
8
18
AMP3 OIP3 (dBm)
TA = –40°C
TA = +25°C
TA = +85°C
TA = +105°C
10
AMP3 GAIN (dB), 3.3V
AMP3 GAIN (dB), 5.0V
40
Figure 44. AMP3 1.9 GHz Noise Figure vs. Frequency by Temperature
Rev. A | Page 16 of 36
ADL5246
35
38
30
25
20
GAIN, 5.0V
OP1dB, 5.0V
OIP3, 5.0V
NOISE FIGURE, 5.0V
GAIN, 3.3V
OP1dB, 3.3V
OIP3, 3.3V
NOISE FIGURE, 3.3V
15
10
5
2.15
2.20
2.25
2.30
FREQUENCY (GHz)
32
14
28
12
24
32
OIP3, 3.3V
36
34
30
TA = –40°C
TA = +25°C
TA = +85°C
TA = +105°C
32
30
26
22
OP1dB, 5.0V
2.15
28
24
OP1dB, 3.3V
28
2.20
20
2.30
2.25
FREQUENCY (GHz)
Figure 45. AMP3 2.2 GHz Gain, OIP3 at POUT = 0 dBm/Tone, OP1dB, and
Noise Figure vs. Frequency
16
OIP3, 5.0V
26
2.10
12233-027
0
2.10
34
AMP3 OIP3 AND OP1dB (dBm), 3.3V
40
12233-030
40
AMP3 OIP3 AND OP1dB (dBm), 5V
AMP3 GAIN, OIP3, OP1dB,
AND NOISE FIGURE (dB, dBm)
Data Sheet
Figure 48. AMP3 2.2 GHz OIP3 at POUT = 0 dBm/Tone and OP1dB vs.
Frequency by Temperature
45
16
6
12
4
8
35
30
2.1GHz, 5.0V
2.2GHz, 5.0V
2.3GHz, 5.0V
2.1GHz, 3.3V
2.2GHz, 3.3V
2.3GHz, 3.3V
25
2.15
2.20
2.25
4
2.30
20
–10
12233-028
FREQUENCY (GHz)
5
9
–5
15
20
TA = –40°C, 5.0V
TA = +25°C, 5.0V
TA = +85°C, 5.0V
TA = +105°C, 5.0V
TA = –40°C, 3.3V
TA = +25°C, 3.3V
TA = +85°C, 3.3V
TA = +105°C, 3.3V
8
AMP3 NOISE FIGURE (dB)
S11 (dB)
S12 (dB)
S22 (dB)
–10
10
Figure 49. AMP3 2.2 GHz OIP3 vs. POUT by Frequency
0
AMP3 MAGNITUDE (dB)
0
POUT (dBm)
Figure 46. AMP3 2.2 GHz Gain vs. Frequency by Temperature
–15
–20
–25
7
6
5
4
2.15
2.20
FREQUENCY (GHz)
2.25
2.30
3
2.10
12233-029
–30
2.10
–5
Figure 47. AMP3 2.2 GHz Input Return Loss (S11), Output Return Loss (S22),
and Reverse Isolation (S12) vs. Frequency
2.15
2.20
FREQUENCY (GHz)
2.25
2.30
12233-032
2
2.10
12233-031
8
20
AMP3 OIP3 (dBm)
TA = –40°C
TA = +25°C
TA = +85°C
TA = +105°C
10
AMP3 GAIN (dB), 3.3V
AMP3 GAIN (dB), 5V
40
Figure 50. AMP3 2.2 GHz Noise Figure vs. Frequency by Temperature
Rev. A | Page 17 of 36
45
41
47
40
39
43
35
30
25
20
15
GAIN, 5.0V
OP1dB, 5.0V
OIP3, 5.0V
NOISE FIGURE, 5.0V
GAIN, 3.3V
OP1dB, 3.3V
OIP3, 3.3V
NOISE FIGURE, 3.3V
10
OIP3, 5.0V
37
39
TA = –40°C
TA = +25°C
TA = +85°C
TA = +105°C
35
33
35
OIP3, 3.3V
31
27
31
OP1dB, 3.3V
29
19
27
5
23
AMP3 OIP3 AND OP1dB (dBm), 3.3V
Data Sheet
AMP3 OIP3 AND OP1dB (dBm), 5.0V
AMP3 GAIN, OIP3, OP1dB,
AND NOISE FIGURE (dB, dBm)
ADL5246
OP1dB3, 5.0V
2.65
2.70
FREQUENCY (GHz)
25
2.50
11
21
19
TA = –40°C
TA = +25°C
TA = +85°C
TA = +105°C
7
5
17
15
3
13
1
11
–1
9
–3
7
2.55
2.60
FREQUENCY (GHz)
2.65
40
35
30
25
5
2.70
20
–10
11
–5
10
AMP3 NOISE FIGURE (dB)
AMP3 MAGNITUDE (dB)
0
5
10
15
20
Figure 55. AMP3 2.6 GHz OIP3 vs. POUT by Frequency
0
–10
S11 (dB)
S12 (dB)
S22 (dB)
–20
–25
TA = –40°C, 5.0V
TA = +25°C, 5.0V
TA = +85°C, 5.0V
TA = +105°C, 5.0V
TA = –40°C, 3.3V
TA = +25°C, 3.3V
TA = +85°C, 3.3V
TA = +105°C, 3.3V
9
8
7
6
2.55
2.60
FREQUENCY (GHz)
2.65
2.70
5
2.50
12233-035
–30
2.50
–5
POUT (dBm)
Figure 52. AMP3 2.6 GHz Gain vs. Frequency by Temperature
–15
2.5GHz, 5.0V
2.6GHz, 5.0V
2.7GHz, 5.0V
2.5GHz, 3.3V
2.6GHz, 3.3V
2.7GHz, 3.3V
Figure 53. AMP3 2.6 GHz Input Return Loss (S11), Output Return Loss (S22),
and Reverse Isolation (S12) vs. Frequency
2.55
2.60
FREQUENCY (GHz)
2.65
2.70
12233-038
–5
2.50
45
12233-034
AMP3 GAIN (dB), 5.0V
9
15
2.70
2.65
Figure 54. AMP3 2.6 GHz OIP3 at POUT = 0dBm/Tone and OP1dB vs.
Frequency and Temperature
AMP3 OIP3 (dBm)
23
AMP3 GAIN (dB), 3.3V
25
13
2.60
FREQUENCY (GHz)
Figure 51. AMP3 2.6 GHz Gain, OIP3 at POUT = 0 dBm/Tone, OP1dB, and
Noise Figure vs. Frequency
15
2.55
12233-036
2.60
12233-037
2.55
12233-033
0
2.50
Figure 56. AMP3 2.6 GHz Noise Figure vs. Frequency by Temperature
Rev. A | Page 18 of 36
ADL5246
1.5
110
80
–10
TA = –40°C, 5.0V
TA = +25°C, 5.0V
TA = +105°C, 5.0V
TA = –40°C, 3.3V
TA = +25°C, 3.3V
TA = +105°C, 3.3V
70
–20
AMP1 SUPPLY CURRENT (mA)
S11 (dB)
S12 (dB)
S22 (dB)
–30
–40
–50
60
50
40
2.15
2.20
FREQUENCY (GHz)
2.25
2.30
20
–10
12233-040
–70
2.10
38
160
AMP3 SUPPLY CURRENT (mA)
180
2.1GHz, 5.0V
2.2GHz, 5.0V
2.3GHz, 5.0V
2.1GHz, 3.3V
2.2GHz, 3.3V
2.3GHz, 3.3V
32
30
5
10
15
20
25
Figure 61. AMP1 Supply Current vs. POUT by Temperature
40
34
0
POUT (dBm)
Figure 58. Full Chain 2.2 GHz Magnitude of Input Return Loss (S11), Output
Return Loss (S22), and Reverse Isolation (S12) vs. Frequency at Maximum Gain
36
–5
12233-043
30
–60
28
140
3.135V
3.300V
3.465V
4.750V
5.000V
5.250V
120
100
80
60
40
TEMPERATURE (°C)
Figure 59. Full Chain 2.2 GHz OIP3 vs. POUT by Frequency at Maximum Gain
Rev. A | Page 19 of 36
Figure 62. AMP3 Supply Current vs. Temperature by Voltage
12233-044
110
100
90
80
70
60
50
40
30
20
20
20
0
15
10
POUT (dBm)
10
–10
5
–40
0
12233-041
–5
–20
FULL CHAIN MAGNITUDE (dB)
12233-042
Figure 60. AMP1 Supply Current vs. Temperature by Voltage
0
FULL CHAIN OIP3 (dBm)
90
TEMPERATURE (°C)
Figure 57. Full Chain 2.2 GHz Gain, OIP3 at POUT = 5 dBm/Tone, OP1dB, and
Noise Figure vs. Frequency at Maximum Gain
26
–10
100
FREQUENCY (GHz)
80
20
70
1.0
2.30
2.25
60
2.20
50
2.15
25
–40
10
2.10
30
40
15
35
30
2.0
40
–30
20
GAIN, 3.3V
OP1dB, 3.3V
OIP3, 3.3V
NOISE FIGURE, 3.3V
20
2.5
GAIN, 5.0V
OP1dB, 5.0V
OIP3, 5.0V
NOISE FIGURE, 5.0V
3.135V
3.300V
3.465V
4.750V
5.000V
5.250V
45
0
25
50
10
3.0
–10
30
55
–20
3.5
–30
35
60
AMP1 SUPPLY CURRENT (mA)
4.0
NOISE FIGURE (dB)
40
12233-039
FULL CHAIN GAIN, OIP3, OP1dB (dB, dBm)
Data Sheet
ADL5246
Data Sheet
400
25
300
250
20
PERCENT (%)
AMP3 SUPPLY CURRENT (mA)
REPRESENTS THREE
BATCH LOTS
TA = –40°C, 5.0V
TA = +25°C, 5.0V
TA = +105°C, 5.0V
TA = –40°C, 3.3V
TA = +25°C, 3.3V
TA = +105°C, 3.3V
350
200
15
10
150
5
–5
0
5
10
15
20
25
30
POUT (dBm)
0
35
12233-045
50
–10
36
37
38
39
40
41
AMP1 OIP3 (dB)
Figure 63. AMP3 Supply Current vs. POUT by Temperature
12233-048
100
Figure 66. AMP1 OIP3 Distribution at 2.2 GHz, POUT = 0 dBm/Tone
25
20
REPRESENTS THREE
BATCH LOTS
REPRESENTS THREE
BATCH LOTS
20
PERCENT (%)
PERCENT (%)
15
10
15
10
5
10.5
11.0
11.5
12.0
12.5
13.0
AMP1 GAIN (dB)
0
0.90
12233-046
0
10.0
0.95
1.00
1.05
1.10
1.15
1.20
AMP1 NOISE FIGURE (dB)
Figure 64. AMP1 Gain Distribution at 2.2 GHz
12233-049
5
Figure 67. AMP1 Noise Figure Distribution at 2.2 GHz
40
35
REPRESENTS THREE
BATCH LOTS
REPRESENTS THREE
BATCH LOTS
30
30
PERCENT (%)
20
20
15
10
10
0
20.0
20.5
21.0
21.5
22.0
22.5
23.0
23.5
AMP1 OP1dB (dBm)
24.0
0
11.0
11.5
12.0
12.5
13.0
13.5
AMP3 GAIN (dB)
Figure 68. AMP3 Gain Distribution at 2.2 GHz
Figure 65. AMP1 OP1dB Distribution at 2.2 GHz
Rev. A | Page 20 of 36
14.0
12233-050
5
12233-047
PERCENT (%)
25
Data Sheet
ADL5246
20
25
REPRESENTS THREE
BATCH LOTS
10
REPRESENTS THREE
BATCH LOTS
20
AMP2 GAIN (dB)
PERCENT (%)
0
15
10
–10
–20
–30
5
AMP3 OP1dB (dBm)
–50
12233-051
0
26.0 26.5 27.0 27.5 28.0 28.5 29.0 29.5 30.0 30.5 31.0 31.5 32.0
0
0.5
1.0
1.5
2.0
REPRESENTS THREE
BATCH LOTS
REPRESENTS THREE
BATCH LOTS
–10
AMP2 GAIN (dB)
15
10
5
–20
–30
–40
35.0
35.5
36.0
36.5
37.0
37.5
38.0
38.5
39.0
AMP3 OIP3 (dB)
–50
12233-052
34.5
REPRESENTS THREE
BATCH LOTS
25
20
15
10
5.5
6.0
6.5
7.0
7.5
12233-053
5
AMP3 NOISE FIGURE (dB)
1
1.5
2
VGAIN1, VGAIN2 (V)
30
5.0
0.5
2.5
3
3.5
Figure 73. Distribution of AMP2 Gain vs. VGAIN1, VGAIN2 at 1.5 GHz, 5 V Supply,
LG, Both Gain Controls Varied, VGAIN1 = VGAIN2
Figure 70. AMP3 OIP3 Distribution at 0 dBm/Tone, 2.2 GHz
4.5
0
12233-055
PERCENT (%)
20
PERCENT (%)
3.5
0
25
0
4.0
3.0
Figure 72. Distribution of AMP2 Gain vs. VGAIN1, VGAIN2 at 1.5 GHz, 5 V Supply,
HG, Both Gain Controls Varied, VGAIN1 = VGAIN2
Figure 69. AMP3 OP1dB Distribution, 2.2 GHz
0
34.0
2.5
VGAIN1, VGAIN2 (V)
12233-054
–40
Figure 71. AMP3 Noise Figure Distribution, 2.2 GHz
Rev. A | Page 21 of 36
ADL5246
Data Sheet
TERMINOLOGY
Full Chain Configuration
The full chain configuration is a serial connection of Amplifier 1
(AMP1), Amplifier 2 (AMP2), and Amplifier 3 (AMP3), in that
order. The performance data shown in Table 1 and Figure 57
through Figure 59 are measured without any filters or attenuators
between amplifiers.
Low Gain (LG) Mode
The amplifier within AMP2 is bypassed and inactive. However,
the input and output attenuators remain active.
Maximum Gain
When AMP2is in HG mode, VGAIN1 = VGAIN2 = 0 V.
High Gain (HG) Mode
The amplifier within AMP2 is active and not bypassed. In
addition, the input and output attenuators are active.
Rev. A | Page 22 of 36
Data Sheet
ADL5246
THEORY OF OPERATION
between a low gain range and a high gain range. When the LNA is
bypassed, it is also not powered, reducing the supply current by
approximately 59 mA.
BASIC CONNECTIONS
The basic connections for operating the ADL5246 are shown in
Figure 74. The schematic of AMP3 is configured for operation
at 2.2 GHz.
Each VVA may be controlled independently or in tandem via
VGAIN1 and VGAIN2. Bias is supplied to AMP2 via VPOS1 and
VPOS2. VPOS1 provides the bias to the amplifier circuit, and
VPOS2 provides bias to the VVAs. Therefore, both VPOS1 and
VPOS2 must be connected to bias to operate AMP2.
Amplifier 1 (AMP1)
AMP1 in the ADL5246 is a broadband low noise amplifier. The
radio frequency (RF) input is internally matched to 50 Ω and
optimally matched for the minimum noise figure and is
unconditionally stable. The RF output is internally matched for 50
Ω. The RF inputs and outputs require dc blocking capacitors (C8
and C9) for operation. DC bias is supplied through Inductor L1
and is connected to the RFOUT1 pin. Three decoupling capacitors
(C40, C41, and C5) prevent RF signals from propagating on the dc
supply lines. The value of L1 must be high enough to isolate the
bias from RF; however, the exact value is not critical for operation.
The self resonance of L1 has little effect upon the operation of
AMP1, within reasonable limits. AMP1 is completely independent
from the rest of the ADL5246 and may be left unpowered if not
needed. When AMP1 is not in use, terminate the RFIN1 and
RFOUT1 pins to ground via a 100 pF capacitor and a 50 Ω
resistor in series on each pin.
Inductors L2 and L3 with capacitors C2, C4, C7, C16, C17, and
C20 prevent RF signals from propagating on the dc supply lines.
The L2 value has some bearing on the gain of AMP2, with the
10 nH value giving an unhindered frequency response as low as
approximately 0.6 GHz.
AMP2 is sensitive to capacitance on the VPOS2 bias line. Place all
bypass capacitors as shown in Figure 74. Excessive capacitance
between L3 and Pin 28 (VPOS2) can cause undesirable gain loss.
When AMP2 is not in use, terminate the RFIN2 and RFOUT2
pins to ground via a 100 pF capacitor and a 50 Ω resistor in series
on each pin.
Table 5. Bypass Switch Logic
AMP2 is a 50 Ω internally matched RF VGA consisting of two
VVAs with an LNA in between them. RFIN2 and RFOUT2 are
internally ac-coupled with a 20 pF on-chip capacitor. The LNA
has an integral bypass switch that allows the user to choose
VSW1
VSW1
Mode
Undefined
High Gain Mode
Low Gain Mode
Undefined
Amplifier 2 (AMP2)
RFOUT2
VSW1 VGAIN2
VPOS2
VPOS1
C6
100pF
RFIN2
VGAIN1
C40
0.1µF
R3
100Ω
C3
1.5pF λ2
R2
100Ω
R4
100Ω
C13
100pF
C5
100pF
L1
100nH
RFOUT1
30
RFIN3
C22
100pF
R5
100Ω
C14
100pF
C41
1000pF
C9
100pF
C15
100pF
C21
100pF
L6
1nH
λ1
15
13
6
16
18
C2
0.1µF
C20
0.1µF
C4
1000pF
C17
1000pF
C7
10pF
C16
100pF
11
C24
100pF
L3
100nH
28
32
λ3
RFIN1
AMP3
AMP1
C8
100pF
VVA1
26
L4
100nH
RFOUT3
C23
100pF
GND1 GND2 GND3
ADL5246
AMP2
R1
0Ω
C1
2.7pF
VVA2
2
C26
0.1µF
C25
1000pF
L2
10nH
21
VCC2
EP
4
5
7
8
9
12 14 17 19 22
1
3
10 20 23 24 25 27 29 31
GND
NIC PINS
TIE TO GND
Figure 74. Basic Connections
Rev. A | Page 23 of 36
12233-056
VCC1
C11
100pF
VSW1
0
1
0
1
0
0
1
1
ADL5246
Data Sheet
Amplifier 3 (AMP3)
AMP3 is a broadband 1⁄2 watt driver requiring band specific
matching to achieve the specified performance. The input and
output are easily matched using a combination of series and
shunt capacitors and a microstrip line serving as an inductor.
VPOS2 provides dc bias to the internal bias circuit. Bias for the
output stage is supplied to the amplifier via the L4 inductor that
is connected to RFOUT3. Therefore, both VPOS2 and VCC2 must
be connected to bias to operate AMP3. Capacitors C24, C25, and
C26 provide the power supply decoupling. When AMP3 is not in
use, terminate the RFIN3 and RFOUT3 pins to ground via a 100 pF
capacitor and a 50 Ω resistor in series on each pin. Figure 78
shows the matching components for operation at 2.2 GHz.
Gain Control
The integrated VVAs are controlled by VGAIN1 and VGAIN2.
The attenuators maybe controlled independently, if desired. The
gain control voltage range is 0 V to 3.3 V. R4 and R5 isolate the
gain control circuit from external capacitance. Capacitors C14
and C15 provide decoupling.
VSW1 and VSW1 are complementary 3 V logic that is used to
control the bypass switch operation and are detailed in Table 5.
R2 and R3 isolate the logic control circuitry from external
capacitance. The C6 and C11 capacitors provide decoupling.
Figure 9 through Figure 14 show that operating AMP2 at 5 V
gives greater gain range; however, operating at 3.3 V gives better
phase linearity. Operating at 5 V gives better temperature stability,
as shown in Figure 17. It is possible to operate the gain control
section at 5 V while operating the remainder of the ADL5246 at
3.3 V for reduced power consumption.
Amplifier 3 Matching
The input and output of the driver amplifier, AMP3, can be
matched to 50 Ω using two to three external components. The
microstrip transmission line is used as an inductor. The matching
component values are listed in Table 6. All capacitors are
Murata GRM15 series (0402 size), L4 is a Coilcraft® 0603CS
series (0603 size). The 0603 size is preferred over the 0402 size
for additional current handling capability. The self resonance of
L4 has little bearing on the performance of AMP3, within
reasonable limits. For all frequency bands, the placement of C1,
C3, and L6 are critical. Table 7 lists the component spacing for
C1, C3, and L6. The placement of C3 and R1 are fixed for the
matching network on the evaluation board. The spacing is 69 mils
and 301 mils, respectively. In the case of 0.75 GHz and 0.9 GHz,
a 2 Ω resistor is used in place of the capacitor in the C21 location.
Table 6. Matching Component Values on the ADL5246 Evaluation Board
Frequency (GHz)
0.75
0.9
1.9
2.2
2.6
C21
2Ω
2Ω
100 pF
100 pF
100 pF
C3 (pF)
9
6
2
1.5
1.0
L6 (nH)
3.3
3.3
1
1
1
C1 (pF)
8.2
6
2.7
2.7
2.2 F
C23 (pF)
100
100
100
100
100
Table 7. Matching Component Spacing on the ADL5246 Evaluation Board
Frequency (GHz)
0.75
0.9
1.9
2.2
2.6
C3: λ1 (mils)
69
69
69
69
69
L6: λ2 (mils)
24
24
24
24
24
Rev. A | Page 24 of 36
R1 (mils)
301
301
301
301
301
C1: λ3 (mils)
528.4
422.4
184.2
75.4
75.4
R1 (Ω)
0
0
0
0
0
Data Sheet
ADL5246
VPOS2
28
VCC2
GND
27
ADL5246
L4
100nH
C23
100pF
R1
0Ω
RFOUT3
26
C1
8.2pF
λ3
GND
RFIN3
NIC
GND
GND
21
22
23
24
25
λ1
C3
9pF
λ2
L6
3.3nH
12233-057
C21
2Ω
Figure 75. AMP3 Matching Circuit at 0.75 GHz
VPOS2
28
VCC2
GND
27
ADL5246
L4
100nH
C23
100pF
R1
0Ω
RFOUT3
26
λ3
GND
RFIN3
NIC
GND
GND
21
22
23
24
C1
6pF
25
λ1
C3
6pF
λ2
L6
3.3nH
12233-058
C21
2Ω
Figure 76. AMP3 Matching Circuit at 0.9 GHz
Rev. A | Page 25 of 36
ADL5246
Data Sheet
VPOS2
28
VCC2
GND
27
RFOUT3
26
L4
100nH
ADL5246
R1
0Ω
λ3
GND
RFIN3
NIC
GND
GND
21
22
23
24
C23
100pF
C1
2.7pF
25
λ1
C3
2pF
λ2
L6
1nH
12233-059
C21
100pF
Figure 77. AMP3 Matching Circuit at 1.9 GHz
VPOS2
28
VCC2
GND
27
L4
100nH
ADL5246
R1
0Ω
λ3
RFOUT3
C23
100pF
26
C1
2.7pF
GND
RFIN3
NIC
GND
GND
21
22
23
24
25
λ1
C3
1.5pF
λ2
L6
1nH
12233-060
C21
100pF
Figure 78. AMP3 Matching Circuit at 2.2 GHz
Rev. A | Page 26 of 36
Data Sheet
ADL5246
VPOS2
28
VCC2
GND
27
RFOUT3
26
L4
100nH
ADL5246
C23
100pF
R1
0Ω
λ3
C1
2.2pF
GND
RFIN3
NIC
GND
GND
21
22
23
24
25
λ1
C3
1pF
λ2
L6
1nH
12233-061
C21
100pF
Figure 79. AMP3 Matching Circuit at 2.6 GHz
13
ERROR VECTOR MAGNITUDE (EVM) PERFORMANCE
12
EVM is a measure used to quantify the performance of a digital
radio transmitter or receiver. A signal received by a receiver has
all constellation points at their ideal locations; however, various
imperfections in the implementation (such as magnitude
imbalance, noise floor, and phase imbalance) cause the actual
constellation points to deviate from their ideal locations.
11
10
9
EVM (%)
8
4
3
2
•
•
0
–25
–20
–15
–10 –5
0
5
10
15
MEAN OUTPUT POWER (dBm)
20
25
30
12233-062
1
In general, a receiver exhibits three distinct EVM limitations vs.
received input signal power.
At strong signal levels, the distortion components falling in
band due to nonlinearities in the device components cause
strong degradation to EVM as signal levels increase.
At medium signal levels, where the signal chain behaves in a
linear manner and the signal is well above any notable noise
contributions, EVM has a tendency to reach an optimum level
determined dominantly by the quadrature accuracy and the
precision of the test equipment. As signal levels decrease such
that noise is a major contribution, the EVM performance vs.
the signal level exhibits a decibel for decibel degradation
with decreasing signal level.
At lower signal levels, where noise proves to be the dominant
limitation, the decibel EVM proves to be directly proportional
to the SNR.
6
5
Figure 80 shows the EVM vs. the mean output power for a full
chain connection (AMP1 driving AMP2 driving AMP3)
operating at 2.2 GHz.
•
7
Figure 80. EVM vs. Mean Output Power (POUT) of Full Chain Connection at
2.2 GHz, 64 QAM, 5 MSPS, α = 0.2 Root Raised Cosine Filter, PIN = −3.7 dBm
Rev. A | Page 27 of 36
ADL5246
Data Sheet
THERMAL INFORMATION AND RECOMMENDED
PCB LAND PATTERN
FULL CHAIN OPERATION CONSIDERATIONS
The majority of the heat generated during operation is removed via
the exposed paddle on the bottom of the package. Figure 81 shows
the recommended land pattern for the ADL5246. To minimize
thermal impedance, the exposed paddle on the 5 mm × 5 mm
LFCSP package is soldered down to a ground plane. To improve
thermal dissipation, 25 thermal vias are arranged in a 5 × 5 array
under the exposed paddle. The land pattern on the ADL5246
evaluation board provides a thermal resistance (θJA) of 16.5°C/W.
For the best thermal performance, add as many thermal vias as
possible under the exposed pad of the LFCSP. If multiple ground
layers exist, tie them together using vias. For more information
on land pattern design and layout, see the AN-772 Application
Note, A Design and Manufacturing Guide for the Lead Frame
Chip Scale Package (LFCSP).
The gain of a cascaded series of amplifiers may differ from a simple
summation of the gain of each amplifier in the chain due to
impedance matching considerations.
Take the following precautions in the PCB layout of a full chain
connection of AMP1 driving AMP2 driving AMP3:
•
•
137.8 mils
122.0 mils
19.69
mils
122.0 mils
192.92
mils
12 mils
16.46 mils
25 mils
35 mils
12233-063
12.0
mils
Figure 81. Recommended Land Pattern Under ADL5246
Rev. A | Page 28 of 36
The VPOS2 pin may couple RF from the three amplifiers into
AMP2 and lead to instability. Therefore, it is recommended
that the VPOS2 trace be well shielded from the other
amplifiers. To accomplish this with the ADL5246 evaluation
board, the VPOS2 trace passes through a via to the bottom
side of the PCB close to Pin 28.
At frequencies below 1.5 GHz, there can be more than 40 dB
of gain from the full chain connection. With so much gain
available, take care to maintain stable operation. Coupling
from trace to trace on the PCB can be a significant factor
leading to instability. Minimizing coupling between the
amplifiers through good PCB layout is important. It can be
helpful to reduce the overall gain with resistance before AMP3
(such as R10 on the evaluation board) or to include filters
or attenuators between the amplifiers.
Data Sheet
ADL5246
EVALUATION BOARD
The schematic of the ADL5246 evaluation board is shown in
Figure 82. All RF traces on the evaluation board have a
characteristic impedance of 50 Ω and are fabricated from FR408
material. The traces are grounded coplanar waveguide (GCPWG)
with a width of 25 mils, spacing to ground of 20 mils, and dielectric
thickness of 13 mils. To ensure broadband performance, the inputs
and outputs of AMP1, AMP2, and AMP3 are ac-coupled with
100 pF capacitors.
The bias to AMP1 is provided through the L1 inductor. VPOS1
and VPOS2 provide bias to AMP2. The L2 and L3 inductors
provide a high impedance to the RF signals that might be present
on these pins. The AMP3 bias circuit receives bias from VPOS2.
The AMP3 output receives bias through the L1 inductor. Bypassing
capacitors are recommended on all supply lines to minimize RF
coupling. AMP3 on the ADL5246 evaluation board is configured
for 2.2 GHz operation.
The evaluation board is designed so that the gain control pins of
AMP2 can be controlled individually or in tandem using VGAIN1
and VGAIN2. The gain range is switched by providing the
appropriate logic level to the internal bypass switch via VSW1
and VSW1. See Table 5 for switch control logic information.
By default, the ADL5246 evaluation board is configured to evaluate
each of the amplifiers individually. To configure the evaluation
board to cascade AMP1, AMP2, and AMP3, remove the C9, C13,
C21, and C22 blocking capacitors and install the C10, C12, C18,
and C19 capacitors. The C33, C34, C31, C32, L8, and L7
components are place holders that allow for adding filters between
the gain stages, if required. If a filter is not being used, install a 0 Ω
resistor as a jumper in place of L7 and L8. Inductor L5 is provided
for optional interstage tuning between RFOUT2 and RFIN3.
Table 8. Evaluation Board Configurations Options
Component
VCC1, VCC2
VPOS1, VPOS2,
GND1, GND2,
GND3
R6, R7
U1
RFIN1, RFOUT1,
RFIN2, RFOUT2,
RFIN3, RFOUT3
R8, R9, R10, R11
C8, C9
C5, C40, C41
Function
Power supply and ground test loops.
Default Value
Installed
Jumpers to connect VPOS1 and VPOS2 to the internal power plane.
ADL5246ACPZN the device under test.
RF input and output SMA connecters.
R6, R7 = 0 Ω
Installed
Installed
Jumpers to facilitate the modification of the RF connections between the amplifier blocks.
AC coupling capacitors for AMP1.
Power supply decoupling capacitors for AMP1. Of these three capacitors, C5 must be
located closest to the device.
L1
The bias for AMP1 comes through L1 when connected to a 5 V supply. L1 must be high
impedance for the frequency of operation, while providing low resistance for the dc current.
Logic control test loops for the AMP2 integrated bypass switch.
R8, R9, R10, R11 = 0 Ω
C8, C9 = 100 pF
C5 = 100 pF,
C40 = 0.1 µF,
C41 = 1000 pF
L1 = 100 nH
VSW1, VSW1
R2, R3, C6, C11
VGAIN1, VGAIN2
R4, R5, C14, C15
C13, C22
C2, C4, C7, C16,
C17, C20
L2, L3
L5
C21, C23
R2 and R3 isolate the switch control pins from the external capacitance. C6 and C11
provide the decoupling.
VGAIN1 and VGAIN2 are test loops to apply the control voltage to the integrated VVAs.
R4 and R5 isolate the gain control pins from external capacitance. C14 and C15 provide the
decoupling.
AC coupling capacitors for AMP2.
Power supply decoupling capacitors for AMP2. Of these six capacitors, C7 and C16 must be
located closest to the device.
The bias for AMP2 comes through L2 and L3 when connected to a 5 V supply. L2 and L3
must be high impedance for the frequency of operation, while providing low resistance for
the dc current.
L5 is an optional tuning element, which can aid gain, bandwidth, and OP1dB in some
circumstances.
AC coupling capacitors for AMP3.
Rev. A | Page 29 of 36
Installed
R2, R3 = 100 Ω,
C6, C11 = 100 pF
Installed
R4, R5 = 100 Ω,
C14, C15 = 100 pF
C13, C22 = 100 pF
C7, C16 = 100 pF,
C2, C20 = 0.1 µF,
C4, C17 = 1000 pF
L2 = 10 nH,
L3 = 100 nH
L5 = do not install (DNI)
C21, C23 = 100 pF
ADL5246
Data Sheet
Component
L6, C3
Function
AMP3 input matching elements.
C24, C25, C26
Power supply decoupling capacitors for AMP1. Of these three capacitors, C24 must be
located closest to the device.
L4
The bias for AMP3 comes through L4 when connected to a 5 V supply. L4 must be high
impedance for the frequency of operation, while providing low resistance for the dc current.
C1 is the output matching element for AMP3. R1 is a placeholder for the optional tuning
configurations.
Optional components for loop integration.
C1, R1
C10, C12, C18,
C19, C27 to C34,
L7, L8
Rev. A | Page 30 of 36
Default Value
L6 = 1 nH,
C3 = 1.5 pF
C24 = 100 pF,
C25 = 1000 pF,
C26 = 0.1 µF
L4 = 100 nH
C1 = 2.7 pF,
R1 = 0 Ω
C10, C12, C18, C19, C27
to C34, L7, and L8 = DNI
Data Sheet
ADL5246
RFIN2
RFOUT1
C9
100pF
C13
100pF
C10
DNI
C12
DNI
L8
DNI
C34
DNI
C33
DNI
R8
0Ω
VPOS2
R9
0Ω
C27
C28
DNI
DNI
L3
R7
100nH
VPOS
0Ω
VCC1
C16
C20
0.1µF
C17
100pF 1000pF
C23
L1
RFOUT3
100pF
100nH
100pF
VSW1
R2
100Ω
C6
RFOUT1
GND
RFIN2
GND
VPOS2
GND
RFOUT3
GND
GND
RFIN1
GND
NIC
NIC
U1
ADL5246
VSW1
NIC
NIC
NIC
24
23
22
21
20
19
18
17
L4
λ2
λ1
100nH
R10
1.5pF
L6
1nH
0Ω
C29
DNI
C31
DNI
L5
C18
DNI
DNI
C30
DNI
GND TO PADDLE
C26
0.1µF
RFIN3
C21
C19
DNI
R11
0Ω
100pF
C22
RFOUT2
100pF
VPOS1
L2
R6
10nH
0Ω
C2
0.1µF
C4
C7
1000pF
100pF
GND1
R3
100Ω
VSW1
R4
100Ω
VGAIN1
GND2
GND3
R5
100Ω
VGAIN2
C11
C14
C15
100pF
100pF
100pF
12233-064
VPOS
C24
C25
100pF 1000pF
L7
DNI
C32
DNI
10
11
12
13
14
15
16
100pF
C3
GND
GND
NIC
RFIN3
GND
NIC
RFOUT2
VCC2
0Ω
C1
2.7pF
32
31
30
29
28
27
26
25
PAD
1
2
3
4
5
6
7
8
C8
9 NIC
GND
VPOS1
NIC
VSW1
NIC
VGAIN1
VGAIN2
RFIN1
R1
λ3
C41
C5
1000pF 100pF
C40
0.1µF
Figure 82. Evaluation Board Schematic
Rev. A | Page 31 of 36
12233-066
Data Sheet
12233-065
ADL5246
Figure 84. Evaluation Board Layout Bottom
Figure 83. Evaluation Board Layout Top
Rev. A | Page 32 of 36
Data Sheet
ADL5246
CHARACTERIZATION INFORMATION
The ADL5246 was characterized with multiple samples obtained
from three batch lots. Each ADL5246 was attached to its own
circuit board that was dedicated and tuned to one of the AMP3
frequency bands. This created a body of boards dedicated to
each band. AMP1 and AMP2 operate over a broad frequency
range and do not require tuning. Aggregating boards with their
AMP3 tuned to the various bands increased the sample size for
the characterization of AMP1 and AMP2.
The plots show the performance obtained by the typical
ADL5246 chosen to demonstrate each amplifier, rather than
showing the numerical median of all the samples measured for
any one parameter.
Characterization measurements employed an Agilent Technologies
PNA-X vector network analyzer, scalar rack and stack equipment,
a noise figure analyzer, and temperature forcing equipment, all
under software control.
All three amplifiers are powered on even when not directly in
use and this made heat a concern when testing in a high
temperature environment. Two 10 mm × 10 mm heat sinks are
attached to the back of the circuit board with Arctic Silver thermal
adhesive. This lowered the θJA at the top of the package from
16.5°C/W without the heat sink to 12.5°C/W with one, making
operating AMP3 at P1dB output power levels in a 105°C ambient
temperature possible without reaching the maximum junction
temperature of the ADL5246.
The typical performance figures represent one typical ADL5246
with performance near the median of a body of available samples.
A typical example ADL5246 was selected to represent AMP1
and a different ADL5246 was selected to represent AMP2. Separate
examples are used for each of the AMP3 bands; therefore, the
AMP3 plots do not show the same ADL5246 board retuned to
each band.
The circuit boards used for device characterization are fabricated
with Isola FR408, which offers a low coefficient of thermal
expansion (CTE) and lower attenuation than standard FR4 without
the fragility of Rogers materials.
Rev. A | Page 33 of 36
ADL5246
Data Sheet
OUTLINE DIMENSIONS
PIN 1
INDICATOR
5.10
5.00 SQ
4.90
0.30
0.25
0.18
25
24
0.50
BSC
32
1
PIN 1
INDICATOR
3.40
3.30 SQ
3.20
EXPOSED
PAD
17
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.05
0.20 REF
SEATING
PLANE
PKG-4280
16
9
8
BOTTOM VIEW
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5.
05-29-2013-A
TOP VIEW
0.45
0.40
0.35
Figure 85. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
5 mm × 5mm Body, Very Very Thin Quad
(CP-32-20)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADL5246ACPZN-R7
ADL5246-EVALZ
1
Temperature Range
−40°C to +105°C
Package Description
32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Evaluation Board
Z = RoHS Compliant Part.
Rev. A | Page 34 of 36
Package Option
CP-32-20
Data Sheet
ADL5246
NOTES
Rev. A | Page 35 of 36
ADL5246
Data Sheet
NOTES
©2014–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12233-0-9/15(A)
Rev. A | Page 36 of 36